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Corner effect in double and triple gate FinFETs

Conference Paper · October 2003

DOI: 10.1109/ESSDERC.2003.1256829 · Source: IEEE Xplore

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Alex Burenkov J. Lorenz

Fraunhofer Institute for Integrated Systems and Device Technology IISB Fraunhofer Institute for Integrated Systems and Device Technology IISB
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 Corner Effect in Double and Triple Gate
FinFETs
A. Burenkov, J. Lorenz
Fraunhofer Institute of Integrated Systems and Device Technology
Schottkystrasse 10, 91058 Erlangen, Germany
[email protected]

Abstract FinFETs is a possible negative impact of the corner ef-

fect which is known to deteriorate the electrical perform-
The corner effect is known as a leakage current en- ance of the shallow trench isolated (STI) MOS transis-
hancement at the edges of the active areas in the shallow tors.
trench isolated CMOS transistors. It usually deteriorates The task of this work is to investigate the role of the
the transistor performance. In this work, the corner ef- corner effect on the electrical performance of FinFET
fect for FinFET transistors with the minimum feature transistors with minimum feature size of 50 nm, espe-
size of 50 nm is investigated by coupled three- cially for the triple gate wrap around transistor design,
dimensional process and device simulation. In contrast using coupled three-dimensional (3D) process and device
to earlier CMOS generations, the corner effect in small simulation.
size FinFETs for typical device parameters does not lead
to an additional leakage current and therefore does not 2. Device geometry
deteriorate the FinFET transistor performance. This
holds for both double and triple gate FinFETs. Two device geometries have been considered in this
work: the gate wrap around triple gate FinFET transistor
1. Introduction and the double gate FinFET transistor in which the upper
part of the gate electrode is separated from the gate oxide
FinFET is a promising architecture for MOS transis- by an additional nitride layer of 10 nm thickness. The
tors with gate lengths of 50 nm and smaller [1]. The geometrical shape of the simulated transistor structures
main feature of the FinFET is that the active area of the are depicted in Figures 1 and 2.
transistor is realized as a thin silicon wire between the
source and drain contacts. Technologically, the silicon
fin is cut-out by an etching process from a silicon-on-
oxide layer. Several variants of the gate design in Fin-
FETs have been suggested [2-4]. The simplest gate de-
sign consists of a deposition of the gate material on the
silicon fin after the gate oxidation and a subsequent
structuring of the gate material to define the gate length.
In the triple gate FinFET which results in this case, the
gate wraps around the rectangular silicon fin from three
sides. The triple gate FinFET has a large effective chan-
nel width: as will be illustrated below, the effective gate
width of the transistor is equal to two times the thickness
of the silicon-on-oxide layer plus the width of the silicon
fin, Weff = 2*Tfin + Wfin. An alternative and more conser-
vative gate architecture includes the preservation of a
hard mask on top of the silicon fin before the gate depo-
sition. In this case, there is no direct contact between the
gate electrode and the gate oxide on top of the silicon fin
and this part of the fin does not contribute to the effective
gate width of the transistors, Weff = 2*Tfin. For a square
cross section of the fin, one third of potentially usable Figure 1. Geometrical shape of the triple gate Fin-
gate width is lost if this transistor design is used, and FET.
consequently, a drive current which is about 1/3 lower is The triple gate FinFET transistor shown in Figure 1 con-
expected. sists of the silicon substrate, buried oxide isolation, the
The use of the gate wrap around design is attractive silicon fin, and the gate electrode. The gate oxide and
since a significantly higher drive current can be achieved other isolation and contact materials are not shown in
for the same minimum feature size. One of the intuitive this figure for clarity. The size of the silicon fin shown in
objections against the gate-wrap-around design of the Figure 1 is 50x50x200 nm3. The thickness of the buried
oxide is 0.1 µm. A gate oxide of 2 nm is used for all 4. Simulation results
transistors considered.
The double gate FinFET transistor differs from the The results of the simulation of the electrical proper-
triple gate transistor by an additional nitride layer seen in ties of three FinFET transistor variants are presented in
Figure 2 which isolates the gate electrode from the upper Figures 3 and 4. The two variants of the triple gate
part of the active area. Additionally, the source and drain NMOS FinFET shown in the figure differ from each
contacts are shown in Figure 2. other by different channel doping. The variant marked
“Triple Gate 1” has the channel doping of 1015cm-3,
“Triple Gate 2” has the channel doping of 3·1017cm-2.
Figure 3 shows the sub-threshold characteristics of the
investigated FinFETs for a drain voltage of 1 V, source
and bulk contacts being at zero bias, while Figure 4 de-
picts the transistor transfer characteristics in linear scale.

Figure 2. Geometrical shape of the double gate

FinFET.
Figure 3. Simulated sub-threshold transfer charac-
teristics of the triple gate and double gate FinFETs
3. Process and device simulation at drain voltage of 1 V

The geometrical shape of the transistors have been

obtained in two stages. First, a two-dimensional simula-
tion in a vertical cut through the middle of the gate per-
pendicular to the axis of the fin was performed. The re-
sult of the two-dimensional simulation was extended into
third direction in accordance with the layout of the tran-
sistors shown in Figures 1 and 2. In case of the double
gate FinFET this also includes the nitride layer which
isolates the upper part of the fin. The source and drain
implantation was simulated three-dimensionally using
the ion implantation module IMP3D [5]. Arsenic im-
plantation with an energy of 10 keV and a dose of
2x2.5·1015cm-2 under tilt angle of ±45º in direction per-
pendicular to the fin length was used for source and drain
formation. Oxide spacers of 25 nm width were used to
properly position the source and drain doping relative to
the gate electrode. A final RTA annealing at 1000ºC for Figure 4. Simulated transfer characteristics of the
10 s was simulated using the pair-diffusion model of the triple gate and double gate FinFETs at drain voltage
three-dimensional version of the DIOS [6] process of 1 V
simulators of the ISE AG. Two levels of channel doping
were used in this work, 1015cm-3 and 3·1017cm-2 of boron. Although “Triple Gate 1” and “Double Gate” FinFETs
The first one is representative for the non-doped silicon have a completely identical doping in the active area, the
fins which are attractive because of the minimization of performance of the triple gate transistor is better than the
the effects associated with the random doping distribu- one of the double gate transistor. In fact, the “Triple Gate
tion, the second one is typical for normally doped NMOS 1” has an about 50% lower leakage current and a 19%
transistors. Three-dimensional device simulation have higher on-current at VD=VG=1V. On the other hand side,
been performed using the DESSIS [7] device simulator if “Triple Gate 2” is compared with the “Double Gate”,
of ISE AG.
the “Triple Gate 2” has a slightly higher on-current, but 5 to 7 show the leakage current distributions at gate volt-
simultaneously a much (factor 182) lower leakage cur- age of -0.5 V in the three transistors considered.
rent compared to “Double Gate”.

Figure 8. Electrostatic potential distribution in the

Figure 5. Leakage current distribution in the lateral lateral cut through the middle of the gate of the tri-
cut through the middle of the gate of the triple gate ple gate FinFET with the channel doping of
15 -3 15 -3
FinFET with a channel doping of 10 cm 10 cm

Figure 6. Leakage current distribution in the lateral Figure 9. Electrostatic potential distribution in the
cut through the middle of the gate of the double lateral cut through the middle of the gate of the
15 -3
gate FinFET with a channel doping of 10 cm double gate FinFET with the channel doping of
15 -3
10 cm

Figure 7. Leakage current distribution in the lateral

cut through the middle of the gate of the triple gate Figure 10. Electrostatic potential distribution in the
17 -3
FinFET with a channel doping of 3·10 cm lateral cut through the middle of the gate of the tri-
ple gate FinFET with the channel doping of
Again, the triple gate FinFET appears to be more advan- 17 -3
3·10 cm
tageous in its electrical performance.
To clarify the physical background of the better per- No leakage current enhancement in the corners of the
formance of the triple gate FinFET in comparison to the fin is observed. In contrast, a depletion of the leakage
double gate FinFET of the same size, we present some of current in the upper corners of fin is seen in Figures 5
the typical distributions inside of the transistors. Figures
 to 7. The depletion is much more pronounced in the two from the drain through the middle of the fin. In the result,
triple gate FinFETs. the potential distributions shown in Figures 8 to 10 are
established inside of the transistors.
The corner effect at negative gate voltages results in a
penetration of the negative surface potential into the ac-
tive silicon and the consequence is the reverse corner
effect, this means the depletion of the leakage current in
the corners seen in Figures 5 to 7.
Figures 11 to 13 illustrate the current distributions in
the electrically open transistors, VD=VG=1V. The current
density is mainly concentrated close to the surface and
drops down rapidly. The enhancement of the current due
to corner effect extends only over a very small region
near the corner. This is due to a short screening lengths
inside of inversion layer. The major effect in the double
gate transistor is the suppression of the current near the
upper surface of the fin. As it is seen in Figure 12, the
inversion layer at the upper surface of silicon fin is not
Figure 11. Current distribution in the lateral cut through completely suppressed. This is due to a small thickness
the middle of the gate of the electrically open triple gate of the shielding nitride layer of 10 nm.
FinFET with the channel doping of 1015 cm-3 The distribution of the current in Figure 12 also ex-
plains why the on-current of the double gate transistors is
higher than a simple estimation of 2/3 of the current of
the triple gate transistors. In fact, Figure 12 shows that
the upper part of the fin also contributes to the total cur-
rent of the open double gate transistor. A slight en-
hancement of the current in the corners of the fin in the
open transistors is observed for all three transistors con-
sidered.

5. Conclusion
The corner effect known to increase the leakage cur-
rents in shallow trench isolated CMOS transistors does
not deteriorate the performance of the small size Fin-
FETs. In contrast, the corner effect improves the per-
Figure 12. Current distribution in the lateral cut
formance of the FinFETs since the on-current is en-
through the middle of the gate of the electrically
hanced at the corners and the leakage current is sup-
open double gate FinFET with the channel doping
15 -3 pressed. Due to positive influence of the corner effect,
of 10 cm
the triple gate wrap around design of the FinFET appears
to be more advantageous in comparison to the double
gate design.

6. Acknowledgement

This work has been partially performed within the

project NESTOR supported by the European Commis-
sion as the IST project 2001-34114.

References
[1] M. Ieong et al., ULIS Conf. Proc. 2003, p. 69-72.
[2] D. Hisamoto et al., IEDM Digest 1998, p.1032-4.
Figure 13. Current distribution in the lateral cut [3] N. Lindert et al., IEEE Electron Dev. Lett. 22, No.
through the middle of the gate of the electrically 10, 2001, p. 487-489.
open triple gate FinFET with the channel doping of [4] M. Lemme et al., ULIS 2002, p. 159-162.
17 -3 [5] A. Burenkov et al., IEICE Trans. Electronics, E83-C,
3·10 cm
No. 8, 2000, p. 1259-1266.
The physical reason for this is the penetration of the [6] DIOS, Release 8.0, ISE AG, Zurich, 2002.
negative electrical potential from the gate electrode into [7] DESSIS, Release 8.0, ISE AG, Zurich, 2002.
the corners and the penetration of the positive potential

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