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(B) Simulate The Simplified Logic Expression Using VHDL and Verify It's Working

The document contains VHDL code to simulate various digital logic circuits including a logic expression, full adder, full subtractor, magnitude comparator, 4:1 multiplexer, 2:4 decoder, D flip-flop, switched tail counter, and mod-8 up counter. Each circuit is defined with an entity that specifies the ports, and an architecture that defines the logic using VHDL processes and assignments.

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Aparna Roy
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27 views

(B) Simulate The Simplified Logic Expression Using VHDL and Verify It's Working

The document contains VHDL code to simulate various digital logic circuits including a logic expression, full adder, full subtractor, magnitude comparator, 4:1 multiplexer, 2:4 decoder, D flip-flop, switched tail counter, and mod-8 up counter. Each circuit is defined with an entity that specifies the ports, and an architecture that defines the logic using VHDL processes and assignments.

Uploaded by

Aparna Roy
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.(b) Simulate the simplified logic expression using VHDL and verify it’s working.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity exp is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
f : out STD_LOGIC);
end exp;

architecture Behavioral of exp is

begin
f<=((not(a)and b) or (a and not(b)) or (a and b and c));

end Behavioral;
Input

Output
2(b). Simulate the Adder, Subtractor, Magnitude Comparator using VHDL and verify it’s
working.

Full Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end adder;

architecture Behavioral of adder is

begin
sum <= a xor b xor c;
carry <= ((a and b) or (b and c) or (c and a));

end Behavioral;
Input

Output
Full Subtractor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity subtractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC;
br : out STD_LOGIC);
end subtractor;

architecture Behavioral of subtractor is

begin

d<= a xor b xor c;


br<=((not(a) and b)or(not(a) and c)or(b and c));

end Behavioral;
Input

Output
Magnitude Comparator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity magnitude is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
g : out STD_LOGIC;
l : out STD_LOGIC;
e : out STD_LOGIC);
end magnitude;

architecture Behavioral of magnitude is

begin

g<=a and not(b);


l<=not(a) and b;
e<=((not(a) and not(b)) or (a and b));

end Behavioral;
Input

Output
3.(b) Simulate 4;1 Multiplexer using VHDL and verify it’s working.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC);
end mux;

architecture Behavioral of mux is

begin

y<=d(0) when s="000" else


d(1) when s="001" else
d(2) when s="010" else
d(3) when s="011" else
d(4) when s="100" else
d(5) when s="101" else
d(6) when s="110" else
d(7);

end Behavioral;
Input

Output
4.(b) Simulate 2:4 Decoder using VHDL and verify it’s working.
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decode is

Port ( s : in STD_LOGIC_VECTOR (02 downto 0);

y : out STD_LOGIC_VECTOR (07 downto 0));

end decode;

architecture Behavioral of decode is

begin

process(s)

begin

if(s="000")then

y<="01111111";

elsif(s="001")then

y<="10111111";

elsif(s="010")then

y<="11011111";

elsif(s="100")then

y<="11110111";

if(s="101")then

y<="11111011";

elsif(s="110")then

else

y<="11111110";

end if;

end if;

end process;

end Behavioral;
Input

Output
5.(b) Simulate D Flip Flop using VHDL and verify it’s working.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dflipflop is

Port ( clk : in STD_LOGIC;

d : in STD_LOGIC;

q : inout STD_LOGIC:='0';

qb : inout STD_LOGIC:='1');

end dflipflop;

architecture Behavioral of dflipflop is

begin

process(clk)

begin

if rising_edge(clk) then

q<=d;

qb<=not(d);

end if;

end process;

end Behavioral;
Input

Output
6.(b) Design and develop the VHDL code for Switched Tail counter. Simulate and verify it’s working.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jccounter is

Port ( clk : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (3 downto 0):="0000");

end jccounter;

architecture Behavioral of jccouter is

begin

process(clk)

begin

if falling_edge(clk)then

q<=(not(q(0))&q(3downto 1));

end if;

end process;

end Behavioral;
Input

Output
8.(b) Design and develop the VHDL code for Mod-8 up counter. Simulate and verify it’s
working.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod8 is
Port ( clk : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (0 downto 0):="0000");
end mod8;

architecture Behavioral of mod8 is

begin
process(clk)
begin
if rising_edge(clk) then q <= q+1;
if q = "0111" then q<="0000";
end if;
end if;
end process;
end Behavioral;
Input

Output

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