Scribd
Upload
3K views

"Digital Technique": Micro Project Work Submitted by

This document describes a project to design a 4-bit adder circuit using a 0.25 um CMOS technology. The objectives are to minimize delay, area usage, and power consumption. The project involved research and simulation phases. In the research phase, different adder architectures were evaluated based on area and delay. Gate-level logic families were also compared. In the simulation phase, each gate was optimized for delay and power before simulating a 1-bit full adder and the full 4-bit adder. The worst case delay and average power of the 4-bit adder design are estimated.

Uploaded by

sudarshan sonawane
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
3K views

"Digital Technique": Micro Project Work Submitted by

This document describes a project to design a 4-bit adder circuit using a 0.25 um CMOS technology. The objectives are to minimize delay, area usage, and power consumption. The project involved research and simulation phases. In the research phase, different adder architectures were evaluated based on area and delay. Gate-level logic families were also compared. In the simulation phase, each gate was optimized for delay and power before simulating a 1-bit full adder and the full 4-bit adder. The worst case delay and average power of the 4-bit adder design are estimated.

Uploaded by

sudarshan sonawane
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 9

4-bit adder

Department of second year Computer Engineering

“Digital Technique”

Micro project work submitted By:


1. Sudarshan Arjun Sonawane
2. Santosh Sakharam Sonavane
3. Mungaji Eknath Thube

4-bit adder Page 1


4-bit adder

CERTIFICATE

This is to certify that MR. --------------------------------------------------------------------


Of Third semester of Diploma in ‘Computer Engineering’ of institute’ K.S.S.E.D.
Polytechnic College Shevgaon’. has submitted the Micro-project satisfactorily in
subject “Digital Technique” for academic year 2018 to 2019 as prescribed in the
curriculum.

Place: - Rakshi Enrollment No: ---------------

Date: ------------- Exam.Seat:-----------

Subject Teacher HOD Principal

4-bit adder Page 2


4-bit adder

INDEX
Sr.No Point Name

1. Introduction

2. Components /References/Objective

3. Procedure

4. Pin Connection Diagram

5. Full-Adder

4-bit adder Page 3


4-bit adder

Introduction

The topic of the course project is to design a 4-bit adder in the standard 0.25 um CMOS Technology.
The main objectives of the project is to minimize the total delay of the adder (i.e. the worst case delay of
the circuit), the area used to implement the adder, and its average power consumption. That in mind,
the team was able to split the project into 2 phases: the research phase and the simulation phase. In the
research phase, the team had to compare different adder architectures clearly defining the advantages
and disadvantages of each one in terms of area and delay to be able to choose what could be the most
efficient adder architecture for the design of a 4-bit adder. Another essential task in the research phase
was to decide on the gate level implementation of the circuit, compare the different logic
families’implementations for each gate, and finally decide on the proper logic family implementation for
each gate in light of the project objectives stated beforehand. Once the research phase was
accomplished, the team had to move on to the simulation phase. In the simulation phase, the team had
to design each gate separately and optimize it to achieve the optimum delay and
powerconsumption,thensimulate a 1-bit full adder, and finally simulate the whole 4-bit adder. The
simulation phase concludes the project by estimating the worst case delay of the 4-bit adder design and
the average power consumption of the circuit.

4-bit adder Page 4


4-bit adder

Objective
-
To investigate the logical properties of the exclusive-OR function.
-To implement a number of different logic functions by means of exclusive-OR gates and to investigate
their logical properties.

References

Donald P.Leach: Experimental in Digital Principles, 3rdEdition Malvino/Leach: Digital Principles and
Applications Bartee: Digital Computer Fundamentals, 6thEdition

Components

1-74LS04 hex-inverter (NOT) TTL IC 1-74LS08 Quad-two input AND TTL IC 1-74LS32 Quad-two input OR
TTL IC 1-74LS86 exclusive OR (EX-OR) TTL IC 1-DC Voltmeter 1- +5V Power supply

4-bit adder Page 5


4-bit adder

 Procedure

1) Connect the circuit in fig 2-1.Using 0= 0 V dc and 1= +5V dc, verify that the circuit will
perform the exclusive-OR function by completing the truth table. 2) Connect the circuit in fig 2-
2.Using 0= 0 V dc and 1= +5V dc, verify that the circuit will perform the exclusive-OR function
by completing the truth table. 3) Connect the half-adder circuit in fig 2-3b.Using 0= 0 V dc and
1= +5V dc, construct a truth table for this circuit by applying the inputs A and B as shown in
table 3 and record the resulting sum and carry output measured.
4) Use the exclusive-OR gates to construct the full-adder in Fig 2-4a. Construct its truth table
using the same procedure as in step1. For each input, record the sum and carry output of each
half- adder as well as the OR-gate output.

4-bit adder Page 6


4-bit adder

 Pin Connection Diagram

4-bit adder Page 7


4-bit adder

 Full-Adder

A full-adder is a logic circuit having 3 inputs A,B and C ( which is the carry from the previous
stage) and 2 outputs (Sum and Carry), which will perform according to table 3. The full-adder
can handle three binary digits at a time and can therefore be used to add binary numbers in
general.
The simplest way to construct a full adder is to connect two half- adder and an OR gate as
shown in Fig 2-4. The full-adder is then the fundamental logic circuit incorporated in digital
computers to perform arithmetic functions.

4-bit adder Page 8


4-bit adder

4-bit adder Page 9

You might also like