CSS 422 Hardware and Computer

Organization

Digital Logic
Ver. 1.1

Professor Tyler Folsom

The slides are re-produced by the courtesy of

Dr. Arnie Berger and Dr. Wooyoung Kim
 Topic

Chapter 1, 2, 3 by Berger
Chapter 3 by Null

• Digital Logic and Combinational Circuit

- Logic and Gates
- Karnaugh maps and Boolean equations
- Combinational Circuit Design

2
 Logical Gates
• The Gate is the basic element of all digital systems
– Three types of gates form the “atomic” elements

A
C is TRUE if and only if (A is TRUE AND
AND C C = A·B
B B is TRUE)

A
OR C C=A+ B C is TRUE iff (A is TRUE OR B is TRUE)
B

NEGATION SYMBOL

A NOT B B=A B is TRUE iff A is FALSE

3
 A B AB A+B ~A
Notation 0 0 0 0 1
0 1 0 1 1
1 0 0 1 0
1 1 1 1 0

A
AND C C = A·B C = AB; C = A⌃ B; C = A & B
B

A
OR C C=A+ B C = A⌄ B; C = A | B
B

NEGATION SYMBOL

A NOT B B=A B = ~A; B = A’; B = !A

4
When you open your computer box, what
do you see?
 Integrated Circuits
• Integrated Circuits (IC) are built from gates

• A gate is an electronic circuit: the fundamental building blocks of digital

systems
• Simple gates are combined to create more complex functions

6
 Circuit Packages

• (a) is a Dual Inline Package (DIP). A popular format for 40 years for low
and medium level of integration. Used in the 7400/5400 series of
Transistor-Transistor Logic (TTL) devices.
• Memory is often in SIP (Single Inline Package).
• (b) is a through-hole package with more leads than a DIP. Used for higher
level integration.
• (c ) is a surface mount device. Trickier to solder, but more robust and
compact. 7
 NAND Gate Example
A B ~(AB)
0 0 1 PIN 1

0 1 1
1 0 1
1 1 0
To 0 V
(Ground)
Pin 1
Pin 7

B A Typical NAND gate circuit

Quad, 2-input NAND gate
• 74LS00
• Cost: ~ $0.10
C • Propagation delay ~ 5 nsec
D
• 14-pin Dual in-line package (DIP)
• Circuits vary from 8 pin DIP packages
to over 600 pin high-density packages
Pin 14
Pin 8 To +3.3V (5V)
8
 Gates and Logic
• Digital computers use the binary system, instead of decimal
– ALL digital computers are collections of switches made from transistors
– A switch is ON or OFF
• Principles of Logic (a branch of Philosophy / Mathematics) are useful to
describe the digital circuits in computers
– True/False, 1/0, On/OFF, High/Low all describe the same possible states of a
digital system

on/off switch
A B C
+
C = A AND B

Battery Symbol
- Light bulb (load)

A
AND C C = A·B 9
B
 Positive and negative logic

• Which voltage to assign to true or false is an

arbitrary decision.
• Most circuits use positive logic: 0V is false,
and high voltage is true.
• 0 usually means 0 to 1.2V.
• High is most commonly 5V or 3.3V.
• Anything above 2.5V is considered high.
• For negative logic, we could equate true with
low voltage, and false with high voltage
10
 Exclusive OR ( XOR ) Gate
A
A
XOR C
A
B
A· B
C=A + B

B
C
A

A· B C= A· B + A ·B
B
C=A + B

Physical Connection

C is TRUE iff ((A is TRUE AND B is FALSE) OR (A is FALSE AND B is TRUE))

Alternatively
C is TRUE iff A ≠ B
 Logic Gates
Algebraic
Name Graphical Symbol Truth Table
Function
A B F
A F=A B 0 0 0
AND F or 0 1 0
B F = AB 1 0 0
1 1 1
A B F
A 0 0 0
OR F F=A+B 0 1 1
B 1 0 1
1 1 1

F=A A F
NOT A F or 0 1
1 0
F = A’

A B F
A 0 0 1
NAND F F = AB 0 1 1
B 1 0 1
1 1 0
A B F
A 0 0 1
NOR F F=A+B 0 1 0
B 1 0 0
1 1 0
A B F
A 0 0 0
XOR F F=A B 0 1 1
B 1 0 1
1 1 0 12
 Boolean Arithmetic is different
Same
• Commutative Different
AB = BA; A+B = B+A • Inverse
• Associative A*(~A) = 0 = False
(AB)C = A(BC) A+(~A) = 1 =True
(A+B)+C = A+(B+C) • AA = A; A+A = A
• Identity • Distributive!
A+0=A; A*1=A A+(BC) = (A+B)(A+C)
• Distributive • No precedence of AND over
A(B+C) = (AB) + (AC) OR!
 Basic Identities of Boolean Algebra

Basic Postulates
A•B=B•A A+B=B+A Commutative Laws
A • (B + C) = (A • B) + (A • C) A + (B • C) = (A + B) • (A + C) Distributive Laws
1•A=A 0+A=A Identity Elements
A• A =0 A+ A =1 Inverse Elements
Other Identities
0•A=0 1+A=1
A•A=A A+A=A
A • (B • C) = (A • B) • C A + (B + C) = (A + B) + C Associative Laws
A•B= A + B A +B= A• B DeMorgan's Theorem
 Mathematical Logic

• Implication: p→q; if p, then q; p only if q.

p is sufficient for q; q is necessary for p.
• Equivalence: p↔q; p if and only if q; p iff q;
p=q.
p q p →q p↔q
T T T T
T F F F
F T T F
F F T T

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 Tautology

• A tautology is a logical expression whose truth

table is always true for any inputs.
• (p→q)↔(~p + q)
• The contrapositive is always true
(p→q)↔(~q → ~p)
• The converse (q → p) need not be true.

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 Dual

• Swap AND with OR

• Swap 0 with 1
• The dual of a tautology is always true
~(AB) ↔(~A + ~B)
~(A+B) ↔((~A)(~B))
• Which Boolean Laws are duals?

17
 From Circuit to Boolean Equation
• We can easily interpret the function of a given circuit

A
A· B

B
C
A
(A · B) + (A · B)

A· B
B

C = A + B = A XOR B

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How to build a circuit with a given logic?
 Designing a Digital System
• We can use the concept of a Truth Table as a design tool
A 000
D0
a B
D0
001

D1
D1

C
010
D2
D2
b D3
011
D3

100
D4 D4
101
D5 D5
110
D6 D6
c 111
D7 D7

3 X 8 line decoder
Figure 11.15 Decoder with 3 Inputs and 23 = 8 Outputs

• Suppose that we want to design a digital system, such as the above “line
decoder” (used for line selection)
abc = 000 à D0 =1 abc = 100 à D4 =1
abc = 001 à D1 =1 abc = 101 à D5 =1
abc = 010 à D2= 1 abc = 110 à D6= 1
abc = 011 à D3= 1 abc = 111 à D7= 1
 Design a Circuit
• Designing a digital system starts from designing a chip, which consists of a
number of gates (simple or combinational)
• Gates are composed of, Inputs, Outputs and Logic Gates (the three atomic
gates, AND, OR, NOT)
• How to start?

1. Based on the purpose of the system, decide the number of inputs and the
number of outputs (inputs and outputs are binary: on / off)
– Figure out how many bits needed for input and output
2. Draw a truth table for each input combination and output combination
– For example, how many combinations for three bits of input? Derive a Boolean
equation for each output
3. Connect inputs to outputs using logic gates
4. Test if your circuit matches with the design – the logic in truth table
21
 Design a 3 x 8 Line Decoder
1. Decide the number of inputs and the number of outputs (inputs and outputs are
binary)
– Three bits for input, eight bits for output

A A 000 D0
D0

B
001
D1 D1
C
010
D2 D2

011
D3
B D3

100
D4 D4

101
D5 D5

110
D6 D6

C 111
D7
D7

Figure 11.15 3 X 8 line

Decoder with 3decoder
Inputs and 23 = 8 Outputs
22
 Design a 3 x 8 Line Decoder
2. Draw a truth table for each input combination and output combination
a b c D0 D1 D2 D3 D4 D5 D6 D7
abc = 000 à D0 =1
abc = 001 à D1 =1
abc = 010 à D2= 1
0 0 0 1 0 0 0 0 0 0 0
abc = 011 à D3= 1
0 0 1 0 1 0 0 0 0 0 0
abc = 100 à D4 =1
abc = 101 à D5 =1 0 1 0 0 0 1 0 0 0 0 0
abc = 110 à D6= 1
0 1 1 0 0 0 1 0 0 0 0
abc = 111 à D7= 1
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Design a 3 x 8 Line Decoder
3. Derive a Boolean equation for each output
a b c D0 D1 D2 D3 D4 D5 D6 D7
D0 =
D1 =
D2=
0 0 0 1 0 0 0 0 0 0 0
D3 =
0 0 1 0 1 0 0 0 0 0 0
D4 =
D5 = 0 1 0 0 0 1 0 0 0 0 0
D6 =
D7 =
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Design a 3 x 8 Line Decoder
• Obtain Boolean equation for each output

D0 = ~a ~b ~c
D1 = ~a ~b c
D2 = ~a b ~c
D3 = ~a b c
D4 = a ~b ~c
D5 = a ~b c
D6 = a b ~c (use ~ instead of overbar, easier to type…)
D7 = a b c

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 Design a 3 x 8 Line Decoder
4. Connect inputs to outputs using logic gates
A 000
D0 = ~a ~b ~c D0

B
D1 = ~a ~b c
001
D1
D2 = ~a b ~c
C
D3 = ~a b c 010
D2

D4 = a ~b ~c
D5 = a ~b c 011
D3

D6 = a b ~c
100
D7 = a b c D4

101
D5

110
D6

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111
D7
 Design a 3 x 8 Line Decoder
5. Test! (Use Logisim)
A 000
abc = 000 à D0 =1 D0

abc = 001 à D1 =1 B

abc = 010 à D2= 1 001

D1
abc = 011 à D3= 1
C
abc = 100 à D4 =1 010
D2
abc = 101 à D5 =1
abc = 110 à D6= 1 011
D3
abc = 111 à D7= 1

100
D4

101
D5

110
D6

27
111
D7
 Another Example

A B C x • Suppose you have to design a circuit system

0 0 0 1 that produces the output X based on the
0 0 1 0
three inputs: A, B, and C
0 1 0 0
• Draw the circuit diagram for this system
0 1 1 0
X = (~A~B~C)+(A~B~C)+(A~BC)+(AB~C)
1 0 0 1

1 0 1 1 X = (~A~B~C)+(A~B~C)+(A~B~C)+(A~B~C)+ (A~BC)+(AB~C)

1 1 0 1
X = (~A~B~C)+(A~B~C )+(A~BC)+(A~B~C)+(AB~C)+(A~B~C)
1 1 1 0

x =( B*C) + (A*B) + (A*C)

Please Review Boolean Algebra!

Null’s Chapter 3.2

Berger’s Chapter 3
 Karnaugh Maps
• We want to systematically derive a Boolean equation from a truth table
• The Karnaugh Map (pronounced “car know”) is a graphical method of
simplifying the “Sum of Products” (minterm) truth table
• Based upon Boolean algebra simplification (A*B) + (A*B) = B
– Why?
• Commutative Law: (A*B) + (C*B) = (B*A) + (B*C)
• First Distributive Law: B *( A + C ) = (B*A) + (B*C)
• Third Law of Complementation: A + A = 1
• Finally: A*1 = A
• Therefore
(A*B) + (A*B) = B * ( A + A ) = B * 1 = B
• http://sourceforge.net/projects/k-map/files/k-map/0.4/Kmap-04-setup.exe/download

30
 Karnaugh Maps – 2
• For each output, you have to build one k-map
• For the 3 x 8 line decoder, we need eight k-maps
• Rules for building a Karnaugh Map of a truth table
– Rule 1: # cells = # of possible combinations of input variables
• The number of cells = 2(NUMBER OF INPUT VARIABLES)
• For example,
– 3 input variables: A, B, C = 23 = 8 cells
– 4 input variables: A, B, C, D = 24 = 16 cells
– 5 input variables: A, B, C, D, E = 25 = 32 cells
– Rule 2: The horizontal and vertical axes are labeled such that only one
variable changes from complemented to un-complemented ( or vice
versa) as you go across or down
– The first and last cells in a row or in a column are considered to
be adjacent to each other
31
 Karnaugh Maps – 3
K-Map for 3 input variables
K-Map for 4 input variables

AB AB AB AB
AB AB AB AB
CD
C
CD
C
CD

CD
K-Map for 5 input variables

ABC ABC ABC ABC ABC ABC ABC ABC

Note:
DE 1- The colored lines are actually
adjacent to each other
DE 2- The corner cells are adjacent
3- The variables are organized
DE so that only one variable changes
as you go from cell to cell, including
DE the opposite ends (Gray code)
4- Diagonals are not adjacent
 Simplification using K-Maps
1. Construct one Karnaugh Map for each output variable
2. Place a “1” in every cell that has a 1 in the corresponding row of the truth table
3. Form thelargest possible loops of cells containing 1, 2, 4, 8,16, etc.,
adjacent “1” terms
4. Any cell can be involved in any number of loops, but each new loop must contain
at least one entry that is not contained in any other loop, in order to avoid a
redundant loop
– “loop within loop” is NOT ALLOWED!
5. Inspect the map for any loops whose terms are all enclosed in other loops and remove
those loops
6. Each loop represents a simplified minterm (sum of product) of the logic equation
– Simplify the loop by removing any variable that appears in its complemented
and un-complemented form

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 Design a 3 x 8 Line Decoder
3. Derive a Boolean equation for each output
a b c D0
K-Map for 3 input variables

0 0 0 1
a b a b ab a b
0 0 1 0
c 1

c 0 1 0 0

0 1 1 0
Focus only one output (D0) at a time
1 0 0 0
1. Fill out the cells which have 1 only
1 0 1 0
(others are zero)
2. Read the cell with 1: D0 = a b c 1 1 0 0
Note: ab is not equal to a b 1 1 1 0
~(ab) = (~a) + (~b)
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 Design a 3 x 8 Line Decoder
• Do it for each output
a b c D1
K-Map for 3 input variables
0 0 0 0
a b a b ab a b
0 0 1 1
c

c 1
0 1 0 0

0 1 1 0
D1 = ~a ~b c
1 0 0 0
1 0 1 0
(I will use ~ instead of )
1 1 0 0
1 1 1 0

35
 K-Map Examples
AB AB AB AB
CD 1 1 1

This K-Map has three loops. Notice that the yellow

loop is actually adjacent.
CD 1 1 1
The equation is X = (~A*~C) + (~B*~C) + (A*B*C)

CD 1

CD 1

AB AB AB AB
CD 1 1
This K-Map first appears to have two loops. The diagonal are not
adjacent,
but by first rotating the map around the vertical axis and then around
CD a
horizontal axis, we can cluster the four terms into a single 2 by 2
CD loop.

The equation is X = ~B*~D

CD 1 1

36
 K-Map Examples – 2
AB AB AB AB
CD 1 1 1 1 This K-Map can really be simplified.

X = ~C
CD 1 1 1 1

CD

CD

AB AB AB AB
CD 1 1 1 1 Here we have two loops. The blue loop wraps around the top and
bottom edges, enclosing 8 terms, and the red loop encloses one column
of 4 terms. The equation is
CD 1

X = ~D + ~A*B
CD 1

CD 1 1 1 1

37
Simplification using K-Map

A B C x
AB AB AB AB
0 0 0 1 C 1 1 1
0 0 1 0 C 1
0 1 0 0
0 1 1 0
1 0 0 1 x = B*C + A*B + A*C

1 0 1 1 Simplified equation

1 1 0 1
1 1 1 0
 Designing the Hardware
A *A B *B C *C

NOT NOT NOT

B*C

AND
x = B*C + A*B + A*C

A*B

OR
AND X

A*C

AND
 Prove Algebraically
Step 1: x = A*B*C + A*B*C + A*B*C + A*B*C //From Truth Table
Step 2: x = A*B*C + A*B*C + A*B(C + C) // First Law of Distribution
Step 3: x = A*B*C + A*B*C + A*B // Law of Complementation
Step 4: x = A*B*C + A(B*C + B) // First Law of Distribution
Step 5: x = A*B*C + A[(B+C)*(B + B)] // Second Law of Distribution
Step 6: x = A*B*C + A(B+C) // Law of Complementation
Step 7: x = A*B*C + A*B + A*C // First Law of Distribution
Step 8: x = B(A*C + A) + A*C // First Law of Distribution
Step 9: x = B[(A+A)*(C + A)] + A*C // Second Law of Distribution
Step 10:x = B(C + A) + A*C // First Law of Distribution

Step 11:x = B*C + B*A + A*C // First Law of Distribution

 Another Example
A B C D X 1. X = A*B*~C*~D + A*~B*C*~D + A*B*C*~D + ~A*~B*~C*D
+ ~A*B*~C*D + ~A*~B*C*D + ~A*B*C*D
0 0 0 0 0
2. X = A*B*~D*( ~C + C ) + A*~B*C*~D + ~A*~C*D* ( ~B+ B )
1 0 0 0 0 + ~A*C*D*( B + ~B )
0 1 0 0 0 3. X = A*B*~D + A*~B*C*~D + ~A*D*( C + ~C )
4. X = A*B*~D + A*~B*C*~D + ~A*D
1 1 0 0 1 5. X = A*~D*(B + ~B*C) + ~A*D
0 0 1 0 0 6. X = A*~D*(C + B) + ~A*D //Second law of Dist.
1 0 1 0 1
0 1 1 0 0
1 1 1 0 1
0 0 0 1 1
1 0 0 1 0 AB AB AB AB
0 1 0 1 1 1
CD
1 1 0 1 0
0 0 1 1 1 CD 1 1
1 0 1 1 0 X = ~A*D + A*B*~D + A*C*~D
CD 1 1
0 1 1 1 1
1 1 1 1 0 CD 1 1
 Revisit K-maps

• What if there is a “don’t care” condition?

• The output could be either 0 or 1, but the value

will not affect the system logic. So, we don’t
care about this output!

• Some system produces an output that we “Do

not care!”

How to design this system with K-maps? 42

K-Map with “don’t care” Condition
A B AB AB AB
CD
x

CD
1 x

CD x 1

CD
x 1

• X can be 0 or 1
• Choose so the expression can be as simple as possible.
• What’s the Boolean equation? 43
K-Map with “don’t care” Condition
A B AB AB AB
CD
1

CD
1 1

CD 1 1

CD
0 1

• X can be 0 or 1
• Choose so the expression can be as simple as possible.
• What’s the Boolean equation? 44
 Read-Only Memory (ROM)
• Memory that is implemented with combinational circuits
– Combinational circuits are often referred to as “memoryless” circuits because
their output depends only on their current input and no history of prior inputs is
retained

• Memory unit that performs only the read operation

– Binary information stored in a ROM is permanent and is created during the
fabrication process
– A given input to the ROM (address lines) always produces the same output
(data lines)
– Because the outputs are a function only of the present inputs, ROM is a
combinational circuit

45
Read-Only Memory (ROM)

11.8

Truth Table for a ROM

 A0
Memory as Logic
A1
A2 • How many memory
A3 locations can you have if
Address bits you have four input bits?
0 0 0 0 0 1
0 0 0 1 0 0
0 0 1 0 0 0
0 0 1 1 0 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 0 1 DATA BIT 1
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0 0 DATA BIT 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 0 1 0 0
1 1 1 0 0 0
1 1 1 1 1 0

47
More Examples of Combinational Circuit

48
 Simple Multiplexer (MUX)
• The MUX circuit allows one of two (or more) logical signals to be selected
 Multiplexers

A, B, C are control lines to determine:

50
which one of the eight input lines to be gated.
 Multiplexers – cont’d

(a) An eight-input multiplexer. (b) The same multiplexer wired

to compute the majority
function.
51
 Decoders

A 3-to-8 decoder circuit:

Depending on the inputs, only one of eight outputs is 1.
52
 Comparators

A simple 4-bit comparator.

53
 Arithmetic Circuits

(a) Truth table for a half- (b) Logic diagram for a

adder. half-adder.
54
 Arithmetic Circuits – cont’d

(a) Truth table for a full-adder. (b) Logic diagram for a full-
adder. 55
ALU: Arithmetic Logic Units

A 1-bit ALU 56
 From 1-bit ALU to 8-bit ALU
Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and
invert signals are not shown for simplicity.

57
 Summary
• Digital computer is a binary system
• Bit, byte, word, long are the examples of data units in a computer
• Gate is a fundamental building block of all digital systems
• Logic gates are expressed with Boolean equation
• K-maps are used to derive Boolean equations from a truth table
• Design a digital system (combinational circuit)
– Draw truth table
– Draw K-maps to derive Boolean equations
– Draw a circuit diagram based on the equations
• Decoder, Multiplexer, ALU, comparators are the examples of digital
systems

58