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MUX 2-1 Behavioral

This document describes the design and testing of a 2-to-1 multiplexer. It includes steps for modeling, defining inputs/libraries, determining the process flow, creating a test bench, and simulation. The design entity defines the multiplexer with inputs x, y, s and output m. The architecture uses an if/else statement in a process to set m to x if s=0 or y if s=1. The testbench simulates the multiplexer by changing the input values over time and checking the output z.

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61 views

MUX 2-1 Behavioral

This document describes the design and testing of a 2-to-1 multiplexer. It includes steps for modeling, defining inputs/libraries, determining the process flow, creating a test bench, and simulation. The design entity defines the multiplexer with inputs x, y, s and output m. The architecture uses an if/else statement in a process to set m to x if s=0 or y if s=1. The testbench simulates the multiplexer by changing the input values over time and checking the output z.

Uploaded by

Faza Rosyadan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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-Multiplexer 2-to-1 (Behavioral)

-Metode atau rencana pengerjaannya:

1. Tentukan modelling sesuai yang diinginkan.


2. Ketik apa yang dibutuhkan sebelum prosesnya (library,input,dll).
3. Tentukan alur (proses) sesuai dengan modelling yang sudah ditentukan.
4. Buat file test bench.
5. Setelah proses test bench sudah selesai.
6. Simulasikan.

-Design

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is

Port ( x : in STD_LOGIC;

y : in STD_LOGIC;

s : in STD_LOGIC;

m : out STD_LOGIC);

end mux;

architecture Behavioral of mux is

begin

process (x,y,m)

begin

if (s='0') then

m<=x;

elsif (s='1') then

m<=y;

end if;

end process;
end Behavioral;

-testbench

--------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 01:30:26 09/27/2019

-- Design Name:

-- Module Name: D:/Xilinx/New folder/data/Mux2/mux_band.vhd

-- Project Name: Mux2

-- Target Device:

-- Tool versions:

-- Description:

--

-- VHDL Test Bench Created by ISE for module: mux

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test. Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation

-- simulation model.
--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY mux_band IS

END mux_band;

ARCHITECTURE behavior OF mux_band IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux

PORT(

x : IN std_logic;

y : IN std_logic;

sel : IN std_logic;

z : OUT std_logic

);

END COMPONENT;

--Inputs

signal x : std_logic := '0';

signal y : std_logic := '0';

signal sel : std_logic := '0';


--Outputs

signal z : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mux PORT MAP (

x => x,

y => y,

sel => sel,

z => z

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

x <= '1';

y <= '0';

sel <= '1';

wait for 20 ns;

x <= '0';
y <= '1';

sel <= '0';

wait for 20 ns;

wait;

end process;

END;

x y s z
0 1 0 0
0 1 0 1

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