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Exp. 6: Introduction To Sequential Logic: Objectives

This document describes an experiment on sequential logic using a 4-bit up counter and 4-bit up-down counter. It includes the objectives, materials required, and procedures to design and test each counter in Verilog. For the 4-bit up counter, the student wrote code for the module and a test bench to verify it counts from 0 to 15. For the 4-bit up-down counter, the code allows it to count up or down based on a mode signal, and it was also tested with a bench. Both counters were able to reset to 0 and continue counting in the observed cycles.

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38 views

Exp. 6: Introduction To Sequential Logic: Objectives

This document describes an experiment on sequential logic using a 4-bit up counter and 4-bit up-down counter. It includes the objectives, materials required, and procedures to design and test each counter in Verilog. For the 4-bit up counter, the student wrote code for the module and a test bench to verify it counts from 0 to 15. For the 4-bit up-down counter, the code allows it to count up or down based on a mode signal, and it was also tested with a bench. Both counters were able to reset to 0 and continue counting in the observed cycles.

Uploaded by

hunny
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Student Name : Manas Sharma

Roll Number : 111801023

Course Name : Digital Circuits Lab

Experiment Title : Introduction to Sequential Logic

Exp. 6: Introduction to Sequential Logic

OBJECTIVES:
 To familiarize with up/down synchronous counters

MATERIALS REQUIRED:

Computer with Vivado PC suite and ZYBO board for Verilog implementation.

EXPERIMENTS:

1. Four bit up Counter

Theory:
A four-bit synchronous up counter is used to count from 0(0000 in binary)
and increment the count up to 15(1111 in binary). In synchronous up counter,
the clock inputs of all flip-flops are connected together and are triggered by
input pulses.

D-Register
A register is one which registers/stores/remembers data. Since a flip-flop
stores 1-bit data, it is called a 1-bit register. In any practical application, it
is required to store large amount of data. So, a practical register stores
multi-bit data.
Up-Counter

An up-counter is used to count up the values from 0(0000 in binary) to


15(1111). When reset pin is pressed, count resets to 0.

Procedure:

(i) Create a new project and create the source files for
fourBitUpCounter module.
(ii) Write the following code for fourBitUpCounter module in its
source file.
Verilog Code for fourBitUpCounter module

(iii) Develop a self-checking test bench to verify the


fourBitUpCounter module. The theory and procedure for the
same is explained below.

(iv) For creating a self-checking test-bench, add new source file


under simulation tab and write the following code and verify the
fourBitUpCounter module.

(v) Run behavioral simulation of fourBitUpCounter test-bench and


observe the console output.
Verilog Code for fourBitUpCounter testBench

Observations:

1. The behavioral simulation of the above four-bit Up Counter


was found out to be as following.
2. After f(i.e. 15) is encountered, another cycle from 0 to 15
starts.
3. When reset is set as 1, count is resettled to 0, and cycle
continues from there.

Result:

The four-bit up counter module was designed using Verilog and the output
for all possible iterations, a self-checking test bench was employed to
simulate the four-bit up counter.

2. Four bit up-down Counter

Theory:

Down Counter: A four bit down counter is a digital counter circuit, which
provides a binary countdown from binary 1111 to 0000. This circuit used
four D-type flip flops, which are positive edge triggered.

Up down counter: Bi-directional counters, also known as Up/Down


counters are capable of counting in either direction through any given
count sequence and the count forward or count backward can be
controlled using control mode.

Procedure:

(i) Create a new project and create source file for upDownCounter
module.

(ii) Write the following code in upDownCounter source file.


(iii) Develop a self-checking test bench to verify the upDown module.
The theory and procedure for the same is explained below.

(iv) For creating a self-checking test-bench, add new source file under
simulation tab and write the following code and verify the
upDownCounter module.

(v) Run the behavioral simulation for upDownCounter test-bench and


observe the console.

Verilog Code for upDownCounter module


Verilog Code for upDownCounter test-bench

Observation:

1. The behavioral simulation of the above four-bit upDownCounter was


found out to be as following.

2. We observe that when mode is set to 1, the program operates as up


counter and when the mode is 0, it operates as down counter.

3. If we reset the counter, the up counter resets to 0000.


Results:

(i) We were able to realize up-down counter using enable and reset
pins.
(ii) We realized both up and down counter in a single code, where we
can control the mode of operation of the counter.

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