What is a System on a Chip?

l Integration of a complete system, that until recently

consisted of multiple ICs, onto a single IC.

PCI SRAM

CPU
ROM
DSP

MPEG
UDL DRAM

SoC
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System Chips

l Why? l Characteristics:
♦ Complex applications
♦ Very large transistor counts
♦ Progress of technology on a single IC
allows it ♦ Mixed technology on the
♦ High performance same chip (digital, memory,
♦ Battery life analog, FPGA)
♦ Short market window ♦ Multiple clock frequences
♦ Cost sensitivity ♦ Different testing strategies
and test sets

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 SoC Target Applications

l Telecommunications, networking:
♦ ATM switches, Ethernet switches, bridges, routers

l Portable consumer products:

♦ Cellular phones, pagers, organizers

l Multimedia:
♦ Digital cameras, games, digital video

l Embedded Control
♦ Automotive, printers, smart cards, disk drives

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What are embedded cores?

l Core: Pre-designed, pre-verified complex functional blocks
also termed IP, megacells, system-level macros, virtual
components
♦ Processor Cores: ARM, MIPS, IBM PowerPC, BIST logic
♦ DSP Cores: TI, Pine, Oak
♦ Peripherals: DMA Controller, MMU
♦ Interface: PCI, USB
♦ Multimedia: JPEG Compression, MPEG decoder
♦ Networking: Ethernet Controller, ATM switches

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 Core Types
.

l Soft core
♦ A synthesizable HDL description

l Firm core
♦ A gate-level netlist that meets timing assessment.

l Hard core
♦ Includes layout and technology-dependent timing information

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Core Concerns
l Cost-of-Test and Time-to-Market concerns have lead to a
Core-Based Design approach.
l Goal is to supply easy-to-integrate cores to the system-on-
a-chip market.
l Core design and core integration are major issues.
l System-on-Board vs. System-on-Chip:
♦ Analogy: Reuse of pre-designed components on a system

♦ Difference: SoC components are only manufactured and tested

in the final system

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 Core Test Challenges?
l Distributed Design and Test Development
l Test Access to Embedded Cores
l SoC-Level Test Optimization
l On top of:
♦ Traditional Challenges: Trade-off test quality, test development
time, IC cost, test application cost
♦ New Deep-Submicron Design Challenges: by 2005 it is
predicted 100nm technology, clock > 3.5 GHz, supply 0.9-1.2 V”
♦ New Deep-Submicron Test Challenges: new defects such as
noise, crosstalk, soft errors
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Core Test Challenges?

l Distributed development: test knowledge transfer includes test
methods, protocols and pattern data, core-internal DFT. Core-based
design and test is spread over company and time

l Test Access to Embedded Cores: often # cores terminals > # IC

pins. Need to test cores as stand-alone units: provide core access
from IC pins and isolate cores when testing from other modules

l SoC-Level Test Optimization: SoC consists of simple and complex

cores, UDL, interconnect logic. SoC test should address all of this:
♦ Test quality, cost, bandwidth and area

♦ Trade-off between test vector count, application time, area and power
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 Core Test Challenges?
l There is no direct access to the core cell ports from the primary inputs
and primary outputs of the chip.

l Creation of peripheral access often involves an additional DFT effort.

♦ Core integration

l Use of multiple cores within one design with different DFT strategies

l Core Testing Strategy:

♦ Decouple embedded core level test from system chip test
♦ Identify adequate core test methodology
♦ Create mechanism for core test access
♦ Identify and implement system-chip level test methodology

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Internal Core Test

l The core integrator has little knowledge of the
adopted core’s structural content.
l Core builder won’t know which test method to adopt,
the type of fault, or desired level of fault coverage.
♦ Several versions of a core may be available, each
using different parameters or a different DFT strategy.
l The organization responsible for testing the overall
chip should define the DFT and Test strategy.
l If intellectual property (IP) is not an issue, a standard
DFT approach can be used.
♦ Nondisclosure agreements (NDA’s) may be adequate.
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 Generic Core Test Access Architecture

CUT
source TAM TAM sink
wrapper

•Test Pattern Source and Sink:

•Generates test stimuli and performs test analysis
•Test Access Mechanism (TAM):
•Transports test patterns to/from CUT
•Core Test Wrapper:
•Provides switching of core terminals to functional I/O or TAM
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Generic SoC Test Access Architecture

PCI
SRAM

CPU CUT ROM

TAM TAM
source wrapper sink

MPEG
UDL DRAM

SoC

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 Test Access Mechanism (TAM)
l There are two parameters involved with a TAM:
♦ TAM capacity (number of wires): needs to meet core’s
data rate (minimum) and it cannot be more than bandwidth of
source/sink (maximum). Trade-off between test quality, test
time, area
♦ TAM length (wire length): on/off chip source/sink. TAM
length can be shortened if it is shared with other modules or is
is shared with functional hardware

l TAM Implementations: Multiplexed Access, Reused

System Bus, Transparent, Boundary Scan

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Test Access Mechanism (TAM)

• Connect wire to all core

terminals and multiplex onto
Core A
existing IC pins

• Test mode per core controls

Core A multiplexer
N
• Common for memories and
block based ASICs
Core A

SoC
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 Test Access Mechanism (TAM)

Benefits
- Embedded core can be tested as stand alone device
- Translation from core-level to system-level is easy
- Simple silicon debug and diagnosis

Drawbacks
- Method is not scalable. If #core terminals > # IC pins
=> parallel to serial conversion => difficult at-speed testing
- Area and control circuitry grows

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Reused System Bus

l Motivation: Many SoCs have an on-chip system bus that

connects to most cores anyway. Reuse system bus as TAM
is cheap w.r.t. siicon area

Benefits
- Low area

Drawbacks
- Fixed bus does not allow trade-offs (area, quality, test time)
- Difficult to integrate scan design or BIST

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 Transparent TAM
Transparent Path: path from source
to sink with no information loss

Examples of transparency: scan

PCI chains, arithmetic functions,
SRAM embedded memories, blocks of basic
CPU CUT ROM gates AND, OR, INV, MUX
source
wrapper

MPEG
UDL DRAM
sink
SoC

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Transparent TAM

Benefits
- Low area cost for TAM in case of reuse of existing hardware

Drawbacks
- Core test access depends on other modules
- During core design, core environments are unknown. Core
user has to add TAMs in the cores.
- Translation from core-level to IC-level test might be
complicated (e.g., latencies of cores)

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 Boundary Scan Methods
l Isolation ring
♦ Boundary scan chain
♦ Internal (parallel) scan for sequential cores
s Higher test application time.

l Partial isolation ring

♦ Place some core I/O’s in a boundary scan chain.

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Boundary Scan: Isolation Ring

l Boundary scan chain for accessing Core I/O’s

l Internal scan chain.

Chip

UDL UDL

Core

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 Boundary Scan: Partial Isolation Ring
l Not all core I/O’s placed in boundary scan chain.
l Need observability (for testing UDL 1) for core inputs
omitted from boundary scan chain.
l Need controllability (for testing UDL 2) for core outputs
omitted from boundary scan chain.

Chip

UDL UDL
1 2
Core

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Core Test Wrapper

l Wrapper’s Task:

♦ Interface between core and rest of chip (TAM)

♦ Switching ability between:

s normal operation of core
s core test mode

s interconnect test mode (bypass mode)

♦ Width adaptation: serial-to-parallel at core inputs, parallel-

to-serial at core outputs

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 Core Test Wrapper
wrapper wrapper wrapper
bypass

scan chain
scan chain scan chain
scan chain

scan chain scan chain

scan chain

Core B Core B Core B

test control block test control block test control block

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Core Test Wrapper: Normal Mode

wrapper wrapper wrapper

scan chain
scan chain scan chain
scan chain

scan chain scan chain

scan chain

Core B Core B Core B

test control block test control block test control block

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 Core Test Wrapper: Test Mode
wrapper wrapper wrapper

scan chain
scan chain scan chain
scan chain

scan chain scan chain

scan chain

Core B Core B Core B

test control block test control block test control block

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Core Test Wrapper: Bypass Mode

wrapper wrapper wrapper
CUT

scan chain
scan chain scan chain
scan chain

scan chain scan chain

scan chain

Core B Core B Core B

test control block test control block test control block

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