Layout of a Inverter

Lecture 3 VDD
VDD
CMOS Fabrication Process Qp
Qp
Peter Cheung
Department of Electrical & Electronic Engineering Vi Vo vi vo
Imperial College London

Qn
Qn

GND
URL: www.ee.ic.ac.uk/pcheung/
E-mail: [email protected]

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The CMOS Process - photolithography (1) The CMOS Process - photolithography (2)

(a) Bare silicon wafer (d) Expose resist to UV light (f) Etch away oxide
through a MASK
Silicon Wafer
Silicon Wafer

(b) Grow Oxide layer

SiO2 ~ 1µm
Silicon Wafer Silicon Wafer (g) Remove remaining resist

(c) Spin on photoresist (e) Remove unexposed resist

photoresist Silicon Wafer

Silicon Wafer Silicon Wafer

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 Mask 1: N-well Diffusion Mask 2: Define Active Regions

• SiO2 is etched using Phosphorous Diffusion • Mask 2 creates the SiO2

Photoresist Photoresist
Mask 1. active regions where
the MOSFETs will be
SiO2 placed
n-well
p-substrate
p-substrate
A thick field oxide is grown using a
contruction technique called Local Oxidation
• Phosphorous is Of Silicon (LOCOS).
diffused into the
unmasked regions of n-well SiO2
silicon creating an n- p-substrate • The thick oxide regions n-well
well for the fabrication provides isolation
of p-channel devices between the MOSFETs p-substrate

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Mask 3: Polysilicon Gate Mask 4: n+ Diffusion

• A high quality thin oxide • Mask 4 is used to

Thin Oxide Arsenic Implant
is grown in the active SiO2 control a heavy arsenic
area (~100A->300A) implant and create the
n-well Photoresist
• Mask 3 is used to source and drain of the SiO2
deposit the polysilicon p-substrate n-channel devices.
gate (most critical step) • This is a self-aligned n-well
structure. p-substrate
The polysilicon layer is usually arsenic doped
(n-type). The photolithography in this step is the
most demanding since it requires the finest The polysilicon gate acts like a barrier for this
resolution to create the narrow MOS channels. implant to protect the channel region.

SiO2 SiO2
n+ n+ n+
n-well n-well
p-substrate p-substrate
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 Mask 5: p+ Diffusion Mask 6: Contact Holes

• Mask 5 is used to • A thin layer of oxide is

Boron Implant
control a heavy Boron deposited over the entire
wafer oxide
implant and create the Photoresist
source and drain of the SiO2 • Mask 6 is used to pattern
the contact holes SiO2
n-channel devices. p + n+ n+ p+ p+ n+
• This is a self-aligned n-well • Etching opens the holes.
n-well
structure. p-substrate
p-substrate
The polysilicon gate acts like a barrier for this
Etched contact holes
implant to protect the channel region.

SiO2 SiO2
p + n+ n+ p+ p+ n+ p + n+ n+ p+ p + n+
n-well n-well
p-substrate p-substrate

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Mask 7: Metalization Cross section of a CMOS Inverter

• A thin layer of aluminum

is evaporated or p + n+
SiO2
p+ p + n+
VDD
n+
sputtered onto the wafer.
n-well vi vo
• Mask 7 is used to
pattern the VDD
p-substrate
interconnection.
Qp
Aluminum Interconnection p+ n+ n+ p+ p+ n+
Vi Vo Qn Qp
n-well
Qn Source-Body
SiO2 Connection Source-Body
p+ n+ n+ p+ p+ n+
p-substrate Connection
n-well
p-substrate

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 Physical Layout of an Inverter Dimension of transistors

n-well

PMOS active region VDD L L

NMOS active region Qp

n+ diffusion W n+ Poly n+ W p+ Poly p+

p+ diffusion vi vo
Source Drain Source Drain
Poly 1 (poly-Si gate) n-well Gate
Gate
Qn
Contact Hole
GND n-channel MOSFET p-channel MOSFET
Metal 1

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Photo cross-section of a transistor Advanced metalization with polishing

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 Latch-up problem (1) Latch-up (con’t)

‹ As shown above, the p+ region of the p-transistor, the n-well and the p- substrate form a
parasitic pnp transistor T1. ‹ T1 and T2 form a thyristor circuit.
‹ The n- well, the p- substrate and the p+ source of the n-transistor forms another parasitic ‹ If Rw and/or Rs are not 0, and for some
npn transistor T2. reason (power-up, current spike etc), T1 or
‹ There exists two resistors Rw and Rs due to the resistive drop in the well area and the T2 are forced to conduct, Vdd will be
substrate area. shorted to Gnd through the small
resistances and the transistors.
‹ Once the circuit is 'fired', both transistors
will remain conducting due to the voltage
drop across Rw and Rs. The only way to
get out of this mode is to turn the power
off.
‹ This condition is known as latch-up.
‹ To avoid latch-up, substrate-taps (tied to
Gnd) and well-taps (tied to Vdd) are
inserted as frequently as possible. This
has the effect of shorting out Rw and Rs.

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