FinFET Based 3-Bit Flash ADC on 32nm

Technology
Supriya Sara Mathew¹, Lijesh L²
¹PG Scholar, Department of ECE, Musaliar College of Engineering and Technology, Pathanamthitta, Kerala
²Associate Professor, Department of ECE, Musaliar College of Engineering and Technology, Pathanamthitta, Kerala

Abstract— Power utilization is a noteworthy issue in every to Binary code encoder. Resistor ladder is utilized for
single electronic circuit. So as to accomplish the power producing different reference voltages. The incoming analog
utilization, circuit scaling is essential. In CMOS based circuits signal is compared with these generated reference voltages
scaling ought to be conceivable up to oblige extend after that it using the comparator array and the corresponding
will show short channel impacts. To overcome this thermometer code will be generated [6]. These thermometer
disadvantage FINFET has been introduced. Comparator is one codes are given to the advanced encoder which will change
of the segments above all required in simple to advanced over them to the relating binary codes.
converter. Operational Amplifiers are the real constituent of
analog and mixed-signal systems. Speed requirement for fast
applications, for instance, ADC and DAC lead to extended
enthusiasm for amplifiers with high gain and speed. FinFET is
a champion among the most reassuring progressions to
structure underneath 50nm. FinFET transistors in basic circuit
setup presents vital upgrade appeared differently in relation to
ordinary single gate CMOS structure. In this paper, we present
a FINFET based Flash ADC. The fundamental parameters
considered in the execution investigation are delay and power
utilization. LT-Spice simulation software is utilized for design
and investigation of the circuits in the above determined 32nm
scaling range.

Keywords—Flash ADC, FinFET, Comparator, Encoder

I. INTRODUCTION
Analog-to-digital converters are used to convert real
world analog signals into digital representations of those
signals. As we know that the digital signal processing can Fig.1. Block Diagram of 3-Bit Flash ADC
then efficiently extract information from the signals. ADCs
find use in communications, audio, sensors, video and many III. FINFET TECHNOLOGY
other applications [1]. High-speed, low-resolution ADCs are
used in oscilloscopes, digital high-speed wire line and Multi-gate FETs are an option in contrast to planar
wireless communications and radar. Flash and time- MOSFETs, which enhanced the drain potential screening out
of the channel because of quality of extra gates. In all multi-
interleaved ADCs architectures are typically used for high-
gate devices, the two gate FETs or tri-gate FETs are
speed applications. There are various types ADC
increasingly attractive because of littler parasitic
architecture in which first is pipeline ADC [2]. Its operating capacitances and hearty conduct against irregular dopant
speed is high but below flash with medium resolution. conduct. The Trigate FETs are having decreased fringing
Second ADC architecture is SAR ADC [3]. It is appropriate capacitances yet at the expense of complex creation process.
for low power and medium-to-high goals applications with The FinFETs are the rising gadgets in this mechanical time
moderate speed. Third ADC design is Sigma-delta ADC [4]. which are having negligible power utilization, insusceptible
It is reasonable for high goals and low speed applications. to short channel effects, littler area necessity and higher
Forth ADC architecture is Flash ADC [5]. It can work at fast speed of activity [7].
and low goals. So we can say that Flash ADC is the quickest
The FinFETs are grouped in fundamental two classes: (a)
ADC in correlation with other ADC models. The flash Independent Gate FinFET (IGF) (b) Short Gate FinFET
ADC is the best choice in high speed low resolution (SGF). IG FinFETs are having four terminals while SGF are
applications. It is highly used in high data rate links, high otherwise called three terminal FinFETs. The entryways are
speed instrumentation, radar, digital oscilloscopes and disconnected in IGF structures while the front and the back
optical communications. Since flash ADC is working in doors are shorted to one another in SGF structures as
parallel change technique, most extreme working recurrence appeared in Fig.2. SGF structures are having higher ON
in the scope of gigahertz is conceivable. Comparator design current when contrasted with IGF structure on the grounds
is also a challenge for design of Flash ADCs. that SGF structure mutually utilizes both the entryways for
electrostatic control of the channel. Be that as it may, an IGF
II. FLASH ADC structure offers the adaptability to apply distinctive signals
The General block diagram for a 3 bit Flash ADC is on the diverse gates however at the expense of bigger chip
given in below Fig.1. A Flash ADC is framed of mostly three territory.
blocks- Resistor ladder, Comparator array and Thermometer
 A. Conventional Two Stage Op-Amp
A customary two phase operational amplifier with
compensation capacitor Cc is exhibited in Fig.5. The
amplifier incorporates the course phases of voltage to current
and current to voltage converters. The primary stage
comprises of a differential amplifier that changes over the
differential information voltages to differential currents. The
differential currents are connected to the present current
Fig.2. Comparison between SGF and IGF mirror stack that recovers the differential voltage. This is
obviously only a differential voltage amplifier. The second
IV. RESISTOR LADDER stage incorporates a MOSFET regular source that changes
over the input voltage of the second stage to the current [10].
The resistor ladder is designed mainly to provide a stable This operation amp is so much utilized that is called
reference voltage to the comparators [8]. The resistor ladder conventional two phase operation amp. Capacitor CC is
network is formed by 2N resistors which generates the utilized for Miller pay to expand the phase margin.
reference voltage. The reference voltage for all comparator
is one least significant bit (LSB) less than the reference
voltage for the comparator immediately above it. The ladder
divides main reference voltage into 2N equally spaced
voltages.

Fig.5. Conventional Two-Stage CMOS Op-Amp

This operation amp is so much utilized that is called

Fig.3. Resistor Ladder for 3-bit flash ADC conventional two phase operation amp. Capacitor CC is
utilized for Miller pay to expand the phase margin.
V. COMPARATOR
Block diagram of an amplifier with a differential input B. Proposed Two Stage Op-Amp
and a single-ended output is shown in Fig.4. Here, another two-stage single-ended differential
amplifier with FinFET innovation is presented. The past
circuit executed with MOSFET is supplanted by FinFET
transistors [11]. Fig.6 demonstrates the general structure of
the amplifier utilized for planning.

Fig.4. Block diagram of two-stage Op-Amp

Two-stage amplifier is made of four principle parts. This

include a differential amplifier in the input, second gain
circuit, bias circuit and compensation circuit [9]. Given that
the circuit load is capacitive, the buffer stage isn't required in
the enhancer. Differential amplifier at the input obtains a
larger share of the total amplifier gain to improve noise
performance and offset. To have most extreme swing in the
yield, the second stage is generally utilized as a
straightforward common source. Compensation circuit is
additionally used to balance out and the inclination circuit
has the errand of giving the predisposition voltages of the Fig.6. Proposed Two-Stage FinFET Op-Amp
amplifier circuit.
 All transistors are FinFET and as appeared in the figure more inputs are 1 at a time, the input with highest priority is
the second gate of every n-FinFET transistors are associated represented in the output.
with GND and the back door of p-FinFET transistors is
associated with Vdd. Here M1, M2, M3, M4 and M5 frame
TABLE I. TRUTH TABLE OF 8:3 PRIORITY ENCODER
the main phase of amplifier. M1 and M2 is differential pair
and M3 and M4 are utilized as the load for the differential
combine transistors. M6 and M7 together assume the job of
common source and frame the second phase of amplifier. M5
assumes the job of current source to the amplifier. M8
together with Ibias assumes the job of bias circuit for the
amplifier. Cc is utilized for Miller pay in the amplifier
structure.
The amplifier open loop gain can be communicated as
the increase of two phases:
𝐴𝑣=(2∗𝑔𝑚2∗ 𝑔𝑚6)/(𝐼5∗𝐼6∗(𝛌𝟐+ 𝛌 3)∗(𝛌 6+𝛌 7)) (1)
Along these lines, the gain depends to transconductance
gm and the channel length modulation parameter λ. FinFET
compelling portability is higher than mass transistors due to
non-doping channels and subsequently builds gm. Channel
length modulation parameter (λ) in FinFET is impressively Suppose if the input lines T2, T4 and T7 are logic 1
limited because of better control of short channel impacts in simultaneously irrespective of the other inputs, only T7 will
double gate structure. Thus, the gain can be expanded by be encoded and the output will be 111. Similarly, if T3 = 1,
FinFET. the state of T2, T1 and T0 is irrelevant or don’t care and the
output is equal to 011.
VI. PRIORITY ENCODER
A priority encoder is one of the types of encoders in
which an ordering is imposed to the inputs that means
compared with the standard encoder, it includes the priority
function. However, this priority is based on the relative
magnitudes of the inputs. Hence, the input with larger
magnitude is the one that is encoded first. Priority encoders
can select the inputs with highest priority in many practical
applications. This process of selection is called arbitration.
One of the most common examples of arbitration is that,
there is numerous input devices in computer system and
several of which devices attempt to supply the data to the
computer simultaneously. In those cases, a priority encoder Fig.8. Priority Encoder using Logic Gates
enables the input device having the highest priority among
those devices trying to access the computer at the same time. B. 8:3 Priority Encoder Using MUX
MUX based encoders operate at high speed and covers
the small chip area compared to the dynamic logic encoding
technique. This encoder is implemented by grouping the
results of smaller length MUX based encoder to develop a
high bit resolution encoder to convert thermometer code into
binary output. It gives better result than previous encoders in
terms of power consumption, speed and space.

Fig.7.Block Diagram of 4:2 Priority Encoders

A. 8:3 Priority Encoder Using Logic Gates

The truth table of a thermometer – to – binary priority
encoder is shown below. This type of encoder has 8 inputs
and three outputs that generate corresponding binary code.
A priority is assigned to each input so that when two or Fig.9. Priority Encoder using MUX
C. Proposed 8:3 Priority Encoder Using TGs B. Transient Analysis of Two Stage FinFET Op-Amp
We have designed our proposed encoder using four 2:1
multiplexers. These MUXs are implemented by
transmission gates. The block diagram of the proposed
encoder is illustrated by the given Fig.10. We have designed
a 2:1 MUX using two transmission gates(TG).This design
requires less number of transistor compared to others as well
as less average power consumption. A 2:1 MUX using TG
is shown below.

C. ACAnalysis of Two Stage FinFET Op-Amp

Fig.10. Circuit of a 2:1 MUX using TG

Our proposed architecture is shown in below.

D. Power Analysis of Two Stage FinFET Op-Amp

Fig.11. Priority Encoder using TG

VII. RESULTS AND SIMULATION

A. Schematic of Two Stage FinFET Op-Amp

Fclk = 1/T = 1/0.3 sec = 3.33 Hz

Dynamic Power Dissipation = Fclk * Vdd² * CL
= 3.33 * 0.8² * 30pF = 0.6393 pW
Static Power Dissipation = 0.268 µW
E. Propagation Delay of Two Stage FinFET Op-Amp H. Propagation Delay of FinFET Transmission Gate

F. Analysis of FinFET Transmission Gate

I. Schematic of FinFET Based 3-bit Flash ADC

G. Power Dissipation of FinFET Transmission Gate

J. Transient Analysis of 3-bit Flash ADC

VIII. CONCLUSION
The requirement of low power circuits for
communication applications is increasing as a result of rapid
improvement in systems requiring system on chips (SoC)
such as wireless handheld devices like tablet PC, smart
Phones and Satellite Phones. The flash ADCs are highly
advantageous in this regards. However, the conventional
CMOS based flash ADCs are restricted by area
requirements and operation delay. The communication
bandwidths that are used currently for SoC applications
require low power ADCs with programmable reference
voltage for analog to digital conversion. The speed of a
Flash ADC depends on the speed of the comparators.
FinFET based comparators and priority encoders proved to
be of low power dissipation and propagation delay than
MOSFET based comparators and priority encoders. So in
order to use a high speed and low power flash ADC, it is
better to implement it using FinFET technology.

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