STA326

2.1 HIGH EFFICIENCY

DIGITAL AUDIO SYSTEM

1 FEATURES Figure 1. Package

■ Wide supply voltage range (10-36V)
■ 3 Power Output Configurations
– 2x30W + 1x60W, 8Ω+4Ω @ 10% THD
– 2x60W, 8Ω @ 10% THD PowerSO36 (Slug up)
– 1x120W, 4Ω @ 10% THD
■ Power SO-36 Package Table 1. Order Codes
■ 2.1 Channels of 24-Bit DDX®
Part Number Package
■ 100dB SNR and Dynamic Range
■ 32kHz to 192kHz Input Sample Rates STA326 PowerSO36 (Slug up)
■ Digital Gain/Attenuation +48dB to -80dB in STA32613TR Tape & Reel
0.5dB steps
■ Post-EQ User Programmable Mix with default
■ 4 x 22-bit User Programmable Biquads (EQ) per
2.1 Bass Management settings
Channel
■ Variable Max Power Correction for lower full-
■ I2C Control power THD
■ 2-Channel I2S Input Data Interface ■ 4 Output Routing Configurations
■ Individual Channel and Master Gain/ ■ Selectable Clock Input Ratio
Attenuation ■ 96kHz Internal Processing Sample Rate, 24 to
■ Individual Channel and Master Soft and Hard 28-bit precision
Mute ■ QXpander
■ Individual Channel Volume and EQ Bypass ■ Video Application: 576 fs input mode suporting
■ Bass/Treble Tone Control
■ Dual Independent Programmable Limiters/ 2 DESCRIPTION
Compressors The STA326 is an integrated solution of digital au-
■ Automodes™ dio processing, digital amplifier control, and DDX-
– 31 Preset EQ Curves Power Output Stage, thereby creating a high-pow-
– 15 Preset Crossover Settings er single-chip DDX® solution comprising of high-
– Auto Volume Controlled Loudness quality, high-efficiency, all digital amplification.
– 3 Preset Volume Curves The STA326 can be configured via digital control
– 2 Preset Anti-Clipping Modes to operate in several output modes providing up to
– Preset Nighttime Listening Mode 2.1 channels of power output to speakers.
– Preset TV AGC This device is capable to deliver up to 2x30W +
■ Input and Output Channel Mapping 1x60W in 2.1 mode or 2x60W in stereo mode.
■ AM Noise Reduction and PWM Frequency The IC can also be configured as a single
Shifting Modes paralelled full-bridge capable of high-current oper-
■ Soft Volume Update and Muting ation and 1x120W output.
■ Auto Zero Detect and Invalid Input Detect Also provided in the STA326 are a full assortment
Muting of digital processing features. This includes up to
■ Over Current and over-temperature protection 4 programmable 28-bit biquads (EQ) per channel,
with programmable recovery and bass/treble tone control. Automodes™ enable
■ Thermal warning indicator with programmable a time-to-market advantage by substantially re-
auto output power reduction ducing the amount of software development need-
■ Selectable De-emphasis ed for certain functions. This includes Auto

Rev. 2
May 2006 1/43
STA326

Volume loudness, preset volume curves, preset EQ settings, etc. New advanced AM radio inerference re-
duction modes.
The serial audio data input interface accepts all possible formats, including the popular I2S format.
Three channels of DDX® processing are provided. This high quality conversion from PCM audio to DDX's
patented tri-state PWM switching waveform provides over 100dB SNR and dynamic range.

Figure 2.
SDA SCL

I 2C

System Control

LRCKI OUT1A
Serial Data
Audio EQ, Mix,
Input, Quad OUT1B
BICKI Crossver, DDX ®
Channel Half-Bridge
Volume, Limiter Processing
Mapping & Power Stage OUT2A
SDI_12 Processing
Resampling
OUT2B
EAPD
System Timing

PLL TWARN FAULT

Power-Down
CLK

Figure 3. Channel Signal Flow Diagram through the Digital Core

I 2S
Input Channel EQ Crossover Volume 4X
Re-sampling Mix Filter DDX®
Mapping Processing Limiter Interp DDX
Output

2.1 EQ Processing
Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block.
In this block, upto 4 user-defined Biquads can be appplied to each of the two channels.
Pre-scaling, dc-blocking high-pass, de-emphasis, bass, and tone control filters can also be applied based
on various configuration parameter settings.
The entire EQ block can be bypassed for all channels simulatneously by setting the DSPB bit to '1'. And
the CxEQBP bits can be used to bypass the EQ functionality on a per channel basis. Figure below shows
the internal signal flow through the EQ block.

2.2 Mix Processing

The Post-EQ Mix block takes the two channel outputs from the EQ block and outputs three channels of
data. By default, Channels 1 and 2 outputs are essentially pass-through of Channels 1 and 2 inputs com-
ing from the EQ block. An additional channel is created as a result of a sum & mix of the two input chan-
nels. See Figure 30. By default, this 3rd channel of data is an equal mix of channel 1 and 2 data. Normally
this third channel will be used as the subwoofer in the 2.1 configuration. An additional filtering stage is
found after the mix block in order to implement crossover filtering. The crossover filters can be automati-
cally configured from the AutoMode Crossover (XO) bits or these filters can be manually programmed for
any type and frequency crossover.

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 STA326

2.3 Output Mode Configurations

Figure 4. Channel Signal Flow through the EQ Block

Re-sampled
Input Pre High-Pass De- Bass T reble
BQ#1 BQ#2 BQ#3 BQ#4
Scale Filter Emphasis Filter Filt er
To
Mix

4 Biquads If CxT CB = 0
If HPB = 0
User defined if AMEQ = 00 If DEMP = 1 BT C: Bass Boost /Cut
P reset EQ if AMEQ = 01 T T C: T reble Boost/Cut
Auto Loudness if AMEQ = 10

If DSPB = 0 & CxEQB = 0

Figure 5. 2-Channel (Full-bridge) Power, OCFG(1…0) = 00

Half OUT1A
Bridge

Channel 1
Half
Bridge OUT1B

Half OUT2A
Bridge
Channel 2

Half
Bridge OUT2B

Figure 6. - 2.1-Channel Power Configuration OCFG(1…0) = 01

Half Channel 1
Bridge
OUT1A

Half Channel 2
Bridge
OUT1B

Half OUT2A
Bridge
Channel 3

Half
Bridge
OUT2B

Figure 7. 1-Channel Mono-Parallel Configuration, OCFG(1…0) = 11

OUT1A
Half
Bridge

Half OUT1B
Bridge
Channel 3

Half
Bridge OUT2A

Half
Bridge OUT2B

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STA326

3 Pin Function and Specifications

Figure 8. Pin Connection (Top view)

VCCSign 36 1 N.C.
VSS 35 2 N.C.
VDD 34 3 OUT2B
GND 33 4 VCC2B
BICKI 32 5 N.C.
LRCKI 31 6 GND2B
SDI 30 7 GND2A
VDDA 29 8 VCC2A
GNDA 28 9 OUT2A
XTI 27 10 OUT1B
PLL FILTER 26 11 VCC1B
RES 25 12 GND1B
SDA 24 13 GND1A.
SCL 23 14 N.C.
RESET 22 15 VCC1A
CONFIG 21 16 OUT1A
VL 20 17 GNDCLEAN
VDD REG 19 18 GND REG

D04AU1540

Table 2. Pin Function

Pin Type Name Description
1, 2, 5, 14 N.C. Not Connected
3 O OUT2B Output half bridge 2B
4 I/O VCC2B Positive supply
6 I/O GND2B Negative Supply
7 I/O GND2A Negative Supply
8 I/O VCC2A Positive supply
9 O OUT2A Output half bridge 2A
10 O OUT1B Output half bridge 1B
11 I/O VCC1B Positive supply
12 I/O GND1B Negative Supply
13 I/O. GND1A Negative Supply
15 I/O VCC1A Positive supply
16 O OUT1A Output half bridge 1A
17 I/O GNDCLEAN Logic reference ground
18 I/O GNDREG Substrate ground
19 I/O VREG1 Internal +5V regulator voltage
20 I/O VL Digital Supply 3.3V
21 I CONFIG Configuration pin (mono parallel)
22 I RESET Reset
23 I SCL I²C Serial Clock
24 I/O SDA I²C Serial Data
25 RES Reserved This pin must be connected to GND
26 I PLL FILTER Connection to PLL filter
27 I XTI PLL Input Clock
28 I/O GNDA Analog Ground
29 I/O VDDA Analog Supply 3.3
30 I SDI_12 I²S Serial Data Channels 1 & 2
31 I/O LRCKI I²S Left/Right Clock,
32 I BICKI I²S Serial Clock
33 I/O GND Digital Ground
34 I/O VDD Digital Supply 3.3V
35 I/O VSS Internal - 5V (Relative to Vcc)
36 I/O VCCSIGN Internal signal supply

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 STA326

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit
VDD3 3.3V Digital Power Supply -0.5 to 4 V
VDDA 3.3V Analog Power Supply -0.5 to 4 V
Vi Voltage on input pins -0.5 to (VDD+0.5) V
Vo Voltage on output pins -0.5 to (VDD+0.5) V
Tstg Storage Temperature -40 to +150 °C
Tamb Ambient Operating Temperature -20 to +85 °C
Tj Operating Junction Temperature 0 to +150 °C
VCC DC Supply Voltage 40 V
VMAX Maximum voltage on pins 20 5.5 V

Table 4. Thermal Data

Symbol Parameter Min Typ Max Unit
Rthj-case Thermal resistance Junction to case (thermal pad) 2.5 °C/W
Tj-SD Thermal Shut-down Junction Temperature 150 °C
TWARN Thermal Warning Temperature 130 °C
Th-SD Thermal Shut-down Hysteresis 25 °C

Table 5. Recommended Dc Operating Conditions

Symbol Parameter Value Unit
VDD3 I/O Power Supply 3.0 to 3.6 V

4 Electrical Characteristcs
(VDD3 = 3.3V ± 0.3V; Tamb = 25°C; unless otherwise specified)

4.1 GENERAL INTERFACE ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note
Iil Low Level Input no pull-up Vi = 0V 1 µA 1
Iih High Level Input no pull-down Vi = VDD3 2 µA 1
IOZ Tristate output leakage without Vi = VDD3 2 µA 1
pullup/down
Vesd Electrostatic Protection Leakage < 1µA 2000 V 2
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin.
Note 2: Human Body Model

4.2 DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS

Symbol Parameter Test Condition Min. Typ. Max. Unit
VIL Low Level Input Voltage 0.8 V
VIH High Level Input Voltage 2.0 V
Vhyst Schmitt Trigger Hysteresis 0.4 V
Vol Low Level Output IoI = 2mA 0.15 V
Voh High Level Output Ioh = -2mA VDD -0.15 V

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STA326

4.3 POWER ELECTRICAL CHARACTERISTCS

(VL = 3.3V; Vcc = 30V; Tamb = 25°C unless otherwise specified)

Symbol Parameter Test conditions Min. Typ. Max. Unit

RdsON Power Pchannel/Nchannel Id=1A 200 270 mΩ
MOSFET RdsON
Idss Power Pchannel/Nchannel Vcc=35V 50 µA
leakage Idss
gN Power Pchannel RdsON Matching Id=1A 95 %
gP Power Nchannel RdsON Id=1A 95 %
Matching
Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 1 10 20 ns
td ON Turn-on delay time Resistive load 100 ns
td OFF Turn-off delay time Resistive load 100 ns
tr Rise time Resistive load 25 ns
tf Fall time Resistive load; as fig. 1 25 ns
VCC Supply voltage operating voltage 10 36 V
IVCC- Supply Current from Vcc in PWRDN = 0 3 mA
PWRDN PWRDN
IVCC-hiz Supply current from Vcc in Tri- Vcc=30V; Tri-state 22 mA
state
IVCC Supply current from Vcc in Input pulse width = 50% Duty; 80 mA
operation Switching Frequency = 384Khz;
(both channel switching) No LC filters;
Iout-sh Overcurrent protection threshold 4 6 A
(short circuit current limit)
VUV Undervoltage protection threshold 7 V
tpw-min Output minimum pulse width No Load 70 150 ns
Po Output Power THD = 10%
(Full-bridge mode) RL = 4Ω; VS = 17V 30 W
RL = 8Ω; VS = 32V 60 W
Po Output Power THD = 1%
(Binary half-bridge mode) RL = 4Ω; VS = 17V 25 W
RL = 8Ω; VS = 32V 46 W
Po Mono mode output power THD = 10% 60 W
RL = 4Ω; VS = 32V 120 W
THD+N Total Harmonic Distortion + Noise Po = 1 Wrms 0.07 %
Po = 40 Wrms 0.1
SNR Signal to Noise Ratio A-Weighted 99 dB
DDX® Mode
Signal to Noise Ratio, Binary Mode 92 dB
Binary Half-Bridge Mode A-Weighted
η Efficiency DDX® Mode 89 %
Binary 87 %

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 STA326

5 FUNCTIONAL DESCRIPTION
5.1 PIN DESCRIPTION

5.1.1 OUT1A, 1B, 2A & 2B (Pins 16, 10, 9 & 3)

Output Half Bridge PWM Outputs 1A, 1B, 2A & 2B provide the inputs signals to the speaker devices.
Half Bridge Power Outputs 1A, 1B, 2A & 2B deliver audio power to the speaker loads. Using DDX stereo
configuration mode, outputs 1A (+) and 1B (-) comprise Channel 1 and outputs 2A (+) and 2B (-) comprise
Channel 2. Using binary 2.1 channel configuration mode, output 1A is for Channel 1 and output 1B is for
Channel 2 and outputs 2A (+) and 2B (-) comprise Channel 3. Using DDX mono-high power output mode
(Config connected to VREG1), outputs 1A and 1B are shorted (+) and outputs 2A and 2B are shorted (-)
comprising a single BTL output with twice output current capability for Channel 3.

5.1.2 RESET (Pin 22)

Driving RESET low sets all outputs low and returns all register settings to their defaults. The reset is asyn-
chronous to the internal clock.

5.1.3 I2C Signals (Pins 23 & 24)

The SDA (I2C Data) and SCL (I2C Clock) pins operate per the I2C specification. See Section 4.0. Fast-
mode (400kB/sec) I2C communication is supported.

5.1.4 GNDA & VDDA: Phase Locked Loop Power (Pins 28-29)
The phase locked loop power is applied here. This +3.3V supply must be well bypassed and filtered for
noise immunity. The audio performance of the device is critically dependent upon the PLL circuit.

5.1.5 CLK: Master Clock In (Pin 27)

This is the master clock in required for the operation of the digital core. The master clock must be an in-
teger multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256*Fs) for
a 48kHz sample rate, which is the default at power-up. Care must be taken to avoid over-clocking the
device i.e provide the device with the nominally required system clock; otherwise, the device may not prop-
erly operate or be able to communicate.
5.1.6 FILTER_PLL: PLL Filter (Pin 26)
PLL Filter connects to external filter components for PLL loop compensation. Refer to the schematic dia-
gram for the recommended circuit.

5.1.7 BICKI: Bit Clock In (Pin 32)

The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64*Fs, for ex-
ample using I2S serial format.

5.1.8 SDI_12: Serial Data Input (Pin 30)

PCM audio information enters the device here. Six format choices are available including I2S, left- or right-
justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

5.1.9 CONFIG: Configuration input (Pin 21)

The configuration input pin is normally connected to ground. Using the mono-high power BTL configura-
tion requires the CONFIG input pin be shorted to VREG1.

5.1.10 LRCKI: Left/Right Clock In (Pin 31)

The Left/Right clock input is for data word framing. The clock frequency will be at the input sample rate Fs.
5.2 AUDIO PERFORMANCE
TBD

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STA326

6 STA326 I2C BUS SPECIFICATION

The STA326 supports the I2C protocol. This protocol defines any device that sends data on to the bus as
a transmitter and any device that reads the data as a receiver. The device that controls the data transfer
is known as the master and the other as the slave. The master always starts the transfer and provides
the serial clock for synchronization. The STA326 is always a slave device in all of its communications.

6.1 COMMUNICATION PROTOCOL

6.1.1 Data Transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock
is high is used to identify a START or STOP condition.

6.1.2 Start Condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
stable in the high state. A START condition must precede any command for data transfer.

6.1.3 Stop Condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A STOP condition terminates communication between STA326 and the bus master.

6.1.4 Data Input

During the data input the STA326 samples the SDA signal on the rising edge of clock SCL. For correct
device operation the SDA signal must be stable during the rising edge of the clock and the data can
change only when the SCL line is low.

6.2 DEVICE ADDRESSING

To start communication between the master and the STA326, the master must initiate with a start condi-
tion. Following this, the master sends 8-bits (MSB first) onto the SDA line corresponding to the device
select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In
the STA326 the I2C interface uses a device addresse of 0x34 or 0011010x.
The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write
mode. After a START condition the STA326 identifies the device address on the bus. If a match is found,
it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device
identification byte is the internal space address.

6.3 WRITE OPERATION

Following the START condition the master sends a device select code with the RW bit set to 0. The
STA326 acknowledges this and then the master writes the internal address byte.
After receiving the internal byte address the STA326 again responds with an acknowledgement.

6.3.1 Byte Write

In the byte write mode the master sends one data byte. This is acknowledged by the STA326. The master
then terminates the transfer by generating a STOP condition.

6.3.2 Multi-byte Write

The multi-byte write modes can start from any internal address. Sequential data byte writes will be written
to sequential addresses within the STA326.
The master generating a STOP condition terminates the transfer.

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 STA326

6.4 READ OPERATION

6.4.1 Current Address Byte Read

Following the START condition the master sends a device select code with the RW bit set to 1. The
STA326 acknowledges this and then responds by sending one byte of data. The master then terminates
the transfer by generating a STOP condition.

6.4.1.1Current Address Multi-byte Read

The multi-byte read modes can start from any internal address. Sequential data bytes will be read from
sequential addresses within the STA326. The master acknowledges each data byte read and then gen-
erates a STOP condition terminating the transfer.

6.4.2 Random Address Byte Read

Following the START condition the master sends a device select code with the RW bit set to 0. The
STA326 acknowledges this and then the master writes the internal address byte. After receiving, the in-
ternal byte address the STA326 again responds with an acknowledgement. The master then initiates an-
other START condition and sends the device select code with the RW bit set to 1. The STA326
acknowledges this and then responds by sending one byte of data. The master then terminates the trans-
fer by generating a STOP condition.

6.4.2.1Random Address Multi-byte Read

The multi-byte read modes could start from any internal address. Sequential data bytes will be read from
sequential addresses within the STA326. The master acknowledges each data byte read and then gen-
erates a STOP condition terminating the transfer.

6.5 Write Mode Sequence

Figure 9. I2C Write Procedure

ACK ACK ACK
BYTE DEV-ADDR SUB-ADDR DATA IN
WRITE

START RW STOP

ACK ACK ACK ACK

MULTIBYTE DEV-ADDR SUB-ADDR DATA IN DATA IN
WRITE

START RW STOP

6.6 Read Mode Sequence

Figure 10. I2C Read Procedure

ACK NO ACK

CURRENT
ADDRESS DEV-ADDR DATA
READ

START RW STOP
ACK ACK ACK NO ACK
RANDOM
ADDRESS DEV-ADDR SUB-ADDR DEV-ADDR DATA
READ

START RW START RW STOP

RW= ACK ACK ACK NO ACK
HIGH
SEQUENTIAL
CURRENT DEV-ADDR DATA DATA DATA
READ
START STOP
ACK ACK ACK ACK ACK NO ACK
SEQUENTIAL
RANDOM DEV-ADDR SUB-ADDR DEV-ADDR DATA DATA DATA
READ
START RW START RW STOP

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STA326

7 REGISTER DESCRIPTION

Table 6. Register Summary

Address Name D7 D6 D5 D4 D3 D2 D1 D0
0x00 ConfA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0
0x01 ConfB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0
0x02 ConfC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
0x03 ConfD MME ZDE DRC BQL PSL DSPB DEMP HPB
0x04 ConfE SVE ZCE DCCV PWMS AME RES MPC MPCV
0x05 ConfF EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0
0x06 Mmute MMute
0x07 Mvol MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0
0x08 C1Vol C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0
0x09 C2Vol C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0
0x0A C3Vol C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0
0x0B Auto1 AMPS AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0
0x0C Auto2 XO3 XO2 XO1 XO1 AMAM2 AMAM1 AMAM0 AMAME
0x0D Auto3 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0
0x0E C1Cfg C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB
0x1F C2Cfg C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB
0x10 C3Cfg C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP
0x11 Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0
0x12 L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0
0x13 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0
0x14 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0
0x15 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0
0x16 Cfaddr2 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0
0x17 B1cf1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16
0x18 B1cf2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8
0x19 B1cf3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0
0x1A B2cf1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16
0x1B B2cf2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8
0x1C B2cf3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0
0x1D A1cf1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16
0x1E A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8
0x1F A1cf3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0
0x20 A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16
0x21 A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8
0x22 A2cf3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0
0x23 B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16
0x24 B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8
0x25 B0cf3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0
0x26 Cfud WA W1
0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
0x29 RES RES RES RES RES RES RES RES RES
0x2A RES RES RES RES RES RES RES RES RES
0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8
0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0
0x2D Status PLLUL FAULT TWARN

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 STA326

7.1 CONFIGURATION REGISTER A (Address 00h)

D7 D6 D5 D4 D3 D2 D1 D0
FDRB TWAB TFRB IR1 IR0 MCS2 MCS1 MCS0
0 1 1 0 0 0 1 1

7.1.1 Master Clock Select

BIT R/W RST NAME DESCRIPTION
0 R/W 1 MCS0 Master Clock Select: Selects the ratio between the input
I2S sample frequency and the input clock.
1 R/W 1 MCS1
2 R/W 0 MCS2
The STA326 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, and 96kHz. Therefore the
internal clock will be:
■ 32.768Mhz for 32kHz
■ 45.1584Mhz for 44.1khz, 88.2kHz, and 176.4kHz
■ 49.152Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs).
The correlation between the input clock and the input sample rate is determined by the status of the MCSx
bits and the IR (Input Rate) register bits. The MCSx bits determine the PLL factor generating the internal
clock and the IR bit determines the oversampling ratio used internally.

Table 7. IR and MCS Settings for Input Sample Rate and Clock Rate
Input Sample Rate
IR MCS(2..0)
fs (kHz)
000 001 010 011 100 101
32, 44.1, 48 00 768fs 512fs 384fs 256fs 128fs 576fs
88.2, 96 01 384fs 256fs 192fs 128fs 64fs x
176.4, 192 1X 384fs 256fs 192fs 128fs 64fs x

7.1.2 Interpolation Ratio Select

BIT R/W RST NAME DESCRIPTION
4...3 R/W 00 IR (1...0) Interpolation Ratio Select: Selects internal interpolation ratio based
on input I2S sample frequency
The STA326 has variable interpolation (re-sampling) settings such that internal processing and DDX out-
put rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-
through) or provides a down-sample by a factor of 2.
The IR bits determine the re-sampling ratio of this interpolation.

Table 8. IR bit settings as a function of Input Sample Rate

Input Sample Rate Fs (kHz) IR (1,0) 1st Stage Interpolation Ratio

32 00 2 times over-sampling
44.1 00 2 times over-sampling
48 00 2 times over-sampling
88.2 01 Pass-Through
96 01 Pass-Through
176.4 10 Down-sampling by 2
192 10 Down-sampling by 2

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STA326

7.1.3 Thermal Warning Recovery Bypass

BIT R/W RST NAME DESCRIPTION

5 R/W 1 TWRB Thermal-Warning Recovery Bypass:

0 – Thermal warning Recovery enabled
1 – Thermal warning Recovery disabled

If the Thermal Warning Adjustment is enabled (TWAB=0), then the Thermal Warning Recovery will deter-
mine if the adjustment is removed when Thermal Warning is negative. If TWRB=0 and TWAB=0, then
when a thermal warning disappears the gain adjustment determined by the Thermal Warning Post-
Scale(default = -3dB) will be removed and the gain will be added back to the system. If TWRB=1 and
TWAB=0, then when a thermal warning disappears the Thermal Warning Post-Scale gain adjustment will
remain until TWRB is changed to zero or the device is reset.

7.1.4 Thermal Warning Adjustment Bypass

BIT R/W RST NAME DESCRIPTION

6 R/W 1 TWAB Thermal-Warning Adjustment Bypass:

0 – Thermal warning adjustment enabled
1 – Thermal warning adjustment disabled

The on-chip STA326 Power Output block provides feedback to the digital controller using inputs to the
Power Control block. The TWARN input is used to indicate a thermal warning condition. When TWARN
is asserted (set to 0) for a period greater than 400ms, the power control block will force an adjustment to
the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning
volume adjustment is applied, whether the gain is reapplied when TWARN is de-asserted is dependent
on the TWRB bit.

7.1.5 Fault Detect Recovery Bypass

BIT R/W RST NAME DESCRIPTION

7 R/W 0 FDRB Fault Detector Recovery Bypass:

0 – Fault Detector Recovery enabled
1 – Fault Detector Recovery disabled

The DDX Power block provides feedback to the digital controller using inputs to the Power Control block.
The FAULT input is used to signal a fault condition (either over-current or thermal). When FAULT is as-
serted (set to 0), the power control block will attempt automatic recovery from the fault by asserting the tri-
state signal in a sequence to reset the fault and retest the fault status. The sequence period can range
from 0.1 milliseconds to 1 second as defined by the Fault-Detect Recovery Constant register (FDRC reg-
isters 29-2Ah). This sequence is repeated for as long as the fault condition exists. This feature is enabled
by default but can be disabled by setting the FDRB control bit to 1. If Fault-Detect Recovery is disabled
(not recommended), an output stage FAULT will cause a shut-down condition, which must be reset either
by toggling the external reset pin or via a VCC power cycle to the IC.

7.2 CONFIGURATION REGISTER B (Address 01h)

D7 D6 D5 D4 D3 D2 D1 D0
C1IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0
1 0 0 0 0 0 0 0

7.2.1 Serial Audio Input Interface Format

BIT R/W RST NAME DESCRIPTION
3…0 R/W 0000 SAI (3...0) Serial Audio Input Interface Format: Determines the interface format of
the input serial digital audio interface.

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7.3 Serial Data Interface

The STA326 serial audio input was designed to interface with standard digital audio components and to
accept a number of serial data formats. The STA326 always acts as a slave when receiving audio input
from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/
right clock LRCKI (pin 33), serial clock BICKI (pin 31), and serial data 1 & 2 SDI12 (pin 32).
The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (Configuration Reg-
ister B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB-
First. Available formats are shown in Figure 11 and the tables that follow.

Figure 11. General Serial Input and Output Formats

2
IS

LRCLK Left Right

SCLK

SDATA MSB LSB MSB LSB MSB

Left Justified

LRCLK Left Right

SCLK

SDATA MSB LSB MSB LSB MSB

Right Justified

LRCLK Left Right

SCLK

SDATA MSB LSB MSB LSB MSB

For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First.
Table 10 below lists the serial audio input formats supported by STA326 as related to BICKI = 32/48/64fs,
where the sampling rate fs = 32/44.1/48/88.2/96/176.4/192 kHz.

Table 9. First Bit Selection Table

SAIFB Format

0 MSB-First

1 LSB-First

Note: Serial input and output formats are specified distinctly.

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Table 10. Supported Serial Audio Input Formats

BICKI SAI (3...0) SAIFB Interface Format

32fs 1100 X I2S 15bit Data
1110 X Left/Right-Justified 16bit Data
48fs 0100 X I2S 23bit Data
0100 X I2S 20bit Data
1000 X I2S 18bit Data
0100 0 MSB First I2S 16bit Data
1100 1 LSB First I2S 16bit Data
0001 X Left-Justified 24bit Data
0101 X Left-Justified 20bit Data
1001 X Left-Justified 18bit Data
1101 X Left-Justified 16bit Data
0010 X Right-Justified 24bit Data
0110 X Right-Justified 20bit Data
1010 X Right-Justified 18bit Data
1110 X Right-Justified 16bit Data
64fs 0000 X I2S 24bit Data
0100 X I2S 20bit Data
1000 X I2S 18bit Data
0000 0 MSB First I2S 16bit Data
1100 1 LSB First I2S 16bit Data
0001 X Left-Justified 24bit Data
0101 X Left-Justified 20bit Data
1001 X Left-Justified 18bit Data
1101 X Left-Justified 16bit Data
0010 X Right-Justified 24bit Data
0110 X Right-Justified 20bit Data
1010 X Right-Justified 18bit Data
1110 X Right-Justified 16bit Data

Table 11. Serial Input Data Timing characteristics (Fs = 32 to 192kHz)

BICKI FREQUENCY (slave mode) 12.5MHz max.

BICKI pulse width low (T0) (slave mode) 40 ns min.
BICKI pulse width high (T1) (slave mode) 40 ns min.
BICKI active to LRCKI edge delay (T2) 20 ns min.
BICKI active to LRCKI edge delay (T3) 20 ns min.
SDI valid to BICKI active setup (T4) 20 ns min.
BICKI active to SDI hold time (T5) 20 ns min.

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Figure 12.

T2 T3

LRCKI
T1
T0
BICKI
T4
SDI

T5

7.3.1 Delay Serial Clock Enable

BIT R/W RST NAME DESCRIPTION

5 R/W 0 DSCKE Delay Serial Clock Enable:

0 – No serial clock delay
1 – Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices

7.3.2 Channel Input Mapping

BIT R/W RST NAME DESCRIPTION

6 R/W 0 C1IM 0 – Processing channel 1 receives Left I2S Input

1 – Processing channel 1 receives Right I2S Input

7 R/W 1 C2IM 0 – Processing channel 2 receives Left I2S Input

1 – Processing channel 2 receives Right I2S Input

Each channel received via I2S can be mapped to any internal processing channel via the Channel Input
Mapping registers. This allows for flexibility in processing. The default settings of these registers map
each I2S input channel to its corresponding processing channel.

7.4 CONFIGURATION REGISTER C (Address 02h)

D7 D6 D5 D4 D3 D2 D1 D0

CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

1 0 0 0 0 1 0

7.4.1 DDX® Power Output Mode

BIT R/W RST NAME DESCRIPTION

1...0 R/W 10 OM (1...0) DDX Power Output Mode:

Selects configuration of DDX® output.

The DDX® Power Output Mode selects how the DDX® output timing is configured. Different power de-
vices can use different output modes. The DDX-2060/2100/2160 recommended use is OM = 10. When
OM=11 the CSZ bits determine the size of the DDX® compensating pulse.

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Table 12. DDX® Output Modes

OM (1,0) Output Stage – Mode

00 Not Used
01 Not Used
10 STA500/505/508
11 Variable Compensation

7.4.2 DDX® Variable Compensating Pulse Size

The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact
Apogee applications for support when deciding this function.

7.4.3 DDX® Variable Compensating Pulse Size

BIT R/W RST NAME DESCRIPTION
6...2 R/W 10000 CSZ (4...0) Compensating Pulse Size Select
The DDX® variable compensating pulse size is not recommended to be used except in special circum-
stances . Contact STMicroelectronics applications for support when deciding this function.

Table 13. DDX® Compensating Pulse

CSZ (4…0) Compensating Pulse Size

00000 0 Clock period Compensating Pulse Size
00001 1 Clock period Compensating Pulse Size
… …
10000 16 Clock period Compensating Pulse Size
… …
11111 31 Clock period Compensating Pulse Size

7.5 Configuration Register D (Address 03h)

D7 D6 D5 D4 D3 D2 D1 D0

MME ZDE DRC BQL PSL DSPB DEMP HPB

0 0 0 0 0 0 0 0

7.5.1 High-Pass Filter Bypass

BIT R/W RST NAME DESCRIPTION

0 R/W 0 HPB High-Pass Filter Bypass Bit.

0 – AC Coupling High Pass Filter Enabled
1 – AC Coupling High Pass Filter Disabled

The STA326 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of
this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker
damage.

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 STA326

7.5.2 De-Emphasis
BIT R/W RST NAME DESCRIPTION

1 R/W 0 DEMP De-emphasis:

0 – No De-emphasis
1 – De-emphasis

By setting this bit to HIGH, or one (1), de-emphasis will implemented on all channels. DSPB (DSP Bypass,
Bit D2, CFA) bit must be set to 0 for De-emphasis to function.

7.5.3 DSP Bypass

BIT R/W RST NAME DESCRIPTION
2 R/W 0 DSPB DSP Bypass Bit:
0 – Normal Operation
1 – Bypass of EQ and Mixing Functionality

Setting the DSPB bit bypasses all the EQ and Mixing functionality of the STA326 Core.

7.5.4 Post-Scale Link

BIT R/W RST NAME DESCRIPTION
3 R/W 0 PSL Post-Scale Link:
0 – Each Channel uses individual Post-Scale value
1 – Each Channel uses Channel 1 Post-Scale value
Post-Scale functionality is an attenuation placed after the volume control and directly before the conver-
sion to PWM. Post-Scale can also be used to limit the maximum modulation index and therefore the peak
current. A setting of 1 in the PSL register will result in the use of the value stored in Channel 1 post-scale
for all three internal channels.

7.5.5 Biquad Coefficient Link

BIT R/W RST NAME DESCRIPTION
4 R/W 0 BQL Biquad Link:
0 – Each Channel uses coefficient values
1 – Each Channel uses Channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM
space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.

7.5.6 Dynamic Range Compression/Anti-Clipping Bit

BIT R/W RST NAME DESCRIPTION
5 R/W 0 DRC Dynamic Range Compression/Anti-Clipping
0 – Limiters act in Anti-Clipping Mode
1 – Limiters act in Dynamic Range Compression Mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in
anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dy-
namic range compression mode the limiter threshold values vary with the volume settings allowing a night-
time listening mode that provides a reduction in the dynamic range regardless of the volume level.

7.5.7 Zero-Detect Mute Enable

BIT R/W RST NAME DESCRIPTION
6 R/W 1 ZDE Zero-Detect Mute Enable: Setting of 1 enables the automatic zero-
detect mute
Setting the ZDE bit enables the zero-detect automatic mute. When ZDE=1, the zero-detect circuit looks

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at the input data to each processing channel after the channel-mapping block. If any channel receives
2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this func-
tion is enabled.

7.5.8 Sub-Mix Enable

BIT R/W RST NAME DESCRIPTION
7 R/W 0 SME Sub-Mix Enable:
0 - Sub Mix into Left/Right Disabled
1 - Sub Mix into Left/Right Enabled
Setting the SME bit enables a scaled-mix of the content from the Sub channel (i.e. channel 3) into the main
Left & Right channels (i.e. channels 1 & 2). The Sub-Mix resides post-volume & gain compression pro-
cessing.

7.6 CONFIGURATION REGISTER E (ADDRESS 04H)

D7 D6 D5 D4 D3 D2 D1 D0

SVE ZCE RES PWMS AME RES MPC MPCV

0 0 0 0 0 0 0 0

7.6.1 Max Power Correction Variable

BIT R/W RST NAME DESCRIPTION

0 R/W 0 MPCV Max Power Correction Variable:

0 – Use Standard MPC Coefficient
1 – Use MPCC bits for MPC Coefficient

By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the
MPCC registers (address 0x27-0x28) it becomes possible to adjust the THD at maximum unclipped power
to a lower value for a particular application.

7.6.2 Max Power Correction

BIT R/W RST NAME DESCRIPTION

7 R/W 1 MPC Max Power Correction:

0 – MPC Disabled
1 – MPC Enabled

Setting the MPC bit corrects the STA500/505/508 power device at high power. This mode will lower the
THD+N of a full STA500 DDX® system at maximum power output and slightly below.

7.6.3 Noise Shaper BandWidth Selection

BIT R/W RST NAME DESCRIPTION

2 R/W 0 NSBW Noise Shaper BandWidth Select

0 – 4th Order Noise Shaper
1 – 3rd Order Noise Shaper

DDXi-2101 provides the ability to the user to select two types of noise-shaper order. This facilitates the
user to essentially make the appropriate bandwidth selection for their design thereby achieving optimal
noise performance. It is recommended to set NSBW = '1' when the device is initialized via I2C.

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 STA326

7.6.4 AM Mode Enable

BIT R/W RST NAME DESCRIPTION

3 R/W 0 AME AM Mode Enable:

0 – Normal DDX® operation.
1 – AM reduction mode DDX® operation.

The STA326 features a DDX® processing mode that minimizes the amount of noise generated in the fre-
quency range of AM radio. This mode is intended for use when DDX® is operating in a device with an
active AM tuner. The SNR of the DDX® processing is reduced to ~83dB in this mode, which is still greater
than the SNR of AM radio.

7.6.5 PWM Speed Mode

BIT R/W RST NAME DESCRIPTION

4 R/W 0 PWMS PWM Speed Selection: Normal or Odd

Table 14. PWM Output Speed Selections

PWMS (1...0) PWM Output Speed

0 Normal Speed (384kHz) All Channels

1 Odd Speed (341.3kHz) All Channels

7.6.6 Zero-Crossing Volume Enable

BIT R/W RST NAME DESCRIPTION

6 R/W 1 ZCE Zero-Crossing Volume Enable:

1 – Volume adjustments will only occur at digital zero-crossings
0 – Volume adjustments will occur immediately

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-cross-
ings no clicks will be audible.

7.6.7 Soft Volume Update Enable

BIT R/W RST NAME DESCRIPTION
7 R/W 1 SVE Soft Volume Enable:
1 – Volume adjustments will use soft volume
0 – Volume adjustments will occur immediately
The STA326 includes a soft volume algorithm that will step through the intermediate volume values at a
predetermined rate when a volume change occurs. By setting SVE=0 this can be bypassed and volume
changes will jump from old to new value directly. This feature is only available if individual channel volume
bypass bit is set to ‘0’.

7.7 Configuration Register F (Address 05h)

D7 D6 D5 D4 D3 D2 D1 D0
EAPD PWDN ECLE RES BCLE IDE OCFG1 OCFG0
0 1 0 1 1 1 1 0

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7.7.1 Output Configuration Selection

BIT R/W RST NAME DESCRIPTION
1…0 R/W 00 OCFG Output Configuration Selection
(1…0) 00 – 2-channel (Full-bridge) Power, 1-channel DDX is default

Table 15. Output Configuration Selections

OCFG (1...0) Output Power Configuration
00 2 Channel (Full-Bridge) Power, 1 Channel DDX:
1A/1B ◊ 1A/1B
2A/2B ◊ 2A/2B
01 2(Half-Bridge).1(Full-Bridge) On-Board Power:
1A ◊ 1A Binary
2A ◊ 1B Binary
3A/3B ◊ 2A/2B Binary
10 Reserved
11 1 Channel Mono-Parallel:
3A ◊ 1A/1B
3B ◊ 2A/2B

7.7.2 Invalid Input Detect Mute Enable

BIT R/W RST NAME DESCRIPTION
2 R/W 1 IDE Invalid Input Detect Auto-Mute Enable:
0 – Disabled
1 – Enabled
Setting the IDE bit enables this function, which looks at the input I2S data and clocking and will automati-
cally mute all outputs if the signals are perceived as invalid.

7.7.3 Binary Clock Loss Detection Enable

BIT R/W RST NAME DESCRIPTION
5 R/W 1 BCLE Binary Output Mode Clock Loss Detection Enable
0 – Disabled
1 – Enabled
Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when
input clocking is lost.

7.7.4 Auto-EAPD on Clock Loss Enable

BIT R/W RST NAME DESCRIPTION

7 R/W 0 ECLE Auto EAPD on Clock Loss

0 – Disabled
1 – Enabled

When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.

7.7.5 Powerdown
BIT R/W RST NAME DESCRIPTION

6 R/W 1 PWDN Software Power Down:

0 – Powerdown mode operation (auto soft-mute enabled)
1 – Normal Operation

If the powerdown bit is set low, a powerdown sequence is initiated resulting in a soft mute of all the chan-
nels and PWM outputs are damped.

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7.7.6 External Amplifier Power Down

BIT R/W RST NAME DESCRIPTION

7 R/W 0 EAPD External Amplifier Power Down:

0 – External Power Stage Power Down Active
1 – Normal Operation

EAPD is used to actively power down a connected DDX® Power device. This register has to be written to
1 at start-up to enable the DDX® power device for normal operation.

7.8 VOLUME CONTROL

7.8.1 Master Controls

7.8.1.1Master Mute Register (Address 06h)
D7 D6 D5 D4 D3 D2 D1 D0

MMUTE

7.8.1.2Master Volume Register (Address 07h)

D7 D6 D5 D4 D3 D2 D1 D0

MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

1 1 1 1 1 1 1 1

Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.

7.8.2 Channel Controls

7.8.2.1Channel 1 Volume (Address 08h)

D7 D6 D5 D4 D3 D2 D1 D0
C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0
0 1 1 0 0 0 0 0

7.8.2.2Channel 2 Volume (Address 09h)

D7 D6 D5 D4 D3 D2 D1 D0

C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

0 1 1 0 0 0 0 0

7.8.2.3Channel 3 Volume (Address 0Ah)

D7 D6 D5 D4 D3 D2 D1 D0

C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

0 1 1 0 0 0 0 0

7.8.3 Volume Description

The volume structure of the STA326 consists of individual volume registers for each of the three channels
and a master volume register, and individual channel volume trim registers. The channel volume settings

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are normally used to set the maximum allowable digital gain and to hard-set gain differences between cer-
tain channels. These values are normally set at the initialization of the IC and not changed. The individual
channel volumes are adjustable in 0.5dB steps from +48dB to -80 dB. The master volume control is nor-
mally mapped to the master volume of the system. The values of these two settings are summed to find
the actual gain/volume value for any given channel.
When set to 1, the Master Mute will mute all channels, whereas the individual channel mutes (CxM) will
mute only that channel. Both the Master Mute and the Channel Mutes provide a “soft mute” with the vol-
ume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing
rate (~96kHz). A “hard mute” can be obtained by commanding a value of all 1’s (FFh) to any channel vol-
ume register or the master volume register. When volume offsets are provided via the master volume reg-
ister any channel whose total volume is less than –100dB will be muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per chan-
nel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates will
occur immediately.
The STA326 also features a soft-volume update function that will ramp the volume between intermediate
values when the value is updated, when SVE = 1 (configuration register E). This feature can be disabled
by setting SVE = 0.
Each channel also contains an individual channel volume bypass. If a particular channel has volume by-
passed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects
the volume setting, the master volume setting will not affect that channel. Also, master soft-mute will not
affect the channel if CxVBP = 1.
Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel

Table 16. Master Volume Offset as a function of MV (7..0).

MV (7..0) Volume Offset from Channel Value
00000000 (00h) 0dB
00000001 (01h) -0.5dB
00000010 (02h) -1dB
… …
01001100 (4Ch) -38dB
… …
11111110 (FEh) -127dB
11111111 (FFh) Hard Master Mute

Table 17. Channel Volume as a function of CxV (7..0)

CxV (7..0) Volume

00000000 (00h) +48dB
00000001 (01h) +47.5dB
00000010 (02h) +47dB
… …
01100001 (5Fh) +0.5dB
01100000 (60h) 0dB
01011111 (61h) -0.5dB
… …
11111110 (FEh) -79.5 dB
11111111 (FFh) Hard Channel Mute

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 STA326

7.9 AUTOMODE REGISTERS

7.9.1 Register – AutoModes EQ, Volume, GC (Address 0Bh)

D7 D6 D5 D4 D3 D2 D1 D0

AMPS AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0

1 0 0 0 0 0 0

Table 18. AutoMode EQ

AMEQ (1,0) Mode (Biquad 1-4)

00 User Programmable

01 Preset EQ – PEQ bits

10 Auto Volume Controlled Loudness Curve

11 Not used

By setting AMEQ to any setting other than 00 enables AutoMode EQ. When set, biquads 1-4 are not user
programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used
the pre-scale value for channels 1-2 becomes hard-set to –18dB.

Table 19. AutoMode Volume

AMV (1,0) Mode (MVOL)

00 MVOL 0.5dB 256 Steps (Standard)

01 MVOL Auto Curve 30 Steps

10 MVOL Auto Curve 40 Steps

11 MVOL Auto Curve 50 Steps

Table 20. AutoMode Gain Compression/Limiters

AMGC (1...0) Mode
00 User Programmable GC
01 AC No Clipping
10 AC Limited Clipping (10%)
11 DRC Nighttime Listening Mode

7.9.2 AMPS – AutoMode Auto Prescale

BIT R/W RST NAME DESCRIPTION
0 R/W 0 AMPS AutoMode Pre-Scale
0 – -18dB used for Pre-scale when AMEQ /= 00
1 – User Defined Pre-scale when AMEQ /= 00

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7.9.3 Register – AutoMode AM/Pre-Scale/Bass Management Scale (Address 0Ch)

D7 D6 D5 D4 D3 D2 D1 D0
XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME
0 0 0 0 0 0 0 0

7.9.3.1AutoMode AM Switching Enable

BIT R/W RST NAME DESCRIPTION
0 R/W 0 AMAME AutoMode AM Enable
0 – Switching Frequency Determined by PWMS Setting
1 – Switching Frequency Determined by AMAM Settings
3…1 R/W 000 AMAM (2…0) AM Switching Frequency Setting
Default: 000

Table 21. AutoMode AM Switching Frequency Selection

AMAM (2..0) 48kHz/96kHz Input Fs 44.1kHz/88.2kHz Input Fs

000 0.535MHz – 0.720MHz 0.535MHz – 0.670Mhz
001 0.721MHz – 0.900MHz 0.671MHz – 0.800MHz
010 0.901MHz – 1.100MHz 0.801MHz – 1.000MHz
011 1.101MHz – 1.300MHz 1.001MHz – 1.180MHz
100 1.301MHz – 1.480MHz 1.181MHz – 1.340Mhz
101 1.481MHz – 1.600MHz 1.341MHz – 1.500MHz
110 1.601MHz – 1.700MHz 1.501MHz – 1.700MHz
When DDX® is used concurrently with an AM radio tuner, it is advisable to use the AMAM bits to automat-
ically adjust the output PWM switching rate dependent upon the specific radio frequency that the tuner is
receiving. The values used in AMAM are also dependent upon the sample rate determined by the ADC
used.

7.9.3.2AutoMode Crossover Setting

BIT R/W RST NAME DESCRIPTION

7…4 R/W 0 XO (3…0) AutoMode Crossover Frequency Selection

000 – User Defined Crossover coefficients are used
Otherwise – Preset coefficients for the crossover setting desired

The XO bits are used to either select one of the 15 preset crossover frequency settings or enable the user
to implement custom crossover filters. The preset crossover settings signify the crossover frequency se-
lected for the 2nd order low pass and 1st order high pass filters used on the processing channels. If a dif-
ferent crossover frequency, other than those available, is desired, then the user needs to set XO = 000
and design custom high-pass and low-pass filters. These filters should then be written to the device coef-
ficient RAM using the I2C communication. Please refer to section 8.6.
Table 22. Crossover Frequency Selection
XO (2..0) Bass Management - Crossover Frequency
0000 User
0001 80 Hz
0010 100 Hz
0011 120 Hz
0100 140 Hz
0101 160 Hz
0110 180 Hz
0111 200 Hz

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 STA326

Table 22. Crossover Frequency Selection (continued)

XO (2..0) Bass Management - Crossover Frequency
1000 220 Hz
1001 240 Hz
1010 260 Hz
1011 280 Hz
1100 300 Hz
1101 320 Hz
1110 340 Hz
1111 360 Hz
7.9.4 Register - Preset EQ Settings (Address 0Dh)
D7 D6 D5 D4 D3 D2 D1 D0
PEQ4 PEQ3 PEQ2 PEQ1 PEQ0
0 0 0 0 0

Table 23. Preset EQ Selection

PEQ (3..0) Setting
00000 Flat
00001 Rock
00010 Soft Rock
00011 Jazz
00100 Classical
00101 Dance
00110 Pop
00111 Soft
01000 Hard
01001 Party
01010 Vocal
01011 Hip-Hop
01100 Dialog
01101 Bass-Boost #1
01110 Bass-Boost #2
01111 Bass-Boost #3
10000 Loudness 1 (least boost)
10001 Loudness 2
10010 Loudness 3
10011 Loudness 4
10100 Loudness 5
10101 Loudness 6
10110 Loudness 7
10111 Loudness 8
11000 Loudness 9
11001 Loudness 10
11010 Loudness 11
11011 Loudness 12
11100 Loudness 13
11101 Loudness 14
11110 Loudness 15
11111 Loudness 16 (most boost)

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7.10 Channel Configuration Registers

7.10.1 Channel 1 Configuration (Address 0Eh)

D7 D6 D5 D4 D3 D2 D1 D0

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

0 0 0 0 0 0 0 0

7.10.2 Channel 2 Configuration (Address 0Fh)

D7 D6 D5 D4 D3 D2 D1 D0

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

0 0 0 0 0 0 0 0

7.10.3 Channel 3 Configuration (Address 10h)

D7 D6 D5 D4 D3 D2 D1 D0

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP

0 0 0 0 0 0

EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the
prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in
any combination) are bypassed for that channel.
CxEQBP:
– 0 Perform EQ on Channel X – normal operation
– 1 Bypass EQ on Channel X
Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given
channel the two filters that tone control utilizes are bypassed.
CxTCB:
– 0 Perform Tone Control on Channel x – (default operation)
– 1 Bypass Tone Control on Channel x
Each channel can be configured to output either the patented DDX PWM data or standart binary PWM
encoded data. By setting the CxBO bit to ‘1’, each channel can be individually controlled to be in binary
operation mode.
Also, there is the capability to map each channel independently onto any of the two limiters available within
the STA326 or even not map it to any limiter at all (default mode).

Table 24. Channel Limiter Mapping Selection

CxLS (1,0) Channel Limiter Mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

Each PWM Output Channel can receive data from any channel output of the volume block. Which channel
a particular PWM output receives is dependent upon that channel’s CxOM register bits.

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 STA326

Table 25. Channel PWM Output Mapping

CxOM (1...0) PWM Output From

00 Channel 1

01 Channel 2

10 Channel 3

11 Not used

7.11 Tone Control (Address 11h)

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

0 1 1 1 0 1 1 1

Table 26. Tone Control Boost/Cut Selection

BTC (3...0)/TTC (3...0) Boost/Cut

0000 -12dB

0001 -12dB

… …

0111 -4dB

0110 -2dB

0111 0dB

1000 +2dB

1001 +4dB

… …

1101 +12dB

1110 +12dB

1111 +12dB

7.12 DYNAMICS CONTROL

7.12.1 Limiter 1 Attack/Release Threshold (Address 12h)

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0 1 1 0 1 0 1 0

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7.12.2 Limiter 1 Attack/Release Threshold (Address 13h)

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0 1 1 0 1 0 0 1

7.12.3 Limiter 2 Attack/Release Rate (Address 14h)

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0 1 1 0 1 0 1 0

7.12.4 Limiter 2 Attack/Release Threshold (Address 15h)

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

0 1 1 0 1 0 0 1

7.12.5 Dynamics Control Description

The STA326 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce
the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively
reduce the dynamic range for a better listening environment (such as a night-time listening mode, which
is often needed for DVDs.) The two modes are selected via the DRC bit in Configuration Register D, bit
5 address 0x03. Each channel can be mapped to Limiter1, Limiter2, or not mapped.
If a channel is not mapped, that channel will clip normally when 0 dB FS is exceeded. Each limiter will
look at the present value of each channel that is mapped to it, select the maximum absolute value of all
these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the
mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers. When the Attack Thesehold has been
exceeded, the limiter, when active, will automatically start reducing the gain. The rate at which the gain
is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for
that limiter. The gain reduction occurs on a peak-detect algorithm.
The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The
output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to
the release threshold, determined by the Release Threshold register.
When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent
upon the Release Rate register. The gain can never be increased past its set value and therefore the
release will only occur if the limiter has already reduced the gain. The release threshold value can be used
to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynam-
ic range to virtually zero and cause program material to sound “lifeless”.
In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack thresh-
old is set relative to the maximum volume setting of the channels mapped to that limiter and the release
threshold is set relative to the maximum volume setting plus the attack threshold.

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 STA326

Figure 13. - Basic Limiter and Volume Flow Diagram

Limiter RMS

Gain/Volume

Input Output
Gain Attenuation Saturation

Table 27. Limiter Attack Rate Selection Table 28. Limiter Release Rate Selection

LxA (3...0) Attack Rate dB/ms LxR (3...0) Release Rate dB/ms

0000 3.1584 Fast 0000 0.5116 Fast

0001 2.7072 0001 0.1370

0010 2.2560 0010 0.0744

0011 1.8048 0011 0.0499

0100 1.3536 0100 0.0360

0101 0.9024 0101 0.0299

0110 0.4512 0110 0.0264

0111 0.2256 0111 0.0208

1000 0.1504 1000 0.0198

1001 0.1123 1001 0.0172

1010 0.0902 1010 0.0147

1011 0.0752 1011 0.0137

1100 0.0645 1100 0.0134

1101 0.0564 1101 0.0117

1110 0.0501 1110 0.0110

1111 0.0451 Slow 1111 0.0104 Slow

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7.12.6 Anti-Clipping Mode 7.12.7 Dynamic Range Compression Mode

Table 29. Limiter Attack Table 31. Limiter Attack Threshold Selection
Threshold Selection (AC-Mode) (DRC-Mode).

LxAT (3...0) AC (dB relative to FS) LxAT (3...0) DRC (dB relative to Volume)
0000 -12 0000 -31
0001 -10 0001 -29
0010 -8 0010 -27

0011 -6 0011 -25

0100 -4 0100 -23

0101 -2 0101 -21

0110 0 0110 -19

0111 -17
0111 +2
1000 -16
1000 +3
1001 -15
1001 +4
1010 -14
1010 +5
1011 -13
1011 +6
1100 -12
1100 +7
1101 -10
1101 +8
1110 -7
1110 +9
1111 -4
1111 +10

Table 32. Limiter Release Threshold Selection

Table 30. Limiter Release (DRC-Mode).(
Threshold Selection (AC-Mode).
DRC (db relative to Volume
LxRT (3...0)
LxRT (3...0) AC (dB relative to FS) + LxAT)
0000 -∞ 0000 -∞
0001 -29dB 0001 -38dB
0010 -20dB 0010 -36dB
0011 -16dB 0011 -33dB
0100 -14dB 0100 -31dB
0101 -12dB 0101 -30dB
0110 -10dB 0110 -28dB
0111 -8dB 0111 -26dB
1000 -7dB 1000 -24dB
1001 -6dB 1001 -22dB
1010 -5dB 1010 -20dB
1011 -4dB 1011 -18dB
1100 -3dB 1100 -15dB
1101 -2dB 1101 -12dB
1110 -1dB 1110 -9dB
1111 -0dB 1111 -6dB

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 STA326

8 USER PROGRAMMABLE PROCESSING

8.1 EQ - BIQUAD EQUATION

The biquads use the equation that follows. This is diagrammed in Figure 14 below.
Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2]
= b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2]
where Y[n] represents the output and X[n] represents the input. Multipliers are 28-bit signed fractional
multipliers, with coefficient values in the range of 800000h (-1) to 7FFFFFh (0.9999998808).
Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner:
– CxHy0 = b1/2
– CxHy1 = b2
– CxHy2 = -a1/2
– CxHy3 = -a2
– CxHy4 = b0/2
The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in
the fourth biquad for channel 3

Figure 14. - Biquad Filter

b0 /2 2 +
-1
Z Z -1

b1 /2 2 + 2 -a1 /2

Z -1 Z -1

b2 + -a2

8.2 PRE-SCALE
The Pre-Scale block which precedes the first biquad is used for attenuation when filters are designed that
boost frequencies above 0dBFS. This is a single 28-bit signed multiplier, with 800000h = -1 and 7FFFFFh
= 0.9999998808. By default, all pre-scale factors are set to 7FFFFFh.

8.3 POST-SCALE
The STA326 provides one additional multiplication after the last interpolation stage and before the distor-
tion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this
multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All chan-
nels can use the same settings as channel 1 by setting the post-scale link bit.

8.4 MIX/BASS MANAGEMENT

The STA326 provides a post-EQ mixing block per channel. Each channel has 2 mixing coefficients, which
are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block.
These coefficients are accessible via the User Controlled Coefficient RAM described below. The mix co-
efficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (-
8388608) are used used to provide three channels of output from two channels of filtered input.

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Table 33. Mix/Bass Management Block Diagram

Channel #1
from EQ C1MX1

High-Pass Channel#1
+ XO to GC/Vol
Channel #2 Filter
from EQ
C1MX2

C2MX1

High-Pass Channel#2
+ XO to GC/Vol
Filter

C2MX2

C3MX1

Low-Pass
+ XO Channel#3
Filter to GC/Vol

C3MX2

User-defined Mix Coefficients Crossover Frequency determined

by XO setting.
User-defined when XO = 000

After a mix is achieved, STA326 also provides the capability to implement crossver filters on all channels
corresponding to 2.1 bass management solution. Channels 1-2 use a 1st order high-pass filter and chan-
nel 3 uses a 2nd order low-pass filter corresponding to the setting of the XO bits of I2C register 0Ch. If XO
= 000, user specified crossover filters are used.
By default these coefficients correspond to pass-through. However, the user can write these coefficients
in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd
order crossover filters. This output is then passed on to the Volume/Limiter block.

8.5 Calculating 24-Bit Signed Fractional Numbers from a dB Value

The pre-scale, mixing, and post-scale functions of the STA326 use 24-bit signed fractional multipliers to
attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to
+1. It is possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the
equations below.
– Non-Inverting Phase Numbers 0 to +1 :
– Coefficient = Round(8388607 * 10^(dB/20))
– Inverting Phase Numbers 0 to -1 :
– Coefficient = 16777216 - Round(8388607 * 10^(dB/20))
As can be seen by the preceding equations, the value for positive phase 0dB is 0x7FFFFF and the value
for negative phase 0dB is 0x800000.

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8.6 USER DEFINED COEFFICIENT RAM

8.6.1 Coefficient Address Register 1 (Address 16h)

D7 D6 D5 D4 D3 D2 D1 D0
CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0
0 0 0 0 0 0 0 0

8.6.2 Coefficient b1Data Register Bits 23...16 (Address 17h)

D7 D6 D5 D4 D3 D2 D1 D0
C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16
0 0 0 0 0 0 0 0

8.6.3 Coefficient b1Data Register Bits 15...8 (Address 18h)

D7 D6 D5 D4 D3 D2 D1 D0
C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8
0 0 0 0 0 0 0 0

8.6.4 Coefficient b1Data Register Bits 7...0 (Address 19h)

D7 D6 D5 D4 D3 D2 D1 D0
C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0
0 0 0 0 0 0 0 0

8.6.5 Coefficient b2 Data Register Bits 23...16 (Address 1Ah)

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

0 0 0 0 0 0 0 0

8.6.6 Coefficient b2 Data Register Bits 15...8 (Address 1Bh)

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

0 0 0 0 0 0 0 0

8.6.7 Coefficient b2 Data Register Bits 7...0 (Address 1Ch)

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

0 0 0 0 0 0 0 0

8.6.8 Coefficient a1 Data Register Bits 23...16 (Address 1Dh)

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

0 0 0 0 0 0 0 0

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STA326

8.6.9 1.1.9Coefficient a1 Data Register Bits 15...8 (Address 1Eh)

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

0 0 0 0 0 0 0 0

8.6.10 Coefficient a1 Data Register Bits 7...0 (Address 1Fh)

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

0 0 0 0 0 0 0 0

8.6.11 Coefficient a2 Data Register Bits 23...16 (Address 20h)

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

0 0 0 0 0 0 0 0

8.6.12 Coefficient a2 Data Register Bits 15...8 (Address 21h)

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

0 0 0 0 0 0 0 0

8.6.13 Coefficient a2 Data Register Bits 7...0 (Address 22h)

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

0 0 0 0 0 0 0 0

8.6.14 Coefficient b0 Data Register Bits 23...16 (Address 23h)

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0 0 0 0 0 0 0 0

8.6.15 Coefficient b0 Data Register Bits 15...8 (Address 24h)

D7 D6 D5 D4 D3 D2 D1 D0
C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8
0 0 0 0 0 0 0 0

8.6.16 Coefficient b0 Data Register Bits 7...0 (Address 25h)

D7 D6 D5 D4 D3 D2 D1 D0
C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0
0 0 0 0 0 0 0 0

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 STA326

8.6.17 Coefficient Write Control Register (Address 26h)

D7 D6 D5 D4 D3 D2 D1 D0

RA R1 WA W1

0 0 0 0

Coefficients for EQ, Mix and Scaling are handled internally in the STA326 via RAM. Access to this RAM
is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this func-
tion. First register contains the coefficient base address, five sets of three registers store the values of the
24-bit coefficients to be written or that were read, and one contains bits used to control the read or write
of the coefficient (s) to RAM. The following are instructions for reading and writing coefficients.

8.7 Reading a coefficient from RAM

■ write 8-bits of address to I2C register 16h
■ write ‘1’ to bit R1 (D2) of I2C register 26h
■ read top 8-bits of coefficient in I2C address 17h
■ read middle 8-bits of coefficient in I2C address 18h
■ read bottom 8-bits of coefficient in I2C address 19h

8.8 Reading a set of coefficients from RAM

■ write 8-bits of address to I2C register 16h
■ write ‘1’ to bit RA (D3) of I2C register 26h
■ read top 8-bits of coefficient in I2C address 17h
■ read middle 8-bits of coefficient in I2C address 18h
■ read bottom 8-bits of coefficient in I2C address 19h
■ read top 8-bits of coefficient b2 in I2C address 1Ah
■ read middle 8-bits of coefficient b2 in I2C address 1Bh
■ read bottom 8-bits of coefficient b2 in I2C address 1Ch
■ read top 8-bits of coefficient a1 in I2C address 1Dh
■ read middle 8-bits of coefficient a1 in I2C address 1Eh
■ read bottom 8-bits of coefficient a1 in I2C address 1Fh
■ read top 8-bits of coefficient a2 in I2C address 20h
■ read middle 8-bits of coefficient a2 in I2C address 21h
■ read bottom 8-bits of coefficient a2 in I2C address 22h
■ read top 8-bits of coefficient b0 in I2C address 23h
■ read middle 8-bits of coefficient b0 in I2C address 24h
■ read bottom 8-bits of coefficient b0 in I2C address 25h

8.9 Writing a single coefficient to RAM

■ write 8-bits of address to I2C register 16h
■ write top 8-bits of coefficient in I2C address 17h
■ write middle 8-bits of coefficient in I2C address 18h
■ write bottom 8-bits of coefficient in I2C address 19h
■ write 1 to W1 bit in I2C address 26h

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8.10 Writing a set of coefficients to RAM

■ write 8-bits of starting address to I2C register 16h
■ write top 8-bits of coefficient b1 in I2C address 17h
■ write middle 8-bits of coefficient b1 in I2C address 18h
■ write bottom 8-bits of coefficient b1 in I2C address 19h
■ write top 8-bits of coefficient b2 in I2C address 1Ah
■ write middle 8-bits of coefficient b2 in I2C address 1Bh
■ write bottom 8-bits of coefficient b2 in I2C address 1Ch
■ write top 8-bits of coefficient a1 in I2C address 1Dh
■ write middle 8-bits of coefficient a1 in I2C address 1Eh
■ write bottom 8-bits of coefficient a1 in I2C address 1Fh
■ write top 8-bits of coefficient a2 in I2C address 20h
■ write middle 8-bits of coefficient a2 in I2C address 21h
■ write bottom 8-bits of coefficient a2 in I2C address 22h
■ write top 8-bits of coefficient b0 in I2C address 23h
■ write middle 8-bits of coefficient b0 in I2C address 24h
■ write bottom 8-bits of coefficient b0 in I2C address 25h
■ write 1 to WA bit in I2C address 26h
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients
corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects.
When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (e.g.
0, 5, 10, 15, …, 45 decimal), and the STA326 will generate the RAM addresses as offsets from this base
value to write the complete set of coefficient data.

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 STA326

Table 34. RAM Block for Biquads, Mixing, and Scaling

Index (Decimal) Index (Hex) Coefficient Default

0 00h Channel 1 – Biquad 1 C1H10 (b1/2) 000000h
1 01h C1H11 (b2) 000000h
2 02h C1H12 (a1/2) 000000h
3 03h C1H13 (a2) 000000h
4 04h C1H14 (b0/2) 400000h
5 05h Channel 1 – Biquad 2 C1H20 000000h
… … … … …
19 13h Channel 1 – Biquad 4 C1H44 400000h
20 14h Channel 2 – Biquad 1 C2H10 000000h
21 15h C2H11 000000h
… … … … …
39 27h Channel 2 – Biquad 4 C2H44 400000h
40 28h High-Pass 2ndOrder Filter C12H0 (b1/2) 000000h
41 29h For XO = 000 C12H1 (b2) 000000h
42 2Ah C12H2 (a1/2) 000000h
43 2Bh C12H3 (a2) 000000h
44 2Ch C12H4 (b0/2) 400000h
45 2Dh Low-Pass 2nd Order Filter C12L0 (b1/2) 000000h
46 2Eh For XO = 000 C12L1 (b2) 000000h
47 2Fh C12L2 (a1/2) 000000h
48 30h C12L3 (a2) 000000h
49 31h C12L4 (b0/2) 400000h
50 32h Channel 1 – Pre-Scale C1PreS 7FFFFFh
51 33h Channel 2 – Pre-Scale C2PreS 7FFFFFh
52 34h Channel 1 – Post-Scale C1PstS 7FFFFFh
53 35h Channel 2 – Post-Scale C2PstS 7FFFFFh
54 36h Channel 3 – Post-Scale C3PstS 7FFFFFh
55 37h Thermal Warning – Post Scale TWPstS 5A9DF7h
56 38h Channel 1 – Mix 1 C1MX1 7FFFFFh
57 39h Channel 1 – Mix 2 C1MX2 000000h
58 3Ah Channel 2 – Mix 1 C2MX1 000000h
59 3Bh Channel 2 – Mix 2 C2MX2 7FFFFFh
60 3Ch Channel 3 – Mix 1 C3MX1 400000h
61 3Dh Channel 3 – Mix 2 C3MX2 400000h
62 3Eh UNUSED
63 3Fh UNUSED

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8.11 Variable Max Power Correction (Address 27h-28h):

MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place
of the default coefficient when MPCV = 1.

Table 35.

D7 D6 D5 D4 D3 D2 D1 D0

MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

0 0 1 0 1 1 0 1

MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

1 1 0 0 0 0 0 0

8.12 Fault Detect Recovery (Address 2Bh-2Ch):

FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE
output will be immediately asserted low and held low for the time period specified by this constant. A con-
stant value of 0001h in this register is ~.083ms. The default value of 000C specifies ~.1mSec.

Table 36.

D7 D6 D5 D4 D3 D2 D1 D0

FRDC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

0 0 0 0 1 1 0 0

Figure 15.

OUTY
Vcc

(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc

(1/4)Vcc
+Vcc

t
Duty cycle = 50% DTr DTf
M58
OUTY R 8Ω
INY

M57 +
-
V67 =
vdc = Vcc/2
gnd
D02AU1448

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 STA326

9 SCHEMATIC DIAGRAMS

Table 37. Component Selection Table 1

Load Inductor Capacitor

4Ω 10uH 1.0uF

6Ω 15uH 470nF

8Ω 22uH 470nF

Table 38. Component Selection Table 2

Load Inductor Capacitor

4Ω 22uH 680nF

6Ω 33uH 470nF

8Ω 47uH 390nF

Figure 16. Schematic Diagram for 2(Half-bridge).1(Full-bridge)-channel On-board Power.

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STA326

Figure 17. Schematic Diagram for 2-channel (Full-bridge) Power.

Figure 18. Schematic Diagram for 1-channel Mono-Parallel Power..

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 STA326

Figure 19. PowerSO36 Slug Up Mechanical Data & Package Dimensions

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.25 3.43 0.128 0.135 MECHANICAL DATA
A2 3.1 3.2 0.122 0.126
A4 0.8 1 0.031 0.039
A5 0.2 0.008
a1 0.030 -0.040 0.0011 -0.0015
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0.039
E 13.9 14.5 0.547 0.57
E1 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
E4 2.9 3.2 0.114 1.259
e 0.65 0.026
e3 11.05 0.435
G 0 0.075 0 0.003
H 15.5 15.9 0.61 0.625
h 1.1 0.043
L 0.8 1.1 0.031 0.043
N 10˚ 10˚
s 8˚ 8˚ PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.

7183931 D

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STA326

Table 39. Revision History

Date Revision Description of Changes

July 2005 1 First Issue

May 2006 2 Changed from preliminary data to maturity.

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 STA326

Please Read Carefully:

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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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