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Experiment No.: 1: Aim of The Experiment

The document describes an experiment to design a 4-bit ALU using VHDL that can perform operations like addition, subtraction, AND, NAND, XOR, XNOR, OR, and pass. The objectives are to model the ALU in VHDL, simulate it, synthesize and implement it on a PLD, and verify the results. The document provides background on what an ALU is and its basic components before describing the steps to write the VHDL code, simulate it, synthesize for a PLD, program the PLD, test it, and observe the results.

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Niranjan Tawade
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64 views

Experiment No.: 1: Aim of The Experiment

The document describes an experiment to design a 4-bit ALU using VHDL that can perform operations like addition, subtraction, AND, NAND, XOR, XNOR, OR, and pass. The objectives are to model the ALU in VHDL, simulate it, synthesize and implement it on a PLD, and verify the results. The document provides background on what an ALU is and its basic components before describing the steps to write the VHDL code, simulate it, synthesize for a PLD, program the PLD, test it, and observe the results.

Uploaded by

Niranjan Tawade
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment No.

: 1
Aim of the experiment:
To write VHDL code for 4 bit ALU to perform following operations: add, subtract, AND,
NAND, XOR, XNOR, OR, & ALU pass and simulate, synthesis and implement on PLD

Objectives:
1. Model 4-bit ALU in VHDL
2. Simulation using proper inputs
3. Synthesis and implementation of ALU in PLD
4. Verify the result on PLD

Theory:
An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and bitwise
logical operations on integer binary numbers. It is a fundamental building block of the central
processing unit (CPU) found in many computers. Powerful and complex ALUs are often used in
modern, high performance CPUs, FPUs and graphics processing units (GPUs).

The inputs to an ALU are the data to be operated on (called operands) and a code (select
line) indicating the operation to be performed. The ALU's output is the result of the performed
operation.

A basic ALU has four parallel data buses consisting of two input operands (A and B),
select line and a result output (Y) as shown in figure 1. Each data bus is a group of signals that
conveys one binary integer number. Typically, the A, B and Y bus widths (the number of signals
comprising each bus) are identical and match the native word size of the encapsulating CPU.

The select input is a parallel bus that conveys to the ALU an operation selection code,
which is an enumerated value that specifies the desired arithmetic or logic operation to be
performed by the ALU, as shown in table 1.

The select size (its bus width) is related to the number of different operations the ALU
can perform; for example, a three-bit select line can perform eight different ALU operations.
Figure 1 : ALU Top Module

Table 1 : ALU operations

Select Line ALU Operation to be performed

000 Addition of Inputs A and B

001 Substation

010 Logical AND

011 Logical NAND

100 Logical XOR

101 Logical XNOR

110 Logical OR

111 ALU Pass A


Apparatus:

1. PC with CAD tool for coding VHDL language


2. Appropriate PLD with data and power connectors
3. PLD user manual for pin configuration

Procedure:

1. Write the VHDL code for 4-bit ALU RAM.


2. Check the Syntax error.
3. Write Test bench and simulate the design
4. Write the UCF for the selected PLD
5. Synthesize, implement the module
6. Program the targeted PLD
7. Apply the input and observe the output

VHDL Code:

RTL Schematic:

UCF:

Test bench:

Waveforms:

Observations:

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Conclusion:

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