FAULT DETECTION

AND CORRECTION

STLD CASE STUDY

NAME : KHUSHBOO
ROLL NO. : 02051202818
BRANCH : ECE(EVENING)
Introduction
With the advances in science and technology, modern devices are becoming more and more
complex every day. As the device complexity increases, testing becomes even more complex. To
decrease the test cost, the time required to test a device needs to be decreased. So, we simply need to
devise a test set that is small in size.
All manufactured VLSI chips are tested for defects. But it is not possible to generate or apply
vectors to test all possible defects in a chip. So defects are modeled as faults to ease the test
generation process. Among the various existing fault models, the single stuck-at fault model is
widely accepted because of its closeness to actual defects and the algorithmic possibilities it offers
for generating test vectors.

Types of Circuit
Types of digital circuits under study are simple two stage combinational circuits. The practical
digital circuits, which are composed of AND, OR, NOT, NAND and NOR gates are alone chosen
for evaluating the performance of the methods in survey. Furthermore, the methods derived for
obtaining tests for this class of circuits are general enough to be applied to circuits consisting of
gates other than these five types, such as the XOR gate, with minor modifications. It is assumed that
the response delays of all the gate elements are the same.

Types of Fault

The faults considered in this study are assumed to be fixed or permanent or non transient faults,
which means that without having them fixed or repaired, the fault will be permanently there. Most
of the faults occurring in currently used circuits, such as resistor-transistor logic circuits (RTL),
diode-transistor logic circuits(DTL), and transistor-transistor logic circuits (TTL), are those which
cause a wire to be stuck-at-zero(s-a-0) or stuck-at-one(s-a-1). Restricting our consideration to just a
class of faults is technically justified, since most circuit failures exhibit symptomatically identical
effects. This class of faults occur in circuits with discrete components as well as integrated circuits.
A multiple fault is defined as the simultaneous occurrence of any possible combination of s-a-0 and
s-a-1 faults.
There are some faults in a circuit which are undetectable. A fault of a combinational circuit
is said to be detectable if there exists a test by which we can judge whether or not the circuit has
such a fault; otherwise, we call the fault undetectable. A combinational circuit is said to be
irredundant if any logic fault that occurred at any part of the circuit will cause a change in the
switching function that the fault-free circuit realizes. All s-a-0 and s-a-1 faults in a circuit are
detectable if and only if the circuit is irredundant if and only if the function that the circuit realizes
is a minimized function. Two faults are said to be indistinguishable if the truth tables of the output
functions of the circuits with these two faults are completely identical.

Fault Detection & Test Minimization Methods

Minimizing test sets is simply termed as test set compaction. Most commonly used method is
fault table method.
A. Fixed Scheduled Test Minimization Method
If x1, x2,…..,xn are the input variables to a single output
circuit whose fault-free (correct) output is z = z(x1,…..xn).
f1,f2,…..fi are the erroneous outputs, each corresponding to
one of the possible faults f1,f2,….fi. Table I shows fault table

F with output combinations for possible input combinations[14] of the chosen circuit. Each
corresponding faulty and fault-free outputs are compared using Exclusive-OR operation results
zf1,zf2…zfi single bit erroneous outputs shows in fault detection table Table II. The complete test set
for any fi is the set of input combinations xj =(x1j,x2j ……xnj)
such that

z(xj) zfi(xj) =
1 (1)
for all 1 i  l, 1 j
 2n
TABLE I. FAULT TABLE

Test X
1
X
2 .. X
n Z f
1
f
2 … f
i

No
1 0 0 .. 0 0 1 0 … 0
2 0 0 1 1 1 0 … 1
. . . .. . . . . … .
. . . . . . . .
. . . . . . . .
2n 1 1 .. 1 0 0 0 … 1

TABLE II. FAULT DETECTION TABLE

Test X1 X2 .. Xn Z Zf1 Zf2 … Zfi
No
1 0 0 .. 0 0 1 0 … 0
2 0 0 1 1 0 1 … 0
. . . .. . . . . … .
. . . . . . . .
. . . . . . . .
2n 1 1 .. 1 0 0 0 … 1
In Fixed Scheduled Test Minimization(FSTM) method , the above two tables are generated for the
given combinational circuit They are fault table and fault detection table. In fault table 2n test vectors
are generated, where n is the number of inputs present in the circuit. Instead of testing 2 n test vectors,
essential test set is found using a new method named as FSTM method. It removes redundancy in test
set by grouping test numbers, detecting the same fault. Test numbers detecting single faults alone are
also collected as essential test numbers.

B. Heuristic Method
In Heuristic Test minimization method, fault table alone is created. A diagnosing tree is created by
dissecting the fault diagnostic matrix into two sub matrices based on essential test number. The test
number is added to essential test set. Column numbers in these two matrices are added to the root
node of the tree as right and left siblings. Left subtree contains fault-free output column numbers
from the matrix(0s) and right subtree contains faulty output column numbers from the matrix(1s).
The process is repeated until both left and right children results in a single column number in them.
Essential test set is found after removing redundant test numbers in nodes.
C. Path Sensitizing Method
 In this method fault detection test may be found by examining the paths of transmission from
the location of an assumed fault to one of its primary outputs. The path-sensitizing method is very
attractive from the point of view of not requiring the construction of the fault table and is useful for
the fault detection of tree like circuits. But for general non-tree like circuits, the process of
exhausting all possible single paths, then all possible pair of paths, then all possible groups of three
paths and so on, involves quite a lot of searching and computation, even when done by a computer.
When fan-out exists, there occurs the additional problem of sensitizing a set of paths which in fact
contain all connections. It would be desirable if such tests could be found by direct inspection of the
circuit. Unfortunately no such direct technique has been discovered.

D. Equivalent-Normal-Form Method
The Equivalent Normal Form (ENF) of a circuit is obtained by expressing the output of each
gate as a sum-of-products expression of its inputs and preserving the identity of each gate by a
suitable subscript. Each subscripted input variable in a ENF is called literal. An appearance of a
literal in a term is also called a literal. An equivalent normal form corresponds to a two-level AND-
OR circuit. In the AND-OR circuit each literal corresponds to a circuit input and to a unique path
from that input to the circuit output. On the other hand, in the equivalent normal form two variables
may have different subscripts because they are associated with two different paths, although they
correspond to the same input in the original multilevel circuit.
Path sensitizing method and Equivalent-normal-form method are both based on the concept of
path sensitizing. ENF method has several advantages over Path sensitizing method. The ENF method
is an analytical method that provides a vehicle for systematically finding the most desirable tests,
those which each detect many faults in the circuit. Single paths that are not sensitizable are usually
easily seen from the ENF.

E. Two- Level- Circuit Fault Detection

The previous methods of construction of a complete fault-detection test set for a
combinational circuit using the two basic approaches. First approach is to examine each “individual
fault”(the fault-table method). Second approach is to examine each “path”(the path sensitizing
method and the ENF method). A third approach to the problem is instead of examining each
individual fault or each path, it is proposed to examine each gate of the circuit.
This method may be considered to have two versions: a graphical and a tabular. The graphical
version will first be presented which uses the Karnaugh map, hence is convenient to apply to circuits
with a small number of input variables, say not more than six, but preferably not more than four.
Then, just as what was done in the minimization of switching functions, this Karnaugh map version
is extended to a tabular method in a similar manner as that of Quine-McCluskey.
1) Karnaugh Map Method
The purpose of this method is to develop a map technique. At first, minimum two-level sum-
of-products will be considered. Factored forms of these expressions will also be investigated, but in
all cases the assumption will be made that no redundancy is present in the circuit. It is very useful for
circuits with a small number of variables, and becomes complicated when the number of variables
increases. To overcome this difficulty, the tabular method can be used.
2) Tabular method
Tabular method consists of three steps. First step is the determination of a minimal complete s-a-0
test set T0. Second step is the determination of a minimal complete s-a-1 test set T1. Third part is the
minimal complete s-a-0 and s-a-1 test set T is the union of T0 and T1This method uses exactly the
same principles of Karnaugh map method but without maps. It allows the circuit to have any finite
number of input variables.
F. Multilevel-circuit Fault Detection
The design of fault-detection experiments for multilevel combinational circuits is based on the
ideas of "path sensitization" and "equivalent normal form". Armstrong proved that a set of fault-
detection tests devised for the equivalent normal form is also a valid set of tests for the original
circuit[10]. Thus the problem of designing experiments for multilevel circuits is equivalent to the
design of experiments for the two-level equivalent normal forms.

G. ENF- Karnaugh map Method

This method is the combination of ENF method and Karnaugh map method. In this method, a
Karnaugh map technique for deriving a fault-detection experiment for multilevel circuits, which will
give the same result as that obtained by the ENF method. It is much simpler technique than the ENF
method, as it does not use a scoring technique and is without the complemented ENF. An ENF
corresponds to a two level AND-OR circuit. Consequently, the techniques developed for two-level
circuits can now be applied, with several modifications to the ENF’s.

H. Boolean Difference Method

Boolean difference is defined as being the exclusive-or operation between two boolean
functions, one representing the normal circuit and other representing the faulty circuit. Thus if the
Boolean difference is a 1, a fault is indicated. Assume that there is a switching function that has one
output F and n inputs x1,x2,….xn, so F(X) = F(x1,x2,….,xn ). If one of the inputs to the switching
function was in error, say input xi , then the output would be F(x1,…..,x’i,……,xn).To analyze the
action of the circuit when an error occurs, it is desirable to know under what circumstances the two
outputs are the same[5].
I. SPOOF Method
An efficient and easy-to-drive method for obtaining tests for detection of single and multiple
faults is presented which is based on the use of the Structure and Parity Observing Output Function
(SPOOF). SPOOF provides the information needed for complete analysis of the effects of possible
faults on the functional characteristics of a given circuit.
The structure- and parity-observing output function (SPOOF) with the adjective disjunctive
indicates that repeatedly used the distributive property u(v V w) = uv V uw to obtain an expression in
disjunctive normal form (i.e., "sum-of-products" form). By using instead, the distributive property u
V vw = (u V v)(u V w), one can obtain a similar expression for the network output function in
"product-of-sums" form called a conjunctive SPOOF.

J. Genetic Algorithm Method

. Genetic Algorithm approach proposed in this work overcomes the problem of creating a very
large fault table. Test numbers are chosen at random and evolutionary strategy is used for improving
the solution. Binary combinations of only chosen tests in a genome (chromosome) are generated and
their fitness are evaluated. The entire fault table need not to be constructed. Fault table construction is
based on random numbers generated in each generation. Optimal solution is not guaranteed in all
cases. Genetic Algorithm consumes less memory location for minimization process.

K. Integer Linear Programming Method

In Integer Linear Programming Method [ILP], two tables are generated for the given
combinational circuit (boolean expression in sum-of-products form). They are fault table (Table 1)
and fault detection table (Table 2). Based on fault detection table fault diagnostic matrix is formed.
The diagnostic matrix Fjn is formed with test number rows and zf1, zf2 .zfi columns alone as shown in
Table III.
 TABLE III. DIAGNOSTIC MATRIX {FJN}.
Test Fault number ( n)
number
( J) 1 2 3 4 . . . . . . n
1 1 0 0 0 . . . . . . 0
2 1 0 1 0 . . . . . . 1
3 0 1 0 1 . . . . . . 0
. . . . . . . . . . . .
. . . . . . . . . . . .
J 0 0 1 0 . . . . . . 1

In the above matrix rows identifies test numbers and columns identifies fault numbers. The
Primal ILP is formulated from fault diagnostic matrix. This method can be adopted for complex
VLSI circuits and results best optimal solution with exponential complexity. Suppose a
combinational circuit has n faults, integer values {0,1} are assigned to variables f1, f2, …, fn. in the
fault set F. Vector set V with n inputs for each test number j is assigned integer values {0, 1} for
variables Vj , j = 1, 2, . . .
, J (where J is 2n), to each vector. Without loss of generality, it is assumed that all n faults are
detected by these vectors. The problem of finding the minimal test set is to find the smallest subset of
these vectors that detects all the faults. In this primal problem, the test set is chosen as follows: The
vector j is included in the selected vector set, if Vj = 1. The vector j is discarded in the selected vector
set, if Vj = 0.
The fault set and test set are simulated without dropping faults. The result is represented as a
diagnostic matrix of 0’s and 1’s as shown in Table III.

Advantages and limitations of fault detection and test minimization

methods
Methods Advantages Limitations
Sl
No

1 Fault Table Suitable for It requires the

Method Simple circuits construction of
fault table

2 Heuristic Suitable for It requires the

Method Simple and tree- construction of
like circuits fault table and
extensive
computations for
isolating fault-
free from faulty
responses.
 Path Suitable for Non- The process of Boolean Conceptually Suitable for
3 8
Sensitizing tree like circuits. exploring all the Difference simple and Simple digital
Method The path- possible paths Method straightforward circuits only.
sensitizing originating from ways of deriving Complexity of
method is very the output of test sequences for computation
attractive from gates involves a combinational increases with
the point of view lot of searching circuits. the number of
of not requiring operations. inputs.
the construction SPOOF An efficient and Suitable for
9
of the fault table. Method easy-to-drive Simple digital
Equivalent- ENF method The method does method for the circuits only.
4 detection of
Normal-Form detects certain not guarantee a
Method paths that are not complete single and
sensitizable in diagnosis of the multiple faults.
other methods. given circuit as Genetic Adopts Genetic
the scoring 10
Algorithm evolutionary Algorithms
technique Method techniques to greatly rely on
employed yields arrive at compact random numbers.
a completely test set. It Optimal solution
different paths eliminates the is not guaranteed
for ENF and its need for a very always.
complement. large fault table
Two- Level- A very simple and The Karnaugh and thereby
5 reduces the space
Circuit Fault direct methods map method
Detection suitable for any requires complexity to a
Methods: two-level AND- irredundant greater extent.
Karnaugh OR(OR- circuits with a The method is
AND,NAND- suitable for any
Map Method maximum of 6
and Tabular OR,etc) input variables complex circuits.
irredundant Integer Linear It can be adopted Space
Method circuits. Tabular only. 11
Programming for complex VLSI complexity is
method does not
Although Method circuits. Optimal exponential.
employ k-map solution is
Tabular method
technique. assured.
does not restrict
the number of
variables,
irredundancy is a
constraint.
Multilevel- This can be Irredundancy is a
6
circuit Fault applied to constraint.
Detection multilevel circuits
with more than
two levels.
ENF- It is much simpler Restricted to two
7
Karnaugh technique than the level AND-OR
map Method ENF method, as it circuits only.
does not use a
scoring technique
and is without the
complemented
ENF.