LT3957

Boost, Flyback, SEPIC and

Inverting Converter
with 5A, 40V Switch
FEATURES DESCRIPTION
n Wide Input Voltage Range: 3V to 40V The LT®3957 is a wide input range, current mode DC/DC
n Single Feedback Pin for Positive or Negative converter which is capable of generating either positive
Output Voltage or negative output voltages. It can be configured as either
n Internal 5A/40V Power Switch a boost, flyback, SEPIC or inverting converter. It features
n Current Mode Control Provides Excellent Transient an internal low side N-channel power MOSFET rated for
Response 40V at 5A and driven from an internal regulated 5.2V
n Programmable Operating Frequency (100kHz to supply. The fixed frequency, current-mode architecture
1MHz) with One External Resistor results in stable operation over a wide range of supply
n Synchronizable to an External Clock and output voltages.
n Low Shutdown Current < 1μA
n
The operating frequency of LT3957 can be set with an
Internal 5.2V Low Dropout Voltage Regulator
n
external resistor over a 100kHz to 1MHz range, and can
Programmable Input Undervoltage Lockout with
be synchronized to an external clock using the SYNC pin.
Hysteresis
n
A minimum operating supply voltage of 3V, and a low
Programmable Soft-Start
shutdown quiescent current of less than 1μA, make the
n Thermally Enhanced QFN (5mm × 6mm) Package
LT3957 ideally suited for battery-powered systems.
The LT3957 features soft-start and frequency foldback
APPLICATIONS functions to limit inductor current during start-up.
n Automotive L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
n Telecom All other trademarks are the property of their respective owners. Patents pending.
n Industrial

TYPICAL APPLICATION
High Efficiency Output Boost Converter Efficiency vs Output Current
10μH VOUT 100
VIN
24V VIN = 12V
4.5V TO 16V
600mA
10μF 10μF
200k 95
VIN SW s2

EN/UVLO GND 90
EFFICIENCY (%)

95.3k LT3957
85
SGND SENSE1
SYNC SENSE2 226k
80
FBX
RT SS VC INTVCC 15.8k 75

41.2k
0.33μF 6.8k 4.7μF 70
300kHz
0 100 200 300 400 500 600
22nF OUTPUT CURRENT (mA) 3957 TA01b

3957 TA01a

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LT3957
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
TOP VIEW
VIN, EN/UVLO (Note 5), SW ......................................40V
INTVCC ......................................................VIN + 0.3V, 8V

SYNC

FBX
NC
NC

RT
SS

VC
SYNC ..........................................................................8V 36 35 34 33 32 31 30
VC, SS .........................................................................3V NC 1 28 INTVCC
RT ............................................................................................... 1.5V NC 2 27 VIN
SENSE1, SGND .................. Internally Connected to GND SENSE2 3 SGND
37
SENSE2..................................................................±0.3V SGND 4 25 EN/UVLO
24 SGND
FBX ................................................................. –6V to 6V
SENSE1 6 23 SGND
Operating Junction Temperature Range
(Note 2).................................................. –40°C to 125°C SW 8 SW 21 SW
Maximum Junction Temperature .......................... 125°C SW 9
38
20 SW
Storage Temperature Range .................. –65°C to 125°C NC 10
12 13 14 15 16 17

GND
GND
GND
GND
GND
GND
UHE PACKAGE
36-LEAD (5mm s 6mm) PLASTIC QFN
TJMAX = 125°C, θJA = 42°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3957EUHE#PBF LT3957EUHE#TRPBF 3957 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
LT3957IUHE#PBF LT3957IUHE#TRPBF 3957 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LT3957
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Range 3 40 V
VIN Shutdown IQ EN/UVLO = 0V 0.1 1 μA
EN/UVLO = 1.15V 6 μA
VIN Operating IQ VC = 0.3V, RT = 41.2k 1.7 2.3 mA
VIN Operating IQ with Internal LDO Disabled VC = 0.3V, RT = 41.2k, INTVCC = 5.5V 350 400 μA
SW Pin Current Limit l 5 5.9 6.8 A
SW Pin On Voltage ISW = 3A 100 mV
SENSE2 Input Bias Current Current Out of Pin –65 μA
Error Amplifier
FBX Regulation Voltage (VFBX(REG)) FBX > 0V (Note 3) l 1.569 1.6 1.631 V
FBX < 0V (Note 3) l –0.816 –0.800 –0.784 V
FBX Overvoltage Lockout FBX > 0V (Note 4) 6 8 10 %
FBX < 0V (Note 4) 7 11 14 %
FBX Pin Input Current FBX = 1.6V (Note 3) 70 100 nA
FBX = –0.8V (Note 3) –10 10 nA
Transconductance gm (ΔIVC /ΔFBX) (Note 3) 230 μS
VC Output Impedance (Note 3) 5 MΩ
VFBX Line Regulation (ΔVFBX /[ΔVIN • VFBX(REG)]) FBX > 0V, 3V < VIN < 40V (Notes 3, 6) 0.04 0.06 %/V
FBX < 0V, 3V < VIN < 40V (Notes 3, 6) 0.03 0.06 %/V
VC Current Mode Gain (ΔVVC /ΔVSENSE) 10 V/V
VC Source Current VC = 1.5V, FBX = 0V, Current Out of Pin –15 μA
VC Sink Current FBX = 1.7V 12 μA
FBX = –0.85V 11 μA
Oscillator
Switching Frequency RT = 140k to SGND, FBX = 1.6V, VC = 1.5V 80 100 120 kHz
RT = 41.2k to SGND, FBX = 1.6V, VC = 1.5V 270 300 330 kHz
RT = 10.5k to SGND, FBX = 1.6V, VC = 1.5V 850 1000 1200 kHz
RT Voltage FBX = 1.6V 1.2 V
SW Minimum Off-Time 220 275 ns
SW Minimum On-Time 240 320 ns
SYNC Input Low 0.4
SYNC Input High 1.5
SS Pull-Up Current SS = 0V, Current Out of Pin –10 μA
Low Dropout Regulator
INTVCC Regulation Voltage l 5 5.2 5.45 V
INTVCC Undervoltage Lockout Threshold Falling INTVCC 2.6 2.7 2.85 V
UVLO Hysteresis 0.15 V

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LT3957
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Current Limit VIN = 40V 32 40 55 mA
VIN = 15V 95 mA
INTVCC Load Regulation (ΔVINTVCC / VINTVCC) 0 < IINTVCC < 20mA, VIN = 8V –1 –0.5 %
INTVCC Line Regulation (ΔVINTVCC / [ΔVIN • VINTVCC]) 6V < VIN < 40V 0.02 0.05 %/V
Dropout Voltage (VIN – VINTVCC) VIN = 5V, IINTVCC = 20mA, VC = 0V 450 mV
INTVCC Current in Shutdown EN/UVLO = 0V, INTVCC = 6V 17 μA
INTVCC Voltage to Bypass Internal LDO 5.5 V
Logic Inputs
EN/UVLO Threshold Voltage Falling VIN = INTVCC = 6V l 1.17 1.22 1.27 V
EN/UVLO Voltage Hysteresis 20 mV
EN/UVLO Input Low Voltage IVIN Drops Below 1μA 0.4 V
EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 1.7 2 2.5 μA
EN/UVLO Pin Bias Current High EN/UVLO = 1.33V 20 100 nA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: The LT3957 is tested in a feedback loop which servos VFBX to the
may cause permanent damage to the device. Exposure to any Absolute reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
Maximum Rating condition for extended periods may affect device Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative
reliability and lifetime. to regulated VFBX(REG).
Note 2: The LT3957E is guaranteed to meet performance specifications Note 5: For 3V ≤ VIN < 6V, the EN/UVLO pin must not exceed VIN.
from the 0°C to 125°C operating junction temperature. Specifications over Note 6: EN/UVLO = 1.33V when VIN = 3V.
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3957I is guaranteed over the full –40°C to 125°C operating junction
temperature range.

TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.

Positive Feedback Voltage Negative Feedback Voltage Quiescent Current

vs Temperature, VIN vs Temperature, VIN vs Temperature, VIN
1605 –788 1.8
REGULATED FEEDBACK VOLTAGE (mV)

REGULATED FEEDBACK VOLTAGE (mV)

–790 VIN = INTVCC = 3V

VIN = 40V SHDN/UVLO = 1.33V
QUIESCENT CURRENT (mA)

1600 VIN = 24V –792 1.7 VIN = 40V

–794 VIN = 8V VIN = 24V
VIN = 8V
1590 –796 1.6

–798
VIN = INTVCC = 3V, VIN = 40V VIN = INTVCC = 3V
1585 –800 VIN = 24V 1.5
SHDN/UVLO = 1.33V
–802

1580 –804 1.4

–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3957 G01 3957 G02 3957 G03

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 LT3957
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.

Dynamic Quiescent Current Normalized Switching

vs Switching Frequency RT vs Switching Frequency Frequency vs FBX
12 1000 120

10 100

NORMALIZED FREQUENCY (%)

8 80

RT (kΩ)
IQ(mA)

6 100 60

4 40

2 20

0 10 0
100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 –0.8 –0.4 0 0.4 0.8 1.2 1.6
SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) FBX VOLTAGE (V)
3957 G04 3957 G05 3957 G06

Switching Frequency SW Pin Current Limit SW Pin Current Limit

vs Temperature vs Temperature vs Duty Cycle
325 6.6 6.6
RT = 41.2k
320
6.4 6.4
SWITCHING FREQUENCY (kHz)

315
SW PIN CURRENT LIMIT (A)

SW PIN CURRENT LIMIT (A)

310
6.2 6.2
305

300 6.0 6.0

295
5.8 5.8
290
285
5.6 5.6
280
275 5.4 5.4
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C) DUTY CYCLE (%)
3957 G07 3957 G08 3957 G09

EN/UVLO Threshold EN/UVLO Hysteresis Current

vs Temperature EN/UVLO Current vs Voltage vs Temperature
1.28 40 2.4

1.26
30 2.2
EN/UVLO CURRENT (μA)
EN/UVLO VOLTAGE (V)

EN/UVLO RISING
IEN/UVLO (μA)

1.24
20 2.0
1.22 EN/UVLO FALLING

10 1.8
1.20

1.18 0 1.6
–50 –25 0 25 50 75 100 125 0 10 20 30 40 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) EN/UVLO VOLTAGE (V) TEMPERATURE (°C)
3957 G10 3957 G11 3957 G12

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 LT3957
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.

INTVCC Minimum Output

INTVCC vs Temperature Current Limit vs VIN INTVCC Load Regulation
5.4 90 5.3
TJ = 125°C VIN = 6V
80 INTVCC = 3V

70 5.2

INTVCC CURRENT (mA)

5.3

INTVCC VOLTAGE (V)

60
INTVCC (V)

5.1
50
5.2
40
5.0
30
5.1 20 4.9
10

5.0 0 4.8
–50 –25 0 25 50 75 100 125 1 10 100 0 10 20 30 40 50 60
VIN (V)
TEMPERATURE (°C) INTVCC LOAD (mA)
3957 G14
3957 G13 3957 G15

INTVCC Dropout Voltage Internal Switch On-Resistance

INTVCC Line Regulation vs Current, Temperature vs Temperature
5.30 700 50
VIN = 5V 125°C
45
600
40
75°C
DROPOUT VOLTAGE (mV)

5.25

ON-RESISTANCE (mΩ)
500 35
INTVCC VOLTAGE (V)

25°C 30
400
5.20 25
300 0°C
20
–40°C 15
200
5.15
10
100
5
5.10 0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 –50 –25 0 25 50 75 100 125
VIN (V) INTVCC LOAD (mA) TEMPERATURE (°C)
3957 G16
3957 G17 3957 G18

Internal Switch On-Resistance SEPIC Typical Start-Up SEPIC FBX Frequency Foldback
vs INTVCC Waveforms Waveforms During Overcurrent
28.2
VIN = 12V VIN = 12V
VOUT
28.0 10V/DIV

27.8
ON-RESISTANCE (mΩ)

27.6 VOUT VSW

5V/DIV 20V/DIV
27.4

27.2 IL1A + IL1B

IL1A + IL1B 5A/DIV
27.0 2A/DIV

3957 G20 3957 G21

26.8 5ms/DIV 50μs/DIV
SEE TYPICAL APPLICATION: 5V TO 16V INPUT, SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
26.6
3 4 5 6 7 8 12V OUTPUT SEPIC CONVERTER 12V OUTPUT SEPIC CONVERTER
INTVCC (V)
3957 G19

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 LT3957
PIN FUNCTIONS
NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave INTVCC (Pin 28): Regulated Supply for Internal Loads
these pins open or connect them to the adjacent pins. and Gate Driver. Supplied from VIN and regulated to
5.2V (typical). INTVCC must be bypassed to SGND with a
SENSE2 (Pin 3): The Current Sense Input for the Control
minimum of 4.7μF capacitor placed close to pin. INTVCC
Loop. Connect this pin to SENSE1 pin directly or through
can be connected directly to VIN, if VIN is less than 8V.
a low pass filter (connect this pin to SENSE1 pin through
INTVCC can also be connected to a power supply whose
a resistor, and to SGND through a capacitor).
voltage is higher than 5.5V, and lower than VIN, provided
SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal that supply does not exceed 8V.
Ground. All small-signal components should connect to
VC (Pin 30): Error Amplifier Compensation Pin. Used to
this ground. SGND is connected to GND inside the IC to
stabilize the voltage loop with an external RC network.
ensure Kelvin connection for the internal switch current
Place compensation components between the VC pin
sensing. Do not connect SGND and GND externally.
and SGND.
SENSE1 (Pin 6): The Current Sense Output of the Inter-
FBX (Pin 31): Positive and Negative Feedback Pin. Re-
nal N-channel MOSFET. Connect this pin to SENSE2 pin
ceives the feedback voltage from the external resistor
directly or through a low pass filter (connect this pin to
divider between the output and SGND. Also modulates the
SENSE1 pin through a resistor, then connect SENSE2 to
switching frequency during start-up and fault conditions
SGND through a capacitor).
when FBX is close to SGND.
SW (Pins 8, 9, 20, 21, Exposed Pad Pin 38): Drain of
SS (Pin 32): Soft-Start Pin. This pin modulates compen-
Internal Power N-channel MOSFET.
sation pin voltage (VC) clamp. The soft-start interval is
GND (Pins 12, 13, 14, 15, 16, 17): Ground. These pins set with an external capacitor between SS pin and SGND.
connect to the source terminal of internal power N-channel The pin has a 10μA (typical) pull-up current source to
MOSFET through an internal sense resistor. GND is con- an internal 2.5V rail. The soft-start pin is reset to SGND
nected to SGND inside the IC to ensure Kelvin connection by an undervoltage condition at EN/UVLO, an INTVCC
for the internal switch current sensing. Do not connect undervoltage or overvoltage condition or an internal
GND and SGND externally. thermal lockout.
EN/UVLO (Pin 25): Shutdown and Undervoltage Detect RT (Pin 33): Switching Frequency Adjustment Pin. Set
Pin. An accurate 1.22V (nominal) falling threshold with the frequency using a resistor to SGND. Do not leave this
externally programmable hysteresis detects when power pin open.
is okay to enable switching. Rising hysteresis is generated
SYNC (Pin 34): Frequency Synchronization Pin. Used to
by the external resistor divider and an accurate internal
synchronize the switching frequency to an outside clock.
2μA pull-down current. An undervoltage condition resets
If this feature is used, an RT resistor should be chosen
soft-start. Tie to 0.4V, or less, to disable the device and
to program a switching frequency 20% slower than the
reduce VIN quiescent current below 1μA.
SYNC pulse frequency. Tie the SYNC pin to SGND if this
VIN (Pin 27): Input Supply Pin. The VIN pin can be locally feature is not used. SYNC is bypassed when FBX is close
bypassed with a capacitor to GND (not SGND). to SGND.

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LT3957
BLOCK DIAGRAM
L1 CDC D1
VIN VOUT

•
R4 R3
CIN
L2 COUT
•
EN/UVLO VIN SW
25 27
8, 9, 20,
A10 21, 38
IS1 –
2μA + 1.22V
2.5V INTERNAL
REGULATOR
AND UVLO CURRENT
IS2
LIMIT
10μA UVLO
Q3 A8 5.2V LDO M2
INTVCC
2.5V G4 28
2.7V
IS3 CVCC
A11
1.72V – TLO
+ 165˚C
DRIVER
G6 SR1
– A12 VC –
+A7 G5 R O G2 M1
–0.88V + S
SENSE1
Q2 PWM 6
COMPARATOR RSENSE
GND
1.6V + A6
– 48mV
A1 12, 13, 14,
– SLOPE VISENSE +
15, 16, 17
SENSE
SENSE2
+
RAMP + 3
A2 RAMP A5
–0.8V – GENERATOR –
1.28V –
+A3 G1 100kHz-1MHz
OSCILLATOR

1.2V
FREQUENCY
+
FOLDBACK
+ A4 Q1

– FREQ
PROG

FBX VC SS SYNC RT SGND

31 30 32 34 33
4, 23, 3957 F01
R2 24, 37
VOUT
CC2 RC CSS RT
R1
CC1

Figure 1. LT3957 Block Diagram Working as a SEPIC Converter

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 LT3957
APPLICATIONS INFORMATION
Main Control Loop The LT3957 has overvoltage protection functions to
The LT3957 uses a fixed frequency, current mode control protect the converter from excessive output voltage
scheme to provide excellent line and load regulation. Op- overshoot during start-up or recovery from a short-circuit
eration can be best understood by referring to the Block condition. An overvoltage comparator A11 (with 20mV
Diagram in Figure 1. hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
The start of each oscillator cycle sets the SR latch (SR1) reset pulse. Similarly, an overvoltage comparator A12
and turns on the internal power MOSFET switch M1 through (with 10mV hysteresis) senses when the FBX pin voltage
driver G2. The switch current flows through the internal exceeds the negative regulated voltage (–0.8V) by 11%
current sensing resistor RSENSE and generates a voltage and provides a reset pulse. Both reset pulses are sent to
proportional to the switch current. This current sense the main RS latch (SR1) through G6 and G5. The power
voltage VISENSE (amplified by A5) is added to a stabilizing MOSFET switch M1 is actively held off for the duration of
slope compensation ramp and the resulting sum (SLOPE) an output overvoltage condition.
is fed into the positive terminal of the PWM comparator A7.
When SLOPE exceeds the level at the negative input of A7 Programming Turn-On and Turn-Off Thresholds with
(VC pin), SR1 is reset, turning off the power switch. The the EN/UVLO Pin
level at the negative input of A7 is set by the error amplifier
The EN/UVLO pin controls whether the LT3957 is enabled
A1 (or A2) and is an amplified version of the difference
or is in shutdown state. A micropower 1.22V reference,
between the feedback voltage (FBX pin) and the reference
a comparator A10 and a controllable current source IS1
voltage (1.6V or –0.8V, depending on the configuration). allow the user to accurately program the supply voltage
In this manner, the error amplifier sets the correct peak at which the IC turns on and off. The falling value can be
switch current level to keep the output in regulation. accurately set by the resistor dividers R3 and R4. When
The LT3957 has a switch current limit function. The current EN/UVLO is above 0.4V, and below the 1.22V threshold,
sense voltage is input to the current limit comparator A6. the small pull-down current source IS1 (typical 2μA) is
If the SENSE2 pin voltage is higher than the sense current active.
limit threshold VSENSE(MAX) (48mV, typical), A6 will reset The purpose of this current is to allow the user to program
SR1 and turn off M1 immediately.
the rising hysteresis. The Block Diagram of the comparator
The LT3957 is capable of generating either positive or and the external resistors is shown in Figure 1. The typical
negative output voltage with a single FBX pin. It can be falling threshold voltage and rising threshold voltage can
configured as a boost, flyback or SEPIC converter to gen- be calculated by the following equations:
erate positive output voltage, or as an inverting converter
(R3 + R4)
to generate negative output voltage. When configured as VVIN,FALLING = 1.22 •
a SEPIC converter, as shown in Figure 1, the FBX pin is R4
pulled up to the internal bias voltage of 1.6V by a volt- VVIN,RISING = 2µA • R3 + VIN,FALLING
age divider (R1 and R2) connected from VOUT to SGND.
Comparator A2 becomes inactive and comparator A1 For applications where the EN/UVLO pin is only used as
performs the inverting amplification from FBX to VC. a logic input, the EN/UVLO pin can be connected directly
When the LT3957 is in an inverting configuration, the to the input voltage VIN for always-on operation.
FBX pin is pulled down to –0.8V by a voltage divider
connected from VOUT to SGND. Comparator A1 becomes
inactive and comparator A2 performs the noninverting
amplification from FBX to VC.

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LT3957
APPLICATIONS INFORMATION
INTVCC Regulator Bypassing and Operation In SEPIC or flyback applications, the INTVCC pin can be
connected to the output voltage VOUT through a blocking
An internal, low dropout (LDO) voltage regulator produces
diode, as shown in Figure 2, if VOUT meets the following
the 5.2V INTVCC supply which powers the gate driver, as
conditions:
shown in Figure 1. The LT3957 contains an undervoltage
lockout comparator A8 for the INTVCC supply. The INTVCC 1. VOUT < VIN (pin voltage)
undervoltage (UV) threshold is 2.7V (typical), with 0.1V 2. VOUT < 8V
hysteresis, to ensure that the internal MOSFET has suf-
ficient gate drive voltage before turning on. When INTVCC A resistor RVCC can be connected, as shown in Figure 2, to
is below the UV threshold, the internal power switch will limit the inrush current from VOUT. Regardless of whether
be turned off and the soft-start operation will be triggered. or not the INTVCC pin is connected to an external voltage
The logic circuitry within the LT3957 is also powered from source, it is always necessary to have the driver circuitry
the internal INTVCC supply. bypassed with a 4.7μF low ESR ceramic capacitor to ground
immediately adjacent to the INTVCC and SGND pins.
The INTVCC regulator must be bypassed to SGND imme-
diately adjacent to the IC pins with a minimum of 4.7μF If LT3957 operates at a low VIN and high switching fre-
ceramic capacitor. Good bypassing is necessary to supply quency, the voltage drop across the drain and the source of
the high transient currents required by the MOSFET gate the LDO PMOS (M2 in Figure 1) could push INTVCC to be
driver. below the UV threshold. To prevent this from happening,
the INTVCC pin can be shorted directly to the VIN pin. VIN
In an actual application, most of the IC supply current is must not exceed the INTVCC Absolute Maximum Rating
used to drive the gate capacitance of the internal power (8V). In this condition, the internal LDO will be turned off
MOSFET. The on-chip power dissipation can be significant and the gate driver will be powered directly from VIN. It is
when the internal power MOSFET is being driven at a high recommended that INTVCC pin be shorted to the VIN pin if
frequency and the VIN voltage is high. VIN is lower than 3.5V at 1MHz switching frequency, or VIN
An effective approach to reduce the power consumption of is lower than 3.2V at 100kHz switching frequency. With
the internal LDO for gate drive and to improve the efficiency the INTVCC pin shorted to VIN, however, a small current
is to tie the INTVCC pin to an external voltage source high (around 16μA) will load the INTVCC in shutdown mode.
enough to turn off the internal LDO regulator.
DVCC RVCC
INTVCC VOUT

LT3957 CVCC
4.7μF

SGND
3957 F02

Figure 2. Connecting INTVCC to VOUT

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 LT3957
APPLICATIONS INFORMATION
Operating Frequency and Synchronization Duty Cycle Consideration
The choice of operating frequency may be determined by Switching duty cycle is a key variable defining con-
on-chip power dissipation (a low switching frequency may verter operation. As such, its limits must be considered.
be required to ensure IC junction temperature does not Minimum on-time is the smallest time duration that the
exceed 125°C), otherwise it is a trade-off between efficiency LT3957 is capable of turning on the power MOSFET. This
and component size. Low frequency operation improves time is typically about 240ns (see Minimum On-Time in
efficiency by reducing gate drive current and MOSFET the Electrical Characteristics table). In each switching
and diode switching losses. However, lower frequency cycle, the LT3957 keeps the power switch off for at least
operation requires a physically larger inductor. Switching 220ns (typical) (see Minimum Off-Time in the Electrical
frequency also has implications for loop compensation. Characteristics table).
The LT3957 uses a constant-frequency architecture that
The minimum on-time, minimum off-time and the switching
can be programmed over a 100kHz to 1000kHz range
frequency define the minimum and maximum switching
with a single external resistor from the RT pin to SGND,
duty cycles a converter is able to generate:
as shown in Figure 1. A table for selecting the value of RT
for a given operating frequency is shown in Table 1. Minimum duty cycle = minimum on-time • frequency
Table 1. Timing Resistor (RT ) Value Maximum duty cycle = 1 – (minimum off-time • frequency)
SWITCHING FREQUENCY (kHz) RT (kΩ)
Programming the Output Voltage
100 140
200 63.4 The output voltage VOUT is set by a resistor divider, as
300 41.2 shown in Figure 1. The positive and negative VOUT are set
400 30.9 by the following equations:
500 24.3 ⎛ R2 ⎞
VOUT,POSITIVE = 1.6V • ⎜ 1+ ⎟
600 19.6 ⎝ R1⎠
700 16.5
⎛ R2 ⎞
800 14 VOUT,NEGATIVE = –0.8V • ⎜ 1+ ⎟
⎝ R1⎠
900 12.1
1000 10.5 The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
The operating frequency of the LT3957 can be synchronized during normal operation is less than 1% (this translates
to an external clock source. By providing a digital clock to a maximum value of R1 at about 158k).
signal into the SYNC pin, the LT3957 will operate at the
SYNC clock frequency. The LT3957 detects the rising edge
of each clock cycle. If this feature is used, an RT resistor
should be chosen to program a switching frequency 20%
slower than SYNC pulse frequency. It is recommended that
the SYNC pin has a minimum pulse width of 200ns. Tie
the SYNC pin to SGND if this feature is not used.

3957f

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LT3957
APPLICATIONS INFORMATION
Soft-Start FBX Frequency Foldback
The LT3957 contains several features to limit peak switch When VOUT is very low during start-up, or an output short-
currents and output voltage (VOUT) overshoot during circuit on a SEPIC, an inverting, or a flyback converter, the
start-up or recovery from a fault condition. The primary switching regulator must operate at low duty cycles to keep
purpose of these features is to prevent damage to external the power switch current below the current limit, since
components or the load. the inductor current decay rate is very low during switch
off time. The minimum on-time limitation may prevent the
High peak switch currents during start-up may occur in
switcher from attaining a sufficiently low duty cycle at the
switching regulators. Since VOUT is far from its final value,
programmed switching frequency. So, the switch current
the feedback loop is saturated and the regulator tries to
may keep increasing through each switch cycle, exceed-
charge the output capacitor as quickly as possible, resulting
ing the programmed current limit. To prevent the switch
in large peak currents. A large surge current may cause
peak currents from exceeding the programmed value, the
inductor saturation or power switch failure.
LT3957 contains a frequency foldback function to reduce
The LT3957 addresses this mechanism with the SS pin. the switching frequency when the FBX voltage is low (see
As shown in Figure 1, the SS pin reduces the power the Normalized Switching Frequency vs FBX graph in the
MOSFET current by pulling down the VC pin through Typical Performance Characteristics section).
Q2. In this way the SS allows the output capacitor to
During frequency foldback, external clock synchroniza-
charge gradually toward its final value while limiting the
tion is disabled to prevent interference with frequency
start-up peak currents. The typical start-up waveforms
reducing operation.
are shown in the Typical Performance Characteristics
section. The inductor current IL slewing rate is limited by Loop Compensation
the soft-start function.
Loop compensation determines the stability and transient
Besides start-up (with EN/UVLO), soft-start can also be performance. The LT3957 uses current mode control to
triggered by the following faults: regulate the output which simplifies loop compensation.
1. INTVCC < 2.85V The optimum values depend on the converter topology, the
component values and the operating conditions (including
2. Thermal lockout (TLO > 165°C) the input voltage, load current, etc.). To compensate the
Any of these three faults will cause the LT3957 to stop feedback loop of the LT3957, a series resistor-capacitor
switching immediately. The SS pin will be discharged by network is usually connected from the VC pin to SGND.
Q3. When all faults are cleared and the SS pin has been Figure 1 shows the typical VC compensation network.
discharged below 0.2V, a 10μA current source IS2 starts For most applications, the capacitor should be in the
charging the SS pin, initiating a soft-start operation. range of 470pF to 22nF, and the resistor should be in the
range of 5k to 50k. A small capacitor is often connected
The soft-start interval is set by the soft-start capacitor
in parallel with the RC compensation network to attenu-
selection according to the equation:
ate the VC voltage ripple induced from the output voltage
1.25V ripple through the internal error amplifier. The parallel
TSS = CSS •
10µA capacitor usually ranges in value from 10pF to 100pF. A
practical approach to design the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should
then be checked across all operating conditions, including
load current, input voltage and temperature. Application
Note 76 is a good reference on loop compensation.
3957f

12
 LT3957
APPLICATIONS INFORMATION
The Internal Power Switch Current On-Chip Power Dissipation and Thermal Lockout (TLO)
For control and protection, the LT3957 measures the The on-chip power dissipation of LT3957 can be estimated
internal power MOSFET current by using a sense resistor using the following equation:
(RSENSE) between GND and the MOSFET source. Figure 3 PIC ≈ I2SW • D • RDS(ON) + V2PEAK • ISW • ƒ • 200pF/A +
shows a typical waveform of the internal switch current VIN • (1.6mA + ƒ • 10nC)
(ISW).
where RDS(ON) is the internal switch on-resistance which
Due to the current limit (minimum 5A) of the internal power can be obtained from the Typical Performance Characteris-
switch, the LT3957 should be used in the applications tics section. VSW(PEAK) is the peak switch off-state voltage.
that the switch peak current ISW(PEAK) during steady state The maximum power dissipation PIC(MAX) can be obtained
normal operation is lower than 5A by a sufficient margin by comparing PIC across all the VIN range at the maximum
(10% or higher is recommended). output current . The highest junction temperature can be
The LT3957 switching controller incorporates 100ns estimated using the following equation:
timing interval to blank the ringing on the current sense TJ(MAX) ≈ TA + PIC(MAX) • 42°C/W
signal across RSENSE immediately after M1 is turned on.
This ringing is caused by the parasitic inductance and It is recommended to measure the IC temperature in steady
capacitance of the PCB trace, the sense resistor, the diode, state to verify that the junction temperature limit is not
and the MOSFET. The 100ns timing interval is adequate exceeded. A low switching frequency may be required to
for most of the LT3957 applications. In the applications ensure TJ(MAX) does not exceed 125°C.
that have very large and long ringing on the current sense If LT3957 die temperature reaches thermal lockout
signal, a small RC filter can be added to filter out the excess threshold at 165°C (typical), the IC will initiate several
ringing. Figure 4 shows the RC filter on the SENSE1 and protective actions. The power switch will be turned off.
SENSE2 pins. It is usually sufficient to choose 22Ω for A soft-start operation will be triggered. The IC will be en-
RFLT and 2.2nF to 10nF for CFLT. Keep RFLT’s resistance abled again when the junction temperature has dropped
low. Remember that there is 65μA (typical) flowing out of by 5°C (nominal).
the SENSE2 pin. Adding RFLT will affect the internal power
switch current limit threshold: LT3957

SENSE1
⎛ 65µA • RFLT ⎞
ISW _ILIM = ⎜ 1− ⎟ • 5A
RFLT
⎝ 48mV ⎠ SENSE2
CFLT
SGND

ISW 3957 F04

$ISW
Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin
ISW(PEAK)

t
DTS
TS
3957 F03

Figure 3. The Switch Current During a Switching Cycle

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13
LT3957
APPLICATIONS INFORMATION
APPLICATION CIRCUITS Due to the current limit of its internal power switch, the
LT3957 should be used in a boost converter whose maxi-
The LT3957 can be configured as different topologies. The
mum output current (IO(MAX)) is less than the maximum
first topology to be analyzed will be the boost converter,
output current capability by a sufficient margin (10% or
followed by the flyback, SEPIC and inverting converters.
higher is recommended):
Boost Converter: Switch Duty Cycle and Frequency VIN(MIN)
I O(MAX) < • ( 5A − 0.5 • ΔISW )
The LT3957 can be configured as a boost converter for VOUT
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con- The inductor ripple current ΔISW has a direct effect on the
verters are not short-circuit protected. Under a shorted choice of the inductor value and the converter’s maximum
output condition, the inductor current is limited only by output current capability. Choosing smaller values of
the input supply capability. For applications requiring a ΔISW increases output current capability, but requires
step-up converter that is short-circuit protected, please large inductances and reduces the current loop gain (the
refer to the Applications Information section covering converter will approach voltage mode). Accepting larger
SEPIC converters. values of ΔISW provides fast transient response and
allows the use of low inductances, but results in higher
The conversion ratio as a function of duty cycle is
input current ripple and greater core losses, and reduces
VOUT 1 output current capability.
=
VIN 1− D Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
in continuous conduction mode (CCM).
the inductor value of the boost converter can be determined
For a boost converter operating in CCM, the duty cycle using the following equation:
of the main switch can be calculated based on the output
VIN(MIN)
voltage (VOUT) and the input voltage (VIN). The maximum L= • DMAX
duty cycle (DMAX) occurs when the converter has the ΔISW • ƒ
minimum input voltage:
The peak inductor current is the switch current limit (5.9A
VOUT − VIN(MIN) typical), and the RMS inductor current is approximately
DMAX =
VOUT equal to IL(MAX). The user should choose the inductors
having sufficient saturation and RMS current ratings.
Discontinuous conduction mode (DCM) provides higher
conversion ratios at a given frequency at the cost of reduced Boost Converter: Output Diode Selection
efficiencies and higher switching currents.
To maximize efficiency, a fast switching diode with low
Boost Converter: Maximum Output Current Capability forward drop and low reverse leakage is desirable. The
and Inductor Selection peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
For the boost topology, the maximum average inductor ringing across its anode-to-cathode during the on-time.
current is: The average forward current in normal operation is equal
1 to the output current.
I L(MAX) = IO(MAX) •
1− DMAX It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT by a safety margin (a 10V
safety margin is usually sufficient).

3957f

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 LT3957
APPLICATIONS INFORMATION
The power dissipated by the diode is: tON tOFF

$VCOUT
PD = IO(MAX) • VD
VOUT
where VD is diode’s forward voltage drop, and the diode (AC)
RINGING DUE TO
junction temperature is: TOTAL INDUCTANCE
$VESR (BOARD + CAP)
TJ = TA + PD • RθJA 3957 F05

The RθJA to be used in this equation normally includes the Figure 5. The Output Ripple Waveform of a Boost Converter
RθJC for the device plus the thermal resistance from the board
to the ambient temperature in the enclosure. TJ must not The output capacitor in a boost regulator experiences high
exceed the diode maximum junction temperature rating. RMS ripple currents, as shown in Figure 5. The RMS ripple
current rating of the output capacitor can be determined
Boost Converter: Output Capacitor Selection using the following equation:
Contributions of ESR (equivalent series resistance), ESL
DMAX
(equivalent series inductance) and the bulk capacitance IRMS(COUT) ≥IO(MAX) •
must be considered when choosing the correct output 1− DMAX
capacitors for a given output ripple voltage. The effect of
Multiple capacitors are often paralleled to meet ESR require-
these three parameters (ESR, ESL and bulk C) on the output
ments. Typically, once the ESR requirement is satisfied, the
voltage ripple waveform for a typical boost converter is
capacitance is adequate for filtering and has the required
illustrated in Figure 5.
RMS current rating. Additional ceramic capacitors in par-
The choice of component(s) begins with the maximum allel are commonly used to reduce the effect of parasitic
acceptable ripple voltage (expressed as a percentage of inductance in the output capacitor, which reduces high
the output voltage), and how this ripple should be divided frequency switching noise on the converter output.
between the ESR step ΔVESR and the charging/discharg-
ing ΔVCOUT. For the purpose of simplicity, we will choose Boost Converter: Input Capacitor Selection
2% for the maximum output ripple, to be divided equally The input capacitor of a boost converter is less critical
between ΔVESR and ΔVCOUT. This percentage ripple will than the output capacitor, due to the fact that the inductor
change, depending on the requirements of the application, is in series with the input, and the input current wave-
and the following equations can easily be modified. For a form is continuous. The input voltage source impedance
1% contribution to the total ripple voltage, the ESR of the determines the size of the input capacitor, which is typi-
output capacitor can be determined using the following cally in the range of 1μF to 100μF. A low ESR capacitor
equation: is recommended, although it is not as critical as for the
0.01• VOUT output capacitor.
ESRCOUT ≤
ID(PEAK) The RMS input capacitor ripple current for a boost con-
verter is:
For the bulk C component, which also contributes 1% to
the total ripple: IRMS(CIN) = 0.3 • ΔIL
IO(MAX)
COUT ≥
0.01• VOUT • ƒ

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LT3957
APPLICATIONS INFORMATION
FLYBACK CONVERTER APPLICATIONS Figure 7 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
The LT3957 can be configured as a flyback converter for the
period TS, three subintervals occur: DTS, D2TS, D3TS.
applications where the converters have multiple outputs,
During DTS, M is on, and D is reverse-biased. During
high output voltages or isolated outputs. Due to the 40V
D2TS, M is off, and LS is conducting current. Both LP and
rating of the internal power switch, LT3797 should be used
LS currents are zero during D3TS.
in low input voltage flyback converters. Figure 6 shows a
simplified flyback converter.
VSW
The flyback converter has a very low parts count for mul-
tiple outputs, and with prudent selection of turns ratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
the high peak currents, high peak voltages and consequent ISW

power loss. The flyback converter is commonly used for

an output power of less than 50W. ISW(MAX)

The flyback converter can be designed to operate either

in continuous or discontinuous mode. Compared to con- ID

tinuous mode, discontinuous mode has the advantage of

smaller transformer inductances and easy loop compen- ID(MAX)

sation, and the disadvantage of higher peak-to-average

DTS D2TS D3TS t
current and lower efficiency. TS
3957 F07

SUGGESTED
RCD SNUBBER NP:NS D Figure 7. Waveforms of the Flyback Converter
VIN in Discontinuous Mode Operation
+ – +
CIN VSN CSN RSN ID +
+ LP LS VOUT
COUT The flyback converter conversion ratio in the discontinu-
– ous mode operation is:
DSN

VOUT NS D
ISW
= •
VIN NP D2
SW

LT3957 According to Figure 6, the peak SW voltage is:

GND
3957 F06
VSW(PEAK) = VIN(MAX) + VSN
where VSN is the snubber capacitor voltage. A smaller VSN
Figure 6. A Simplified Flyback Converter results in a larger snubber loss. A reasonable VSN is 1.5
to 2 times of the reflected output voltage:
Flyback Converter: Switch Duty Cycle and Turns Ratio
VOUT • NP
The flyback converter conversion ratio in the continuous VSN = k •
mode operation is: NS
VOUT NS D k = 1.5 ~ 2
= •
VIN NP 1− D

where NS/NP is the second to primary turns ratio. D is

duty cycle.
3957f

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 LT3957
APPLICATIONS INFORMATION
According to the Absolute Maximum Ratings table, the SW output current capability by a sufficient margin (10% or
voltage Absolute Maximum value is 40V. Therefore, the higher is recommended):
maximum primary to secondary turns ratio (for both the VIN(MIN)
continuous and the discontinuous operation) should be. IO(MAX) < • DMAX • ( 5A − 0.5 • ΔISW )
VOUT
NP 40V − VIN(MAX)
≤
NS k • VOUT The transformer ripple current ΔISW has a direct effect on
the design/choice of the transformer and the converter’s
According to the preceding equations, the user has relative
output current capability. Choosing smaller values of
freedom in selecting the switch duty cycle or turns ratio to
ΔISW increases the output current capability, but requires
suit a given application. The selections of the duty cycle
large primary and secondary inductances and reduce the
and the turns ratio are somewhat iterative processes, due
current loop gain (the converter will approach voltage
to the number of variables involved. The user can choose
mode). Accepting larger values of ΔISW allows the use
either a duty cycle or a turns ratio as the start point. The
of low primary and secondary inductances, but results
following trade-offs should be considered when select-
in higher input current ripple, greater core losses, and
ing the switch duty cycle or turns ratio, to optimize the
reduces the output current capability.
converter performance. A higher duty cycle affects the
flyback converter in the following aspects: Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the primary
• Lower MOSFET RMS current ISW(RMS), but higher
MOSFET VSW peak voltage winding, the primary winding inductance can be calculated
using the following equation:
• Lower diode peak reverse voltage, but higher diode
RMS current ID(RMS) VIN(MIN)
L= • DMAX
ΔISW • ƒ
• Higher transformer turns ratio (NP/NS)
It is recommended to choose a duty cycle between 20% The primary winding peak current is the switch current
and 80%. limit (typical 5.9A). The primary and secondary maximum
RMS currents are:
Flyback Converter: Maximum Output Current
POUT(MAX)
Capability and Transformer Design ILP(RMS) ≈
DMAX • VIN(MIN) • η
The maximum output current capability and transformer
design for continuous conduction mode (CCM) is chosen I OUT(MAX)
ILS(RMS) ≈
as presented here. 1− DMAX
The maximum duty cycle (DMAX) occurs when the converter
where η is the converter efficiency.
has the minimum VIN:
Based on the preceding equations, the user should de-
⎛N ⎞
VOUT • ⎜ P ⎟ sign/choose the transformer having sufficient saturation
⎝N ⎠S and RMS current ratings.
DMAX =
⎛N ⎞
VOUT • ⎜ P ⎟ + VIN(MIN) Flyback Converter: Snubber Design
⎝ NS ⎠
Transformer leakage inductance (on either the primary or
Due to the current limit of its internal power switch, the
secondary) causes a voltage spike to occur after the MOS-
LT3957 should be used in a flyback converter whose maxi-
FET turn-off. This is increasingly prominent at higher load
mum output current (IO(MAX)) is less than the maximum
currents, where more stored energy must be dissipated.

3957f

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LT3957
APPLICATIONS INFORMATION
In some cases a snubber circuit will be required to avoid Approximate the required peak repetitive reverse voltage
overvoltage breakdown at the MOSFET’s drain node. There rating VRRM using:
are different snubber circuits (such as RC snubber, RCD NS
snubber, Zener clamp, etc.), and Application Note 19 is a VRRM > •V +V
good reference on snubber design. An RC snubber circuit NP IN(MAX) OUT
can be connected between SW and GND to damp the The power dissipated by the diode is:
ringing on SW pins. The snubber resistor values should
be close to the impedance of the parasitic resonance. The PD = IO(MAX) • VD
snubber capacitor value should be larger than the circuit and the diode junction temperature is:
parasitic capacitance, but be small enough to keep the
snubber resistor power dissipation low. TJ = TA + PD • RθJA

If the RC snubber is insufficient to prevent SW pins over- The RθJA to be used in this equation normally includes the
voltage, the RCD snubber can be used to limit the peak RθJC for the device, plus the thermal resistance from the board
voltage on the SW pins, which is shown in Figure 6. to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
The snubber resistor value (RSN) can be calculated by the
following equation: Flyback Converter: Output Capacitor Selection
NP The output capacitor of the flyback converter has a similar
V 2 SN − VSN • VOUT •
NS operation condition as that of the boost converter. Refer to
RSN = 2 • the Boost Converter: Output Capacitor Selection section
I2 SW(PEAK) • L LK • ƒ
for the calculation of COUT and ESRCOUT.
LLK is the leakage inductance of the primary winding, The RMS ripple current rating of the output capacitors
which is usually specified in the transformer character- in continuous operation can be determined using the
istics. LLK can be obtained by measuring the primary following equation:
inductance with the secondary windings shorted. The
snubber capacitor value (CSN) can be determined using DMAX
IRMS(COUT),CONTINUOUS ≈ IO(MAX) •
the following equation: 1− DMAX
VSN
CCN = Flyback Converter: Input Capacitor Selection
ΔVSN • RSN • ƒ
The input capacitor in a flyback converter is subject to
where ΔVSN is the voltage ripple across CSN. A reasonable a large RMS current due to the discontinuous primary
ΔVSN is 5% to 10% of VSN. The reverse voltage rating of current. To prevent large voltage transients, use a low
DSN should be higher than the sum of VSN and VIN(MAX). ESR input capacitor sized for the maximum RMS current.
A Zener clamp can also be connected between SW and The RMS ripple current rating of the input capacitors in
GND to ensure SW voltage does not exceed 40V. continuous operation can be determined using the fol-
lowing equation:
Flyback Converter: Output Diode Selection
POUT(MAX) 1− DMAX
The output diode in a flyback converter is subject to large IRMS(CIN),CONTINUOUS ≈ •
RMS current and peak reverse voltage stresses. A fast VIN(MIN) • η DMAX
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.

3957f

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 LT3957
APPLICATIONS INFORMATION
SEPIC CONVERTER APPLICATIONS can also be wound on the same core, since identical volt-
The LT3957 can be configured as a SEPIC (single-ended ages are applied to L1 and L2 throughout the switching
primary inductance converter), as shown in Figure 1. This cycle.
topology allows for the input to be higher, equal, or lower For the SEPIC topology, the current through L1 is the
than the desired output voltage. The conversion ratio as converter input current. Based on the fact that, ideally, the
a function of duty cycle is: output power is equal to the input power, the maximum
VOUT + VD D average inductor currents of L1 and L2 are:
=
VIN 1− D DMAX
IL1(MAX) =IIN(MAX) =IO(MAX) •
1− DMAX
in continuous conduction mode (CCM).
IL2(MAX) =IO(MAX)
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter Due to the current limit of its internal power switch,
for applications requiring the output to be disconnected the LT3957 should be used in a SEPIC converter whose
from the input source when the circuit is in shutdown. maximum output current (IO(MAX)) is less than the output
Compared to the flyback converter, the SEPIC converter current capability by a sufficient margin (10% or higher
has the advantage that both the power MOSFET and the is recommended):
output diode voltages are clamped by the capacitors (CIN,
IO(MAX) < (1− DMAX ) • ( 5A − 0.5 • ΔISW )
CDC and COUT), therefore, there is less voltage ringing
across the power MOSFET and the output diodes. The
The inductor ripple currents ΔIL1 and ΔIL2 are identical:
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact ΔIL1 = ΔIL2 = 0.5 • ΔISW
that, in the SEPIC converter, the current through inductor The inductor ripple current ΔISW has a direct effect on the
L1 (which is series with the input) is continuous. choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of ΔISW
SEPIC Converter: Switch Duty Cycle and Frequency
requires large inductances and reduces the current loop
For a SEPIC converter operating in CCM, the duty cycle gain (the converter will approach voltage mode). Accepting
of the main switch can be calculated based on the output larger values of ΔISW allows the use of low inductances,
voltage (VOUT), the input voltage (VIN) and the diode but results in higher input current ripple and greater core
forward voltage (VD). losses and reduces output current capability.
The maximum duty cycle (DMAX) occurs when the converter Given an operating input voltage range, and having chosen
has the minimum input voltage: the operating frequency and ripple current in the induc-
VOUT + VD tor, the inductor value (L1 and L2 are independent) of the
DMAX = SEPIC converter can be determined using the following
VIN(MIN) + VOUT + VD
equation:

SEPIC Converter: The Maximum Output Current VIN(MIN)

L1 = L2 = • DMAX
Capability and Inductor Selection 0.5 • ΔISW • ƒ
As shown in Figure 1, the SEPIC converter contains two
For most SEPIC applications, the equal inductor values
inductors: L1 and L2. L1 and L2 can be independent, but
will fall in the range of 1μH to 100μH.

3957f

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LT3957
APPLICATIONS INFORMATION
By making L1 = L2, and winding them on the same core, the SEPIC Converter: Output and Input Capacitor Selection
value of inductance in the preceding equation is replaced The selections of the output and input capacitors of the
by 2L, due to mutual inductance: SEPIC converter are similar to those of the boost converter.
VIN(MIN) Please refer to the Boost Converter: Output Capacitor
L= • DMAX Selection and Boost Converter: Input Capacitor Selection
ΔISW • ƒ
sections.
This maintains the same ripple current and energy storage SEPIC Converter: Selecting the DC Coupling Capacitor
in the inductors. The peak inductor currents are:
The DC voltage rating of the DC coupling capacitor (CDC,
IL1(PEAK) = IL1(MAX) + 0.5 • ΔIL1 as shown in Figure 1) should be larger than the maximum
IL2(PEAK) = IL2(MAX) + 0.5 • ΔIL2 input voltage:
The maximum RMS inductor currents are approximately VCDC > VIN(MAX)
equal to the maximum average inductor currents. CDC has nearly a rectangular current waveform. During
Based on the preceding equations, the user should choose the switch off-time, the current through CDC is IIN, while
the inductors having sufficient saturation and RMS cur- approximately –IO flows during the on-time. The RMS
rent ratings. rating of the coupling capacitor is determined by the fol-
lowing equation:
SEPIC Converter: Output Diode Selection
VOUT + VD
To maximize efficiency, a fast switching diode with a low IRMS(CDC) >IO(MAX) •
VIN(MIN)
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
A low ESR and ESL, X5R or X7R ceramic capacitor works
the output current.
well for CDC.
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety INVERTING CONVERTER APPLICATIONS
margin (a 10V safety margin is usually sufficient).
The LT3957 can be configured as a dual-inductor inverting
The power dissipated by the diode is: topology, as shown in Figure 8. The VOUT to VIN ratio is:
PD = IO(MAX) • VD VOUT − VD D
=−
where VD is diode’s forward voltage drop, and the diode VIN 1− D
junction temperature is:
in continuous conduction mode (CCM).
TJ = TA + PD • RθJA
The RθJA used in this equation normally includes the RθJC L1 CDC L2
for the device, plus the thermal resistance from the board, VIN
+ –
+ –
to the ambient temperature in the enclosure. TJ must not CIN
COUT VOUT
exceed the diode maximum junction temperature rating. SW +
LT3957 D1

+
GND
3757 F10

Figure 8. A Simplified Inverting Converter

3957f

20
 LT3957
APPLICATIONS INFORMATION
Inverting Converter: Switch Duty Cycle and Frequency Inverting Converter: Selecting the DC Coupling Capacitor
For an inverting converter operating in CCM, the duty cycle The DC voltage rating of the DC coupling capacitor
of the main switch can be calculated based on the negative (CDC, as shown in Figure 10) should be larger than the
output voltage (VOUT) and the input voltage (VIN). maximum input voltage minus the output voltage (nega-
The maximum duty cycle (DMAX) occurs when the converter tive voltage):
has the minimum input voltage: VCDC > VIN(MAX) – VOUT
VOUT − VD CDC has nearly a rectangular current waveform. During
DMAX =
VOUT − VD − VIN(MIN) the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
Inverting Converter: Output Diode and Input Capacitor rating of the coupling capacitor is determined by the fol-
Selections lowing equation:

The selections of the inductor, output diode and input DMAX

IRMS(CDC) >IO(MAX) •
capacitor of an inverting converter are similar to those 1− DMAX
of the SEPIC converter. Please refer to the corresponding
SEPIC converter sections. A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Inverting Converter: Output Capacitor Selection
Board Layout
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC The high power and high speed operation of the LT3957
converters for similar output ripples. This is due to the fact demands careful attention to board layout and component
that, in the inverting converter, the inductor L2 is in series placement. Careful attention must be paid to the internal
with the output, and the ripple current flowing through the power dissipation of the LT3957 at high input voltages,
output capacitors are continuous. The output ripple voltage high switching frequencies, and high internal power switch
is produced by the ripple current of L2 flowing through the currents to ensure that a junction temperature of 125°C is
ESR and bulk capacitance of the output capacitor: not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
⎛ 1 ⎞ tom of the package are SGND and SW terminals of the IC,
ΔVOUT(P – P) = ΔIL2 • ⎜ ESRCOUT +
⎝ 8 • ƒ • COUT ⎟⎠ and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
After specifying the maximum output ripple, the user can in the printed circuit board be used to conduct heat away
select the output capacitors according to the preceding from the IC and into the copper planes with as much as
equation. area as possible.
The ESR can be minimized by using high quality X5R or To prevent radiation and high frequency resonance
X7R dielectric ceramic capacitors. In many applications, problems, proper layout of the components connected
ceramic capacitors are sufficient to limit the output volt- to the IC is essential, especially the power paths with
age ripple. higher di/dt. The following high di/dt loops of different
topologies should be kept as tight as possible to reduce
The RMS ripple current rating of the output capacitor
inductive ringing:
needs to be greater than:
• In boost configuration, the high di/dt loop contains the
IRMS(COUT) > 0.3 • ΔIL2
output capacitor, the internal power MOSFET and the
Schottky diode.
3957f

21
LT3957
APPLICATIONS INFORMATION
• In flyback configuration, the high di/dt primary loop Make sure the inductive ringing does not exceed the
contains the input capacitor, the primary winding, the maximum rating of the internal power MOSFET (40V).
internal power MOSFET. The high di/dt secondary loop The small-signal components should be placed away from
contains the output capacitor, the secondary winding high frequency switching nodes. For optimum load regula-
and the output diode. tion and true remote sensing, the top of the output voltage
• In SEPIC configuration, the high di/dt loop contains sensing resistor divider should connect independently to
the internal power MOSFET, output capacitor, Schottky the top of the output capacitor (Kelvin connection), staying
diode and the coupling capacitor. away from any high dV/dt traces. Place the divider resis-
tors near the LT3957 in order to keep the high impedance
• In inverting configuration, the high di/dt loop contains
FBX node short.
internal power MOSFET, Schottky diode and the coupling
capacitor. Figure 9 shows the suggested layout of the 4.5V to16V
input, 24V output boost converter in the Typical Applica-
Check the stress on the internal power MOSFET by measur-
tion section.
ing the SW-to-GND voltage directly across the IC terminals.

R1 VIA TO VOUT

CSS R2

RT RC CC

36 35 34 33 32 31 30
1 28 CVCC

2 27
3 37 R3
4 25
24 R4
6 LT3957 23

38
8 21
9 20
10
12 13 14 15 16 17

L1 D1
COUT COUT

CIN

VIA TO VOUT
GND VOUT

VIN
3958 F09

VIAS TO SGND GROUND PLANE

VIAS TO SW PLANE

Figure 9. Suggested Layout of the 4.5V to 16V Input. 24V Output Boost Converter in the Typical Application Section

3957f

22
 LT3957
APPLICATIONS INFORMATION
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.

Table 2. Recommended Component Manufacturers

VENDOR COMPONENTS WEB ADDRESS
AVX Capacitors avx.com
BH Electronics Inductors, bhelectronics.com
Transformers
Coilcraft Inductors coilcraft.com
Cooper Bussmann Inductors bussmann.com
Diodes, Inc Diodes diodes.com
General Semiconductor Diodes generalsemiconductor.
com
International Rectifier Diodes irf.com
Kemet Tantalum Capacitors kemet.com
Magnetics Inc Toroid Cores mag-inc.com
Microsemi Diodes microsemi.com
Murata-Erie Inductors, Capacitors murata.co.jp
Nichicon Capacitors nichicon.com
On Semiconductor Diodes onsemi.com
Panasonic Capacitors panasonic.com
Pulse Inductors pulseeng.com
Sanyo Capacitors sanyo.co.jp
Sumida Inductors sumida.com
Taiyo Yuden Capacitors t-yuden.com
TDK Capacitors, Inductors component.tdk.com
Thermalloy Heat Sinks aavidthermalloy.com
Tokin Capacitors nec-tokinamerica.com
Toko Inductors tokoam.com
United Chemi-Con Capacitors chemi-com.com
Vishay Inductors vishay.com
Würth Elektronik Inductors we-online.com
Vishay/Sprague Capacitors vishay.com
Zetex Small-Signal Discretes zetex.com

3957f

23
LT3957
TYPICAL APPLICATIONS
4.5V to 16V Input, 24V Output Boost Converter

L1
10μH D1 VOUT
VIN
24V
4.5V TO 16V CIN COUT 600mA
10μF R3 10μF
25V 200k VIN SW 50V
X5R X5R
EN/UVLO GND s2
R4
95.3k LT3957
SGND SENSE1
R2
SYNC SENSE2 226k
FBX
RT SS VC INTVCC R1
15.8k
RT RC CVCC
CSS 4.7μF
41.2k 0.33μF 6.8k
300kHz 10V
CC X5R
22nF

3957 TA02a

CIN: MURATA GRM31ER61H106KA12

COUT: TAIYO YUDEN UMK325BJ106MM
D1: VISHAY SILICONIX 10BQ040
L1: VISHAY SILICONIX IHLP-5050CE-1

Efficiency vs Output Current

100
VIN = 12V

95

90
EFFICIENCY (%)

85

80

75

70
0 100 200 300 400 500 600
OUTPUT CURRENT (mA) 3957 TA02b

3957f

24
 LT3957
TYPICAL APPLICATIONS
5V to 16V Input, 12V Output SEPIC Converter
CDC
4.7μF, 25V
L1A X5R D1
VOUT
VIN
12V

•
5V TO 16V CIN COUT 1A
4.7μF L1B 22μF
25V 200k VIN SW 16V
X5R • X5R
EN/UVLO GND s2
82.5k
LT3957
SGND SENSE1
SYNC SENSE2 105k
FBX
RT SS VC INTVCC 15.8k

41.2k CVCC
10k
300kHz 0.47μF 4.7μF
10V
10nF X5R

3957 TA03a

CIN, CDC: MURATA GRM21BR61E475KA12L

COUT: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100

Efficiency vs Output Current Load Step Waveforms

100
VIN = 12V VIN = 12V
95
90
VOUT
85 0.5V/DIV
EFFICIENCY (%)

(AC)
80
75
70 IOUT 0.8A
0.5A/DIV
65 0.2A

60
3957 TA03c
55 500μs/DIV

50
0 200 400 600 800 1000
OUTPUT CURRENT (mA) 3957 TA03b

Frequency Foldback Waveforms

Start-Up Waveforms When Output Short-Circuit
VIN = 12V VIN = 12V

VOUT
10V/DIV

VOUT
5V/DIV VSW
20V/DIV

IL1A + IL1B IL1A + IL1B

2A/DIV 5A/DIV

3957 TA03d 3957 TA03e

5ms/DIV 50μs/DIV

3957f

25
LT3957
TYPICAL APPLICATIONS
5V to 16V Input, –12V Output Inverting Converter
CDC
4.7μF, 50V
L1A X7R L1B VOUT
VIN
–12V

•
5V TO 16V CIN COUT 1A
4.7μF D1 22μF
25V 200k VIN SW 16V
X5R X5R
EN/UVLO GND s2
82.5k
LT3957
SGND SENSE1
SYNC SENSE2 105k
FBX
RT SS VC INTVCC 7.5k

41.2k CVCC
10k
300kHz 0.47μF 4.7μF
10V
10nF X5R

3957 TA04a

CIN: MURATA GRM21BR61E475KA12L

CDC: TAIYO YUDEN UMK316BJ475KL
COUT: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100

Efficiency vs Output Current Load Step Waveforms

100
VIN = 12V VIN = 12V
95
90
85 VOUT
EFFICIENCY (%)

1V/DIV
80
(AC)
75
IOUT 0.8A
70
0.5A/DIV
65 0.2A

60
3957 TA04c
55 500μs/DIV

50
0 200 400 600 800 1000
OUTPUT CURRENT (mA) 3957 TA04b

Frequency Foldback Waveforms

Start-Up Waveforms When Output Short-Circuit
VIN = 12V VIN = 12V
VOUT
VOUT 10V/DIV
5V/DIV

VSW
20V/DIV
IL1A + IL1B
2A/DIV
IL1A + IL1B
5A/DIV

3957 TA04d 3957 TA04e

5ms/DIV 50μs/DIV

3957f

26
 LT3957
PACKAGE DESCRIPTION
UHE Package
Variation: UHE28MA
36-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1836 Rev B)
28 27 25 24 23 21 20

0.70 p0.05

30 17
1.88 1.53
31 p 0.05 p 0.05 16
5.50 p 0.05
32 3.00 p 0.05 3.00 p 0.05 15
4.10 p 0.05
33
0.12 14
p 0.05 PACKAGE OUTLINE
34 0.48 p 0.05 13
1.50 REF
35 12
36

1 2 3 4 6 8 9 10
0.25 p0.05
0.50 BSC
2.00 REF
5.10 p 0.05
6.50 p 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 p 0.05 PIN 1 NOTCH

5.00 p 0.10 R = 0.10 1.50 REF R = 0.30 OR
TYP 30 31 32 33 34 35 36 0.35 s 45o
CHAMFER
PIN 1 28
TOP MARK 1
(NOTE 6) 27 2
1.88 p 0.10
2.00 REF 3.00 p 0.10 3
0.12
25 p 0.10 4
24
6.00 p 0.10
23 6
0.48 p 0.10
1.53 p 0.10 8 R = 0.125
21
3.00 p 0.10 TYP
20 9

10

0.40 p 0.10

0.200 REF 17 16 15 14 13 12
0.25 p 0.05 (UHE28MA) QFN 0409 REV B
0.00 – 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3957f

27
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3957
TYPICAL APPLICATIONS
4V to 6V Input, 180V Output Flyback Converter

DANGER! HIGH VOLTAGE!

T1 D1
1:10 VOUT
VIN
180V
4V TO 6V
• 15mA
CIN
100μF
6.3V •
s2 COUT
D2 68nF
s2
220pF
22Ω

75k VIN SW GND

1.80M
EN/UVLO FBX

37.4k SENSE1
LT3957
SGND 22Ω
SYNC SENSE2 15.8k

10nF
RT SS VC INTVCC
4.7μF
140k 0.1μF 10V
100kHz 10k
X5R
100pF
10nF

3957 TA05

T1: TDK DCT15EFD-U44S003

CIN: GRM31CR60J107ME39L
COUT: GRM43QR72J683KW01L
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: DIODES MMSZ5258B

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT3958 High Input Voltage, Boost, Flyback, SEPIC and 5V ≤ VIN < 80V, Current Mode Control, 100kHz to 1MHz Programmable
Inverting Converter with 3.5A/80V Switch Operation Frequency, 5mm × 6mm QFN-36 Package
LT3580 Boost/Inverting DC/DC Converter with 2A Switch, Soft- 2.5V ≤ VIN ≤ 32V, Current Mode Control, 200kHz to 2.5MHz, 3mm × 3mm
Start and Synchronization DFN-8, MSOP-8E
LT3573 Isolated Flyback Converter with 1.25A/60V Integrated 3V ≤ VIN ≤ 40V, No Opto-Isolator or "Third Winding" Required, Up to 7W,
Switch MSOP-16E
LT3574 Isolated Flyback Converter with 0.65A/60V Integrated 3V ≤ VIN ≤ 40V, No Opto-Isolator or “Third Winding” Required, Up to 3W,
Switch MSOP-16
LT3757 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
LTC1871/LTC1871-1/ Wide Input Range, No RSENSE™ Low Quiescent Current Adjustable Switching Frequency, 2.5V ≤ VIN ≤ 36V, Burst Mode Operation
LTC1871-7 Flyback, Boost and SEPIC Controller at Light Load
LTC3803/LTC3803-3/ 200kHz/300kHz Flyback DC/DC Controller VIN and VOUT Limited Only by External Components, ThinSOT™ Package
LTC3803-5

3957f

28 Linear Technology Corporation

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