PSoC® 5LP: CY8C58LP Family

PRELIMINARY Datasheet

5.7 Memory Map Table 5-5. Peripheral Data Address Map (continued)
The Cortex-M3 has a fixed address map, which allows Address Range Purpose
peripherals to be accessed by simple memory access
0x40004F00 – 0x40004FFF Fixed timer/counter/PWMs
instructions.
0x40005000 – 0x400051FF I/O ports control
5.7.1 Address Map
0x40005400 – 0x400054FF External Memory Interface
The 4-GB address space is divided into the ranges shown in (EMIF) control registers
Table 5-4:
0x40005800 – 0x40005FFF Analog Subsystem Interface
Table 5-4. Address Map 0x40006000 – 0x400060FF USB Controller

Address Range Size Use 0x40006400 – 0x40006FFF UDB Configuration

0x00000000 – 0.5 GB Program code. This includes 0x40007000 – 0x40007FFF PHUB Configuration
0x1FFFFFFF the exception vector table at 0x40008000 – 0x400087FF EEPROM
power up, which starts at
address 0. 0x4000A000 – 0x4000A400 CAN
0x20000000 – 0.5 GB Static RAM. This includes a 1 0x4000C000 – 0x4000C800 Digital Filter Block
0x3FFFFFFF MByte bit-band region 0x40010000 – 0x4001FFFF Digital Interconnect Configuration
starting at 0x20000000 and a
32 Mbyte bit-band alias 0x48000000 – 0x48007FFF Flash ECC Bytes
region starting at 0x60000000 – 0x60FFFFFF External Memory Interface
0x22000000. (EMIF)
0x40000000 – 0.5 GB Peripherals. 0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
0x5FFFFFFF
including NVIC, debug, and trace
0x60000000 – 1 GB External RAM.
0x9FFFFFFF
The bit-band feature allows individual bits in SRAM to be read or
0xA0000000 – 1 GB External peripherals. written as atomic operations. This is done by reading or writing
0xDFFFFFFF bit 0 of corresponding words in the bit-band alias region. For
0xE0000000 – 0.5 GB Internal peripherals, including example, to set bit 3 in the word at address 0x20000000, write a
0xFFFFFFFF the NVIC and debug and 1 to address 0x2200000C. To test the value of that bit, read
trace modules. address 0x2200000C and the result is either 0 or 1 depending
on the value of the bit.
Table 5-5. Peripheral Data Address Map Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
Address Range Purpose accesses of words and 16-bit half-words on nonword boundary
0x00000000 – 0x0003FFFF 256 KB flash addresses can also be done, although they are less efficient.

0x1FFF8000 – 0x1FFFFFFF 32 KB SRAM in Code region 5.7.2 Address Map and Cortex-M3 Buses
0x20000000 – 0x20007FFF 32 KB SRAM in SRAM region The ICode and DCode buses are used only for accesses within
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators the Code address range, 0 - 0x1FFFFFFF.

0x40004300 – 0x400043FF Power management The System bus is used for data accesses and debug accesses
within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000
0x40004500 – 0x400045FF Ports interrupt control - 0xFFFFFFFF. Instruction fetches can also be done within the
0x40004700 – 0x400047FF Flash programming interface range 0x20000000 - 0x3FFFFFFF, although these can be slower
than instruction fetches via the ICode bus.
0x40004800 – 0x400048FF Cache controller
The private peripheral bus (PPB) is used within the Cortex-M3 to
0x40004900 – 0x400049FF I2C controller access system control registers and debug and trace module
0x40004E00 – 0x40004EFF Decimator registers.

Document Number: 001-84932 Rev. ** Page 20 of 122