PRoBLEMs 153 PROBLEMS Answers to problems marked by an asterisk are given at the back of the book. 3.1. Consider the circuit shown in Figure P3.1. (a) Show the truth table for the logic function f. (b) If each gate in the circuit is implemented as a CMOS gate, how many transistors are needed? y Figure P3.1. A sum-of-products CMOS circuit. 3.2 (a) Show that the circuit in Figure P3.2 is functionally equivalent to the circuit in Figure PRA. ({b) How many transistors are needed to build this CMOS circuit? s—bo , -« Figure P3.2. A CMOS circuit built with multiplexers. 3.3 (a) Show that the circuit in Figure P3.3 is functionally equivalent to the circuit in Figure P32. (b) How many transistors are needed to build this CMOS circuit if each XOR gate is implemented using the circuit in Figure 3.61d°? 153"3.4 3.5 3.6 3.7 154 CHAPTER 3 © IMPLeMeNTation TecHNOLoGy x A ¥: Figure P3.3 Circuit for problem 3.3. In Section 3.8.8 we said that a six-input CMOS AND gate can be constructed using two three-input AND gates and a two-input AND gate. This approach requires 22 transistors, Show how you can use only CMOS NAND and NOR gates (o build the six-input AND gate, and calculate the number of transistors needed. (Hint: use DeMorgan’s theorem.) Repeat problem 3.4 for an eight-input CMOS OR gate. (a) Give the truth table for the CMOS circuit in Figure P3.4, (b) Derive a canonical sum-of-products expression for the truth table from part (a). How many transistors are needed to build a circuit representing the canonical form if only AND, OR, and NOT gates are used? Figure P3.4_ A three-input CMOS circuit. (a) Give the truth table for the CMOS circuit in Figure P3.5. (b) Derive the simplest sum-of-products expression for the truth table in part (a), How many transistors age needed to build the sum-of-products circuit using CMOS AND, OR and NOT gates?PRosLems 155 Yop 4 vy Lt Figure P3.5 A four-input CMOS circuit. *3.8 Figure P3.6 shows half of a CMOS circuit. Derive the other half that contains the PMOS transistors. Y, _ at Figure P3.6 The PDN in a CMOS circuit. 155CHAPTER 3 © IMPLEMENTATION TECHNOLOGY 3.9 Figure P3.7 shows half of a CMOS circuit. Derive the other half that contains the NMOs transistors. m4 ' rfl | Vy, Figure P3.7 The PUN in a CMOS circuit. 3.10 Derive a CMOS complex gate for the logic function f (x1, x2, 3,4) = Dm(0, 1, 2,4, 5, 6,8, 9, 10). 3.11 Derive a CMOS complex gate for the logic function f (x1, x2,.%3,.%4) = Do m(0, 1, 2, 4,6, 8, 10, 12, 14) 3.12 Derive a CMOS complex gate for the logic function f = xy +.xz. Use as few transistors as possible (Hint: consider). 3.13 Derive a CMOS complex gate for the logic function f' = xy +z + yz. Use as few transis- tors as possible (Hint: consider). 3.14 For an NMOS transistor, assume that k= 20 wA/V?, W/L = 2.5 m/0.5 em, Vos = 5 V,and Vr = 1 V. Calcutate (a) Ip when Vis =5.V (b) fy when Vps = 0.2 3.15 For a PMOS transistor, assume that & = 10 wA/V2, W/L = 2.5 umm/0.5 jum, Vos = =5V, and Vr = —I V, Calculate (a) Ip when Vps = -5V (b) Ip when Vas = —0.2 V 3.16 For an NMOS transistor, assume that k= 20 pA/V?, W/L = 5.0 xm/0.5 um, Vos = 5 V,and Vr = 1 V. For small Vps, calculate Ros. 3.17 For an NMOS transistor, assume that k) = 40 A/V". W/L = 3.5 um/0.35 jum, Vos 3.3 V, and Vr = 0.66 V. For small Vas, 1563.18 3.19 3.20 3.21 PROBLEMS 157 For a PMOS transistor, assume that k, = 10 BA/V?, W/L = 5.0 um/0.5 um, Ves = —5 V, and Vr = —1 V. For Vps = —4.8 V, calculate Rps. For a PMOS transistor, assume that ki, = 16 wA/V?, W/L = 3.5 xm/0.35 pm, Vos = —3.3 V, and Vr = —0.66 V. For Vis = —3.2V, calculate Rps In Example 3.13 we showed how to calculate voltage levels in a pseudo-NMOS inverter. Figure P3.8 depicts a pseudo-PMOS inverter. In this technology, st weak NMOS transistor is used to implement a pull-down resistor. When V, = 0, ¥; has a high value. The PMOS transistor is operating in the triode region, while the NMOS transistor limits the current flow, because it is operating in the saturation region, The current through the PMOS and NMOS transistors has to be the same and is given by equations 3.1 and 3.2. Find an expression for the high-output voltage, Vj = Vor, in terms of Vpp, Vr, kp, and k,, where k, and k, are gain factors as defined in Example 3.13. Yop % Figure P3.8 The pseudo-PMOS inverter. For the circuit in Figure P: 0.5 jum/0.5 wm, W,/Ly calculate the following: (a) The static current, fear (b) The on-resistance of the PMOS transistor (©) Vou (4) The static power dissipated in the inverter (€) The on-resistance of the NMOS transistor (8) Assume that the inverter is used to drive a capacitive load of 70 fF. Using equation 3.4, calculate the low-to-high and high-to-low propagation delays. . assume the values ky, = 60 A/V", ki = 0.4K), Wy /Ln 0 m/0.5 um, Vpp = 5 Vand Vp = 1 V. When V, = 1573.22 3.23 3.24 *3.25 3.26 3.27 *3.28 3.29 3.30 3.31 *3.32 3.33 3.34 158 CHAPTER 3 + IMPLEMENTATION TECHNOLOGY Repeat problem 3.21 assuming that the size of the NMOS transistor is changed to W,/Ly = 4.0 um/0.5 um. Example 3.13 (see Figure 3.72) shows that in the pscudo-NMOS technology the pull-up device is implemented using a PMOS transistor. Repeat this problem for a NAND gate built with pseudo-NMOS technology. Assume that both of the NMOS transistors in the gate have the same parameters, as given in Example 3.14. Repeat problem 3.23 for a pseudo-NMOS NOR gate. (a) For Vin = 4 V, Vou = 4.5 V, Vi. = 1 V, Vor = 0.3 V, and Vpn = 5 V, calculate the noise margins NMy and NM, (b) Consider an cight-input NAND gate built using NMOS technology. If the voltage drop across each transistor is 0,1 V, what is Vo,? What is the corresponding NM; using the other parameters from part (a). Under steady-state conditions, for an n-input CMOS NAND gate, what are the voltage levels of Vor and Vow? Explain. For a CMOS inverter, assume that the load capacitance is C = 150 {F and Vpp = 5 V. The inverter is cycled through the low and high voltage levels at an average rate of f = 75 MHz. (a) Calculate the dynamic power dissipated in the inverter. (b) For a chip that contains the equivalent of 250,000 inverters, calculate the total dynamic power dissipated if 20 percent of the gates change values at any given time. Repeat problem 3.27 for C = 120 fF, Von = 3.3 V, and f = 125 MHz. Ina CMOS inverter, assume that ki = 20 A/V", k/, = 0.4%), Wa /Lq = 5.0 jemn/0.5 jem, Wp/Lp = 5.0 um/0.5 um, and Vpp = 5 V. The inverter drives a load capacitance of 130 fF. (a) Find the high-to-low propagation delay. (b) Find the low-to-high low propagation delay. (c) What should be the dimensions of the PMOS transistor such that the low-to-high and high-to-low propagation delays are equal? Ignore the effect of the PMOS transistor’s size on the load capacitance of the inverter. Repeat problem 3.29 for the parameters k, = 40 wA/V?, 3.5 xm/0.35 jem, and Vpp = 3.3 V. Ina CMOS inverter, assume that W,/L, = 2 and W,/Ly = 4. Fora CMOS NAND gate, calculate the required W/L ratios of the NMOS and PMOS transistors such that the available current in the gate to drive the output both low and high is equal to that in the inverter. Repeat problem 3.31 for a CMOS NOR gate. Repeat problem 3.31 for the CMOS complex gate in Figure 3.16. The transistor sizes should be chosen such that in the worst case the available current is at least as large as i the inverter. K, = 04x kj, Wa/Ln = Wp/Lp = Repeat problem 3.31 for the CMOS complex gate in Figure 3.17.3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42 3.43 3.44 "3.45 3.46 PROBLEMS 159 In Figure 3.69 we showed a solution to the static power dissipation problem when NMOS. pass transistors are used. Assume that the PMOS pull-up transistor is removed from this circuit. Assume the parameters k), = 60 wA/V?, k, = 0.4 xk, Wr /Ln = 1.0 um/0.25 wm, Wy/Lp = 2.0 pm/0.25 jum, Vpp = 2.5 V, and Vr = 0.6 V. For Va = 1.6 V, calculate the following: (a) the static current, Jigar (b) the voltage, Vj, at the output of the inverter (c) the static power dissipation in the inverter (a) If a chip contains 500,000 inverters used in this manner, find the total static power dissipation. / Using the style of drawing in Figure 3.66, draw a picture of a PLA programmed to implement AiGs1,%2,X3) = Dm(1, 2,4, 7). The PLA should have the inputs x1, ....x35 the product terms Pj, ...,P4; and the outputs fy and fa. Using the style of drawing in Figure 3.66, draw a picture of a PLA programmed to implement fu(s1,X3.%3) = m0. 3, 5, 6). The PLA should have the inputs x, ...,.x5; the product terms P,,..., P45 and the outputs fi and fy. Show how the function f; from problem 3.36 can be realized in a PLA of the type shown in Figure 3.65. Draw a picture of such a PLA programmed to implement fi. The PLA should have the inputs x1, ...,.x3; the sum terms $), ..., Sy; and the outputs f; and fs. Show how the function fi from problem 3.37 can be realized in a PLA of the type shown in Figure 3.65. Draw a picture of such a PILA programmed to implement fi. The PLA should have the inputs x), ...x3; the sum terms S), ..., Sa; and the outputs fi and fs. Repeat problem 3.38 using the style of PLA drawing shown in Figure 3.63 Repeat problem 3.39 using the style of PLA drawing shown in Figure 3.63. Given that f; is implemented as described in problem 3.36, list all of the other possible logic functions that can be realized using output f; in the PLA. Given that f; is implemented as described in problem 3.37, list all of the other possible logic functions that can be realized using output /3 in the PLA. Consider the function f (1, x2,.%3) = x1%2-+.x1x3 +323. Show a circuit using 5 two-input lookup-tables (LUTs) to implement this expression, As shown in Figure 3.39, give the truth table implemented in each LUT. You do not need to show the wires in the FPGA. Consider the function f (x1, x2, x3) = Yo m(2. 3, 4, 6, 7). Show how it can be realized using two two-input LUTS. As shown in Figure 3.39, give the truth table implemented in each LUT. You do not need to show the wires in the FPGA. Given the function f = xixoxs + xoxsFs + a straightforward implementation in an FPGA with three-input LUTs requires four LUTs. Show how it can be done using only 3 threc-input LUTs. Label the output of each LUT with an expression representing the logic function that it implements. 1593.47 3.48 3.49 3.50 3.51 160 CHAPTER 3 © IMPLEMENTATION TECHNOLOGY For fin problem 3.46, show a circuit of two-input LUTs that realizes the function. You are to use exactly seven two-input LUTs. Label the output of each LUT with an expression representing the logic function that it implements. Figure 3.39 shows an FPGA programmed to implement a function. The figure shows one pin used for function f, and several pins that are unused. Without changing the programming of any switch that is turned on in the FPGA in the figure, list 10 other logic functions, in addition to f, that can be implemented on the unused pins. Assume that a gate array contains the type of logic cell depicted in Figure P3. in, ..., iny can be connected to either | or 0, or to any logic signal. (a) Show how the logic cell can be used to realize f = x12 +.x3 (b) Show how the logic cell can be used to realize f = x13 +4283. . The inputs inl ind in3 out ind inS in6 in7 Figure P3.9 A gote-array logic cel. Assume that a gate array exists in which the logic cell used is a three-input NAND gate. The inputs to each NAND gate can be connected to either | or O, or to any logic signal. Show how the following logic functions can be realized in the gate array. (Hint: use DeMorgan’s theorem.) (a) f = x32 +23 (b) f= xyx2X4 t+ x2¥3%4 + Write VHDL code to represent the function Sf = xo¥a¥a + Xpxney + Fpxnts + xprary (a) Use your CAD tools to implement f in some type of chip, such as a CPLD. Show the logic expression generated for f by the tools. Use timing simulation to determine the time needed for a change in inputs x;, x2, or x3 to propagate to the output f. (b) Repeat part (a) using a different chip, such as an FPGA for implementation of the circuitPROBLEMS 161 3.52 Repeat problem 3.51 for the function S = (x1 x2 + Fa) + +43 +4) Cr +3 +4) + Hr +23 +4) 3.53 Repeat problem 3.5] for the function LO, oo 87) = xaxske + a1aNs Ke + xaxary + xax4AS 7 3.54 What logic gate is realized by the circuit in Figure P3.10? Does this circuit suffer from any major drawbacks? Figure P3.10 Circuit for problem 3.54. *3.55 What logic gate is realized by the circuit in Figure P3.11? Does this circuit suffer from any major drawbacks? rly Hy Figure P3.11 Circuit for problem 3.55. 161