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Digital Design Lab

The document describes the implementation of an unsigned 4-bit multiplier in Verilog. It uses four half adders and eight full adders. The RTL schematic, design summary, and simulation output showing the multiplication of two 4-bit numbers are presented. It is concluded that the unsigned multiplier has been implemented as intended.

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SHAIK MUSTHAFA
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59 views8 pages

Digital Design Lab

The document describes the implementation of an unsigned 4-bit multiplier in Verilog. It uses four half adders and eight full adders. The RTL schematic, design summary, and simulation output showing the multiplication of two 4-bit numbers are presented. It is concluded that the unsigned multiplier has been implemented as intended.

Uploaded by

SHAIK MUSTHAFA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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endmodule

RTL SCHEMATIC:-

Fig 4.2:- RTL schematic

DESIGN SUMMARY:-

Fig 4.3:- Design Summary

RESULTS:-

Fig 4.4:- Simulation output

CONCLUSION:- The Unsigned Multiplier (Brown’s Multiplier) is implemented in Verilog. Above


multiplier is used for multiplication of two 4-bit binary numbers. It utilises four Half Adders and eight
Full Adders.

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reg reset;

reg clk;

reg [3:0] n;

// Outputs

wire [7:0] out;

// Instantiate the Unit Under Test (UUT)

sum uut (.reset(reset), .out(out), .clk(clk), .n(n));

initial begin

// Initialize Inputs

reset = 0;

clk = 0;

n = 0;

// Wait 100 ns for global reset to finish

n=15;

reset=1;

#20;

reset=0;

end

always #10 clk=~clk;

// Add stimulus here

endmodule

RTL SCHEMATIC :-

Fig 5.1:-RTL Schematic

28 | P a g e
DESIGN SUMMARY:-

Fig 5.2:- Design Summary

RESULTS:-

Fig 5.3:- Simulation outputs

CONCLUSION:- The sum of the N natural numbers design implemented using Verilog.The
Number of Slices ,Flipflops, 4input LUTs,bonded IOBs and GCLKs used are 7,12,15,14 and 1
respectively.

38 | P a g e
RTL SCHEMATIC:-

Fig 6.2:- RTL Schematic

DESIGN SUMMARY:-

Fig 6.3:- Design Summary

RESULTS:-

Fig 6.4:- Simulation output

CONCLUSION:- BCD number is different than binary number. The BCD number system
number are represented up to 9 eg :- 15=1111(binary form), 15=00010101(BCD format)

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RESULTS:-

Fig 11.4 Simulation output

CONCLUSION:- The above serial to parallel converter takes input serially and produce
output parallel. It has used 24 slices, 36 slice flipflops 44-input LUT, 1 GCLK, and 7 IOBs.

58 | P a g e
RTL SCHEMATIC:-

Fig 12.1:- RTL Schematic

DESIGN SUMMARY:-

Fig12.2:- Design Summary

RESULTS:-

Fig 12.3:- Simulation output

CONCLUSION:- RAM is implemented using Verilog. We have done both Read and Write
operation. RAM is Volatile memory and it is divided into two types, static RAM which uses
flipflops as storage elements and Dynamic RAM which uses capacitor to store binary
information.

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RESULTS:-

Fig 13.3 Simulation output

CONCLUSION:- Row to Column decoder takes 4 different inputs up to fourth clock pulse

And from fifth clock pulse Row inputs are converted to Column clock pulse.

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