Rukmini Educational

Charitable Trust

Digital Electronics and

VHDL Laboratory
Manual
B18EC3080

School of Electronics and

Communication Engineering

www.reva.edu.in

Campus Address: Rukmini Knowledge Park, Kattigenahalli, Yelahanka, Bengaluru - 560 064
 REVA University School of ECE

CONTENTS
Sl. Experiment / Page
Description
No. Program No No.
Part A Digital Electronics
1. Course Objectives & Syllabus 02
2. Syllabus / Lab Experiments: 03
3. Introduction 04
4. Front Panel of Digital IC Trainer Kit 32
5. Realization of Logic gates 39
6. 1 Realization of Parallel Adder / Subtractor using IC 7483 43
7. 2 4 Bit Binary to Gray Code conversion and Vice-Versa 55
8. 3 Realization of 4:1 Multiplexer and 1:4 De-multiplexer 60
Arithmetic Circuit realization (Half/Full Adder/ Full Subtractor)
9. 4 75
using Mux
Construction and verification of JK Master-Slave, T type & D type
10. 5 84
Flip-Flops using logic gates
Construction and realization of 3 bit ripple up/down counter using
11. 6 90
IC 7476 and other logic gates
Design and verification of mod-n, 3bit synchronous counter using
12. 7 101
7476 JK FF.
13. Challenge Experiments 104
14. Frequently Asked Viva Questions 105
15. Digital IC’s PIN Details 107
Part B VHDL
1. VHDL Language Overview 113
2. To write a VHDL Code to realize all the Logic gates. 121
3. 1a To write a VHDL Code to realize a 2 to 4 Decoder. 125
4. 1b To write a VHDL Code to realize an 8 to 3 Encoder. 129
5. 1c To write a VHDL Code to realize an 8 to 1 Multiplexer. 133
6. 1d Write VHDL code for 1 TO 4 DEMUX. 135
7. 1e Write VHDL code for N-BIT COMPARATOR. N<3. 137
Write a VHDL code to describe a FULL ADDER using different
8. 2 140
Styles/Types of Description.
To write a VHDL code for a 4 bit binary and 4bit BCD counters
9. 3 144
with Synchronous and Asynchronous reset using Clock Division.
10. 4 Write a VHDL code to control speed, direction of Stepper motor. 148
Write a VHDL code to control speed, direction of DC Motor
5. 154
(PWM Technique).
11. I/O PIN details. 157
12. Model viva questions. 158
13. Viva question and answers. 160

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B18EC3080 L T P C
Digital Electronics and VHDL Lab
Duration :16Wks 0 0 2 2
Prerequisites:

Number system, Fundamentals of Digital Electronics, programming skills.

Course Objectives:

The objectives of this course are to:

1. Design, realization and verification of Boolean Theorems, logic expressions
2. Realize various arithmetic, data path modules, memory modules
3. Understand the FPGA design flow
4. Simulate, synthesize various digital blocks by using VHDL code

Course Outcomes:

On completion of this course the student shall be able to:

1. Verify the truth table for given Boolean function and theorem(a,b,e,k)
2. Design and verification of arithmetic, data path modules, memory modules (a,b,e,k)
3. Develop and debug the codes for various digital blocks (a,b,e,k)
4. Implement and analyze the digital blocks on the targeted FPGA device (a,b,e,k)

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Syllabus
Digital Electronics and VHDL Lab - B18EC3080
Lab Experiments:

1. Realization of parallel Adder and Subtractor.

2. Realization of 3 bit Binary to Grey code conversion and vice versa using basic/Universal
gates.
3. Realization of 4:1 MUX and 1:4 DEMUX using basic/universal gates.
4. Arithmetic circuit realization (Half/Full, Adder/Subtractor) using MUX.
5. Construction and verification of JK master slave, T, D flip flop using logic gates.
6. Construction and realization of n- bit ripple up/down counter using IC 7476 and other
logic gates.
7. Design and verification of n-bit synchronous counter using 7476 JK, T and D flip flops.
8. Write a VHDL program for the following modules.
a. Decoder
b. Encoder with and without priority
c. Multiplexer
d. De-multiplexer
e. Comparator
9. Write a VHDL code to describe function of full adder in data flow, behavioral and
structural style
10. Write VHDL code for a 4-bit binary, BCD counters with synchronous and asynchronous
reset
11. Write a HDL code to control speed and directions of a Stepper motor
Demo experiments
12. Write a HDL code to generate waveforms of different frequency and amplitude using a
DAC.
13. Simulation of digital circuits

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Introduction
In 1854 George Boole introduced a systematic treatment of logic and developed an algebraic
system now known as Boolean algebra. In 1938, C.E. Shannon introduced a two valued
Boolean algebra called switching algebra, which demonstrated that, the properties of bi-stable
electrical switching circuits could be represented through this algebra. With passage of time
Boolean algebra has emerged as a powerful tool and forms the foundation of many theories
of computer science and engineering.

Boolean algebra like any other mathematical system may be defined with a set of elements, a
set of operators and number of axioms or postulates. A set of element is a collection of
objects having a common property.

A logic gate is an elementary building block of a digital circuit. Most logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary
conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic
gates, the low state is approximately zero volts (0 V), while the high state is approximately
five volts positive (+5 V).

There are three basic logic gates: AND, OR, & NOT, and two Universal logic gates NAND
and NOR other logic gates are emerged from basic gates such as X-OR and X-NOR.
Comparing Boolean algebra with arithmetic and ordinary algebra we note the following
differences:

Boolean algebra does not have additive or multiplicative inverses; hence there are no
subtraction or division operations.
Boolean algebra defines an operator called complement which is not available in
normal algebra.
Normal algebra deals with real number, which constitute an infinite set of elements
where as Boolean algebra deals with a set of only two elements 0 and 1 (defined as
two valued Boolean algebra).
The distributive law of '+' over '.' i.e., x + (y. z) = (x + y). (x + z) is valid for Boolean
algebra but not for normal algebra.

Using combinations of logic gates, complex operations can be performed. In theory, there is
no limit to the number of gates that can be arrayed together in a single device. But in practice,
there is a limit to the number of gates that can be packed into a given physical space. Arrays
of logic gates are found in digital integrated circuits (lC’s).

As IC technology advances, the required physical volume for each individual logic gate
decreases and digital devices of the same or smaller size become capable of performing ever-
more complicated operations at ever-increasing speeds.

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Why are NAND and NOR Gates called Universal Gates?

They are called universal gates because all of the other gates may be constructed using only
those two gates. That is important because it's a lot cheaper in practice to make lots of similar
things than a bunch of different things (different gates).

All other gates/functions can be implemented by NOR or NAND gates. So they are called
universal gates. In fact, in chips, entire logic maybe built using only NAND or NOR gates.

Eg: Inverter - NAND with inputs shorted,

AND - NAND followed by an inverter (using NAND) OR - giving inverted inputs to
NAND gate.

Implementing with NAND is easier when considering power and area of the chip. They are
called universal gates as they can be used to design all other logic circuit. Elements like X-
OR, NOR etc. Also these gates can be realized through easy combination of diodes thus
making them easy to use base elements in any chip designing project.

NAND, NOR gates are called universal gates because they can be used to create all the
remaining logical gates. Like sending the same input to the inputs of the NAND or NOR will
make it a NOT gate. Because from them you can create any other one! You can make any
other gate using NAND and NOR. Any other gate i.e. AND, OR, XOR etc can be created
using these basic gates i.e. it needs only NAND and NOR gates to create logical circuits.

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NAND Gate

In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output
which is false only if all its inputs are true; thus its output is complement to that of an AND
gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is
LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction
diodes. By De Morgan's theorem, a two-input NAND gate's logic may be expressed
as AB=A+B, making a NAND gate equivalent to inverters followed by an OR gate.

The NAND gate is significant because any Boolean function can be implemented by using a
combination of NAND gates. This property is called functional completeness. It shares this
property with the NOR gate. Digital systems employing certain logic circuits take advantage
of NAND's functional completeness.
The function NAND (a1, a2, ..., an) is logically equivalent to NOT(a1 AND a2 AND ...
AND an).
NAND gates with two or more inputs are available as integrated circuits in transistor-
transistor logic, CMOS, and other logic families.

Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

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NOR Gate

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to
the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW
(0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of
the negation of the OR operator. It can also be seen as an AND gate with all the inputs
inverted. NOR is a functionally complete operation—NOR gates can be combined to
generate any other logical function. It shares this property with the NAND gate. By contrast,
the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.
In most, but not all, circuit implementations, the negation comes for free—
including CMOS and TTL. In such logic families, OR is the more complicated operation; it
may use a NOR followed by a NOT. A significant exception is some forms of the domino
logic family.

Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

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AND Gate

The AND gate is a basic digital logic gate that implements logical conjunction - it behaves
according to the truth table to the right. A HIGH output (1) results only if all the inputs to the
AND gate are HIGH (1). If none or not all inputs to the AND gate are HIGH, a LOW output
results. The function can be extended to any number of inputs.

Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

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OR Gate

The OR gate is a digital logic gate that implements logical disjunction – it behaves according
to the truth table to the right. A HIGH output (1) results if one or both the inputs to the gate
are HIGH (1). If neither input is high, a LOW output (0) results. In another sense, the
function of OR effectively finds the maximum between two binary digits, just as the
complementary AND function finds the minimum.

Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

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NOT Gate

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation.
The truth table is shown on the right.

Truth Table
Input Output
A Y
0 1
1 0

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EXOR Gate

XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital logic
gate that gives a true (1 or HIGH) output when the number of true inputs is odd. An XOR
gate implements an exclusive or; that is, a true output results if one, and only one, of the
inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output
results. XOR represents the inequality function, i.e., the output is true if the inputs are not
alike otherwise the output is false. A way to remember XOR is "one or the other but not
both".
XOR can also be viewed as addition modulo 2. As a result, XOR gates are used to implement
binary addition in computers. A half adder consists of an XOR gate and an AND gate. Other
uses include subtractors, comparators, and controlled inverters.

Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

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Front Panel of Digital IC Trainer Kit

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Identification of Controls on Digital IC Trainer Kit

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Note: Use Patch chords smoothly & test Patch Chord Continuity for every circuit before
connecting.

To Test, connect Patch chord end A to Input Zero (GND) & B to output LED Indicator. If
LED Glows Green (0) then the patch chord is good or else Replace the patch chord.

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Realization of Logic gates

Aim: To study the operation of Logic gates
1. AND Gate
2. OR Gate
3. NOT Gate
4. EX-OR Gate
5. NAND Gate
6. NOR Gate
Components &equipment’s required: 74LS:08, 32, 04, 86, 00 & 02, IC Trainer Kit, 4mm.
Patch cards etc.

1. AND Gate: IC 7408:

Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

2. OR Gate: IC 7432:

Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

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3. NOT Gate: IC 7404:

Truth Table
Input Output
A Y
0 1
1 0

4. EX-OR Gate: IC 7486:

Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

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5. NAND Gate: IC 7400:

Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

6. NOR Gate: IC 7402:

Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

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7. Truth Table verification of Logic gates using NAND & NOR gates (Universal gates)

Function Using NAND gates Using NOR gates

NOT
gate

AND
gate

OR gate

EX-OR
gate

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 1
Realization of Parallel Adder and Subtractor
Aim: Realization of Parallel Adder and Subtractor using IC 7483.

Parallel adder:
The 7483 IC is a 4-bit parallel adder chip. Note: the chip can also be listed as a 74LS83. The
LS signifies that the chip is a newer, lower-power, faster version. A binary parallel adder is a
digital function that produces the arithmetic sum of two binary numbers in parallel. It consists
of full adders connected in cascades with the output carry from one full adder connected to
input carry of the next full adder.

Parallel adder Theory:

A parallel adder is an arithmetic combinational logic circuit that is used to add more than one
bit of data simultaneously. A full adder adds two bits and a carry to give an output. However,
to add more than one bit of data in length a parallel adder is used. A parallel adder adds
corresponding bits simultaneously using full adders and keeps generating a carry and pushing
it towards the next most significant bit to be added. An n-bit parallel adder uses n full adders
connected in cascade with each full adder adding the two corresponding bits of both the
numbers.
For example, for a binary number A3A2A1A0 and B3B2B1B0, a full adder connected in
cascade would add D0 and B0 and send the result to be displayed (LSB). If a carry is
generated, it will be passed on to the input of the next full adder.

How to design a 4-bit parallel adder?

To add two Hex codes we need four full adders connected in cascade. This is because a hex
code can be represented by four binary bits. The four full adders will connect to each other
via their CARRY outputs. And depending on the position of the bits the full adders add, the
SUM outputs of the full adders will be connected to the display. The least significant bit will
be connected to the LSB of the display. The most significant bit will be connected to the pin
one bit before the MSB of the display. The carry output of the final full adder will be
connected to the MSB pin of the display.
We can use two hex 4×4 keypads to generate the input bits or we can just add the bits
manually. If you want a circuit diagram without the hex keypads as inputs let us know in the
comments. Each row of the keypad is connected to a full adder depending on its significance.
The first full adder receives inputs from the first row of the hex keypad, the second
receives inputs from the second row of the hex keypad and the carry from the first and so on.
The resultant combinational logic circuit is shown below.

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How to design a 4-bit parallel Subtractor?

A 4-bit parallel subtractor is used to subtract a number consisting of 4 bits. This is done by
cascading a series of full subtractors. For an n-bit parallel subtractor, n full subtractors can be
cascaded to achieve the desired output. The connections are exactly the same as that of the 4-
bit parallel adder which we saw earlier in this post. Each of the bit is subtracted from its
corresponding bit of equal significance from the other number. A borrow if generated,
propagates through the cascade of full subtractors.
We use the same 4×4 hex keypads to input data in a full subtractor. The first rows (having the
least significance compared to the other rows) of the hex keypads are connected to the first
full subtractor. The second rows to the second full subtractor’s inputs along with the borrow
from the first full subtractor and so on. The output of each full adder is connected to the
display on the basis of their positional significance in the answer. i.e the output of the first
full subtractor is connected to the LSB of the display. The final borrow output of the final full
subtractor is connected to the MSB pin of the display.

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Components &equipments required: 7483, 7486 & 7404, Digital IC Trainer Kit, 4mm.
Patch cards etc.

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PIN Diagram:

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Circuit Diagram:

Note: A1, A2, A3, A4 & B1, B2, B3, B4 &Cin are the Inputs.
S1, S2, S3, S4 and Cout are the Outputs.
Here A1, B1 & S1 are the LSB Bits.
S is considered as selection Input to select for Addition or Subtraction.
For Addition S=0 & For Subtraction S=1.

4 Bit Adder Operation

If control input S = 0, Addition can be performed.

Example 1: When Cin = 0.
If A4 ,A3, A2, A1 = 1 1 0 0
B4, B3, B2, B1 = 0 0 1 1

Then Sum = S4, S3, S2, S1 = 1 1 1 1

In this Case Cout = 0

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Example 2: When Cin = 0.

If A4 ,A3, A2, A1 = 1 1 0 1
B4, B3, B2, B1 = 1 0 1 1

Then Sum = S4, S3, S2, S1 = 1 0 0 0

In this Case Cout = 1

Example 3: When Cin = 1

1
If A4 ,A3, A2, A1 = 1 1 0 1
B4, B3, B2, B1 = 1 0 1 1

Then Sum = S4, S3, S2, S1 = 1 0 0 1

In this Case Cout = 1

Problems:
A := 1111 1111 1100 1100 0111
B := 0000 0000 0011 0011 1110
Cin : = 0 1 0 1 1
Sum = (Do it yourself)

4 Bit Subtractor +Ve Result

Cout&Cin is shorted & S= 1 (Logic 1)

By normal Subtraction method

Example 1: Subtract
A4 ,A3, A2, A1 = 1 0 0 1
B4, B3, B2, B1 = 0 0 1 1 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = 0 1 1 0

By 1’s Compliment method

I Step: B4, B3, B2, B1 = 0 0 1 1 given number

= 1 1 0 0 1’s complement of Subtrahend.

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II Step:
Adding 1’s complement of Subtrahend to the minuend
A4 ,A3, A2, A1 = 1 0 0 1 Given Larger Number
B4, B3, B2, B1 = + 1 1 0 0
=1 0101

End around carry.

III Step:
Add end around carry to the result.
0 1 0 1 Result except carry
+ 1 Adding carry
0 1 1 0 True Result – Trainer Kit

By 2’s Compliment method

In this case, Cin& S are held at logic 1.

Example 1: Subtract
A4 ,A3, A2, A1 = 1 0 0 1
B4, B3, B2, B1 = 0 0 1 1 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = 0 1 1 0

I Step: B4, B3, B2, B1 = 0 0 1 1 given number

= 1 1 0 0 1’s complement of Subtrahend.
+ 1 Adding 1 to get 2’s Complement.
= 1 1 0 1 2’s omplement of subtrahend.

II Step:
A4 ,A3, A2, A1 = 1 0 0 1 Given Larger Number
B4, B3, B2, B1 = + 1 1 0 1
1 0110

Carry generated

III Step:
Neglect the carry to get true Answer
Therefore Answer = 0 1 1 0 - Trainer Kit

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4 Bit Subtractor – Ve Result

Cout&Cin is shorted & S= 1 (Logic 1)

By normal Subtraction method
Example 1: Subtract
A4 ,A3, A2, A1 = 0 0 1 1 3
B4, B3, B2, B1 = 1 0 0 1 9 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = -6

By 1’s Compliment method

I Step: B4, B3, B2, B1 = 1 0 0 1 given number

= 0 1 1 0 1’s complement of Subtrahend.

II Step:
Adding 1’s complement of Subtrahend to the minuend
A4 ,A3, A2, A1 = 0 0 1 1 Given Larger Number
B4, B3, B2, B1 = +0 1 1 0
= 1 0 0 1 Trainer Kit Final Output

Here No End around carry.

III Step:
Here theoretically perform 1’s Compliment operation to get True Answer.
1 0 0 1 (Trainer Kit Output)
1’s Compliment
0 1 1 0 True Answer

By 2’s Compliment method

In this case, Cin & S are held at logic 1.

Example 1: Subtract
A4 ,A3, A2, A1 = 0 0 1 1 3
B4, B3, B2, B1 = 1 0 0 1 9 Give this from Trainer Kit

Then Difference = S4, S3, S2, S1 = -6

I Step: B4, B3, B2, B1 = 1 0 0 1 given number

=0110 1’s complement of Subtrahend.
+ 1 Adding 1 to get 2’s Complement.
= 0111 2’s Complement of subtrahend.

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II Step:
A4, A3, A2, A1 = 0 0 1 1 Given Larger Number
B4, B3, B2, B1 = + 0 1 1 1
1 0 1 0 Trainr Kit Final Output

Carry Not generated

III Step: Here theoretically perform 2’s Compliment operation to get True Answer.
1 0 1 0 (Trainer Kit Output)
2’s Compliment
0 1 1 0 True Answer

Problems:
A := 0110 1100 0100 0111 1111
B := 0100 0111 0110 1100 1111

Diff = (Do it yourself)

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.
5. Given problems should be worked out & get the outputs.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 2
4 Bit Binary to Gray Code Conversion & Vice Versa

Aim: Realization of 3bit Binary to Gray Code conversion and Vice-Versa using Basic /
Universal gates.

Binary to Gray Code Conversion:

Invented by Emile Baudot (1845-1903)
Originally called a "cyclic-permuted" code.
Telegraph -5 bit codes, Bits stored on a code wheel in the receiver Wheel connected
to the printing disk.
Matched pattern on wheel and received pattern and then actuated head to print.
Exhibited at Universal Exposition, Paris (1878).

Binary Codes:
The usual way of expressing a decimal number in terms of a binary number is known as pure
binary coding. A number of other techniques can be used to represent a decimal number.

Gray Code:
Gray coding is an important code and is used for its speed, it is also relatively free from
errors. In pure binary coding or 8421 BCD then counting from 7 (0 1 1 1) to 8 (1000) requires
4 bits to be changed simultaneously. If this does not happen then various numbers could be
momentarily generated during the transition so creating spurious numbers which could be
read.

Gray coding avoids this since only one bit changes between subsequent numbers. To
construct the code there are two simple rules. First start with all 0s and then proceed by
changing the least significant bit (LSB) which will bring about a new state.

Components &equipments required: IC 7486, Digital IC Trainer Kit, 4mm. Patch cards etc.

Steps for converting Binary to Gray Code:

I Step:
The MSB (most significant bit) in the gray code is same as that of corresponding bit
of the binary code.
II Step:
Then going from MSB to LSB (left to right) perform EX-OR operation on two
adjacent binary digits to obtain gray code digit.

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To convert a Gray-coded number to binary then follow this method:

The binary number and the Gray-coded number will have the same number of bits.
The binary MSB (left-hand bit) and Gray code MSB will always be the same.
To get the binary next-to-MSB (i.e. next digit to the right) add (EX-OR) the binary
MSB and the gray code next-to-MSB. Record the sum, ignoring any carry.
Continue in this manner right through to the end.

Gray coding is a non-BCD, Non-weighted reflected binary code.

Truth Table for Binary to Gray Code conversion:

BCD Binary Input Gray Code Output
Number B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

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K - Maps:

Circuit Diagram for Binary to Gray Code Conversion:

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Truth Table for Gray to Binary Code conversion:

Gray Code Input Binary Output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K - Maps:

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Circuit Diagram for Gray to Binary Code Conversion:

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 3
4:1 Multiplexer / 1:4 De-multiplexer
Using Basic/universal gates

Aim: Realization of 4:1 Multiplexer and 1:4 De-multiplexer Using Basic/universal gates.

Multiplexer:
Multiplexer has many data input lines and one output line.
Multiplexer (MUX) places the data of one of its input lines on the output line.
MUX has a set of “n” address lines to select one of 2n input line
SOP realization is possible using MUX.

A multiplexer is a combinatorial circuit that is given a certain number (usually a power of

two) data inputs, let us say 2n, and n address inputs used as a binary number to select one of
the data inputs. The multiplexer has a single output, which has the same value as the selected
data input.

In other words, the multiplexer works like the input selector. Only one input is selected at a
time, and the selected input is transmitted to the single output.

Demultiplexer:
A demultiplexer (DEMUX) is a device which essentially performs the opposite operation to
the MUX. That is, it functions as an electronic switch (or data distributor) to route an
incoming data signal to one of several outputs.

The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n
address inputs. It has 2n outputs. Output is inverted in IC 74139 1:4 Demultiplixer.

Components &equipments required: IC 74153, 74139, 7404, 7408, 7432, 7400 & 7420.
Digital IC Trainer Kit, 4mm. Patch cards etc.
Connection Diagram MUX:

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Truth Table:
Address
Enable
Select Data Inputs Output
Inputs Comments
Inputs
S1 S0 I0 I1 I2 I3 Y
0 0
0 0 0 X X X I0 Selected
1 1
0 0
0 0 1 X X X I1 Selected
1 1
0 0
0 1 0 X X X I2 Selected
1 1
0 0
0 1 1 X X X I3 Selected
1 1
1 X X X X X X X MUX Disabled

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Circuit Diagram:

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Circuit Diagram:

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Connection Diagram DEMUX:

Truth Table:

Address
Data Input Select Data Outputs
Inputs Comments
S1 S0 Y0 Y1 Y2 Y3
(Da) (Db)
0 0 0 0 0 1 1 1 Y0 Selected

0 1 1 0 1 1 Y1 Selected

1 0 1 1 0 1 Y2 Selected

1 1 1 1 1 0 Y3 Selected

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Circuit Diagram:

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Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.
5. X in the truth table indicates Don’t care condition since depending on the selection
line the data line will be selected.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 4
Arithmetic Circuit Realization
(Half/Full, Adder/Subtractor) using Mux.

Aim: Realization of Arithmetic Circuit (Half/Full, Adder/Subtractor) using Dual Mux

IC74153.

Components &equipments required: IC 74153, 7404. Digital IC Trainer Kit, 4mm. Patch
cards etc.

Realization of Half Adder Using IC 74153

Truth Table: Implementation Table:

TRUTH TABLE
Input Output
A B S C
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1

Circuit Diagram:

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OR
Truth Table:
Input Output
A B S C
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 0
2 1 0 1 0
3 1 1 0 1

Circuit Diagram:

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Realization of Full Adder Using IC 74153

Truth Table: Implementation Table:

Input Output
A B Cin S Cout
0 0 0 0 0 0
1 0 0 1 1 0
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1
7 1 1 1 1 1

Circuit Diagram:

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OR

Truth Table: Implementation Table:

Input Output
A B S Cout
Cin
S1 S0 Ia Ib
0 0 0 0 0 0
cin Logic
1 0
1
0 0 1 0
2 0 1 0 1 0
cin
3 0 1 1 0 1
4 1 0 0 1 0
cin
5 1 0 1
0 1
6 1 1 0 0 1
cin Logic
7 1 1 1 1 1
1

Circuit Diagram:

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Realization of Half Subtractor Using IC 74153

Truth Table: Implementation Table:
Input Output
A B D B
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0

Circuit Diagram:

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OR
Truth Table:
Input Output
A B D B
S1 S0 Ia Ib
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0

Circuit Diagram:

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Realization of Full Subtractor Using IC 74153

Truth Table: Implementation Table:
TRUTH TABLE
Input Output
A B Bin D Bout
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1

Circuit Diagram:

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OR
Truth Table: Implementation Table:
Input Output
A B Bin D Bout
0 0 0 0 0 0
Bin Bin
1 0 0 1
1 1
2 0 1 0 1 1
Logic
3 0 1 1 0 1
1
4 1 0 0 1 0
Logic
5 1 0 1 0 0
0
6 1 1 0 0 0
Bin Bin
7 1 1 1
1 1

Circuit Diagram:

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Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. The Logic levels are applied at the Input for all combinations indicated in Truth Table
& the Output is observed on LED’s.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment – 5
Master- Slave JK, T and D Flip-Flop

Aim: Construction and verification of JK Master-Slave, T type & D type Flip-Flops using
logic gates.

JK Flip-Flop: One way of overcoming the problem with oscillation that occurs with a JK
Flip-Flop when J= K = 1 is to use a so-called master-slave flip- flop which is illustrated in the
circuit diagram.

The master-slave flip-flop is essentially two back-to-back JKFFs, note however, that
feedback from this device is fed back both to the master FF and the slave FF.

Any input to the master-slave flip-flop at J and K is first seen by the master FF part of the
circuit while CLK is High (= 1). This behaviour effectively "locks" the input into the master
FF. An important feature here is that the complement of the CLK pulse is fed to the slave FF.
Therefore the outputs from the master FF are only "seen" by the slave FF when CLK is Low
(=0). Therefore on the High-to-Low CLK transition the outputs of the master are fed through
the slave FF. This means that at most one change of state can occur when J=K = 1 and so
oscillation between the states Q=O and Q= 1 during the same CLK pulse does not occur.

Master-Slave JK Flip-flop
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the “Master” circuit, which
triggers on the leading edge of the clock pulse while the other acts as the “Slave” circuit,
which triggers on the falling edge of the clock pulse. This results in the two sections, the
master section and the slave section being enabled during opposite half-cycles of the clock
signal.
The TTL 74HC76 is a Dual JK flip-flop IC, which contains two individual JK type bistable’s
within a single chip enabling single or master-slave toggle flip-flops to be made. Other JK
flip flop IC’s include the 74LS107 Dual JK flip-flop with clear, the 74LS109 Dual positive-
edge triggered JK flip flop and the 74LS112 Dual negative-edge triggered flip-flop with both
preset and clear inputs.
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from
the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave” flip flop. This feedback
configuration from the slave’s output to the master’s input gives the characteristic toggle of
the JK flip flop.
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the
input condition while the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of
the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR
flip flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated
“slave” flip flop when the clock input goes “LOW” to logic level “0”.

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When the clock is “LOW”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop now responds to the
state of its inputs passed over by the “master” section.
Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop
are fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low”
transition the same inputs are reflected on the output of the “slave” making this type of flip
flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to
the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip
flop is a “Synchronous” device as it only passes data with the timing of the clock signal.

Components &equipments required: IC 7400, & 7410. Digital IC Trainer Kit, 4mm. Patch
cards etc.

Circuit Diagram:

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Truth Table:

Inputs Outputs
CL Comments
J K Qn n
K
0 0 X X X 1 1 Indeterminate State

0 1 X X X 1 0 FF Preset(Set)

1 0 X X X 0 1 FF Cleared(Reset)

1 1 0 0 X Q n-1 n-1 Previous

1 1 0 1 0 1 Reset

1 1 1 0 1 0 Set

1 1 1 1 n-1 Q n-1 Toggle

Note:
Keep = 1 and =1 for verifying the Truth Table of JK Master-
Slave FF & T FF.
Q n is Output level before giving Clock pulse.

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Circuit Diagram:

Truth Table:
Inputs Outputs
Comments
T CLK Qn n
0 0 X X 1 1 Indeterminate State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 X Q n-1 n-1 Previous
1 1 1 n-1 Q n-1 Toggle

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Circuit Diagram:

Truth Table:

Inputs Outputs
Comments
D CLK Qn n
0 0 X X 1 1 Indeterminate State
0 1 X X 1 0 FF Preset(Set)
1 0 X X 0 1 FF Cleared(Reset)
1 1 0 0 1 Data transferred
1 1 1 1 0 Data transferred

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Circuit Diagram:

Procedure:
1. The connections are made as shown in Circuit(by referring IC PIN diagram)
2. The input terminals (JK, T & D) are connected to the toggle switches & the output is
connected to the Output Connector (LED’s).
3. The power is applied between the VCC & Ground terminals.
4. Connect clock pin to the bounce less pulsar HIGH or LOW
5. The Logic levels are applied at the Inputs as indicated in Truth Table & the Output is
observed on LED’s.
6. X in the truth table indicates Don’t Care condition.

Faults & Debugging:

1. Check Continuity of given Patch Chords before circuit Connection.
2. Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
3. Check IC Number for the given circuit & connect the circuit by checking pin details.
4. Check operating voltage connected to IC (+Vcc& Gnd.)
5. To check outputs apply Clock correctly as specified in Procedure.
6. Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

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Experiment -6
3 Bit ripple up/down Counters
Aim: Construction and realization of 3 bit ripple up/down counter using IC 7476 and other
logic gates.

Counters: The synchronous design of any sequential circuit application for example counter
is a design in which all the flip-flops are connected to a common clock input that is, all the
flip-flops are clocked simultaneously. Therefore to get the next state of application actual
inputs of the flip-flop should be designed according to the requirement.

Hence excitation tables are used to design the actual inputs of the flip-flops to get the next
stage. The excitation table gives the combination of input for the required output condition
before and after the application of clock.

Ripple Counter
A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an
external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
Asynchronous counters are also called ripple-counters because of the way the clock pulse
ripples it way through the flip-flops.
The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used. For a 4-
bit counter, the range of the count is 0000 to 1111 (24-1). A counter may count up or count
down or count up and down depending on the input control. The count sequence usually
repeats itself. When counting up, the count sequence goes from 0000, 0001, 0010, ... 1110 ,
1111 , 0000, 0001, ... etc. When counting down the count sequence goes in the opposite
manner: 1111, 1110, ... 0010, 0001, 0000, 1111, 1110, ... etc.
The complement of the count sequence counts in reverse direction. If the uncomplemented
output counts up, the complemented output counts down. If the uncomplemented output
counts down, the complemented output counts up.
There are many ways to implement the ripple counter depending on the characteristics of the
flip flops used and the requirements of the count sequence.

Clock Trigger: Positive edged or Negative edged

JK or D flip-flops
Count Direction: Up, Down, or Up/Down

Asynchronous counters are slower than synchronous counters because of the delay in the
transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits
in the count change synchronously with the assertion of the clock. Examples of synchronous
counters are the Ring and Johnson counter.
It can be implemented using D-type flip-flops or JK-type flip-flops.
The circuit below uses 2 D flip-flops to implement a divide-by-4 ripple counter (2n = 22 = 4).
It counts down.

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Components &equipments required: IC 7476, 7400, 7404, 7408 & 7410. Digital IC Trainer
Kit, 4mm. Patch cards etc.

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Circuit Diagram:

Note:
J & K inputs of Flip-Flops are connected to logic 1 or Keep it open to operate under
toggle mode.
When Preset = 1, Clear = 0; Counter is cleared Q0 = Q1 = Q2 = 0
When Preset = 0, Clear = 1; Counter is preset Q0 = Q1 = Q2 = 1
Keep Preset = 1, Clear = 1 for count mode.

Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

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Circuit Diagram:

Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

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Circuit Diagram:

Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0

Circuit Diagram:

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Note:
When Mode control is at logic 1 counter works as an Up-counter.
When Mode control is at logic 0 counter works as a Down-counter.

Design and verification of mod-n, 3bit synchronous counter using 7476 JK, T & D flip flops.

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Experiment -7
Design and verification of 3 Bit Synchronous Counters

Aim: Design and verification of 3-bit Synchronous counter using IC7476.

Synchronous Counters:
In the previous Asynchronous binary counter tutorial, we saw that the output of one counter
stage is connected directly to the clock input of the next counter stage and so on along the
chain.
The result of this is that the Asynchronous counter suffers from what is known as
“Propagation Delay” in which the timing signal is delayed a fraction through each flip-flop.
However, with the Synchronous Counter, the external clock signal is connected to the clock
input of EVERY individual flip-flop within the counter so that all of the flip-flops are
clocked together simultaneously (in parallel) at the same time giving a fixed time
relationship. In other words, changes in the output occur in “synchronisation” with the clock
signal.
The result of this synchronisation is that all the individual output bits changing state at
exactly the same time in response to the common clock signal with no ripple effect and
therefore, no propagation delay.

Synchronous Counter Summary:

Then to summarise some of the main points about Synchronous Counters:
Synchronous Counters can be made from Toggle or D-type flip-flops.
Synchronous counters are easier to design than asynchronous counters.
They are called synchronous counters because the clock input of the flip-flops
are all clocked together at the same time with the same clock signal.
Due to this common clock pulse all output states switch or change simultaneously.
With all clock inputs wired together there is no inherent propagation delay.
Synchronous counters are sometimes called parallel counters as the clock is fed in
parallel to all flip-flops.
The inherent memory circuit keeps track of the counters present state.
The count sequence is controlled using logic gates.
Overall faster operation may be achieved compared to Asynchronous counters.

Components &equipments required: IC 7476, 7400, 7404, & 7408. Digital IC Trainer Kit,
4mm. Patch cards etc.

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Excitation Tables:

Q (n) Q (n+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

PS NS Flip-Flop Inputs
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
2 0 1 0 0 1 1 0 X X 0 1 X
3 0 1 1 1 0 0 1 X X 1 X 1
4 1 0 0 1 0 1 X 0 0 X 1 X
5 1 0 1 1 1 0 X 0 1 X X 1
6 1 1 0 1 1 1 X 0 X 0 1 X
7 1 1 1 0 0 0 X 1 X 1 X 1

Circuit Diagram:

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Truth Table:
No. of Flip-Flop
Clock Outputs
Pulses Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

K-Maps:

Circuit Diagram:

Note:
Carryout the design similarly

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Assignment:
Design of T flip-flop 3 Bit Synchronous Counters
Design of D flip-flop 3 Bit Synchronous Counters

Procedure:
The connections are made as shown in Circuit(by referring IC PIN diagram)
The input terminals are connected to the toggle switches & the output is connected to
the Output Connector (LED’s).
The power is applied between the VCC & Ground terminals.
Connect clock pin to the bounce less pulsar LOW.
The clock input is applied as indicated in Truth Table & the Output is observed on
LED’s.
X in the truth table indicates irrelevant care condition.

Faults & Debugging:

Check Continuity of given Patch Chords before circuit Connection.
Check the working of Toggle Switch & Output LED Indicator {Initially All output
LED Indicators will be in RED (colour- Logic 1)}
Check IC Number for the given circuit & connect the circuit by checking pin details.
Check operating voltage connected to IC (+Vcc& Gnd.)
To check outputs apply Clock correctly as specified in Procedure.
Apply Exact Combinations of Inputs as in Truth Table & Verify the output.

Assignment:
Design and verification of random sequence counter, 3bit synchronous counter using
7476 JK, T & D flip flops.

Challenge experiments:

1. Design a digital circuit to turn on and turn off the bulb with respect to ambient light
availability.

2. Design a digital circuit to generate 10 clock pulses upon receiving the control signal.

3. Design a digital circuit for 4 bit barrel shifter.

4. Design a digital circuit to perform 2bit* 2bit multiplier.

5. Design a digital circuit to perform 2bit comparator.

6. Design and verification of mod-n, 3bit synchronous counter using 7476 T & D FF.

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Frequently Asking Viva Questions

1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?
7. What are the different methods to obtain minimal expression?
8. What is a Min term and Max term
9. State the difference between SOP and POS.
10. What is meant by canonical representation?
11. What is K-map? Why is it used?
12. What are universal gates?
13. What is a half adder?
14. What is a full adder?
15. What are the applications of adders?
16. What is a half subtractor?
17. What is a full subtractor?
18. What are the applications of subtractors?
19. Realize a full adder using two half adders
20. Realize a full subtractors using two half subtractors
21. What is the internal structure of 7483 IC?
22. What do you mean by code conversion?
23. What are the applications of code conversion?
24. How do you realize a subtractor using full adder?
25. What is a ripple Adder? What are its disadvantages?
26. What are code converters?
27. What is the necessity of code conversions?
28. What is gray code?
29. What is a multiplexer?
30. What is a de-multiplexer?
31. What are the applications of multiplexer and de-multiplexer?
32. What is the difference between multiplexer &demultiplexer?
33. In 2n to 1 multiplexer how many selection lines are there?
34. What is a comparator?
35. What are the applications of comparator?
36. How do you realize a higher magnitude comparator using lower bit comparator
37. Design a 2 bit comparator using a single Logic gates?
38. Design an 8 bit comparator using a two numbers of IC 7485?
39. What are the applications of decoder?
40. What is the difference between decoder & encoder?
41. For n- 2n decoder how many i/p lines & how many o/p lines are there?
42. What are the different codes & their applications?

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43. What are code converters?

44. What is the difference between decoder and de-mux?
45. What is a priority encoder?
46. What is the role of an encoder in communication?
47. What is the advantage of using an encoder?
48. What is the difference between Flip-Flop & latch?
49. What is the advantage of Edge triggering over level triggering?
50. What is the relation between propagation delay & clock frequency of flip-flop?
51. What is race around in flip-flop & how to overcome it?
52. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
53. What is the necessity for sequence generation?
54. What are PISO, SIPO, and SISO with respect to shift register?
55. Differentiate between serial data & parallel data
56. What is the significance of Mode control bit?
57. What is a ring counter?
58. What is a Johnson counter?
59. How many Flip-flops are present in IC 7495?
60. What is an asynchronous counter?
61. How is it different from a synchronous counter?
62. Realize asynchronous counter using T flip-flop
63. What are synchronous counters?
64. What are the advantages of synchronous counters?
65. What is an excitation table?
66. Write the excitation table for D & T FF
67. Design mod-5 synchronous counter using T FF
68. What is a presettable counter?
69. What are the applications of presettable counters?
70. Explain the working of IC 74193
71. What is a decade counter?
72. What do you mean by a ripple counter?
73. Explain the design of Modulo-N counter (N _ 9) using IC 7490

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DIGITAL IC’s PIN DETAILS

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Language Overview

What is VHDL?
VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language. VHDL is a programming language that has been designed and
optimized for describing the behaviour of digital systems.

VHDL has many features appropriate for describing the behaviour of electronic
components ranging from simple logic gates to complete microprocessors and custom
chips. Features of VHDL allow electrical aspects of circuit behaviour (such as rise and
fall times of signals, delays through gates, and functional operation) to be precisely
described. The resulting VHDL simulation models can then be used as building blocks in
larger circuits (using schematics, block diagrams or system-level VHDL descriptions) for
the purpose of simulation.

VHDL is also a general-purpose programming language: just as high-level programming

languages allow complex design concepts to be expressed as computer programs, VHDL allows
the behaviour of complex electronic circuits to be captured into a design system for automatic
circuit synthesis or for system simulation. Like Pascal, C and C++, VHDL includes features
useful for structured design techniques, and offers a rich set of control and data representation
features. Unlike these other programming languages, VHDL provides features allowing
concurrent events to be described. This is important because the hardware described using VHDL
is inherently concurrent in its operation.

One of the most important applications of VHDL is to capture the performance

specification for a circuit, in the form of what is commonly referred to as a test bench. Test
benches are VHDL descriptions of circuit stimuli and corresponding expected outputs that verify
the behaviour of a circuit over time. Test benches should be an integral part of any VHDL project
and should be created in tandem with other descriptions of the circuit.

A standard language
One of the most compelling reasons for you to become experienced with and
knowledgeable in VHDL is its adoption as a standard in the electronic design Community. Using
a standard language such as VHDL virtually guarantees that you will not have to throw away and
recapture design concepts simply because the design entry method you have chosen is not
supported in a newer generation of design tools. Using a standard language also means that you
are more likely to be able to take advantage of the most up-to-date design tools and that you will
have access to a knowledge base of thousands of other engineers, many of whom are solving
problems similar to your own.

A brief history of VHDL

VHDL was developed in the early 1980s as a spin-off of a high-speed integrated circuit
research project funded by the U.S. Department of Defence. During the VHSIC program,
researchers were confronted with the daunting task of describing circuits of enormous scale (for
their time) and of managing very large circuit design problems that involved multiple teams of
engineers. With only gate-level design tools available, it soon became clear that better, more
structured design methods and tools would be needed.
In 1986, the Institute of Electrical and Electronics Engineers, Inc. (IEEE) was presented
with a proposal to standardize the language, which it did in 1987 after substantial enhancements
and modifications were made by a team of commercial, government and academic
representatives. The resulting standard, IEEE 1076-1987, is the basis for virtually every

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simulation and synthesis product sold today. An enhanced and updated version of the language,
IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been responding by
adding these new language features to their products.
Although IEEE Standard 1076 defines the complete VHDL language, there are aspects
of the language that make it difficult to write completely portable design descriptions
(descriptions that can be simulated identically using different vendors’ tools). The problem
stems from the fact that VHDL supports many abstract data types, but it does not address the
simple problem of characterizing different signal strengths or commonly used simulation
conditions such as unknowns and high-impedance.

Soon after IEEE 1076-1987 was adopted, simulator companies began enhancing VHDL
with new, non-standard types to allow their customers to accurately simulate complex electronic
circuits. This caused problems because design descriptions entered into one simulator were often
incompatible with other simulation environments. VHDL was quickly becoming a non-standard.

To get around the problem of non-standard data types, another standard was developed
by an IEEE committee. This standard, numbered 1164, defines a standard package (a VHDL
feature that allows commonly used declarations to be collected into an external library)
containing definitions for a standard nine-valued data type. This standard data type is called
std_logic, and the IEEE 1164 package is often referred to as the Standard Logic package.

The IEEE 1076-1987 and IEEE 1164 standards together form the complete VHDL
standard in widest use today. (IEEE 1076-1993 is slowly working its way into the VHDL
mainstream, but it does not add significant new features for synthesis users.)

Standard 1076.3 (often called the Numeric Standard or Synthesis Standard) defines standard
packages and interpretations for VHDL data types as they relate to actual hardware. This
standard, which was released at the end of 1995, is intended to replace the many custom (non-
standard) packages that vendors of synthesis tools have created and distributed with their
products.

IEEE Standard 1076.3 does for synthesis users what IEEE 1164 did for simulation
users: increase the power of Standard 1076, while at the same time ensuring compatibility
between different vendors’ tools. The 1076.3 standard includes, among other things:

1) A documented hardware interpretation of values belonging to the bit and Boolean

types defined by IEEE Standard 1076, as well as interpretations of the std_logic type defined
by IEEE Standard 1164.
2) A function that provides “don’t care” or “wild card” testing of values based on the
std_logic type. This is of particular use for synthesis, since it is often helpful to express logic in
terms of “don’t care” values.
The ability to separate the behavioural description of a simulation model from the timing
specifications is important for many reasons. One of the major strengths of Verilog HDL
(VHDL’s closest rival) is the fact that Verilog HDL includes a feature specifically intended for
timing annotation. This feature, the Standard Delay Format, or SDF, allows timing data to be
expressed in a tabular form and included into the Verilog timing model at the time of simulation.

The IEEE 1076.4 standard, published by the IEEE in late 1995, adds this capability to
VHDL as a standard package. A primary impetus behind this standard effort (which was dubbed
VITAL, for VHDL Initiative toward ASIC Libraries) was to make it easier for ASIC vendors and
others to generate timing models applicable to both VHDL and Verilog HDL. For this reason, the
underlying data formats of IEEE 1076.4 and Verilog’s SDF are quite similar.

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When should you use VHDL?

Why choose to use VHDL for your design efforts? There are many likely reasons. If
you ask most VHDL tool vendors this question, the first answer you will get is, “It will improve
your productivity.” But just what does this mean? Can you really expect to get your projects
done faster using VHDL than by using your existing design methods?

The answer is yes, but probably not the first time you use it, and only if you apply
VHDL in a structured manner. VHDL (like a structured software design language) is most
beneficial when you use a structured, top-down approach to design. Real increases in
productivity will come later, when you have climbed higher on the VHDL learning curve and
have accumulated a library of reusable VHDL components.

Productivity increases will also occur when you begin to use VHDL to enhance
communication between team members and when you take advantage of the more powerful tools
for simulation and design verification that are available. In addition, VHDL allows you to design
at a more abstract level. Instead of focusing on a gate-level implementation, you can address the
behavioural function of the design.

How will VHDL increase your productivity? By making it easy to build and use libraries
of commonly-used VHDL modules. VHDL makes design reuse feel natural. As you discover the
benefits of reusable code, you will soon find yourself thinking of ways to write your VHDL
statements in ways that make them general purpose. Writing portable code will become an
automatic reflex.
Another important reason to use VHDL is the rapid pace of development in electronic
design automation (EDA) tools and in target technologies. Using a standard language such as
VHDL can greatly improve your chances of moving into more advanced tools (for example, from
a basic low-cost simulator to a more advanced one) without having to re-enter your circuit
descriptions. Your ability to retarget circuits to new types of device targets (for example, ASICs,
FPGAs, and complex PLDs) will also be improved by using a standard design entry method.
VHDL can describe a digital system at several different levels- Behavioral, Data-flow and
Structural.

A. Behavioral description: A digital circuit can be described at the behavioral level in terms of its
function or behavior, without giving any implementation details.

B. Data-flow description: A digital circuit can be described at the data-flow level by giving the logic
equation of that circuit.
C. Structural description: A digital circuit can be described at the structural level by specifying the
interconnection of the gates or flip-flops that comprise the circuit.

The basic design units used in VHDL are entity and architecture.

Entity:
Entity is the basic design unit used in VHDL.
It describes the external boundary of the hardware.
General syntax of the entity is

entity entity-name is
port (list of ports: mode type;
list of ports: mode type);
end [ entity ][entity-name];

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List of ports: which includes all input and output ports

Mode type: This specifies the type of ports such as in, out & inout.
Architecture:
It describes the functionality/behaviour of the entity.

architecture architecture-name of entity-name is

[ declarations ]
begin
architecture body
end [architecture-name];
Note: 1. [ ] - square brackets indicates optional.
2. Signals and components are declared in the declaration part of the architecture.
3. The architecture body contains concurrent or sequential statements.
Process():
A common way of modelling sequential logic in VHDL uses a process.
General syntax of the process is
process (sensitivity-list)
begin
sequential-statements;
end process;
Sensitivity list contains list of signals. Whenever one of the signals in the sensitivity list changes
the sequential statements in the process body are executed in sequence one time.
If statement:
It is commonly used sequential statement.
The basic IF statement has the form
if (condition) then
sequential statements1
else
sequential statements2
end if;

The condition is a Boolean expression, which evaluates to TRUE or FALSE. If it is TRUE

sequential statements1 are executed otherwise sequential statements2 are executed.

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Elsif statement:
Which is alternative way of writing nested IF statements.

The most general form of the ELSIF statement is

if (condition) then
sequential statements
{ elsif (condition) then
sequential statements }
-- 0 or more elsif clauses may be included.
[else sequential statements ]
end if;
The curly brackets indicate that any number of elsif clauses may be included, and the square
brackets indicate that the else clause is optional.
Conditional assignment statement:
This statement has the form
signal-name <= expression1 when condition1
else expression2 when condition2
…
[else expressionN ];

This concurrent statement is executed whenever an event occurs on a signal used in one of
the expressions or conditions.If condition1 is true, signal_name is set equal to the value of the
expression1, else if condition2 is true, signal_name is set equal to the value of expression2, etc.,

Case statement:
The case statement has the general form
case expression is
when choice1 => sequential statements1
when choice2 => sequential statements2
…
[ when others => sequential statements ]
end case;
The expression is evaluated first. If it is equal to “choice1”, then “sequential
statements1” are executed. If it is equal to “choice2”, then “sequential statements2” are executed,
etc.

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Note:

All the possible values of the expression must be included in the choices. If all the values are
not explicitly given, a “when others” clause is required in the case statement.

Variable:
Variable is a VHDL object and must be declared with in the process in which they are used and
are local to that process.
The variable declaration has the form
variable list_of_variable_names : type_name [ := initial value ];

Signal:
Signal is a VHDL object and it is declared in the declaration part of the architecture.
The signal declaration has the form
signal list_of_signal_names : type_name [ := initial value ];
Array:
The array type and array object declarations have the general forms
type array_type_name is array index_range of element_type;
signal array_name: array_type_name [ := initial_values ];
element_type: Which specifies integer or bit or bit_vector etc.

PROCEDURE:

The Procedure to be followed for Software and Hardware Programs are as follows:

Step 1: Go to Start Menu All Programs Xilinx ISE 9.1i and Select Project
Navigator.

Step 2: Go to File Menu and Close any previously opened project if any, and then Select New
Project.

Step 3: Enter the Project name and location and Select the Top level module type as HDL.

Step 4: Select the Device family and Device name as Spartan3 and xc3s400, pin density tq144,-
4 for FPGA.

Step 5: Right click on the source file and select new source speed followed by VHDL module
and Give the file name same as the name of the entity.

Step 6: Define the ports used and their respective directions in the next window that opens.

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Step 7: Write the architecture body and the generics etc. in the incomplete VHDL code
that opens and save the file after completion of editing.

Step 8: Go to the Process view window and right click on the Synthesize - XST and Select
Run. Correct the errors if any.

Step 9: Select and Right click the source file and click on the New Source tab and then
select the Test Bench Waveform and give the appropriate file name for the same.

Step 10: Make the alterations in the Clock information and initial length of the test
bench if needed.

Step 11: Set or Reset the inputs as required and save the test bench waveform file.
Step 12: Go to Process view and under Xilinx ISE Simulator Right click on the Simulate
Behavioral model to see the output for the input conditions.

Step 13: Make the appropriate connections between the PC and the FPGA kit for the
observation of outputs in the FPGA kit and for other Hardware Programming.

Step 14: Select and Right click the source file and click on the New Source tab and then
select the Implementation Constraints file and give the appropriate file name for the
same.

Step 15: Go to Process view and under User Constraints, double click on the Edit
Constraints (Text).

Step 16: Write the code for the user constraints file as required and save the same.

Step 17: Select the main source file and right click on the Implement design in the process
view window and select run.

Step 18: Right click on the Generate Programming file in the process view window and
select run.

Step 19: Under the Generate Programming file tab, right click on the Configure device (Impact)
and click on the Run option.

Step 20: Select the appropriate mode and make changes in the jumper settings of the FPGA Kit
as required, select the appropriate .BIT extension file in the pop up window.

Step 21: Right click on the Chip picture in the pop up window and Select “Program”. Debug the
errors if it is there. Set the conditions for the inputs using Dip switch and observe the
outputs.

Pattern Generator:

Step 22: Click on the bit pattern generator icon on the desktop.

Step 23: Open a new file.

Step 24: Browse the UCF file and assign in and out pins.

Step 25: Select the number of inputs and outputs.

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Step 26: Enable Clock and continuous mode as suitable to the program.

Step 27: Select the number of patterns to be send.

Step 28: Click on the send pattern.

Step 29: Verify the truth table

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Logic Gates

AIM: To write a VHDL Code to realize all the Logic gates.

(1) AND Gate:

Truth Table: Logic Diagram:

A B C
0 0 0
0 1 0
1 0 0
1 1 1

(2) OR Gate:
Truth Table: Logic Diagram:
A B C
0 0 0
0 1 1
1 0 1
1 1 1

(3) NOT Gate:

Truth Table: Logic Diagram:

A A’
0 1
1 0

(4) NAND Gate:

Truth Table: Logic Diagram:

A B C
0 0 1
0 1 1
1 0 1
1 1 0

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(5) NOR Gate:

Truth Table: Logic Diagram:

A B C
0 0 1
0 1 0
1 0 0
1 1 0

(6) XOR Gate:

Truth Table: Logic Diagram:

A B C
0 0 0
0 1 1
1 0 1
1 1 0

(7) XNOR Gate:

Truth Table: Logic Diagram:

A B C
0 0 1
0 1 0
1 0 0
1 1 1

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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity orgate1 is
port ( a,b: in std_logic;
y: out std_logic);
end orgate1;

architecture gate of orgate1 is

begin
y <= a or b;
end gate;

VHDL Code for all gates:

library ieee;
use ieee.std_logic_1164.all;
entity gate is
port ( ain,bin: in std_logic;
op_not: out std_logic;
op_or,op_nor: out std_logic;
op_xor,op_xnor: out std_logic;
op_and,op_nand: out std_logic);
end gate;

architecture logic_gate of gate is

begin
op_not <= not ain;
op_or <= ain or bin;
op_and <= ain and bin;
op_nor <= ain nor bin;
op_nand <= ain nand bin;
op_xor <= ain xor bin;
op_xnor <= ain xnor bin;
end logic_gate;

TRUTHTABLE:

bin ain op_not op_or op_and op_nor op_nand op_xor op_xnor

0 0 1 0 0 1 1 0 1
0 1 0 1 0 0 1 1 0
1 0 1 1 0 0 1 1 0
1 1 0 1 1 0 0 0 1

Write the code for 3-input gates.

Realize the Boolean expression Y= A.(B+C).

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WAVEFORMS:

Write the code for 3-input gates.

RESULT:

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Experiment No. 1a
DECODER

AIM: To write a VHDL Code to realize a 2 to 4 Decoder.

Block Diagram: TRUTH TABLE:

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
entity dec is
port (enable:in std_logic;
d_in:in std_logic_vector(1 downto 0);
d_out:out std_logic_vector(3 downto 0));
end dec;

architecture dec2 of dec is

begin
process (enable,d_in)
begin
if (enable='1') then d_out<="0000";
else
case d_in is
when "00"=>d_out<="0001";
when "01"=>d_out<="0010";
when "10"=>d_out<="0100";
when "11"=>d_out<="1000";
when others=>null;
end case;
end if;
end process;
end dec2;

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--VHDL code for 2 to 4 DECODER (using if else statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder2_4 is
Port ( i : in std_logic_vector(1 downto 0);
en : in std_logic;
y : out std_logic_vector(3 downto 0));
end decoder2_4;

architecture behavioural of decoder2_4 is

begin
process(i,en)
begin
if(en='1') then
if(i="00") then y<="0001";
elsif(i="01") then y<="0010";
elsif(i="10") then y<="0100";
else y<="1000";
end if;
end if;
end process;
end behavioural;

--VHDL code for 2 to 4 DECODER (Structural Description)

--TOP LEVEL MODULE--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder2_4 is
Port(i0,i1,en : in std_logic;
y0,y1,y2,y3: out std_logic);
end decoder2_4;

architecture structural of decoder2_4 is

component notgate
port(a:in std_logic;
b:out std_logic);
end component;

component andgate
port(c,d,e:in std_logic;
f:out std_logic);
end component;
signal s1,s2:std_logic;
begin

u0:notgate port map(i0,s1);

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u1:notgate port map(i1,s2);

u2:andgate port map(s1,s2,en,y0);
u3:andgate port map(s1,i1,en,y1);
u4:andgate port map(i0,s2,en,y2);
u5:andgate port map(i0,i1,en,y3);
end structural;

--LOW LEVEL MODULE—

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity andgate is
port(c,d,e:in std_logic;
f:out std_logic);
end andgate;

architecture Behavioural of andgate is

begin
f<= c and d and e;
end Behavioural;

--LOW LEVEL MODULE--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity notgate is
port(a:in std_logic;
b:out std_logic);
end notgate;

architecture Behavioural of notgate is

begin
b<= not a;
end Behavioural;

Write the code for logic high enable.

Write the code for 3-8 decoder.

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WAVEFORM:

RESULT:

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Experiment No. 1b
ENCODER

AIM: To write a VHDL Code to realize an 8 to 3 Encoder.

BLOCK DIAGRAM:

VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
entity enc1 is
port(enable:in
std_logic;
d_in: in std_logic_vector(7 downto 0);
d_out: out std_logic_vector(2 downto
0));
end enc1;

architecture enc2 of enc1 is

begin
process(enable,d_i
n)
begin
if(enable='1') then d_out<= "000";
else
case d_in is
when "00000001"=>d_out<="000";
when "00000010"=>d_out<="001";
when "00000100"=>d_out<="010";
when "00001000"=>d_out<="011";
when "00010000"=>d_out<="100";
when "00100000"=>d_out<="101";
when "01000000"=>d_out<="110";
when "10000000"=>d_out<="111";
when others=>null;
end case;
end if;
end
process;
end enc2;

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AIM: Write VHDL code for an 8 to 3 ENCODER with priority and without
priority.

TRUTH TABLE:
1. With priority
INPUT (I) OUTPUT (Y)
1XXXXXXX 111
01XXXXXX 110
001XXXXX 101
0001XXXX 100
00001XXX 011
000001XX 010
0000001X 001
00000001 000

2. without priority
INPUT (I) OUTPUT (Y)
00000001 000
00000010 001
00000100 010
00001000 011
00010000 100
00100000 101
01000000 110
10000000 111

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--VHDL code for an 8 to 3 ENCODER with priority

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prencoder8_3 is
Port ( i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end prencoder8_3;

architecture Behavioural of prencoder8_3 is

begin
process(i)
begin
if(i(7)='1') then y<="111";
elsif(i(6)='1') then y<="110";
elsif(i(5)='1') then y<="101";
elsif(i(4)='1') then y<="100";
elsif(i(3)='1') then y<="011";
elsif(i(2)='1') then y<="010";
elsif(i(1)='1') then y<="001";
elsif(i(0)='1') then y<="000";
else y<="ZZZ";
end if;
end process;
end Behavioural;

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--VHDL code for an 8 to 3 ENCODER without priority

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder8_3 is
Port ( i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end encoder8_3;

architecture behavioural of encoder8_3 is

begin
process(i)
begin
case i is
when "00000001"=>y<="000";
when "00000010"=>y<="001";
when "00000100"=>y<="010";
when "00001000"=>y<="011";
when "00010000"=>y<="100";
when "00100000"=>y<="101";
when "01000000"=>y<="110";
when "10000000"=>y<="111";
when others=>null;
end case;
end process;
end behavioural;

WAVEFORM:

RESULT:

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Experiment No. 1c MULTIPLEXER

AIM: To write a VHDL Code to realize an 8 to 1 Multiplexer.

BLOCK DIAGRAM: TRUTH TABLE:

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
entity mux1 is
port (sel:in std_logic_vector(2 downto 0);
a,b,c,d,e,f,g,h:in std_logic;
mux_out:out std_logic);
end mux1;

architecture mux2 of
mux1 is
begin
process(sel,a,b,c,d,e,f,g,
h)
begin
case sel is
when "000"=>mux_out<=a;
when "001"=>mux_out<=b;
when "010"=>mux_out<=c;
when "011"=>mux_out<=d;
when "100"=>mux_out<=e;
when "101"=>mux_out<=f;
when "110"=>mux_out<=g;
when "111"=>mux_out<=h;
when others=>null;
end case;
end process; end mux2;

Write vhdl code for 4 to 1 multiplexer.

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WAVEFORM:

RESULT:

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Experiment No. 1d
DE-MULTIPLEXER

AIM: Write VHDL code for 1 TO 4 DEMUX.

BLOCK DIAGRAM: TRUTH TABLE:

VHDL code for 1 TO 4 DEMUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demux4_1 is
Port ( i : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0));
end demux4_1;

architecture behavioural of demux4_1 is

begin
process(s,i)
begin
y<="0000";
case s is
when "00"=>y(0)<=i;

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when "01"=>y(1)<=i;
when "10"=>y(2)<=i;
when "11"=>y(3)<=i;
when others=>null;
end case;
end process;
end behavioural;

WAVEFORM:

RESULT:

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Experiment No. 1e
Comparator

AIM: Write VHDL code for N-BIT COMPARATOR. Let N =1

Logic Diagram:

Block Diagram: Truth Table:

A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

VHDL Code:
Library ieee ;
Use ieee.std_logic_1164.all;
entity comp1 is
port ( a,b: in std_logic;
g,e,l: out std_logic);
end comp1;

architecture comp2 of comp1 is

begin
e<=a xnor b;
g<= a and (not b);
l<= (not a) and b;
end comp2;

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AIM: Write VHDL code for 2-BIT COMPARATOR. Let N =2

Logic diagram:

Block Diagram:

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Truth Table:
INPUTS
A B G E L
OUTPUTS
(A>B) (A=B) (A<B)
00 00 0 1 0
00 01 0 0 1
00 10 0 0 1
00 11 0 0 1
01 00 1 0 0
01 01 0 1 0
01 10 0 0 1
01 11 0 0 1
10 00 1 0 0
10 01 1 0 0
10 10 0 1 0
10 11 0 0 1
11 00 1 0 0
11 01 1 0 0
11 10 1 0 0
11 11 0 1 0

-- VHDL code for 2-bit comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comp2 is
Port ( a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
l ,e,g: out std_logic);
end comp2;

architecture behavioural of comp2 is

begin
process(a,b)
begin
l<='0';e<='0';g<='0';
if (a<b)then l<='1';
elsif (a=b)then e<='1';
else g<='1';
end if;
end process;
end behavioural;

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Experiment No. 2
ADDERS

AIM: Write a VHDL code to describe the functions of a FULL ADDER

using Following modelling styles.
i) Dataflow description
ii) Behavioural description
iii) Structural description

Logic Diagram for Half Adder: Truth Table:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic Diagram for Full Adder:

TRUTH TABLE:

Ain Bin Cin Sum Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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--VHDL code for FULL ADDER (Dataflow description)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port ( a,b,cin: in std_logic;
Sum,cout: out std_logic);
end full_adder;

architecture dataflow of full_adder is

begin
sum<=a xor b xor cin;
cout<=(a and b) or (b and cin) or (cin and a);
end dataflow;

--VHDL code for FULL ADDER (Behavioural description)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder1 is
Port ( a,b,cin : in std_logic;
sum,cout : out std_logic);
end full_adder1;

architecture behavioural of full_adder1 is

signal s:std_logic_vector(2 downto 0);
begin
s<=a & b & cin;
process(s)
begin
case s is
when "000"=> sum<='0'; cout<='0';
when "001"=> sum<='1'; cout<='0';
when "010"=> sum<='1';cout<='0';
when "011"=> sum<='0';cout<='1';
when "100"=> sum<='1';cout<='0';
when "101"=> sum<='0';cout<='1';
when "110"=> sum<='0';cout<='1';
when "111"=> sum<='1';cout<='1';
when others=> null;
end case;
end process;
end behavioural;

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--VHDL code for FULL ADDER (Structural description)

Block Diagram:

VHDL Code for full adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
Port ( Ain : in std_logic; --Input One
Bin : in std_logic; --Input Two
Cin : in std_logic; --Carry Input
Cout : out std_logic; --Carry Output
Sum : out std_logic); --Sum Output
end FullAdder;

architecture Behavioural of FullAdder is

Component Halfadder
Port ( Ain : in std_logic;
Bin : in std_logic;
Sum : out std_logic;
Carry : out std_logic);
end Component;

Component orgate
Port ( Ain : in std_logic;
Bin : in std_logic;
y : out std_logic);
end Component;

Signal temp1, temp2, temp3: std_logic; -- Signal Declaration

begin
L1: Halfadder port map ( Ain, Bin,temp1,temp2);
L2: Halfadder port map ( temp1,Cin,Sum,temp3);
L3: orgate port map (temp2, temp3,Cout);
end Behavioural;

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Low level modules:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Halfadder is
Port ( Ain, Bin : in std_logic; --2Bit Input
Sum, Carry : out std_logic); --sum& carry
end Halfadder;

architecture archha of Halfadder is

begin
Sum <= Ain xor Bin;
Carry<= Ain and Bin;
end archha;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity orgate is
Port ( Ain, Bin : in std_logic;
y : out std_logic);
end orgate;

architecture archor of orgate is

begin
y<= Ain or Bin;
end archor;

WAVEFORM:

RESULT:

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Experiment No. 3

4 Bit binary, BCD counter

AIM: To write VHDL code for a 4 bit binary, BCD counters with synchronous and
asynchronous reset (using clock division).

VHDL code for 4-bit BCD COUNTER with synchronous Reset(using clock
division)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sbcdcounter is
Port ( sclk,reset: in std_logic;
count : inout std_logic_vector(3 downto 0):= "0000");
end sbcdcounter;

architecture Behavioural of sbcdcounter is

signal clkdiv:std_logic_vector(21 downto 0):="0000000000000000000000";
signal clk:std_logic;
begin
process(sclk)
begin
if(rising_edge(sclk))then clkdiv<=clkdiv+1;
end if;
end process;
clk <=clkdiv(21);

process(clk)
begin
if(rising_edge(clk)) then
if(reset='1')then count<="0000";
else
count<=count+1;
end if;
if(count="1001") then count<="0000";
end if;
end if;
end process;
end Behavioural;

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VHDL code for 4-bit BCD COUNTER with asynchronous Reset(Using clock
division)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity asbcdcounter is
Port ( sclk,reset: in std_logic;
q : out std_logic_vector(3 downto 0):= "0000");
end asbcdcounter;

architecture Behavioural of asbcdcounter is

signal count:std_logic_vector(3 downto 0):="0000";
signal clkdiv:std_logic_vector(21 downto 0):="0000000000000000000000";
signal clk:std_logic;

begin
process(sclk)
begin
if(rising_edge(sclk))then clkdiv<=clkdiv+1;
end if;
end process;

clk <=clkdiv(21);
process(clk,reset)
begin
if(reset='1')then count<="0000";
elsif(rising_edge(clk)) then
if(count="1001") then count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
end Behavioural;

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VHDL code for 4-bit Binary synchronous COUNTER with Reset(using clock
division)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sbincounter is
Port ( sclk,reset: in std_logic;
q : out std_logic_vector(3 downto 0) :="0000");
end sbincounter;

architecture Behavioural of sbincounter is

signal count:std_logic_vector(3 downto 0):="0000";
signal clkdiv:std_logic_vector(21 downto 0):="0000000000000000000000";
signal clk:std_logic;
begin
process(sclk)
begin
if(rising_edge(sclk))then clkdiv<=clkdiv+1;
end if;
end process;
clk <=clkdiv(21);

process(clk)
begin
if(rising_edge(clk)) then
if(reset='1')then count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
end Behavioural;

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VHDL code for 4-bit Binary asynchronous COUNTER with Reset(Using

clock division)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity asbincounter is
Port ( sclk,reset: in std_logic;
q : out std_logic_vector(3 downto 0) :="0000");
end asbincounter;
architecture Behavioural of asbincounter is
signal count:std_logic_vector(3 downto 0):="0000";
signal clkdiv:std_logic_vector(21 downto 0):="0000000000000000000000";
signal clk:std_logic;
begin
process(sclk)
begin
if(rising_edge(sclk))then clkdiv<=clkdiv+1;
end if;
end process;
clk <=clkdiv(21);

process(clk,reset)
begin
if(reset='1')then count<="0000";
elsif(rising_edge(clk)) then
count<=count+1;

end if;
end process;
q<=count;
end Behavioural;

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INTERFACING EXPERIMENT

Experiment No. 4

STEPPER MOTOR

Aim: Write a VHDL code to control speed, direction of Stepper motor.

BLOCK DIAGRAM:

Stepper motor interfacing

A stepper motor translates electrical pulses into mechanical movement. A
conventional motor (AC/DC motor) shaft run freely, whereas the stepper motor
shaft moves in a fixed increment & hence the shaft position can be controlled
precisely, say move by 4° & stop. Stepper motors are used for position control
applications such as dot matrix printers, disk drivers, robotics, etc.
There are two types of stepper motors (SM) --- permanent magnet SM &
variable reluctance SM, depending on the rotor type (whether permanent
magnet is used or not). The permanent magnet SM consists of a permanent
magnet rotor) also called the shaft) surrounded by a stator as shown in fig a.
Generally the stator has 4 windings that are paired with a center-tapped
common as shown in fig b. The centre tap allows a change of current direction in
each of the two coils, hence changing the direction of polarity in the stator poles
which return leads to a change in the direction of rotor rotation.
The rotation of the rotor in a SM along the winding energization sequence is
shown in table.
Depending on the number of teeth on the stator & rotor, the stepper motor
rotates fixed steps per revolution. The commonly available number of steps for
one revolution is 500, 200, 180, 144, 72, 48, and 24. The steps angle, i.e., the
movement of a single step of a stepper motor is calculated as .
Say for 200 steps per revolution. The step angle is per step.

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Similarly step angle for 72 steps per revolution is .

For the 4-step switching sequence shown above, after four steps the same
two windings will be ‘ON’, i.e., the sequence repeats after every 4 steps. After
completing 4 steps, the rotor moves only one tooth pitch. Hence if the rotor has
50 teeth (each teeth is one pole), the no of steps for one complete revolution is 4
steps x 50 rotor teeth = 200 steps / revolution. Hence for smaller step angle (i.e.,
more steps / revolution), the rotor must have more teeth.

To double the number of steps/revolution, say 400 instead of 200, we follow

the 8-step sequence shown in the table. Here, with this method, step size is half
the original size & hence the 8-step sequence is called ‘half stepping’.

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PROCEDURE:

1. Make the connection between FRC9 of the FPGA board to the Stepper motor
connector of the VTU card2.
2. Make the connection between FRC1 of the FPGA board to the Dip switch
connector of the VTU card2.
3. Connect the stepper motor to the VTU card2.
4. Connect the downloading cable and power supply to the FPGA board.
5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial
mode and select the respective BIT file and click program.
6. Make the reset switch on.
7. Using Dip switches verify the speed changes.

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VHDL CODE:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following lines to use the

declarations that are -- provided for instantiating Xilinx
primitive components. --library UNISIM;
--use UNISIM.VComponents.all;

entity STEPPERnew is
Port ( dout : out std_logic_vector(3 downto 0);
clk,reset : in std_logic;
row:in std_logic_vector(1 downto 0);
dir:in std_logic);
end STEPPERnew;

architecture Behavioural of STEPPERnew is

signal clk_div : std_logic_vector(20 downto 0);
signal clk_int: std_logic;
signal shift_reg : std_logic_vector(3 downto 0);
begin
process(clk)begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
end if;
end process;
clk_int<=clk_div(20) when row="00"else
clk_div(18) when row="01"else
clk_div(16) when row="10"else
clk_div(14);
process(reset,clk_int,dir)
begin
if reset='0' then shift_reg <= "1001";
elsif rising_edge(clk_int) then
if dir='0' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<=shift_reg(2 downto 0) & shift_reg(3);
end if;
end if;
end process;
dout <= shift_reg;
end Behavioural;

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UCF file (User Constraint file)

NET "clk" LOC = "p52" ;

NET "dir" LOC = "p76" ;
NET "dout<0>" LOC = "p141" ;
NET "dout<1>" LOC = "p2" ;
NET "dout<2>" LOC = "p4" ;
NET "dout<3>" LOC = "p5" ;
NET "reset" LOC = "p74";
NET "row<0>" LOC = "p77";
NET "row<1>" LOC = "p79";

RESULT:

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Experiment No. 5
DC motor

Aim: Write a VHDL Code to control Speed and Direction of DC motor.

BLOCK DIAGRAM:

INTERFACING DIAGRAM:

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PROCEDURE:

1. Make the connection between FRC9 of the FPGA board to the DC motor
connector of the VTU card2.

2. Make the connection between FRC7 of the FPGA board to the Keys connector
of the VTU card2.

3. Make the connection between FRC1 of the FPGA board to the Dip switch
connector of the VTU card2.

4. Connect the downloading cable and power supply to the FPGA board.

5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial
mode and select the respective BIT file and click program.

6. Make the reset switch on (active low).

7. Press the HEX keys and analyse the speed changes.

VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dcmotor is
generic(bits : integer := 8 ); -- number of bits used for duty cycle.
-- Also determines pwm period.
port ( CLK: in STD_LOGIC; -- 4 MHz clock
RESET,DIR: in STD_LOGIC; -- dircntr
pwm : out std_logic_VECTOR(1 DOWNTO 0);
rly: out std_logic;
ROW: in STD_LOGIC_VECTOR(0 to 3) ); -- this are the row lines
end dcmotor;

architecture dcmotor1 of dcmotor is

signal counter : std_logic_vector(bits - 1 downto 0):="11111110";
signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register
signal DDCLK,tick: STD_LOGIC; -- this has the divided clock.
signal duty_cycle: integer range 0 to 255;
signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines
begin
-- select the appropriate lines for setting frequency
process (CLK, DIV_REG) -- clock divider
begin
if (CLK'event and CLK='1') then
DIV_REG <= DIV_REG + 1;

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end if;
end process;
DDCLK<=DIV_REG(12);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------
-----
tick <= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
when "1110" => duty_cycle <= 255 ; --motor speed 1
when "1101" => duty_cycle <= 200 ; --motor speed 2
when "1011" => duty_cycle <= 150 ; --motor speed 3
when "0111" => duty_cycle <= 100 ; --motor speed 4
when others => duty_cycle <= 100;
end case;
end if;
end process;
process(DDCLK, reset)
begin
if reset = '0' then
counter <= (others => '0');
pwm<="01";
elsif (DDCLK'event and DDCLK = '1') then
counter <= counter + 1;
if counter >= duty_cycle then
pwm(1) <= '0';
else
pwm(1) <= '1';
end if; end if;
end process;
rly<=DIR; --motor direction control
end dcmotor1;

UCF file(User constraint File)

NET "CLK" LOC = "p52";
NET "DIR" LOC = "p76";
NET "pwm<0>" LOC = "p4";
NET "pwm<1>" LOC = "p141";
NET "RESET" LOC = "p74";
NET "rly" LOC = "p2";
NET "ROW<0>" LOC = "p69";
NET "ROW<1>" LOC = "p63";
NET "ROW<2>" LOC = "p59";
NET "ROW<3>" LOC = "p57";

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I/O PIN DETAILS

FRC1 FRC 2 FRC 3 FRC 4 FRC 6 FRC 7
FRC XF400 FRC XF400 FRC XF400 FRC XF400 FRC XF400 FRC XF400
1 74 1 84 1 100 1 112 1 28 1 57
2 76 2 85 2 102 2 116 2 31 2 59
3 77 3 86 3 124 3 119 3 33 3 63
4 79 4 87 4 103 4 118 4 44 4 69
5 78 5 89 5 105 5 123 5 46 5 68
6 82 6 90 6 107 6 131 6 47 6 73
7 80 7 92 7 108 7 130 7 50 7 70
8 83 8 96 8 113 8 137 8 51 8 20
9 VCC 9 Vcc 9 Vcc 9 Vcc 9 Vcc 9 Vcc
10 GND 10 Gnd 10 Gnd 10 Gnd 10 Gnd 10 Gnd

FRC
FRC 5 FRC 8 FRC 9
10
FRC XF400 FRC XF400 FRC XF400 FRC XF400
1 1 1 93 1 60 1 5
2 12 2 95 2 56 2 4
3 13 3 97 3 41 3 2
4 14 4 98 4 40 4 141
5 15 5 99 5 36 9 Vcc
6 17 6 104 6 35 10 Gnd
7 18 7 125 7 32
8 21 8 122 8 10 CLK PIN
XF
9 23 9 129 9 11 52
400
10 24 10 132 10 8
11 26 11 135 11 7
12 27 12 140 12 6
13 5V 13 5V 13 5V
14 -5 14 _5 14 _5
15 Vcc 15 Vcc 15 Vcc
16 Gnd 16 Gnd 16 Gnd

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MODEL VIVA QUESTIONS

1. What does VHDL stands for?

2. Which IEEE standard describes the VHDL language?
3. List the three popular Hardware languages.
4. Which are the different levels of abstraction that can be specified using VHDL?
5. List the different design units of VHDL.
6. Which are the mandatory design units to write VHDL code?
7. Which are the different modes of port declaration?
8. Which are the valid characters for identifier declaration?
9. Which are the different classes of operators?
10. Where do you write the concurrent statements?
11. Where do you write the sequential statement?
12. In which model process statement appears?
13. What is the importance of sensitivity list in process statement?
14. Is VHDL Case sensitive?
15. Does VHDL support multi dimensional arrays?
16. Can combinational circuits be coded inside the process?
17. Does VHDL support operator overloading?
18. Is it possible to write multiple entities for a single architecture?
19. Is it possible to write multiple architectures for a single entity?
20. Where we declare the variable?
21. Write device configuration for CPLD and FPGA Used in your Lab.
22. Expand CPLD and FPGA.
23. Differentiate sequential and concurrent statement.
24. List the different types of wait statements.
25. How you model your program using wait statement?
26. What are the different modelling styles in VHDL?
27. What is the difference between the bit and std_logic?
28. What is the difference between the variable and signals?
29. Name the different VHDL objects.
30. Name the different data types used in VHDL.
31. Explain the VHDL term (i) Entity, (ii) Architecture, (iii) Configuration, (iv) Package,
(v) Driver, (vi) Process, (vii) Attribute, (viii) Generic and (ix) Bus.
32. Write the general syntax for Case, LOOP, Architecture Configuration, package, Process,
Exit.
33. Differentiate between Procedure and Function
34. Explain attribute, event, range
35. How to detect signal edge using attribute?
36. What is synthesis?
37. What is simulation?
38. Differentiate between syntax error and semantic error.
39. Is other clause necessary in VHDL case statement? why?
40. What are the inputs required for synthesis?
41. Which architecture description you preferred? Why?
42. Which Tool you used for simulation?
43. Which Tool you used for synthesis?
44. xc3s400tq144- 3S stands for? what 400 stands for? what tq144 stands for?
45. xc3s400tq144- xc stands for? what -4 stands for?

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46. What is the difference between CPLD and FPGA?

47. What is the difference between synchronous and asynchronous reset?
48. What is the basic element of memory?
49. What do you mean by latch?
50. How you model latch in VHDL?
51. What is the difference between synchronous and asynchronous counter?
52. What is the difference between backend and front-end?
53. Expand ASIC.
54. Expand JTAG.
55. Expand ISE
56. Which IEEE standard supports JTAG?
57. What information is present in .Bit File?
58. What do you mean by configuration?
59. Which file used to configure the CPLD?
60. Which file used to configure the FPGA?
61. What is synchronous reset and asynchronous reset?

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VIVA QUESTION AND ANSWERS

Q. What does VHDL stands for?
VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language.

Q. Types of models in VHDL?

There are 3 types: Data flow Description, Behavioural Description and
Structural Description.
1. Data-flow description: A digital circuit can be described at the data-flow
level by giving the logic equation of that circuit.
2. Behavioural description: A digital circuit can be described at the
behavioural level in terms of Its function or behaviour, without giving
any implementation details.
3. Structural description: A digital circuit can be described at the
structural level by specifying the interconnection of the gates or flip-flops
that comprise the circuit.

Q. What is meant by embedded system?

An embedded system is a computer system designed for specific control functions
within a Larger system, often with real-time computing constraints.

Q. What is an I.C ?
Integrated circuit. A miniaturized electronic circuit that combines a variety of
components like transistors, resistors, capacitors, and diodes all into one
incredibly small piece.

Q. What is FPGA ?
Short for Field-Programmable Gate Array, a type of logic chip that can be
programmed. An FPGA is similar to a PLD, but whereas PLDs are generally
limited to hundreds of gates, FPGAs support thousands of gates. They are
especially popular for prototyping integrated circuit designs. Once the design is
set, hardwired chips are produced for faster performance.
FPGAs offer many design advantages, including:
 Rapid prototyping
 Shorter time to market
 The ability to re-program in the field for debugging
 Lower NRE costs
 Long product life cycle to mitigate obsolescence risk

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Q. xc3s400tq144-4 what xc stands for? what 3S stands for? what 400 stands
for? what tq144 stands for? what -4 stands for? What is the clock frequency of
xc3s400tq144-4 hardware ?
xc  Xilinx component
3S  Spartan 3
400  400K gate density { Logic gates are available in
this chip}
TQ144  Thin Quad 144 pin I.C.
-4  Speed for standard performance
Clock frequency  4.096MHz

Q. What is the IC number for DAC used in your FPGA-testing unit and it
is of how many bit?
The IC number for DAC used in FPGA-testing unit is IC-0808 and it is of 8bit.

Q. What is CPLD ?
(Complex PLD) A programmable logic device that is made up of several simple
PLDs (SPLDs) with a programmable switching matrix in between the logic
blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the
logic design interconnections.

Q. Is VHDL code is case sensitive?

No, it is not a case sensitive.

Q. Is Verilog code is case sensitive?

Yes, verilog code is case sensitive. (Lower case)

Q. Which port you are using to synthesize on FPGA?

Parallel port and It is a 25 pin connector.

Q. What is the expansion for JTAG cable?

Joint Test Action Group.

Q. What is the expansion for VTU Card?

Versatile Testing Unit.

Q. What is the expansion for FRC cable?

Fringe Ribbon Cable.

Q. What is the expansion for UCF File?

User Constraints File.
Q. What is the expansion of ISE?
Integrated Software Environment.

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Q. What is the expansion for IEEE?

Institute of Electrical and Electronics Engineers.

Q. What is the expansion for LUT?

Look-Up Tables (LUTs) are used to implement function generators in CLBs.

Q. What is the expansion for NGD File?

A Native Generic Database (NGD) file that describes the logical design reduced
to Xilinx primitives.

Q. What is the extension for VHDL code?

.vhd

Q. What is the extension for Verilog code?

.v
Q. After running generate programming file what is the extension file
generated?
.bit

Q. What are logic gates?

A programming function that, processes true and false signals.

Q. What are combinational logic circuits?

In digital circuit theory, combinational logic circuit is a type of digital logic which is
implemented by Boolean circuits, where the output is a pure function of the present
input only.

Q. What is the difference between half adder and full adder ?

Sl. No. HALF ADDER FULL ADDER

01. A half adder is “Half” Full adder is called “full” because it

because it includes only will include a carry-in bit and a
one carry bit. carry-out bit.

02. It has 2 inputs It has 3 inputs

Q. What is ENCODER and mention its applications?

An encoder is a device used to change a signal (such as a bit stream) or data
into a code.

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Applications of Encoder:
1. Media:
 Software for encoding audio, video, text into standardized formats:
A compressor encodes data (e.g., audio/video/images) into a smaller
form (see codec)
An audio encoder converts analog audio to digital audio signals
A video encoder converts analog video to digital video signals
An email encoder secures online email addresses from email harvesters
A PHTML encoder preserves script code logic in a secure format that is
transparent to visitors on a web site
2. Job positions:
A Data Entry Encoder may enter data from phone surveys in a coded
format into a database.
A Data Entry Encoder may enter payment amounts from legal tender
documents from financial institutions into a database.
3. Security:
A device or person that encodes or encrypts military messages, such as
the ADFGVX cipher in WWI or the Enigma device in WWII.
A Microchip hopping encoder integrated circuit for non-fixed-code
secured entry.
4. Medical encoding software:
Encoder Pro searches ICD-9-CM, CPT, and HCPCS Level II medical
codes, to increase accuracy and allow ease of auditing for compliance.
5. Transducers:
Transducers (such as optical or magnetic encoders) sense position or
Orientation for
use as a reference or active feedback to control position:
A rotary encoder converts rotary position to an analog (e.g., analog
quadrature) or digital (e.g., digital quadrature, 32-bit parallel, or USB)
electronic signal.
 A linear encoder similarly converts linear position to an electronic
signal.

Q. What is DECODER and mention its applications ?

A decoder is a combinational digital circuit that decodes an n-bit binary input in
to its corresponding decimal level. An n-bit input (A0-A(n)) decoder has 2n
output (E0-E(2n -1)) lines with each line corresponding to a different minterm
or decimal level.

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Applications of Decoder:
Audio decoder, converts analog audio to digital form
Binary decoder, digital circuits such as 1-of-N and seven-segment
decoders
Decompressor (compression decoder), converts compressed data (e.g.,
audio/video/images) to an uncompressed form
Instruction decoder, an electronic circuit that converts computer
instructions into CPU control signals
Video decoder, converts base-band analog video to digital form

Q. What is multiplexer and mention its applications ?

In electronics, a multiplexer or mux is a device that selects one of several
analog or digital input signals and forwards the selected input into a single line.
Multiplexers are mainly used to increase the amount of data that can be sent
over the network within a certain amount of time and bandwidth. A multiplexer is
also called a data selector.

Applications of Multiplexer:
Multiplexer are used in various fields where multiple data need to be
transmitted using a single line. Following are some of the applications of
multiplexers –
Communication system – Communication system is a set of system that
enable communication like transmission system, relay and tributary
station, and communication network. The efficiency of communication
system can be increased considerably using multiplexer. Multiplexer
allow the process of transmitting different type of data such as audio,
video at the same time using a single transmission line.
Telephone network – In telephone network, multiple audio signals are
integrated on a single line for transmission with the help of multiplexers.
In this way, multiple audio signals can be isolated and eventually, the
desire audio signals reach the intended recipients.
Computer memory – Multiplexers are used to implement huge amount
of memory into the computer, at the same time reduces the number of
copper lines required to connect the memory to other parts of the
computer circuit.
Transmission from the computer system of a satellite – Multiplexer
can be used for the transmission of data signals from the computer
system of a satellite or spacecraft to the ground system using the GPS
(Global Positioning System) satellites.

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Q. What is de-multiplexer and mention its applications ?

A De-multiplexer or demux is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input.
Applications of de-multiplexer:
Demultiplexer is used to connect a single source to multiple
destinations. The main application area of demultiplexer is
communication system where multiplexer are used. Most of the
communication system are bidirectional i.e. they function in both ways
(transmitting and receiving signals). Hence, for most of the applications,
the multiplexer and demultiplexer work in sync. Demultiplexer are also
used for reconstruction of parallel data and ALU circuits.
Communication System – Communication system use multiplexer to
carry multiple data like audio, video and other form of data using a
single line for transmission. This process make the transmission easier.
The demultiplexer receive the output signals of the multiplexer and
converts them back to the original form of the data at the receiving end.
The multiplexer and demultiplexer work together to carry out the
process of transmission and reception of data in communication system.
ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU
can be stored in multiple registers or storage units with the help of
demultiplexer. The output of ALU is fed as the data input to the
demultiplexer. Each output of demultiplexer is connected to multiple
register which can be stored in the registers.
Serial to parallel converter – A serial to parallel converter is used for
reconstructing parallel data from incoming serial data stream. In this
technique, serial data from the incoming serial data stream is given as
data input to the demultiplexer at the regular intervals. A counter is
attach to the control input of the demultiplexer. This counter directs the
data signal to the output of the demultiplexer where these data signals
are stored. When all data signals have been stored, the output of the
demultiplexer can be retrieved and read out in parallel.

Q. What is comparator and mention its applications?

A comparator is a device that compares two voltages or currents and switches its
output to indicate which is larger. They are commonly used in devices such as
Analog-to-digital converters (ADCs).

Applications of Comparator:
These are used in the address decoding circuitry in computers and
microprocessor based devices to select a specific input/output device for
the storage of data.

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These are used in control applications in which the binary numbers

representing physical variables such as temperature, position, etc. are
compared with a reference value. Then the outputs from the comparator
are used to drive the actuators so as to make the physical variables
closest to the set or reference value.
Process controllers
Servo-motor control

Q. What are sequential circuits?

Sequential logic is a type of logic circuit whose output depends not only on the
present input but also on the history of the input. There are two types of
sequential circuits namely :- a). Synchronous sequential logic and b). Asynchronous
sequential logic.

Q. What are synchronous sequential logic circuits?

A synchronous sequential circuit changes their states and output values at fixed
points of time, which are specified by the rising and/or falling edge of a free-
running clock signal. Its behavior is defined at discrete instants of time.

Q. What are asynchronous sequential logic circuits?

An asynchronous sequential circuit changes their states and output values
whenever a change in input values occurs. Its behavior depends on the order in
which its input signals change and can be affected at any time.

Q. What are latches?

Latches are memory devices, and can store one bit of data for as long as the
device is powered. It has exactly two stable states. These states are high-output
and low-output. A latch has a feedback path, so information can be retained by
the device.

Q. What are SR latches?

An SR latch (Set/Reset) is an asynchronous device: it works independently of
control signals and relies only on the state of the S and R inputs.

Fig: SR latch made from two NAND gates.

Q. What are shift registers?
Shift registers are a type of sequential logic circuit, mainly for storage of digital
data. They are a group of flip-flops connected in a chain so that the output from
one flip-flop becomes the input of the next flip-flop.

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Q. What are flip flops?

Flip flops are sequential circuits used to store one bit of information at a time.
Which has two stable states i.e., present and past previous state.

Q. What are timers?

A timer is a specialized type of clock that can be used to control the sequence of
an event or process.

Q. What are counters and mention its applications?

Counter is a digital circuit which is able to count from a specific number to
another specific number. Depending upon the counting style the counters can
be divided into two
1 UP counter- which increment one by one (eg. 0,1,,2,3,4,5............15) for a
4 bit counter.
2 Down counter- which decrements one by one (eg.
5,14,13,12,11,10,9,8................0) for a 4 bit counter.

Applications of counter:
Digital clocks
Frequency counter
Binary Counter etc.

Q. What is the difference between Timer and Counter?

A counter is a device that records the number of occurrences of a particular
event. In modern applications, counters are based on electronic devices and the
counters are sequential logic circuit designed to record the number of electric
pulses fed into the counter.
A timer is an application of the counters where a certain signal with a fixed
frequency (hence period) is counted to record the time.

Q. What is a clock?
A clock is a signal that represents the time that a wave stays at a High or Low
state. The rising and falling edges of a clock square wave trigger the activity of
the circuits.

Q. What is meant by digitization?

The process of converting continuous analog signals into a finite number of
discrete states is called digitization.

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Q. What is meant by simulation?

It is a tool to virtually investigate the behavior of the system under study. It is
an attempt to model a real-life or hypothetical situation on a computer so that it
can be studied to see how the system works. Or In other words Simulation is the
process of verifying the logic and timing of a design.

Q. What is meant by logic synthesis?

Logic synthesis is a process that starts from a high level of logic abstraction
(typically Verilog or VHDL) and automatically creates a lower level of logic
abstraction using a library containing primitives.

Q. What is the use of project navigator?

Project Navigator organizes your design files and runs processes to move the
design from design entry through implementation to programming the targeted
Xilinx device.

Q. What is a test bench?

An HDL netlist containing test vectors to drive a simulation.

Q. What is a port?
A logical connector that associates signals across hierarchical boundaries. Port
location refers to a package pin on the IC.

Q. What is a vector?
The logical state of a set of nodes within a circuit as a function of time.

Q. In VHDL code if you are using (3 downto 0) what does “downto” refers
to ?
“downto” refers to little endian systems

Q. In VHDL code if you are using (0 to 3) what does “to” refers to?
“to” refers to Big endian systems

Q. What is meant by schematic?

A schematic is a hierarchical drawing representing a design in terms of user and
library components.

Q. What is meant by RTL schematic?

Register Transfer Level schematic. This schematic shows a representation of
the pre-optimized design in terms of generic symbols, such as adders,
multipliers, counters, AND gates, and OR gates, which are independent of the
targeted Xilinx device.

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Q. What is the function of translate tool?

The Translate process merges all of the input netlists and design constraints and
outputs a Xilinx Native Generic Database (NGD) file, which describes the
logical design reduced to Xilinx primitives.

Q. What is the function of mapping?

Mapping is the process of assigning logic elements to the specific physical
elements that actually implement logic functions in a device. OR

The Map process maps the logic defined by an NGD file into FPGA elements,
such as CLBs and IOBs. The output design is a Native Circuit Description
(NCD) file that physically represents the design mapped to the components in
the Xilinx FPGA.

Q. What is the function of place and route?

The Place and Route process takes a mapped NCD file, places and routes the
design, and produces an NCD file that is used as input for bit stream generation.
OR
Place and route will fit the logic into the logic device and placing the logic
elements in optimal locations and routing the signals from one unit to another in
an optimal way.

Q. What is the function of boundary scan in Xilinx?

Boundary scan is a method used for board-level testing of electronic assemblies.
The primary objectives are the testing of chip I/O signals and the
interconnections between integrated circuits (ICs). It is the method for
observing and controlling all new chip I/O signals through a standard interface
called a Test Access Port (TAP). The boundary scan architecture includes four
dedicated I/O pins for control and is described in IEEE specification 1149.1.

Q. What is boundary scan description language?

Boundary Scan Description Language (BSDL) is a subset of VHDL used to
describe how JTAG (IEEE 1149.1) is implemented in a particular device.

Q. Mention BSDL file format?

BSDL files contain the following elements:
Entity Description
Generic Parameter
Port Description
Use Statements
Pin Mapping(s)
Scan Port Identification

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Instruction Register Description

Register Access Description
Boundary Register Description

Q. What is a bit?
A bit is a binary digit representing 0 or 1.

Q. What is a buffer?
A buffer is an element used to increase the current or drive of a weak signal
and, consequently, increase the fanout of the signal. It is a storage
element.

Q. What is meant tri-state buffer?

A tri-state buffer is that places an output signal in a high-impedance state to
prevent it from contending with another output signal.

Q. What is a BUS?
A group of two or more signals that, carry closely-associated signals in an
electronic design.

Q. What is meant by architecture?

Architecture is the common logic structure of a family of programmable
integrated circuits.

Q. What is ASIC?
An Application-Specific Integrated Circuit (ASIC) is either a full-custom
circuit in which every mask is defined by the user or a semi-custom circuit (gate
array) where only a few masks are defined.

Q. What is the function of std_logic?

It supports other than ‘0’ and ‘1’ like
U – Un-initialized
- – Don’t care
X – Un known
Z – High Impedance
L – Weak low
H – Weak high
W – Weak un known

Q. Which are the basic design units used in VHDL?

Entity and Architecture.

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Q. What is the use of function “Entity” w.r.t. VHDL?

Entity is a basic design tool used in VHDL used to describe the external
boundary of the hardware.
Q. What is the use of function “architecture” w.r.t. VHDL?
Architecture is a basic design tool used in VHDL which describes the
functionality / behavior of the entity.

Q. What does the process statement contains?

Process statement contains sensitivity list.

Q. What is the use of function “signal” w.r.t. VHDL?

Signal is a VHDL object and it is declared in the declaration part of the
architecture.

Q. What is use of function “variable” w.r.t. VHDL?

Variable is a VHDL object and must be declared within the process in which
they are used and are local to the process.

Q. What is use of function “generics” w.r.t. VHDL?

Generics are a means of passing specific information into an entity. They do not
have a mode (direction). In the corresponding declaration, the generics are
declared before the ports.
Q. Which software you are using to write a VHDL and verilog code?
Xilinx 9.1i

Q. Which software you are using for simulation? List any other software’s
used for simulation?
Xilinx ISE Simulator. The other software used is modelsim simulator.

Q. What does the symbol “=>” refers w.r.t. VHDL?

The symbol “=>” refers to imply that means to suggest or to involve by logical
necessity.

Q. What does the symbol “<=” refers w.r.t. VHDL?

The symbol “<=” refers to signal assignment operator or a statement.

Q. Where does the concurrent statements and sequential statements are

used?
Concurrent statements are used in dataflow and structural descriptions.
Sequential statements are used in behavioral descriptions. Ex:- if statement

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Q. What does the symbol “&” refers w.r.t. VHDL?

The symbol “&” refers to concatenation. This operator is used to join together
two arrays end to end to make one longer array.

Q. What is the function of component in structural description?

It is a analogous to a chip socket. It creates an extra interface which allows more
flexibility when building hierarchical system out of its component parts.

Q. Mention different loop statements used in VHDL?

There are three different loop statements in VHDL namely:
a) While loop: This loop tests a Boolean condition at the top of the loop and
only leaves the loop when the condition is false.
b) Un bounded loop: This loop simply loops forever.
c) For loop: Only the for loop is synthesizable and that only if the bounds
are constant. The other loops can be useful in test benches and behavioral
models.

Q. What is chipscope pro ?

Chip Scope Pro is a software-based logic analyzer that allows monitoring the
status of
selected signals in a design in order to detect possible design errors. It provides
several
cores that can be added to a design by generating the cores with the CORE
Generator
tool, instantiating them into the source code, and connecting the cores to the
design
before the synthesis process.

Q. What is stepper motor?

A stepper motor is a motor that converts electrical power into mechanical
power. Stepper motors does not continuously rotate Instead, they rotate in steps
(from which they got the name). Each step is a fraction of a full circle. This
fraction depends mostly from the mechanical parts of the motor, and from the
driving method. Instead of an AC or a DC voltage, they are driven (usually)
with pulses. Each pulse is translated into a degree of rotation. For example, an
1.8o stepper motor, will revolve its shaft 1.8 o on every pulse that arrives. Often,
due to this characteristic, stepper motors are called also digital motors.

Q. Explain DAC?
Digital-to-Analog converter (DAC) is a device that converts a digital (usually
binary) code to an analog signal (current, voltage, or electric charge). An analog-to-digital
converter (ADC) performs the reverse operation. Signals are easily stored and

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transmitted in digital form, but a DAC is needed for the signal to be recognized
by human senses or other non-digital systems.

Q. Explain PWM?
Pulse Width Modulation, abbreviated as PWM, is a method of transmitting
information on
a series of pulses. The data that is being transmitted is encoded on the width of
these
pulses to control the amount of power being sent to a load. In other words, pulse
width modulation is a modulation technique for generating variable width pulses
to represent the amplitude of an input analog signal or wave. The popular
applications of pulse width modulation are in power delivery, voltage regulation
and amplification and audio effects.

Q. What is duty cycle?

A duty cycle is the percentage of one period in which a signal is active. A period
is the
time it takes for a signal to complete an on-and-off cycle. As a formula, a duty
cycle may be expressed as:

where, D = Duty cycle

T = Time the signal is active

P = Total period of the signal

Thus, a 60% duty cycle means the signal is on 60% of the time but off 40% of
the time.

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Q. Difference between FPGA and CPLD?

Sl. No. FPGA CPLD

CPLD contains only a few
FPGA contains up to 100,000 of
01 blocks of logic that reaches up to
tiny logic blocks.
a few thousands.

In terms of architecture, FPGAs In terms of architecture, CPLDs

are considered as ‘fine-grain’ are considered as ‘coarse-grain’
02 devices because it contains a lot because It contains only a few
of tiny logic blocks that could blocks of logic but larger that
reach up to 100,000. reaches up to 100.

FPGAs are great for more CPLDs are better for simpler
03
complex applications ones.

FPGA is a RAM-based digital

logic chip CPLD is EEPROM-based. (Non-
04
volatile memory)
(Volatile memory)

FPGAs are made up of tiny logic CPLDs are made of larger

05
blocks. blocks.

Q. What is a program?
A program is a sequence of instructions, written to perform a specified task with
a computer.

Q. What is software?
A software is a set of program which is the non-tangible component of computers.
Computer software contrasts with computer hardware, which is the physical
component of
computers.

Q. What is hardware?
Hardware, in the computer world, refers to the physical components that make
up a computer system. Some basic computer hardware includes the
motherboard, CPU, RAM,
Hard drive, etc.

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Q. What is an instruction?
An instruction is an order given to a computer processor by a computer
program.

Q. Difference between software and hardware?

Hardware Software
Collection of instructions that enables a
user to interact with the computer.
Software is a program that enables a
Definition Devices that are required to store
computer to perform a specific task, as
and execute (or run) the software. opposed to the physical components of
the system (hardware).
Types Input, storage, processing, control, System software, Programming
and output devices. software, and Application software.
CD-ROM, monitor, printer, video Quick books, Adobe Acrobat, Winoms-
card, scanners, label makers, Cs, Internet Explorer , Microsoft Word
Examples
routers , and modems. , Microsoft Excel
Hardware serve as the delivery system
for software solutions. The hardware of To perform the specific task you need
a computer is infrequently changed, in to complete. Software is generally not
comparison with software and data, needed to for the hardware to perform
Function which are “soft” in the sense that they its basic level tasks such as turning on
are readily created, modified, or erased and responding to input.
on the computer.

Inter
Hardware starts functioning once To deliver its set of instructions,
dependen
software is loaded. Software is installed on hardware.
cy
Hardware failure is random. Software failure is systematic.
Hardware does have increasing Software does not have an increasing
Failure
failure at the last stage. failure rate.
Nature Hardware is physical in nature. Software is logical in nature.

Q. What are signed and unsigned numbers?

An 8 bit number system can be used to create 256 combinations (from 0 to
255), and the

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first 128 combinations (0 to 127) represent positive numbers and next 128
combinations
(128 to 255) represent negative numbers.

The positive numbers are counted in a clockwise direction from 0 and the
negative numbers are counted in a counter-clockwise direction.

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VHDL PART
VHDL LAB Simulated Waveforms
Logic gates:

Decoder:

Encoder:

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8 to 3 Encoder (without priority)

8 to 1 Multiplexer.

1 to 4 Demultiplexer

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Full adder (dataflow description)

Full adder (behavioral description)

Full adder (structural description)

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Full adder using structural, behavioral and dataflow models:

Full adder behavioural description (using procedure and task)

Full adder data flow model

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Binary counter with synchronous reset (using clock division)

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Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

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Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

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Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

Sec / Batch : …………….. Date :………………….. Sec / Batch : …………….. Date :…………………..
Name USN Name USN

Experiment: Table No. …………… Experiment: Table No. ……………

Sl. Component Range Qty Sl. Component Range Qty
No. No.
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Signature of Faculty Signature of Faculty

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