2

I C Protocol
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I2C
Developed by Philips Semiconductor (now NXP) as a simple bidirectional two wire bus
protocol for efficient inter-IC data communication. Originally, the I2 C bus was designed to
link a small number of devices on a single card, such as to manage the tuning of a car radio
or TV.

This bus is called the Inter IC or I2C-bus. All I2C-bus compatible devices incorporate an
on-chip interface which allows them to communicate directly with each other via the
I2C-bus.
Features
➔ Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
➔ Each device connected to the bus is software addressable by a unique address and
simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
➔ It is a true multi-master bus including collision detection and arbitration to prevent
data corruption if two or more masters simultaneously initiate data transfer.
➔ Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in
the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode
Plus, or up to 3.4 Mbit/s in the High-speed mode.
Pg. 4 https://www.nxp.com/docs/en/user-guide/UM10204.pdf
SDA & SCL Signals
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
current-source or pull-up resistor. When the bus is free, both lines are HIGH.
SDA & SCL Signal Levels
➔ Due to the variety of different technology devices (CMOS, NMOS, bipolar)
that can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and
‘1’ (HIGH) are not fixed and depend on the associated level of VDD.
➔ Input reference levels are set as 30 % and 70 % of VDD; VIL is 0.3VDD and
VIH is 0.7VDD.
START & STOP conditions
➔ All transactions begin with a START (S) and are terminated by a STOP (P).
➔ A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START
condition.
➔ A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition.
DATA Validity
➔ The data on the SDA line must be stable during the HIGH period of the clock.
➔ The HIGH or LOW state of the data line can only change when the clock signal on
the SCL line is LOW .
➔ One clock pulse is generated for each data bit transferred.
Byte format
➔ Every byte put on the SDA line must be eight bits long.
➔ The number of bytes that can be transmitted per transfer is unrestricted.
➔ Each byte must be followed by an Acknowledge bit.
➔ Data is transferred with the Most Significant Bit (MSB) first.
➔ If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, for example servicing an internal interrupt, it can
hold the clock line SCL LOW to force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data and releases clock line
SCL.
ACK / NACK
➔ The acknowledge takes place after every byte. The acknowledge bit allows the
receiver to signal the transmitter that the byte was successfully received and another
byte may be sent. The master generates all clock pulses, including the acknowledge
ninth clock pulse.
➔ The transmitter releases the SDA line during the acknowledge clock pulse so the
receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
➔ When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal. The master can then generate either a STOP condition to abort
the transfer, or a repeated START condition to start a new transfer.
ACK / NACK
There are five conditions that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to
respond with an acknowledge.

2. The receiver is unable to receive or transmit because it is performing some real-time

function and is not ready to start communication with the master.

3. During the transfer, the receiver gets data or commands that it does not understand.

4. During the transfer, the receiver cannot receive any more data bytes.

5. A master-receiver must signal the end of the transfer to the slave transmitter.
Slave address and R/W’ bit
After the START condition (S), a slave address is sent. This address is seven bits long
followed by an eighth bit which is a data direction bit (R/W) — a ‘zero’ indicates a
transmission (WRITE), a ‘one’ indicates a request for data (READ).
Master Transmitter
Master Receiver
Master Transceiver
Arbitration
Arbitration, refers to a portion of the protocol required only if more than one master is
used in the system.

A master may start a transfer only if the bus is free. Two masters may generate a START
condition on the bus at the same time. Arbitration is then required to determine which
master will complete its transmission.
Arbitration
Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks
to see if the SDA level matches what it has sent.

This process may take many bits. Two masters can actually complete an entire transaction
without error, as long as the transmissions are identical.

The first time a master tries to send a HIGH, but detects that the SDA level is LOW, the
master knows that it has lost the arbitration and turns off its SDA output driver. The other
master goes on to complete its transaction.
I2C Protocol Summary
I2C in LPC2148
➔ Standard I2C compliant bus interfaces that may be configured as Master or Slave.
➔ Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
➔ Programmable clock to allow adjustment of I2C transfer rates.
➔ Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
I2C Bus configuration
I2C Operating Modes
➔ In a given application, the I2C block may operate as a master, a slave or both.
➔ If processor wishes to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave operation is not interrupted.
➔ If bus arbitration is lost in the master mode, the I2C block switches to the slave mode
immediately and can detect its own slave address or general call address in the same
serial transfer.
Master Transmitter Mode

➔ I2EN must be set to 1 to enable the I2C function.

➔ If AA bit is 0, the I2C interface will not acknowledge any address when another
device is master of the bus. It basically not the master itself but not a slave
either.
➔ STA, STO, SI bts must be 0. The SI bit is cleared by writing 1 to the SIC bit in
the I2CCONCLR register.
Master Transmitter Mode Contd.
➔ The I2C interface will enter the master transmitter mode when software sets the STA
bit. The I2C logic block will send the START condition as soon as the bus is free.
➔ After the START condition is transmitted, the SI bit is set, and the status code in the
I2CSTAT register is 0x08.
➔ This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit.
➔ After slave+r/w transmission and acknowledgement reception the SI bit is set again,
and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or
0x68, 0x78, or 0xB0 if the slave mode was enabled.
Transfer Rate Calculation
LAB Experiment on I2C
Interfacing I2C EEPROM device, 24Cxx series.
24Cxx I2C EEPROM Interfacing
24Cxx I2C EEPROM Interfacing
24Cxx I2C EEPROM Interfacing