A TECHNICAL SEMINAR

ON

HOW SAND IS TRASFER INTO SILICON CHIP

A Seminar Submitted in partial fulfillment of the requirement for

the award of the degree of

BACHELOR OF TECHNOLOGY IN MECHANICAL ENGINEERING

Submitted by

MOKALLA SRIHITHA REDDY

177R5A0323

DEPARTMENT OF THE MECHANICAL ENGINEERING

CMR TECHNICAL CAMPUS

Academic Year 2019-2020

INTRODUCTION:

However brain is the important part of the human being,in the same way chip is most
important component of camera and computer.

 chip is the most complicated part which we manufacture

 first ENIAC computers have 10000 capacitors ,7000 diodes ,70000 resistors
,18000 vaccum tubes are combined and there were almost 500000 wiring
connections and 30 tons weight .,This is totally inserted in a MICROCHIP which
is very very very small.

And this is due to transistors

Instead of vacuum tubes transistors were used and it is the possibility to make a chip.

The amazing journey from sandcastle to Core i7 processor

 STARTING WITH SAND:

The deserts of Arizona are home to Intel’s Fab 32, a $3billion factory
that’s performing one of the most complicated electrical engineering feats
of our time.
It’s here that processors with components measuring just 45 millionths of
a millimetre across are manufactured, ready to be shipped out to
motherboard manufacturers all over the world.

Creating these complicated miniature systems is impressive enough, but

it’s not the processors’ diminutive size that’s the most startling or
impressive part of the process.
It may seem an impossible transformation, but these fiendishly complex
components are made from nothing more glamorous than sand. Such a
transformative feat isn’t simple. The production process requires more
than 300 individual steps.

We’ve taken an in-depth look at Intel’s manufacturing method and

distilled the whole process into 10 stages. So, to find out how sandcastles
become Core i7 processors, read on – and prepare to be amazed.
MOORE’SLAW

According to Moore’s Law, the number of transistors on a chip roughly doubles every
couple of years. As a result, the transistor scale gets smaller and smaller. As the
transistor count climbs, so does the ability to integrate more capabilities onto a chip
andincreasedevicecomplexity.

The cumulative impact of these spiraling increases in capabilities enables today’s

mobile devices, fuels the increasingly Internet-connected and information-rich digital
experiences we seek, and powers industries and our global economy.

Delivering Moore’s Law requires numerous innovations. Intel’s world-first, advanced

transistor design introductions include strained silicon (2003), 45nm with high-
k/metal gate silicon technology (2007), followed by the 32nm 2nd generation high-
k/metal gate silicon technology (2009). Recently, Intel introduced another radical
design change—22nm 3-D Tri-Gate transistors (2011), which entered high-volume
production in 2012.
Step one: Converting sand to silicon

Sand is composed of silica (also known as silicon dioxide), and is the

starting point for making a processor. Sand used in the building industry is
often yellow, orange or red due to impurities, but the type chosen in the
manufacture of silicon is a purer form known as silica sand, which is
usually recovered by quarrying.

Silica sand is also known as silicon dioxide, and as you've no doubt guessed from the
name it's a compound of silicon and oxygen. To get the silicon, the oxygen is
removed by mixing it with carbon and heating it in an electric arc furnace to
temperatures beyond 2,000 degrees C. At those temperatures the carbon reacts with
the oxygen, becoming carbon dioxide and leaving pure silicon in the bottom of the
furnace.

That silicon is then treated with oxygen to remove impurities such as calcium or
aluminium, leaving what's known as metallurgical grade silicon. That's up to 99%
pure.

To extract the element silicon from the silica, it must be reduced (in other
words, have the oxygen removed from it). This is accomplished by heating
a mixture of silica and carbon in an electric arc furnace to a temperature
in excess of 2,000°C.

The carbon reacts with the oxygen in the molten silica to produce carbon
dioxide (a by-product) and silicon, which settles in the bottom of the
furnace. The remaining silicon is then treated with oxygen to reduce any
calcium and aluminium impurities. The end result of this process is a
substance referred to as metallurgical -grade silicon, which is up to 99 per
cent pure.
This is not nearly pure enough for semiconductor manufacture, however,
so the next job is to refine the metallurgical -grade silicon further. The
silicon is ground to a fine powder and reacted with gaseous hydrogen
chloride in a fluidised bed reactor at 300°C to give a liquid compound of
silicon called trichlorosilane.

Impurities such as iron, aluminium, boron and phosphorous also react to

give their chlorides, which are then removed by fractional distillation. The
purified trichlorosilane is vaporised and reacted with hydrogen gas at
1,100°C so that the elemental silicon is retrieved.

During the reaction, silicon is deposited on the surface of an electrically

heated ultra-pure silicon rod to produce a silicon ingot. The end resul t is
referred to as electronic-grade silicon, and has a purity of 99.999999 per
cent.

Step two: Creating a cylindrical crystal

Although pure to a very high degree, raw electronic -grade silicon has a
polycrystalline structure. In other words, it’s made up of lots of small
silicon crystals, with defects called grain boundaries between them.
Because these anomalies affect local electronic behaviour, polycrystalline
silicon is unsuitable for semiconductor manufacturing.

To turn it into a usable material, the silicon must be turned into single
crystals that have a regular atomic structure. This transformation is
achieved through the Czochralski Process. Electronic -grade silicon is
melted in a rotating quartz crucible and held at just above its melting point
of 1,414°C.
A tiny crystal of silicon is then dipped into the molten silicon and slowly
withdrawn while being continuously rotated in the opposite direction to
the rotation of the crucible. The crystal acts as a seed, causing silicon
from the crucible to crystallise around it. This builds up a rod – called a
boule – that comprises a single silicon crystal.

The diameter of the boule depends on the temperature in the crucible, the
rate at which the crystal is ‘pulled’ (which is measured in millimetres per
hour) and the speed of rotation. A typical boule measures 300mm in
diameter.
Step three: Slicing the crystal into wafers
Integrated circuits are approximately linear, which is to say that they’re
formed on the surface of the silicon. To maximise the surface area of
silicon available for making chips, the boule is sliced up into discs called
wafers.

The wafers are just thick enough to allow them to be handled safely during
semiconductor fabrication. 300mm wafers are typically 0.775mm thick.
Sawing is carried out using a wire saw that cuts multiple slices
simultaneously, in the same way that some kitchen gadgets cut an egg into
several slices in a single operation.

Silicon saws differ from these kitchen tools in that the wire is constantly
moving and also carries with it a slurry of silicon carbide, the same
abrasive material that forms the surface of ‘wet -dry’ sandpaper.

The sharp edges of each wafer are then smoothed down to prevent the
wafers from chipping during later processes.
Next, in a procedure called ‘lapping’, the surfaces are polished using an
abrasive slurry until the wafers are flat to within an astonishing 2μm (two
thousandths of a millimetre). The wafer is then etched in a mixture of
nitric, hydrofluoric and acetic acids.

The nitric acid oxides the surfaces to give a thin layer of silicon dioxide –
which the hydrofluoric acid immediately dissolves away to leave a clean
silicon surface – and the acetic acid controls the reaction rate. The result
of all this refining and treating is an even smoother and cleaner surface.

Electronic-grade silicon still isn't perfect, because it has a polycrystalline structure.

That means it's composed of lots of small silicon crystals, and the joins between those
crystals can suffer from defects known as grain boundaries. Those boundaries can
cause chaos with electronic signals, so the structure of the silicon has to be changed.

The process of doing that is called the Czochralski Process, and it involves melting
the silicon crystal in a quartz crucible at just over the melting point of 1,414 degrees
C. A tiny silicon crystal is then dipped into the molten silicon, and it's drawn out
while rotating constantly in the opposite direction to the rotation of the crucible. This
attracts silicon from the crucible, creating what's known as a boule. A boule is a rod
made from a single silicon crystal, and its size depends on the temperature, the rate of
spin and the rate at which the crystal is pulled from the liquid. A typical boule will be
around 300mm across.

Step three: Making a patterned oxide layer

In many of the subsequent steps, the electrical properties of the wafer will
be modified through exposure to ion beams, hot gasses and chemicals. But
this needs to be done selectively to specific areas of the wafer in order to
build up the circuit.
Stage four: A multistage process is used to create an oxide layer in
the shape of the required circuit features
In some cases, this procedure can be achieved using ‘photoresist’, a
photosensitive chemical not dissimilar to that used in making
photographic film (just as described in steps B, C and D, below).

Where hot gasses are involved, however, the photoresist would be

destroyed, making another, more complicated, method of masking the
wafer necessary. To overcome the problem, a patterned oxide layer is
applied to the wafer so that the hot gasses only reach the silicon in those
areas where the oxide layer is missing. Applying the oxide layer mask to
the wafer is a multistage process, as illustrated to the left.

(A) The wafer is heated to a high temperature in a furnace. The surface

layer of silicon reacts with the oxygen present to create a layer of
silicon dioxide.
(B) A layer of photoresist is applied. The wafer is spun in a vacuum so
that the photoresist spreads out evenly over the surface before being baked
dry.

(C) The wafer is exposed to ultraviolet light through a photographic mask

or film. This mask defines the required pattern of circuit features. This
process has to be carried out many times, once for each chi p or rectangular
cluster of chips on the wafer. The film is moved between each exposure
using a machine called a ‘stepper’.

(D) The next stage is to develop the latent circuit image. This process is
carried out using an alkaline solution. During this proc ess, those parts of
the photoresist that were exposed to the ultraviolet soften in the solution
and are washed away.

(E) The photoresist isn’t sufficiently durable to withstand the hot gasses
used in some steps, but it is able to withstand hydrofluoric ac id, which is
now used to dissolve those parts of the silicon oxide layer where the
photoresist has been washed away.

(F) Finally, a solvent is used to remove the remaining photoresist, leaving

a patterned oxide layer in the shape of the required circuit features.

Step five: Creating n-type and p-type regions

The fundamental building block of a processor is a type of transistor

called a MOSFET – you can see how they work below. The type of device
illustrated there is a ‘p-channel’ MOSFET (so-called because it uses p-
type material). Processors also use ‘n -channel’ MOSFETs, which use n-
type material.
MOSFET DESIGN: MOSFETs are the switches at the heart of processor
design
The first step in creating a circuit is to create n -type and p-type regions.
Below is the method Intel uses for its 90nm process and beyond:

(A) The wafer is exposed to a beam of boron ions. These implant

themselves into the silicon through the gaps in a layer of photoresist to
create areas called ‘p-wells’. These are, confusingly enough, used in the n-
channel MOSFETs.
A boron ion is a boron atom that has had an electron removed, thereby
giving it a positive charge. This charge allows the ions to be accelerated
electrostatically in much the same way that electrons are accelerated
towards the front of a CRT television, giving them enough energy to
become implanted into the silicon.
 (B) A different photoresist pattern is now applied, and a beam of
phosphorous ions is used in the same way to create ‘n -wells’ for
the p-channel MOSFETs.
(C) In the final ion implantation stage, following the application of yet
another photoresist, another beam of phosphorous ions is used to
create the n-type regions in the p-wells that will act as the source
and drain of the n-channel MOSFETs.

This has to be carried out separately from the creation of the n -wells
because it needs a greater concentration of phosphorous ions to create n -
type regions in p-type silicon than it takes to create n -type regions in pure,
un-doped silicon.

(D) Next, following the deposition of a patterned oxide layer (because,

once again, the photoresist would be destroyed by the hot gas used here), a
layer of silicon-germanium doped with boron (which is a p -type material)
is applied.
MOSFET CREATION: The properties of the silicon are modified to
produce n-type and p-type regions
Step six: Adding gates to complete the MOSFETs
With the n-type and p-type regions in place, all that is needed to complete
the MOSFETs is the gate. As with many of these steps, the first job is to
produce a patterned oxide layer as described in Step 4. In this case, the
oxide layer will have gaps only in the gate regions of the MOSFETs.
Again, there are different ways of making the gates, but the method
described here is typical.

As shown in the diagram in the ‘Understanding MOSFETs’ box, the first

part of the gate is a very thin insulating layer of silicon dioxide, deposited
on the surface of the silicon between the source and the drain. This is done
using chemical vapour deposition (CVD), a process that ta kes place in a
furnace filled with various gases that cause a chemical reaction to take
place on the surface of the silicon.

To complete the MOSFET, a layer of silicon is applied over the top of the
thin oxide layer to act as a conductor. Again, CVD is u sed, and the silicon
is applied via an oxidation reaction in which gaseous silicon hydride
reacts with oxygen to give silicon and water as products.

A second photoresist pattern is now applied, and the beam changes to phosphorous
ions. These create n-wells. A more powerful phosphorous beam is then applied to
create the regions that will act as the source and drain of the switches, and a pattern
oxide layer is deposited before a layer of silicon-germanium doped with boron is
applied. With the MOSFETs created, the next step is to make the gates that control
their voltage.
Step seven: Connecting the MOSFETs with copper tracks

Once all of this has been done, the wafer will contain billions of
MOSFETs. In order for them to work together as circuits, they need to be
connected together to produce lots of individual chips, each of them still
containing millions of MOSFETs. The process used by Intel is as follo ws:

(A) The initial state of the MOSFETs on the wafer.

(B) Before the addition of copper circuitry can be carried out, a layer of
insulation has to be applied to the wafer so that the interconnecting tracks
don’t short all the MOSFETs. Silicon dioxide is used as the insulator, and
this layer is built up on the surface of the wafer either by oxidising it in a
furnace or by a process of chemical vapour deposition.
With the entire surface of the wafer covered in an insulating layer of
silicon dioxide, it’s no longer possible to make connections to the source,
drain and gate of the MOSFETs.
There are a number of ways of restoring connections, but for simplicity’s
sake we’re going to describe an up-and-coming method called ‘double
damascene’. This method involves two damascene steps – one to create
tungsten connecting pins and the second to make copper interconnects.

(C)Hydroflouric acid is used to etch holes in the silicon dioxide insulation

(through a layer of photoresist)

(D) After that, trenches in the pattern of the required interconnection

tracks are etched into the silicon dioxide through another photoresist
layer.
 (D) A top layer of copper is then applied by electroplating. This fills
the trenches and holes to make contact with the underlying
MOSFETs. The resultant metallic pins that protrude through the
insulating layer are called ‘vias’.

A gate is an electrode that sits between the switch's source and drain, insulated by a
very thin layer of metal oxide. The most recent Intel processors use second-
generation Tri-gate transistors, which as the name suggests uses three-dimensional
gates instead of the traditional two, and they employ a variation on MOSFETs known
as FinFET or multi-gate architectures. These improvements enable Intel to drop the
size of its architecture from 90nm to 22nm and even 14nm while increasing
performance and efficiency.

To create a gate, a thin layer of silicon dioxide is deposited using a process called
Chemical Vapour Deposition, or CVD for short. This takes place in a furnace filled
with gases that cause a chemical reaction on the surface of the silicon. CVD is used
again to apply a layer of silicon, this time by reacting silicon hydride gas with oxygen
to produce silicon and water.

(E) The wafer is now covered in a layer of copper. The final stage is to
take this off. In a process called chemical -mechanical polishing,
the excess copper is removed so that the desired amount is left to
form tracks in the trenches and holes.
Once the gates have been created, the wafer will contain billions of MOSFETs or
FinFETs, ready to be carved up into individual chips containing millions of switches.
But first, the switches and gates need to be connected. That's achieved by putting
down a layer of silicon oxide insulation, to ensure that the interconnecting tracks don't
short out all of the switches. Once that has been applied, it's time to add the copper.
One method of doing that is called the 'double Damascene', and it involves creating
tungsten connecting pins and copper interconnects.

First of all, hydrofluoric acid is used to etch holes in the insulation, guided by a layer
of photoresist. Then the trenches for the interconnection tracks are etched, again
through a layer of photoresist. A top layer of copper is applied by electroplating,
which fills the trenches and holes to make contact with the underlying switches and
which creates metallic pins protruding through the insulating layer. These are known
as vias. Finally, the wafer is polished to remove the excess copper, leaving only the
desired tracks in the trenches and holes.

Step 8: Complete the circuit

You can't always wire up a circuit without having some wires crossing, and that's
disastrous for CPUs: one rogue interconnection could make any tracks that cross it
short out. To avoid this, MOSFETs have multiple metallic layers, each insulated by a
layer of silicon dioxide and connected with vias.
Step 9: Throw out the bad ones

As you can probably imagine, such an incredibly complex process is prone to all
kinds of potential problems, so while each wafer will contain a few hundred 'dies' –
the official name for chips – many of the dies will have, er, died.

A typical yield from a wafer is around 60%, although the numbers depend on the
process used – whenever a manufacturer moves to a new, more compact architecture,
yields inevitably fall until production teething problems have been identified and
addressed. A device called a wafer probe tests the dies, the wafer is sawn up into
individual chips and the non-working ones are discarded. Slightly faulty dies may be
reused as lower specification products.

Step 10: Add bubble wrap

The die may be a completed processor, but it's far too fragile to ship in its current
state. That's why the manufacturer then puts the bare chip in the package that we tend
to visualise when we think of a processor. The die's contacts are connected to the
package's contacts, and it's ready to ship and to stick into a motherboard. All that's left
is some final quality assurance and the processor can begin its journey to the heart of
your PC.

As a final note, fancy watching some video footage of how chips are made? The
following clip is from a few years back, but it's certainly an interesting visual
illustration of how Intel produces chips with 3D transistors.
FINAL STAGES: An insulating layer of silicon dioxide protects the
MOSFETs. Holes etched through it permit connections to be made
Step eight: Completing the circuit
It’s not always feasible to wire up a circuit without wires crossing. If
there was just one rogue interconnection, any tracks that crossed would
short. To avoid this, MOSFETs have more than one metallic layer, each
insulated by another layer of silicon dio xide and connected using vias.
 The wafer is heated to a high temperature in a furnace, creating a layer of silicon
dioxide as the silicon reacts with oxygen
 A layer of photoresist is applied, with the wafer spun in a vacuum to ensure even
coverage and then baked dry
 The wafer is exposed to UV light through a photographic mask or film, once for each
chip or cluster of chips on the wafer. The wafer is moved between each exposure
using a machine called a 'stepper'
 An alkaline solution is applied, dissolving the sections of photoresist that were
exposed to the UV light. Those sections are washed away
 Hydroflouric acid is used to dissolve the parts of the oxide layer where the photoresist
has been washed away
 A solvent is applied to remove the remaining photoresist, leaving a patterned oxide
layer in the shape of the required circuit features

CONCLUSION:

In 1960's there are only 5 transistors in 1 chip

gordon moore&Robert noyce suggested that transistors will be doubled for every 2
years which r presented on the micro chip. It is called Moorse law

INTEGRATED and ELECTRONICS. are combined ......from this INTEL word is

derived.

as the decades are passing ,the transistors are also increasing .how this electronic
changes in the future is we should see.