International Journal of Innovative Technology and Exploring Engineering (IJITEE)

ISSN: 2278-3075, Volume-8 Issue-8 June, 2019

Analysis and Design of 90 nm CMOS Amplifier

for UWB Applications
Kusuma M. S, S. Shanthala, Cyril Prasanna Raj P.
 stage in 90 nm CMOS process technology. Despite the fact
Abstract: An ultra-wideband Low Noise Amplifier (LNA) that low power utilization is accomplished and NF is not
employing a Common Gate (CG) topology with load network acceptable. The NF and dc power consumption (PD) exhibit a
including dual resonance is presented. This LNA has both flat slight lower values in a single-stage cascode LNA
Noise Figure (NF) and wideband input matching in 3.1 GHz-10.6
GHz frequency range applications. The frequency response of demonstrated in [16] using 0.13 µm CMOS technology. In
common gate-common source cascade topology is improved by [14], an input matching network for wideband with
adopting inductive series peaking technique. The proposed LNA dual-RLC-branch is adopted in a two stage CMOS LNA. The
presents 19.11 dB peak power gain at 9 GHz, 17.94 dB gain for the LNA occupies large chip area as 5 inductors are included in
(4.5-9.5) GHz frequency range and 50 Ohm good enough input the design with expensive power dessipation. To minimize the
matching in the desired band by importing 90 nm CMOS process
and model parameters to Advanced Design System (ADS)
power dissipation PD of the LNA in [14], a method of
software. A fine NF less than 2.88 dB is attained in (3.1-10.6) GHz self-forward body bias and forward combining techniques are
frequency range with 9 mW power dissipation from 1.2 V supply described in [6]. The disadvantages incorporate seven
voltage. The input-output reflection coefficients (S11-S22) are inductors altogether and degraded NF.
-17.61 dB and -6.22 dB at 9 GHz respectively. The reverse Distributed Amplifier (DA) topology can afford high-flat
isolations (S12) below -50 dB is achieved.
gain and wideband input matching, but high power utilization
and moderately considerable chip area as the discomforts
Index Terms: Asymmetric T-coil, Bridged shunt series,
Common Gate, Common Source, Low Noise Amplifier, Series when used in UWB applications [5]. The LNA reported in [6]
Peaking, Ultra-wideband. incorporated RC feedback technique to reach admissible
broadband matching and flat gain. Unfortunately, it cannot
I. INTRODUCTION fulfil the prerequisites of large gain and minimum NF at low
power. The two-stage UWB LNA is implemented in [7] by
In recent years, model of Radio Frequency Integrated
using reactive feedback topology to enhance the circuit
Circuits (RFIC) with CMOS process have become more
execution capability in (3-11) GHz frequency range. The
popular as this technology is low cost and consistent with
increased space bound by the transformer-feedback technique
System-On-Chip (SoC) [1]-[9]. The Low Noise Amplifier
circuit is a detriment for the total chip volume. The conquer
(LNA) is an essential section in the front end of an
approach in alignment of gain and noise performance for
Ultra-Wideband (UWB) RF receiver which receives weak
narrowband applications is the inductive degenerated CS
signals from (3.1–10.6) GHz frequency range and enhances
amplifier [17]. A speculation of this circuit for wideband
the power gain with an excellent Signal-to-Noise Ratio
applications is accomplished by substituting gate inductor
(SNR). Adding to it, flat-high power gain, favorable
with multiple reactive networks, in order that the
impedance matching, input-output (i.e., low S11 and S22) and
wide-ranging reactance occurring at input side resonates
low Noise Figure (NF) performance over the entire UWB are
throughout a large frequency range [15][17]. Such viewpoint
required. In recent times, quite a few first-rate CMOS UWB
experiences the large group-delay variations caused because
LNAs have been reported in [1]–[4]. To quote an example, in
of presence of more resonances at the input side of the
[8] a reconfigurable, inductor-less, wideband with
matching network for UWB as an obstacle. Additionally, it
complementary Current-Reuse (CR) Common Source (CS)
expects medium to wide silicon region and presents a massive
topology, joined with a less-current active feedback LNA is
insertion-loss which attenuates the amplifier power gain and
reported. Input devices used in PMOS and NMOS transistors
NF.
in Common-Gate (CG) LNA are present in a complementary
CR structure. This is available along with active
II. LITERATURE REVIEW
shunt-feedback structure to enhance the current efficiency to a
greater extent, reported in [11]. A two-stage LNA reported in Literature review on different LNA designs with respect to
[15] uses current-reuse technique pursued with a cascode process technologies, gate length and LNA topologies are
discussed and summarized in Table I
Revised Manuscript Received on June 12, 2019
Kusuma M S, Research Scholar, Dept. of Telecommunication
Engineering, Bangalore Institute of Technology, Bengaluru, Visvesvaraya
Technological University, India.
Dr. S Shanthala, Prof. & HOD, Dept. of Telecommunication
Engineering, Bangalore Institute of Technology, Bengaluru, Visvesvaraya
Technological University, India.
Dr. Cyril Prasanna Raj P, Senior Member, IEEE, Prof. & Dean, (R &
D), M. S Engineering College, Bengaluru, Visvesvaraya Technological
University, India.

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8 Issue-8 June, 2019

Table I. Literature review on various LNA Topologies and Technologies

Ref. Tech/L(n Topology/ Freq. S21 NF S11 S22 IIP3 P1dB PDC
Year FoM
No m) Stages [GHz] [dB] [dB] [dB] [dB] dBm dBm [mW]
Marcelo
De CR-CS
[8] Souza
CMOS/130 0.1-2.1 19.2 2.4 --- --- 8.6 --- 3.11 35.1
AFB
2017
Nan Li
[9] 2017
CMOS/130 CG 3-12 13.5 4.3 <-11 --- -7 ---- 8.5 3.41
Mahdi
Parvizi
[10] CMOS/130 CG 0.1-2.2 12.3 4.9 <-9 <-10 -10 --- 0.4 17.9
2016

Mahdi CMOS/90 CR-resisti

[11] Parvizi ve shunt 0.1-7.0 12.6 5.5 --- --- -9 -18 0.75 20.89
2015 FB
Meng-Ti
[12] ng Hsu CMOS/180 Cascode 3.1-10.6 10.8 5.5 -8.1 <-9.5 -6.4 --- 6.4 5.1
2014
K.
[13] Yousef CMOS/180 CR-CS 3.1-10.6 12.25 3.8 <-10 <-8.2 2.5 -7 18 ---
2014
Chia-Hsi
CR
[14] ng Wu CMOS/180 3.1-10.6 12.52 2.87 --- --- -6.5 -16 11.8 4.4
2012 cascode
G.
CR
Sapone CMOS/90 7.6 12.5 3-7 -9 --- --- -12 7.2 ---
[15] 2011 cascode
Giang D.
CMOS/ 3.9-
Nguyen Cascode 2.2-9.0 11.3 <-9 --- <5 --- 30 ---
[16] 2008 130 4.6
Andrea
[17] Bevilacq CMOS/180 Cascode 3.1-10.6 9.3 4 -9.9 --- -6.7 --- 9 ---
ua 2004

Marcelo De Souza [8] demonstrated current reuse CS LNA in smaller than -9.5 dB. A NFmin of 5.5 dB, -6.4 dBm of IIP3 and
CMOS 0.13 µm echnology. This architecture is grounded on 6.4 mW power dissipation from 1.1 V supply voltage have
a complementary CR-CS technique along with a low-current been obtained. K. Yousef et. al.,[13] demonstrated the design
active feedback for multi-standard applications. The LNA of CS based CR LNA for UWB functions in 0.18 µm CMOS
reaches 2 dB minimum NF (NFmin), 21.1 dB of voltage gain, technique with limited variations in group delay and
14.3 dBm of IIP3 and power consumption of 7 mW. The optimized noise performance. Through this structure 12.25
amplifier draws 1.5 mw power in low power mode while dB flat gain with less than 3.8 dB NF are attained along with
providing 2.6 dB of NF, 21 dB of power gain and 4.7 dBm of ±25 ps group delay variation using 0.18 µm CMOS
IIP3. Nan Li [9] has reported an ultra-wideband LNA in 130 technology. The wideband matching for input side is fulfilled
nm CMOS technology. The dual resonance and broadband by implementing the poor resistive-capacitive shunt feedback
input matching. Addition of series peaking inductor to CG-CS approach. The optimum group delay variations are obtained
topology favors the extension of frequency response. The by terminating the output stage with resistor and series
flat-high power gain of (13.5±1.5) dB with input return loss peaking element. The measured results of LNA include 2.5
13 dB and 4.3 dB ±0.4 dB of flat NF are obtained in (3-12) dBm and -7.0 dBm of IIP3 and 1dB compression point (P1dB)
GHz frequency band. The die area of 1.09x0.8 mm2 is respectively at 5.5 GHz. Chia-Hsing Wu et al., [14] has
occupied by the fabricated LNA including pads and circuit described CR cascode 0.18 µm CMOS technology LNA for
draws a 8.5 mW power 1.2V supply. Mahdi Parvizi [10][11] UWB functions with superlative linearity property (±15.8 ps
presented the CG low-noise amplifier design in 130 nm IBM variation of group delay). The LNA exhibits 11.8 mW of
CMOS technology. In this LNA design, the complementary power dissipation, 10.2 dB input return loss, a flat-high gain
CR architecture adapts PMOS and NMOS transistors as input of (12.52 ± 0.81) dB and (2.87 ± 0.19) dB of low-flat NF over
devices. The LNA has measured results of gain 12.3 dB, 4.9 the complete UWB frequency range. The third order intercept
dB of NFmin, (IIP3) of -10 dBm, less than 9 dB of S11, S22 is point and 1 dB compression point results are 6.5 dBm and 16
below -10 dB while drawing only 400 µA from a 1V power dBm respectively, at a frequency of 6 GHz.
supply. The same team has published an ultra-low power G. Sapone et al., [15] has developed 2 stage single ended
LNA in 90 nm CMOS process with CR-series inductive LNA in 90 nm CMOS technology for UWB applications. The
peaking technique in 2015. The results demonstrate 12.6 dB input matching at the first stage is established with CR
of voltage gain, 5.5 dB of NF, -9 dBm of IIP3 and -18 dB of topology for (3-10) GHz frequencies. A resonant loaded
P1dB in (0.1-7) GHz bandwidth. Meng-Ting Hsu et. al., [12] cascode amplifier is used at the second phase to enhance
proposed a RC-feedback and FBB technique cascode LNA reverse isolation and power gain. Measurement results
using 0.18 µm TSMC CMOS technology for (3.1-10.6) GHz indicate 12.5 dB of power
frequency range. The measurement results exhibit 10.8 dB gain at 7.6 GHz 3 dB
maximum power gain (S21). The input reflection coefficient, bandwidth, 3 dB of NFmin, a
S11 is less than -80.1 dB, output reflection coefficient, S22 is reverse isolation finer than

Published By:
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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075, Volume-8 Issue-8 June, 2019

45 dB up till 10.6 GHz, 12 ps of group delay variation and compact enough to not substantially modify the gain
consumes 6 mA from 1.2 V power supply. Giang D. Nguyen performance.
et al., [16] implemented LNA using 130 nm CMOS
B. Bridged-Shunt-Series Peaking
technology. The architecture provides 11.3 dB gain, (3.9-4.6)
dB of NF and (3.2 – 5) dBm of IIP3 over a 3 dB bandwidth at In this approach, an inductor is added to split the
(2.2-9) GHz with 30 mW power consumption from a 1.2 V capacitor present at the load into two essential components as
supply. Andrea Bevilacqua et al., [17] demonstrated 180 nm part of capacitive splitting function to achieve significant
CMOS LNA. The amplifier exhibits a 9.3 dB power gain with BWER where in drain parasitic capacitance C1 is very much
S11 of -9.9 dB over the bandwidth, 4 dB of NFmin and 6.7 dBm important, Fig. 2 (a). The response of the amplifier provides
of IIP3 while consuming 9 mW power. the additional bandwidth extension by capacitive dividing
action. The transistor charges C= C1 + C2 when inductor is not
connected, but with incorporating inductor L1, initially
III. LIMITATIONS OF WIDE-BAND AMPLIFIER
capacitor C1 is charged as L1 delays flow of current to the
A wide-band amplifier be required to adhere remaining portion of the network. This step down the rise time
near-consistent power gain and phase linearity over its at the drain and widens the bandwidth [21]. So that the
frequency of interest. The bandwidth prerequisites of combination of bridged shunt with inductive peaking
wideband amplifiers are constantly developed for higher step approach and capacitive splitting of series peaked circuit
forward environment systems. While device scaling provides the bridged-shunt-series-peaked network as shown
constantly decreasing to adapt faster transistors near upper in Fig. 2 (b).
VDD
cutoff frequencies, it is even demand to improve the VDD
CB L2
bandwidth of amplifiers using various techniques which R
empower us to do as such for a particular process technology. R
VOut
There are various approaches have been developed to L L1

enhance the bandwidth of the amplifiers in recent decades Q1

VOut

[18][19][22]. An advancement in the amplifier radio VIn C1 C2

Q1

bandwidth is often accompanied by an analogous fall in its VIn

C1 C2

lower-frequency voltage gain. There are couple of

mechanisms to broaden the amplifier bandwidth. These
methods are described in detail in this section. (a) (b)

A. Bridged Shunt Peaking Fig. 2: A CS amplifier with parasitic capacitance at drain terminal
(a) Circuit coupled with series peaking. (b) Bridged-shunt-series
In bridged shunt peaking method, bandwidth peaked network [20].
extension is accomplished by shunt peaking approach in
which an inductor is in sequence with resistive load shunts the C. Asymmetric T-Coil Peaking
capacitor C connected at the output terminal (Fig. 1(a)).
A method of bridged-shunt-series peaked network provides
= (1) large BWER with a parasitic capacitance ratio, kC > 0.3
(kC= ). However, as the increased value of load
VDD VDD
capacitance ) a large BWER is achieved, but the
L combined action of capacitive splitting of L2 and coupling of
L
CB CB turn into powerless. This restriction is overcome by the
R
R
transformer magnetic coupling force. In the asymmetric
VOut T-coil-peaked circuit amplifier (L1 ≠ L2) [23] [Fig. 3(a)], a
VOut
Q1
Q1
negative mutual inductance is accomplished by wounded
VIn C
VIn
coils. The secondary of inductor L2 supports capacitive
C
splitting to allow initial charging through C1, similar
bridged-shunt-series peaked amplifier. Later, the current
starts to flow in L2 and then to C2. In view of series connection
(a) (b) of capacitor C2 in addition to negative mutual inductance (-M)
element of the T-coil there is an initial boost in the current
Fig. 1: CS amplifier (a) shunt peaking approach.
(b) bridged-shunt peaking method [20]
flow to C2 due to the negative coupling action. This action
The -3 dB bandwidth is extended when inductor grants an enhancement in rise time and in turn BWER. Fig.
3(b) shows the T-model of the transformer with small signal
presents a zero in equation (1) that enhances the impedance
equivalent circuit. The relationship between coefficient of
with frequency and coordinates the declining impedance of
coupling (km) and the mutual inductance (M) is given as,
capacitor. But additionally it results to peaking in the
response. Subsequently, a few methods are required to
exclude peaking with full-scale Bandwidth Extension Ratio .
(BWER). One drive is to add parallel combination of inductor
and capacitor that must be adequate to deny peaking but

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ISSN: 2278-3075, Volume-8 Issue-8 June, 2019

VDD LD2 +M -M
VOut

R
gm1Vgs1
IIn LD1 +M Lg
Vgs1 Cgs1
L1 Rds1
CD1
kin Cgs2
VOut L2 +M -M RD1
L2 VOut
C1
Zin(s) ZL(s)
IIn L1 +M LS
Q1
C1 C2
VIn C1 C2

Fig. 5: The CG stage small signal equivalent circuit with load

network at the drain of M1
(a) (b)
The overall inductance is reduced by the shunt connection of
Fig. 3: A method of asymmetric T-coil peaking (a) Drain parasitic
LG-Cgs2 and LD1, resulting to high resonance frequency ωo, high.
capacitive circuit (b) Equivalent circuit with a T-model of the
transformer.
Several factors are involved in designing the asymmetric
T-coils. Remarkably, the essential magnetic coupling ratio km
(0.3-0.7) is moderately low, which normally prohibits
IV. UWB LNA CIRCUIT DESIGN interleaved T-coil arrangement [24]. The design complexity
The Fig. 4 shows the designed wide-band LNA. It issues of a symmetric coil can be avoided at the cost of
comprises two stages utilizing CG cascade (Q1) and cascade required non-unity turns ratio. Ultimately, architectures which
of Q2 and Q4. To accommodate transformation of output limit parasitic impacts between windings are attractive. The
impedance source follower buffer (Q4 and Q5) is used. The first CG stage of the LNA exhibits the dominated NF given by
small-signal equivalent circuit of CG with the cascade for the equation (3).
wideband matching at input is presented in Fig. 5. The
impedance at the input side is given by equation (2). (3)
where α = gm/gd0 is transistor trans-conductance to the channel
(2) conductance ratio at zero VDS and the channel thermal noise
coefficient is γ. The increase in load impedance ZL(s) for
given rds, the NF is reduced as depicted in equation (3). It is
Where gm1 is trans-conductance of Q1, rds is the output
required to have a load network with high impedance over
resistance of Q1. The capacitance Cgs1 adds the parasitic
wide range of frequency to achieve low and flat NF. In the
capacitance between gate and source of transistor Q1 and an
present circuit structure, the load network provides large
inductor LS is connected to source of Q1. CD1 and ZL represent
parasitic capacitance and load impedance at the drain of Q1 impedance over the wideband by presenting dual resonances
respectively including Cgs2 of the following cascade stage. at low and high frequencies. Conventional circuit design
Channel length modulation in nanoscale CMOS technologies provides a non-flat response of NF with large value at low and
causes shortened channel resistance rds; from (2), the input high band and smaller value in the middle band
impedance Zin turns into a strong function of ZL. independently. On the contradictory, a response of flat NF can
VDD2 be attained by adopting dual-resonant circuit over the total
RD2 range of frequency. The approach of CG stage (Q1) and
VDD1 -

VDD3
cascade stage (Q2 and Q3) united with asymmetric T-Coil
RD1
LD3 peaking bandwidth extension technique presented in [20] is
applied to attain wide band and flat gain response. The
CBP Rf
LD1 LD4 capacitive splitting function of LD2 allows the initial charging
current to flow only to drain to source capacitance Cds. Next
CBP LD2 Q3
Q5 the current set-ups to flow in LD2 and proceed to Cgs. As the
CD
series connection of load capacitor Cgs with the negative
Q1 LS RFout
CG LG
Q4
mutual inductance (-M) of the T-coil, the negative magnetic
RFIN CD R
coupling accommodates an initiatory boost to flow of current
LS Q2
R
to Cgs. This takes into account an enhancement in rise time
VG1
VG2
along with BWER. The gain falling-off of the first CG
Fig. 4: Schematic of the proposed LNA transistor (Q1) is balanced by connecting LG together with LD1
(bridged-shunt-series-peaked network). A low-Q shunt
The dual-resonance load network provides the good peaking at the center band is achieved by the second cascade
impedance matching over the wideband range as shown in stage. The inductor LG provides high-flat power gain of LNA
Fig. 5. For low and high frequencies two resonances are over the wideband of interest.
introduced. The Cgs2 presents a high impedance path (LD1 ||
LD2 || CD1) at the output and at the input, Cgs1 and LS are
resonated simultaneously, selecting less resonance frequency
ωo, low.

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V. RESULTS AND DISCUSSIONS compared with respect to input power. Both are at -13 dBm of
the input power. The value of stability factor (K) is found to
The LNA, the critical component of RF front end is designed
be more than 1 by analyzing the Fig. 10 for operating
and examined for its performance in consideration of
frequency range of (3-11) GHz.
parameters such as high gain, stability, NFmin and linearity.
Simulation results of gain (S21), NF, 1 dB compression point
(P1dB), third order intercept point (IIP3), input-output
reflection coefficients and stability with BSIM3 Predictive
Technology Model (PTM) for 90 nm are obtained for the
amplifier design [25].
The standard 90 nm CMOS process is supported to design
the UWB LNA. The simulated gain, S21 with 50 Ω input
impedance matching and noise figure are plotted in Fig. 6.
The designed architecture has 19.11 dB peak gain at 9 GHz,
and greater than 10 dB from 3.4 GHz to 11 GHz. The flat gain
of 17.94 dB is obtained from 4.5 GHz to 9.5 GHz. The 2.88
dB of NFmin at 6 GHz and an average of 3.3 dB flat NF for
frequencies 3.5-10.6 GHz are achieved. The input-output
reflection coefficients (S11, S22) are shown in Fig. 7. As can be
Fig. 8: Gain Compression Point off the LNA
seen, S11 of less than -12.9 dB for (3-10) GHz and at 9 GHz
-17.61 dB. The S22, average output reflection coefficient is
under -5.46 dB for entire frequency range and less than -6.22
dB at 9 GHz. The S12, the reverse isolation below -50 dB is
achieved.

Fig. 9: IIP3 of the LNA

Fig. 6: S21 and NF of the LNA

Fig.10: The LNA Stability Factor (K) response

Fig. 7: S11 and S22 of LNA
The performance of wideband LNA is evaluated by
using the suitable value of Figure of Merit (FoM) [5]. The
Fig. 8 shows P1dB of the amplifier, the actual response (Vout)
FoM of the designed LNA is 8.47.
and linear response are compared with respect to input power.
The actual response coincide with the theoretical response (4)
from -30 dBm to -21 dBm, there is a difference of 1dB at -20
dBm and the gain decreases with further increase of the input
power. Fig. 9 shows the plot of fundamental power (Vout [1,
0]) and third order power (Vout [-2, 1]), two harmonics,

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Table II. Comparison of the proposed LNA with previously published works for UWB applications

Parameters [15] [14] [11] [9] This Work

Technology (nm) 90 180 90 130 90
Frequency (GHz) 2.6-10.2 3.1-10.6 0.1-7 3-12 3.1-10.6
Peak S21 (dB)/ Freq 12.5 12.52 12.6 13.5 19.11
S11 (dB) -9.0 < -10.25 < -10 < - 11 < -12.90
S22 (dB) --- < -10 < -9 < - 10 < -5.46
NFmin (dB) 3-7 2.87 5.5 4.3 2.88
IIP3 (dBm) --- -6.5 -9 -7 -13.00
P1dB (dBm) -12 --- -18 -- -20.00
PDC (mW) 7.2 11.8 0.75 8.5 9
FoM --- 4.4 6 3.41 8.47
Stability Factor (K) --- --- --- --- K>1

Table II provides the comparison of the performance of the Current-Reused Technique,” IEEE Microwave and Wireless
Components Letters, Vol. 17, No. 3, March 2007, pp. 232-234.
prototype amplifier with state-of-the-art designs narrated in
5. Hee-Tae Ahn, and David J. Allstot, “A 0.5–8.5-GHz Fully Differential
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series-peaking using CG topology. In [9] 3 GHz to 12 GHz, a 6. Kuang-Chi He, Ming-Tsung Li, Chen-Ming Li, and Jenn-Hwan Tarng,
flat-gain is around 13.5 dB, this work shows 17.94 dB “Parallel-RC Feedback Low-Noise Amplifier for UWB Applications,”
IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol.
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FoM when compared to the previous designs in different 3.1–10.6 GHz Low-Noise Amplifier in 0.13 m CMOS,” IEEE
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9. Nan Li, Weiwei Feng, and Xiuping Li, “A CMOS 3–12-GHz Ultra
A wideband inductively degenerated cascade LNA for wideband Low Noise Amplifier by Dual-Resonance Network,”
UWB functions has been demonstrated in 90 nm RF CMOS IEEE Microwave and Wireless Components Letters, Vol. 27,
No. 4, April 2017, pp. 383-385.
technology for (3.1-10.6) GHz frequency range. The present
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Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design
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AUTHORS PROFILE

Mrs. Kusuma M. S. received her M.Tech degree in

Digital Electronics from Visveswaraya Technological
University, Karnataka, India and B.E. degree in
Electronics & Communication Engineering from
Kuvempu University, Karnataka, India. She is currently
working as Assistant Professor at Govt. SKSJTI,
Bengaluru and pursuing Ph.D in Electronics and
Communication Engineering under Visveswaraya Technological University.
Prior to this she worked in WIPRO Technologies as a Project Engineer where
she was responsible for verification of ASIC design. She has 4 years of
industry experience and more than 10 years of teaching experience. Her
research interests include low power VLSI, Wireless sensor networks,
Analog and Digital system design.

Dr. S. Shanthala is working as a Professor and Head,

Dept. of Telecommunication, B.I.T, Bengaluru. She has
a teaching experience of about 27 years. She has
presented & published many papers in several
International and National Conferences & Journals. She
is a life member of MISTE and MIMAPS. Her area of
interest includes Low power VLSI design, Embedded
systems and Digital Signal processing.

Dr. Cyril Prasanna Raj P obtained his PhD from

Coventry University, UK, M. Tech from KREC
Su-rathkal and BE from SJCE Mysore. He is also senior
member of IEEE, and Council Member (Treasurer) IEEE
Sensors Council (Bangalore Chapter). He is working as
Dean (R&D) at MS Engineering College, Bangalore.
Prior to this he was at MS Ramaiah School of Advanced
Studies, Bangalore as HOD-EEE Department for 12 years. He has more than
16 years of experience in teaching and research. At MSEC, Banga-lore he is
also the Director for Innovation and Entrepre-neurship Development Cell
funded by DST. He also has 16 patents, and has commercialized three
products. He has more than 70 journal publications with 300 citations,
authored 14 books and is supervising 8 research scholars under VTU. He has
developed India’s first VLSI design GUI – CYMPLEX and Nanoelectronics
Devices Simulator – NANOCYM. His research interests are Digital System
Design, Im-age processing, Analog and Mixed mode and millimeter-wave IC
building blocks.

Published By:
Blue Eyes Intelligence Engineering
Retrieval Number: G5755058719 /19©BEIESP 1610 & Sciences Publication