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COMBINATIONAL LOGIC

- Consists of input variables, logic gates and output variables.

- The logic gates accept signals from the inputs and generate signals to the outputs. This
process transforms binary information from the given input data to the required output
data. Both input and output data are represented by binary signals.

n input Combinational m output

variables variables
Logic Circuit

Block Diagram of Combinational Circuit

Design Procedure
The design of combinational circuits starts from the verbal outline of the problem and ends in a logic
circuit diagram or a set of Boolean functions from which the logic diagram can be easily obtained.
The procedure involves the following steps:
1. The problem is stated.
2. The number of available input variables and required output variables is determined.
3. The input and out variables are assigned letter symbols.
4. The truth table that defines the required relationships between inputs and outputs is
derived.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.

Sample Problems:
1. Build a car monitoring system that observes four things
 whether the ignition is on or of
 whether the lights are on or of
 if the door are closed or open
 if it is day or night
An alarm would sound if
 The ignition is of and the lights are on
 The ignition is on and the doors are open
 The lights are on and it is day

2. Design a combinational circuit with three inputs and one output. The output is equal to
logic-1 if the binary value of the input is less than equal to 3. The output is 0 otherwise.
Design a 3-input ABC majority function.

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3. A majority function is generated in a combinational circuit when the output is equal to 1 if
the input variables have more than 1’s than 0’s. The output is 0 otherwise. Design a 3-input
ABC majority function.

Typical Combinational Circuit:

1. ADDERS – produces a sum whose length is one digit but when both when both augends and
addend bits are equal to 1, the binary sum consist of two digits.

Kinds of Adders:

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 Half-Adder
o A combinational circuit that performs addition of two bits
o The input variables designate that augends and addend bits; the output
variables produce the sum and carry.

Function Table:
x y c s s = x’y + xy’
0 0 0 0
0 1 0 1
1 0 0 1 c = xy
1 1 1 0

 Full-Adder
o A combinational circuit that forms the arithmetic sum of three input bits.
o It consists of three inputs and two outputs.

Function Table:
x y z c s
0 0 0 0 0
s = x’y’z + x’yz’ + xy’z’ + xyz
0 0 1 0 1 =x y z
0 1 0 0 1
0 1 1 1 0 c = x’yz + xy’z + xyz’ + xyz
1 0 0 0 1
1 0 1 1 0 = xy + xz + yz
1 1 0 1 0 = z (x y) + xy
1 1 1 1 1

2. SUBTRACTOR – Each subtractor bit of the number is subtracted from its corresponding
significant minuend bit to form a diference bit. If the minuend bit is smaller than the
subtrahend bit, a 1 is borrowed from the next significant position.

Kinds of Subtractor:
 Half-Subtractor
o A combinational circuit that subtracts two bits and produces their diference
o It also has an output to specify if a 1 has been borrowed.

Function Table:
x y B D D = x’y + xy’
0 0 0 0 =x y
0 1 1 1
1 0 0 1
B = xy
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1 1 1 0

 Full-Subtractor
o A combinational circuit that subtracts three bits and produces their diferences

Function Table:
x y z B D D = x’y’z + x’yz’ + xy’z’ + xyz
0 0 0 0 0
0 0 1 1 1
=x y z
0 1 0 1 1
0 1 1 1 0 B = x’y’z + x’yz’ + xy’z’ + xyz
1 0 0 0 1 = x’ (y z) + yz
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Example:
1. Design a combinational circuit that adds one to a 4-bit binary number X 3X2X1X0. For example,
if the input of the circuit is X3X2X1X0 = 1101, the output is 1110. Construct it using 3 half-
adders and one not gate.
2. A combinational circuit produces the binary sum of two 2-bit numbers x1x0 and y1y0. The
outputs are c, s1, s0. Design the circuit and use one full adder and one half-adder.
3. Implement the following four Boolean expressions with three half-adders
D=A B C
E = A’BC + AB’C
F =ABC’ + (A’ + B’) C = ABC’ + (AB)’ C
G = ABC

B4 A4 B3 A3 B2 A2 B1 A1
Binary Parallel Adder

C4 C3 C2 C1
FA FA FA FA
C5 Circuit
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S4 S3 S2 S1
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(a) 4-bit Parallel Adder

B4 A4 B3 A3 B2 A2 B1 A1
M

C4 C3 C2 C1
FA FA FA FA
C5

S4 S3 S2 S1
(b) 4-bit Adder- Subtractor
Adder and Subtractor Circuits

Sample:
1. The 4-bit parallel adder is used to add the following 4-bit numbers: A = 1100 B = 1010
2. The adder-subtractor is used to subtract the following unsigned 4-bit numbers: 1100 –
1010.
a. What are the binary values in the nine inputs of the circuit?
b. What are the binary values of the five outputs of the circuit?

Decoders and Encoders

Decoder

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 A combinational circuit the convert binary information from n into lines to a
maximum of 2n unique output lines. If the n-bit decoded information has unused
or don’t care conditions, the decoder output will have fewer than 2n outputs.
 The name decoder is also used in conjunction with some code converters such as
a BCD-to-seven-segment decoder.

xyz D0 D1 D2 D3 D4 D5 D6 D7
000 1 0 0 0 0 0 0 0
001 0 1 0 0 0 0 0 0
010 0 0 1 0 0 0 0 0
011 0 0 0 1 0 0 0 0
100 0 0 0 0 1 0 0 0
101 0 0 0 0 0 1 0 0
110 0 0 0 0 0 0 1 0
111 0 0 0 0 0 0 0 1

x y z
x y z
*** The output variables are mutually
exclusive because only one output can be
equal to 1 at any one time. The output
line whose value is equal to 1 represents
D0 = x’y’z’ the minterm equivalent of the binary
D0 = x’y’z’ number presently available in the input
D1 = x’y’z lines.
D1 = x’y’z
D2 = x’yz’
D2 = x’yz’
D0
D3 = x’yz D1
D3 = x’yz
x D2
D4 = xy’z’ 3X8 D3
D4 = xy’z’ y Decoder D4
z D5
D5 = xy’z D6
D5 = xy’z D7

D6 = xyz’
D6 = xyz’
Block Diagram of 3x8 Decoder
D7 = xyz
D7 = xyz
Example:
1. Implement a full-adder circuit with a decoder and two OR gates.
S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7)

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Decoder with Enable

 some IC decoders are constructed with NAND gates
 since a NAND gate produces the AND operation with a inverted output, it
becomes more economical to generate the decoder minterms in their
complemented form
 IC decoders include one or more enable inputs to control the circuit operation

Example: 2-to-4-line decoder with enable input constructed with NAND gates

D0
EAB D0 D1 D2 D3
000 0 1 1 1
D1 001 1 0 1 1
AA 010 1 1 0 1
011 1 1 1 0
D2 100 1 1 1 1
BB
101 1 1 1 1
D3
110 1 1 1 1
EE 111 1 1 1 1

2-to-4-line decoder with enable (E) input

 All outputs are equal to 1 if enable E is 1, regardless of the values of input A and B.
 When the enable input is 0, the circuit operates as a decoder with complemented
outputs.
 Normal decoder operation occurs only with E = 0, and the outputs are selected when
they are in the 0 state.
 The small circle at input E indicates that the decoder is enabled when E = 0.
 The small circles at the outputs indicate that all outputs are complemented
 A decoder with an n enable input can function as demultiplexer.

D0 D0
A 2x4 D1 A 1x4 D1
Decoder D2 Demultiplexer D2
D3 D3
B B

E E
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Demultiplexer
 A circuit that receives information on a single line and transmits this information
on one of 2n possible output lines
 The selection of a specific output line is controlled by the bit values of n selection
lines
o The single input variable E has a path to all four outputs, but the input
information is directed to only one of the output lines, as specified by the
binary value of the two selection lines A and B.
o For example, if the selection lines AB = 10, output D2 will be the same as
the input value E, while all other outputs are maintained at 1.
o It is the enable input makes the circuit a demultiplexer.

Example:
 Create a 4x16 decoder constructed with two 3x8 decoders with enable
 Construct a 4-to-16-line decoder with five 2-to-4-line decoders with enable
 Construct a 5 x 32 decoder with four 3 x 8 decoders with enable and one 2 x 4
decoder.

Encoders
 A digital circuit that performs the inverse operation of a decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
 The output lines generate the binary code corresponding to the input value.

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Example: octal to binary encoder

Function Table

D0 D1 D2 D3 D4 D5 D6 D7 xyz
1 0 0 0 0 0 0 0 000
z = D1 + D3 + D5 + D7
0 1 0 0 0 0 0 0 001
0 0 1 0 0 0 0 0 010
0 0 0 1 0 0 0 0 011 y = D2 + D3 + D6 + D7
0 0 0 0 1 0 0 0 100
0 0 0 0 0 1 0 0 101 x = D4 + D5 + D6 + D7
0 0 0 0 0 0 1 0 110
0 0 0 0 0 0 0 1 111

o The encoder has eight inputs, one for each of the octal digits and three outputs that
generate the corresponding binary number.
o It is assumed that only one input has a value of 1 at any given time; otherwise the
circuit has no meaning
o The encoder can be implemented with OR gates whose inputs are determined
directly from the function table.

D0
D0 z = D1 + D3 + D5 + D7
D1 z = D1 + D3 + D5 + D7
D1
D2
D2
D3
D3 y = D2 + D3 + D6 + D7
D4 y = D2 + D3 + D6 + D7
D4
D5
D5
D6
D6
D7 x = D4 + D5 + D6 + D7
D7 x = D4 + D5 + D6 + D7

 The encoder in the table has a limitation that only one input can be active at any
given time
 If two inputs are active simultaneously, the output of the encoder will be 111
because all three outputs are equal to 1

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 To resolve this ambiguity, encoder circuits must establish a priority to ensure that
only one input is encoded. If we establish a higher priority for inputs with higher
subscript numbers and if both D 3 and D6 are 1 at the same time, the output will
be 110 because D6 has higher priority than D3
 Another ambiguity is that an output with all 0’s is generated when all inputs are 0
 The problem is that all 0’s is also generated when D0 is equal to 1
 This ambiguity can be resolved by providing an additional output that specifies
the condition that none of the inputs are active.

Priority Encoder
 An encoder circuit that includes the priority function
 The operation of the priority encoder is such that if two or more inputs are equal
to 1 at the same time, the input having the highest priority will take precedence.

Function Table
D0 D1 D2 D3 X Y V
X = D2 + D3
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1 Y = D3 + D1D2’
X X 1 0 1 0 1
X X X 1 1 1 1 V = D0 + D1 + D2 + D3

 The x’s are don’t care conditions that designate the fact that the binary value
may be equal to either 0 or 1
 Input D3 has the highest priority; so regardless of the values of the other inputs,
when this input is 1, the output for xy is 11 (binary 3).
 D2 has the next level and so on.
 A valid-output indicator, designated by V, is set to 1 only when one or more of
the inputs are equal to 1
 If all inputs are 0, V is equal to 0, and the other two outputs of the circuit are not
used.

Maps for a priority encoder

D2 D3 D2 D3
D0 D1 00 01 11 10 00 01 11 10
D0 D1
00 01 00 01
11 10 11 10

00 01
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X = D2 + D3 Y = D3 + D1D2’

Multiplexing
 Means transmitting a large number of information units over a smaller number
of channels or lines.
 Digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line.
 The selection of a particular input line is controlled by a set of selection lines.

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 Normally, there are 2n input lines and n selection lines whose bit combinations
determine without input are selected.

Example: 4-to-1 multiplexer

I0

I1

Y
I2 Y

I3

S1
S0
o Each of the four input lines I0 to I3 is applied to one input of
an AND gate.
o selection lines S1 and S0 are decoded to select a particular
AND gate

S1 S0 Y I0 00
0
0 0 I0 inputs I1 11 4x1 Y
inputs 1
0 1 I1 I2 22 MUX output
output
2 33
1 0 I2 S1
S1 S0
S0
1 1 I3

Select
Select

Function Table Block diagram

Examples:

 Implement the Boolean Function F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15). Function
is implemented with a multiplexer with three selection inputs A, B, and C must be
connected to selection input S2, S1, S0 respectively.

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 Implement the following Boolean function F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
with 4x1 multiplexer and external gates. Connect A and B to the selection lines. The
input requirements for the four data lines will be a function of variables C and D.
These values are obtained by expressing F as a function of C and D for each of the 4
cases when AB = 00, 01, 10, and 11.

 A 4x1 multiplexer has inputs w, x connected to the selection inputs S 1 and S0

respectively. The data inputs I0 through I3 are as follows: I2 = y’z ; I0 = I1 = z ; I3 = y’

 An 8x1 multiplexer has input A, B, C connected to the selection inputs S 2, S1, & S0
respectively. The data inputs I0 through I7 are as follows: I1 = I2 = I7 = 0 ; I3 = I5 = 1 ; I0 =
I4 = D ; and I6 = D’. Determine the Boolean function that the multiplexer implements.

SYNCHRONOUS SEQUENTIAL CIRCUIT

Combinational Logic Circuit – combinational outputs are functions of the present inputs.

Sequential Circuit – outputs at any given time are functions of the external inputs as well as
some stored information determined by previous inputs.

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input output
Combinational
Circuit
Memory
elements

Block Diagram of a Sequential Circuit

State – binary information stored in the memory elements at any given time.

There are two main types of sequential circuits. Their classification depends on the timing of
their signals.

 Synchronous sequential circuit

o A system where behavior can be defined from the knowledge of its
signals at discrete instant of time.
o Events occur at the same time under the control of a clock.

 Asynchronous sequential circuit

o Depends upon the order in which its signals change and can be afected
at any instant of time.

FLIP-FLOPS
 A storage device that is used to remember the state of the circuit
 memory elements used in clocked sequential circuits
 it is capable of storing one bit of information
 flip-flops are constructed by interconnecting logic gates in integrated circuits
 A flip-flop can maintain a binary state indefinitely (as long as power is applied to the
circuit) until directed by an input signal to switch states.
 Once the state of the flip-flop is set, it remains in this way, until changed by the
inputs. Thus, a flip-flop remembers the inputs.

Flip-flop Applications
 flip-flops serves as a storage device, such as storage register which is composed
of flip-flops that stores the individual bits of a binary number
 Also serves as a digital counter. This device is used to keep track of events that
occur in a digital system
 also used as a frequency divider

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Types of Flip-flops

 Set-Reset Flip-flop (RS-FF)

o This device has two inputs, the set S and the reset R. When logic 1 is applied
to S, flip-flop is set to 1 (Q=1). When logic 1 is applied to R, the flip-flop is
reset to 0 (Q=0).

Block Diagram Truth Table Circuit Diagram

Input Output
R
S R Q+1
0 0 No change
0 1 0
1 0 1
S
1 1 Invalid

S Q Q
clk
clk
R Q’ Q’

 JK Flip-flop
o the JK flip-flop is the most commonly used type of flip-flop
o it is very similar to the RS-FF except that a JK-FF accepts logic 1 on both the J
and K inputs.

Block Diagram Truth Table Circuit Diagram

Input Output
J K Q+1 J
0 0 No change
0 1 0
1 0 1 K
1 1 Toggle

J Q Q
clk
clk
K Q’ Q’

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 D Flip-flop
o the D flip-flop is diferent from the RS and JK flip-flops because it only has one
input
o the flip-flop transfers the logic value at the input to the output when a clock
pulse is applied.
o it can therefore be used as a delay device or for storing a simple bit, which
may be 1 or 0

Block Diagram Truth Table Circuit Diagram

D
D Input Output Q
Q D Q+1
0 0
1 1

clk
clk

Q’

 T Flip-flop
o The trigger T-type flip-flop (T-FF) is a less popular type, which can be obtained
by connecting both J and K to logic 1.

Block Diagram Truth Table Circuit Diagram

T
J Q Input Output Q
T Q+1
0 No Change
K Toggle
1

clk
clk

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Q’

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