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Multiplexor 2 A 1

The document contains VHDL code for multiplexor and testbench components. It defines 2-to-1 and 4-to-1 multiplexor entities with ports for inputs, a selector input, and an output. The code provides behavioral architectures that use a case statement to select the appropriate input for the output based on the value of the selector signal. It also includes testbench code that applies stimulus to the inputs and checks the output.

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adrianchoa_09
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67 views

Multiplexor 2 A 1

The document contains VHDL code for multiplexor and testbench components. It defines 2-to-1 and 4-to-1 multiplexor entities with ports for inputs, a selector input, and an output. The code provides behavioral architectures that use a case statement to select the appropriate input for the output based on the value of the selector signal. It also includes testbench code that applies stimulus to the inputs and checks the output.

Uploaded by

adrianchoa_09
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Multiplexor 2 a 1

--------------------------------------------------------------------

--Nombre:Angel Andres Cantillo Fragozo

--Documento:1065639519

--Fecha:18/10/2019

--Proyecto:Tarea 2

--------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity Multiplexor2a1 is

Port ( E0,E1 : in STD_LOGIC_VECTOR (3 downto 0);

selector : in STD_LOGIC_VECTOR (1 downto 0);

Salida : out STD_LOGIC_VECTOR (3 downto 0)

);

end Multiplexor2a1;

architecture Behavioral of Multiplexor2a1 is

begin

with selector select

Salida <= E0 when "00",

E1 when others;

end Behavioral;
-- Code your testbench here

library IEEE;

use IEEE.std_logic_1164.all;

entity simulacion is

--

end simulacion;

architecture Behavioral of Simulacion is

component Multiplexor2a1

Port ( E0 : in STD_LOGIC_VECTOR (3 downto 0);

E1 : in STD_LOGIC_VECTOR (3 downto 0);

selector : in STD_LOGIC_VECTOR (1 downto 0);

Salida : in STD_LOGIC_VECTOR (3 downto 0));

end component;

--Señales de entrada

signal selector: STD_LOGIC_VECTOR (1 downto 0):= '00',

signal E0,E1 : STD_LOGIC_VECTOR (3 downto 0):= (others => '0');

--Señales de salida

signal Salida : STD_LOGIC_VECTOR (3 downto 0);


begin

UO: Multiplexor2a1 Port map

E0 => E0,

E1 => E1,

Salida=> Salida

process begin

--Estimulos de la simulacion with 100ns

wait for 100 ns;

E0 <= '0';

E1 <= "0000";

wait for 100 ns;

E0 <= '1';

E1 <= "0001";

wait for 100 ns;

E0 <= '0';

E1 <= "0110";
wait for 100 ns;

wait;

end process;

end Behavioral;

--------------------------------------------------------------------

--Nombre:Angel Andres Cantillo Fragozo

--Documento:1065639519

--Fecha:18/10/2019

--Proyecto:Tarea 2

--------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity Multiplexor4a1 is

Port ( E0,E1,E2,E3 : in STD_LOGIC_VECTOR (7 downto 0);

selector : in STD_LOGIC_VECTOR (1 downto 0);

Salida : out STD_LOGIC_VECTOR (7 downto 0)

);
end Multiplexor4a1;

architecture Behavioral of Multiplexor4a1 is

begin

with selector select

Salida <= E0 when "00",

E1 when "01",

E0 when "10",

E1 when "11",

E0 when others;

end Behavioral;

--------------------------------------------------------------------

--Nombre:Angel Andres Cantillo Fragozo

--Documento:1065639519

--Fecha:18/10/2019

--Proyecto:Tarea 2

--------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;
entity Multiplexor4a1 is

Port ( E0,E1,E2,E3 : in STD_LOGIC_VECTOR (7 downto 0);

selector : in STD_LOGIC_VECTOR (1 downto 0);

Salida : out STD_LOGIC_VECTOR (7 downto 0)

);

end Multiplexor4a1;

architecture Behavioral of Multiplexor4a1 is

begin

with selector select

Salida <= E0 when "00",

E1 when "01",

E0 when "10",

E1 when "11",

E0 when others;

end Behavioral;

-- Code your testbench here

library IEEE;

use IEEE.std_logic_1164.all;
entity simulacion is

--

end simulacion;

architecture Behavioral of Simulacion is

component Multiplexor4a1

Port ( E0,E1,E2,E3 : in STD_LOGIC_VECTOR (7 downto 0);

selector : in STD_LOGIC_VECTOR (1 downto 0);

Salida : out STD_LOGIC_VECTOR (7 downto 0));

end component;

--Señales de entrada

signal selector: STD_LOGIC_VECTOR (1 downto 0):= (others => '0');

signal E0,E1,E2,E3 : STD_LOGIC_VECTOR (3 downto 0):= (others => '0');

--Señales de salida

signal Salida : STD_LOGIC_VECTOR (7 downto 0);

begin

UO: Multiplexor4a1 Port map

E0 => E0,

E1 => E1,
E2 => E2,

E3 => E3,

selector => selector,

Salida=> Salida

process begin

--Estimulos de la simulacion with 100ns

wait for 100 ns;

E0 <= "00001111";

E0 <= "10001111";

E0 <= "00101011";

E0 <= "10001111";

selector <= "00";

wait for 100 ns;

selector <= "01";

wait for 100 ns;

selector <= "10";

wait for 100 ns;

selector <= "11";

wait for 100 ns;


wait;

end process;

end Behavioral;

--------------------------------------------------------------------

--Nombre:Adolfo Luis Padilla Aldana

--Documento:8851831
--Fecha:19/10/2019

--Proyecto:Tarea 2

--------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity Multiplexor8a1 is

Port ( E0,E1,E2,E3,E4,E5,E6,E7 : in STD_LOGIC_VECTOR (9 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

F : out STD_LOGIC_VECTOR (9 downto 0)

);

end Multiplexor8a1;

architecture Behavioral of Multiplexor8a1 is

begin

with sel select

F <= E0 when "000",

E1 when "001",

E2 when "010",

E3 when "011",

E4 when "100",

E5 when "101",

E6 when "110",
E7 when "111",

E0 when others;

end Behavioral;

-- Code your testbench here

library IEEE;

use IEEE.std_logic_1164.all;

entity simulacion is

--

end simulacion;

architecture Behavioral of Simulacion is

component Multiplexor8a1

Port ( E0,E1,E2,E3,E4,E5,E6,E7 : in STD_LOGIC_VECTOR (9 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

F : out STD_LOGIC_VECTOR (9 downto 0));

end component;

--Señales de entrada

signal sel : STD_LOGIC_VECTOR (1 downto 0):= (others => '0');

signal E0,E1,E2,E3,E4,E5,E6,E7 : STD_LOGIC_VECTOR (9 downto 0):= (others => '0');

--Señales de salida

signal F : STD_LOGIC_VECTOR (9 downto 0);


begin

UO: Multiplexor8a1 Port map

E0 => E0,

E1 => E1,

E2 => E2,

E3 => E3,

E4 => E4,

E5 => E5,

E6 => E6,

E7 => E7,

sel => sel

F => F

);

process begin

--Estimulos de la simulacion with 100ns

wait for 100 ns;

E0 <= "0000011111";

E0 <= "1000011111";

E0 <= "0001010111";

E0 <= "1000011111";

sel <= "00";

wait for 100 ns;


sel <= "01";

wait for 100 ns;

sel <= "10";

wait for 100 ns;

sel <= "11";

wait for 100 ns;

wait;

end process;

end Behavioral;
EJERCICIO 6 COMPONENTS

--------------------------------------------------------------------------------

-- Nombre:Adolfo Luis Padilla Aldana

-- Documento:8851831

-- Fecha:20/10/2019

-- Proyecto:Tarea 2

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity sumador is

Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);

F : out STD_LOGIC_VECTOR (3 downto 0)

);

end sumador;

architecture Behavioral of sumador is

begin

F <= A + B;

end Behavioral;
RESTADOR

------------

--Nombre:Adolfo Luis Padilla Aldana

-- Documento:8851831

-- Fecha:20/10/2019

-- Proyecto:Tarea 2

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity restador is

Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);

F : out STD_LOGIC_VECTOR (3 downto 0)

);

end restador;

architecture Behavioral of restador is

begin

F <= A - B;

end Behavioral;
MULTIPLEXOR

--------------------------------------------------------------------------------

-- Nombre:Adolfo Luis Padilla Aldana

-- Documento:8851831

-- Fecha:20/10/2019

-- Proyecto:Tarea 2

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity sumador is

Port ( I0,I1 : in STD_LOGIC_VECTOR (3 downto 0);

sel : in STD_LOGIC;

F_mux : out STD_LOGIC_VECTOR (3 downto 0)

);

end sumador;

architecture Behavioral of sumador is

begin

with sel select

F_mux <= I0 when '0',

I1 when others;
end Behavioral;

DESING

---------

//-- Nombre:Adolfo Luis Padilla Aldana

//-- Documento:8851831

//-- Fecha:20/10/2019

//-- Proyecto:Tarea 2

//----------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity design is

Port ( A_alu, B_alu : in STD_LOGIC_VECTOR (3 downto 0);

sel_alu : in STD_LOGIC_VECTOR;

F_alu : in STD_LOGIC_VECTOR (3 downto 0)

);

end design ;

architecture Behavioral of design is


component sumador

Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);

F : out STD_LOGIC_VECTOR (3 downto 0)

);

end component;

component restador

Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);

F : out STD_LOGIC_VECTOR (3 downto 0)

);

end component;

component multiplexor

Port ( I0,I1 : in STD_LOGIC_VECTOR (3 downto 0);

sel : in STD_LOGIC;

F_mux : out STD_LOGIC_VECTOR (3 downto 0)

);

end component ;

--Señales internas

signal suma, resta : STD_LOGIC_VECTOR (3 downto 0):= (others => '0');

begin

UO: sumador port map (

A => A_alu,
B => B_alu,

F => suma

);

U1: restador port map (

A => A_alu,

B => B_alu,

F => resta

);

U2: multiplexor port map (

I0 => A_alu,

I1 => B_alu,

sel => sel_alu

F_mux => F_alu

);

end Behavioral;

TESTBENCH

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Simulacion is
--

end Simulacion;

architecture Behavioral of Simulacion is

component design

Port ( A_alu, B_alu : in STD_LOGIC_VECTOR (3 downto 0);

sel_alu : in STD_LOGIC_VECTOR;

F_alu : in STD_LOGIC_VECTOR (3 downto 0)

);

end component ;

-- Señales de las entradas

signal sel_alu : STD_LOGIC:= '0';

signal A_alu, B_alu : STD_LOGIC_VECTOR (3 downto 0):= (others => '0');

-- Señales de salidas

signal F_alu : STD_LOGIC_VECTOR (3 downto 0);

begin

UO: design Port map (

A_alu => A_alu,

B_alu => B_alu,

sel_alu => sel_alu

F_alu => F_alu

);
process begin

--- Estímulos de la simulación wait for 100 ns;

wait for 100 ns;

sel_alu <= '0';

A_alu <= "0100";

B_alu <= "0010";

wait for 100 ns;

sel_alu <= '1';

wait for 100 ns;

sel_alu <= '0';

A_alu <= "0101";

B_alu <= "0011";

wait for 100 ns;

wait;

end process;

end Behavioral;

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