ECE 3410

MICROELECTRONICS I
LECTURE NOTES

Spring 2018

Chris Winstead
Associate Professor
Electrical and Computer Engineering
[email protected]
Copyright © 2018

published by utah state university

department of electrical and computer engineering

http://www.ece.usu.edu

Licensed for redistribution and adaptation under the Creative Commons

Attribution-ShareAlike International 4.0 License, CC-BY-SA-4.0.
Contents

List of Netlists . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Examples . . . . . . . . . . . . . . . . . . . . . . . . 7
List of EveryCircuit Demos . . . . . . . . . . . . . . . . . 10

Introduction 13
Signal sources . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ideal Amplifier Models . . . . . . . . . . . . . . . . . . . . 17
Real Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 21
Equivalent small-signal resistance and impedance . . . . 26
Frequency Response of Amplifiers . . . . . . . . . . . . . 26
Harmonic distortion . . . . . . . . . . . . . . . . . . . . . 33

Operational Amplifier Circuits 35

Amplifiers with finite open-loop gain . . . . . . . . . . . 35
Difference amplifiers . . . . . . . . . . . . . . . . . . . . . 41
Instrumentation amplifiers . . . . . . . . . . . . . . . . . . 44
Non-Ideal Op Amp Characteristics . . . . . . . . . . . . . 46
Frequency Response of Op Amps . . . . . . . . . . . . . . 50
Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Full Power Bandwidth (FPBW) . . . . . . . . . . . . . . . 56
Op Amp Integrators and Differentiators . . . . . . . . . . 57

Introduction to Diodes 63
Ideal switch model . . . . . . . . . . . . . . . . . . . . . . 63
Exponential model . . . . . . . . . . . . . . . . . . . . . . 65
Constant voltage-drop model . . . . . . . . . . . . . . . . 65
Iterative Analysis . . . . . . . . . . . . . . . . . . . . . . . 66
Linearized Model . . . . . . . . . . . . . . . . . . . . . . . 69

Diode Circuits 71
Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . 71
Resistor-diode regulator . . . . . . . . . . . . . . . . . . . 73
Peak rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Envelope detector . . . . . . . . . . . . . . . . . . . . . . . 75
Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . 77
4

Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . 79
Super Diode, Precision Rectifier . . . . . . . . . . . . . . . 83
DC Restoration, Clamped Capacitor . . . . . . . . . . . . 85
Boost converter . . . . . . . . . . . . . . . . . . . . . . . . 86

Memristors 89
Axiomatic Circuit Theory . . . . . . . . . . . . . . . . . . 89
Simulating Memristors . . . . . . . . . . . . . . . . . . . . 94
Memristor Applications . . . . . . . . . . . . . . . . . . . 99
Exploring Memristor Controversies . . . . . . . . . . . . . 105
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Introduction to MOSFETs 111

Why do we need transistors? . . . . . . . . . . . . . . . . 111
Electrical Characteristics . . . . . . . . . . . . . . . . . . . 112
NMOS RTL Inverter Analysis . . . . . . . . . . . . . . . . 114
Behavior in Saturation . . . . . . . . . . . . . . . . . . . . 118
Some important DC configurations . . . . . . . . . . . . . 120
MOSFETs as Switches . . . . . . . . . . . . . . . . . . . . 123
MOSFETs as Amplifiers . . . . . . . . . . . . . . . . . . . 130
Amplifier analysis: general principles . . . . . . . . . . . 139
Common-Gate amplifier configuration . . . . . . . . . . . 140
Source Follower configuration . . . . . . . . . . . . . . . . 145
Biasing MOSFET amplifiers . . . . . . . . . . . . . . . . . 147
Frequency response of CMOS amplifiers . . . . . . . . . 153

Introduction to BJTs 159

DC passive bias configurations . . . . . . . . . . . . . . . 161
BJT small-signal characteristics . . . . . . . . . . . . . . . 163
BJT amplifiers with passive bias . . . . . . . . . . . . . . . 164

Basic Electronic Device Theory 167

Some relevant chemistry . . . . . . . . . . . . . . . . . . . 167
Energy band theory . . . . . . . . . . . . . . . . . . . . . . 168
Semiconductor materials . . . . . . . . . . . . . . . . . . . 171

The PN Junction 183

Neutral bias . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Reverse Bias . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Forward Bias . . . . . . . . . . . . . . . . . . . . . . . . . . 192
The “Ideal” Diode Model . . . . . . . . . . . . . . . . . . 194
SPICE Diode Models . . . . . . . . . . . . . . . . . . . . . 198
Optoelectronic Behavior of PN Junctions . . . . . . . . . 200
LEDs and Direct vs Indirect Bandgaps . . . . . . . . . . . 210
Diodes as Particle Detectors and Geiger Counters . . . . 211
 5

Field Effect Transistors 213

Physical Structure . . . . . . . . . . . . . . . . . . . . . . . 213
MOSFET at Zero Gate Bias . . . . . . . . . . . . . . . . . . 215
MOSFET in Weak Inversion . . . . . . . . . . . . . . . . . 216
MOSFET in Strong Inversion (triode) . . . . . . . . . . . . 218
Channel Pinchoff (saturation) . . . . . . . . . . . . . . . . 220
MOSFET Energy Bands . . . . . . . . . . . . . . . . . . . 222
Body Effect (aka Back-Gate Effect) . . . . . . . . . . . . . 224

Bibliography 225
List of Netlists

1 envelope_detector.sp . . . . . . . . . . . . . . . . . . 76
2 bridge_rectifier.sp . . . . . . . . . . . . . . . . . . . . 78
3 basic_regulator.sp . . . . . . . . . . . . . . . . . . . . 81
4 superdiode.sp . . . . . . . . . . . . . . . . . . . . . . 84
5 741.sp (top lines showing port order) . . . . . . . . 84
6 dc_restorer.sp . . . . . . . . . . . . . . . . . . . . . . 86
7 boost_converter.sp . . . . . . . . . . . . . . . . . . . 87
8 DC sweep of common-source degeneration resistances138
9 AC simulation of CS configuration . . . . . . . . . . 156
10 Gain/BW tradeoff in CS configuration . . . . . . . . 157
11 diode_dc.sp . . . . . . . . . . . . . . . . . . . . . . . 199
12 tunnel_diode_model.sp . . . . . . . . . . . . . . . . 208
13 tunnel_diode_oscillator.sp . . . . . . . . . . . . . . . 209
List of Examples

1 Low-pass RC circuit . . . . . . . . . . . . . . . . . . . . . 15
2 High-pass RC circuit . . . . . . . . . . . . . . . . . . . . . 15
3 Linearization of a sensor . . . . . . . . . . . . . . . . . . . 23
4 Linearization of a thermistor model . . . . . . . . . . . . 24
5 Bias current in inverting configuration . . . . . . . . . . . 46
6 Maximum resistance due to I bias . . . . . . . . . . . . . . 46
7 Inverting configuration with offset voltage . . . . . . . . 48
8 Closed-loop frequency response, low-gain . . . . . . . . 52
9 Closed-loop frequency response, high-gain . . . . . . . . 52
11 Max-Value Circuit . . . . . . . . . . . . . . . . . . . . . . . 64
12 Min-Value Circuit . . . . . . . . . . . . . . . . . . . . . . . 64
13 Min-value circuit with 0.7V drop model . . . . . . . . . . 65
14 Iterative analysis . . . . . . . . . . . . . . . . . . . . . . . 66
15 Iteration with linearized model . . . . . . . . . . . . . . . 70
16 Half-wave rectifier with vin < 0 . . . . . . . . . . . . . . . 71
17 Half-wave rectifier with vin = 1V . . . . . . . . . . . . . . 71
18 Four-diode voltage regulator design . . . . . . . . . . . . 79
19 Two Diode Regulator with Op Amp Buffer . . . . . . . . 82
20 Diode as a nonlinear resistor . . . . . . . . . . . . . . . . 92
21 Static CMOS logic design . . . . . . . . . . . . . . . . . . 125
22 Static CMOS XOR gate . . . . . . . . . . . . . . . . . . . . 126
23 Passive-biased CS amp with source degeneration . . . . 135
24 Common-gate configurations . . . . . . . . . . . . . . . . 142
25 Source Follower output resistance . . . . . . . . . . . . . 145
26 Current-mirror active bias . . . . . . . . . . . . . . . . . . 147
27 Output offset with current-mirror bias . . . . . . . . . . . 149
28 Voltage divider bias . . . . . . . . . . . . . . . . . . . . . . 161
29 Feedback bias . . . . . . . . . . . . . . . . . . . . . . . . . 162
30 Charge density in doped semiconductors . . . . . . . . . 172
31 Fermi levels in doped silicon . . . . . . . . . . . . . . . . 174
32 Drift current in a homogeneous material. . . . . . . . . . 177
33 Drift and diffusion currents . . . . . . . . . . . . . . . . . 180
34 Junction capacitance due to depletion . . . . . . . . . . . 188
36 Zener temperature coefficients. . . . . . . . . . . . . . . . 191
10

37 Realistic and Approximate Diode Models . . . . . . . . . 196

38 Subthreshold operation . . . . . . . . . . . . . . . . . . . . 216
39 Subthreshold leakage current . . . . . . . . . . . . . . . . 217
List of EveryCircuit Demonstrations

2 Ideal Voltage Amplifier . . . . . . . . . . . . . . . . . . . . 17

4 Ideal Band-Pass Amplifier Model . . . . . . . . . . . . . . 31
6 Capacitive Coupling . . . . . . . . . . . . . . . . . . . . . 32
8 Inverting configuration . . . . . . . . . . . . . . . . . . . . 37
10 Non-inverting configuration . . . . . . . . . . . . . . . . . 39
12 Voltage follower configuration . . . . . . . . . . . . . . . 40
14 Difference amplifier (differential mode) . . . . . . . . . . 41
16 Non-inverting circuit with bias and offset . . . . . . . . . 48
18 Closed-loop frequency response . . . . . . . . . . . . . . 53
20 Diode connected NMOS device . . . . . . . . . . . . . . . 121
22 NMOS bias network . . . . . . . . . . . . . . . . . . . . . 122
24 NMOS RTL inverter . . . . . . . . . . . . . . . . . . . . . . 124
26 NMOS pull-up and pull-down . . . . . . . . . . . . . . . 124
28 Transmission gate track-and-hold circuit . . . . . . . . . . 129
30 NMOS Common-Source Amplifier . . . . . . . . . . . . . 131
32 PMOS Common-Source Amplifier . . . . . . . . . . . . . 132
34 CS amplifier with bypass capacitor . . . . . . . . . . . . . 138
36 Common-Gate configuration . . . . . . . . . . . . . . . . 143
38 Common-Gate bypass configuration . . . . . . . . . . . . 143
40 Two stage amp with current mirror bias . . . . . . . . . . 150
42 Two-stage amplifier with ideal feedback bias . . . . . . . 152
44 Two-stage amplifier with PMOS feedback bias . . . . . . 152
46 Common-Emitter with feedback bias . . . . . . . . . . . . 165
48 Correlated Double Sampling . . . . . . . . . . . . . . . . 204
Introduction

Rsig
Signal sources +
+
vsig −
Electronic circuits and systems can be loosely divided into two
classes: those that process signals, which are electrical repre- −
sentations of information, and those that convey or convert Figure 1: Thévenin equivalent voltage signal source.
electrical power. In this course we are primarily concerned with
circuits that process signals, in the broadest possible sense. A
signal may convey physical information, e.g. an audio signal +

produced from a microphone, or it may convey discrete or vsig Rsig

digital information as part of a computational process. Regard-
less of the context, we will always view signals as electrical −

information, either a current or voltage. Figure 2: Norton equivalent current signal source.
A transducer is a device that converts a physical signal into
an electrical one. From the circuit perspective, we usually model1
a transducer as either a voltage source or a current source. 1
A model is a useful approximation of a physical
Every signal source has an associated internal impedance, device or system. We use models to simplify our
understanding of complex electronic components.
represented by Thévenin or Norton equivalent circuits.

Spectrum and Frequency Response

Most information-bearing signals are not constant. A signal x (t)
that changes over time can be represented as a superposition
of sinusoidal signals with various magnitudes, frequencies
and phases. The function that characterizes the magnitudes
and phases at each frequency is called the signal’s complex-
valued Fourier spectrum, written X ( jω ). The theory of spectral
transforms is quite sophisticated, but in this course we mostly
require a simplified version known as the steady-state. For our
purposes, we may consider the Laplace transform X (s) to be
equivalent to the Fourier spectrum, with s = jω.
On a modern digital oscilloscope, a signal’s spectrum can be
viewed by selecting a Fast Fourier Transform (FFT) display,
which reports the signal’s magnitude spectrum, equal to the
complex magnitude | X ( jω )|. Since X ( jω ) is a complex function,

Figure 3: Example FFT display on an oscilloscope.

14 ece3410 lecture notes

the magnitude is obtained as

| X ( jω )|2 = X ( jω ) × X ∗ ( jω ).

The magnitude spectrum is typically expressed in units of 40

decibels, and the complex phase ∠X ( jω ) is usually expressed

VS (s) (dB)
in degrees (0◦ to 360◦ ).
The individual sinusoidal signal components are expressed 20

as
v a (t) = VA sin (ω0 t + φ) ,
0
where VA is the zero-to-peak amplitude, ωs is the signal fre- 101 102 103 104 105
quency in radians per second, t is the time in seconds, and φ is ω (rad/sec)
the phase-shift in radians. Figure 4: A sinusoid has a single Fourier component
A pure or single-tone sinusoid has a magnitude spectrum that appears as an impulse function on the spectral
representation. In this case the magnitude is 40 dB,
represented by a single impulse function which corresponds to a time-domain zero-to-peak
amplitude of 200 V.
1
VA (ω ) = V δ ( ω − ωs ) .
2 A
The impulse height in decibels is 20 log10 (VA /2). So a zero-to-
peak magnitude of 1 V corresponds to −6 dB, 10 V corresponds
to 14 dB, 100 V corresponds to 34 dB, and so on. Frequency Units:
When signals pass through electronic circuits, their magni- • ω = 2π f
tude and phase are altered. The circuit’s transfer function is the • f is in Hz (cycles per second)
ratio of the output spectrum to the input spectrum. If a circuit’s • ω is in radians per second.
input is X (s) and its output is Y (s), then the transfer function is • ω is “omega”, not w.
• A magnitude V in dB is 20 log10 (V )
Y (s)
H (s) = . • A power P in dB is 10 log10 ( P).
X (s)

We may interpret the transfer function in terms of frequency by

substituting s = jω. The transfer function’s magnitude response
is usually expressed in decibels as

| H (ω )| (dB) = 20 log10 | H (ω )|
= 10 log10 | H (ω )|2 .

When expressed in decibels, the magnitude reveals useful in- R R

formation about the circuit. When | H (ω )| = 0 dB, the output’s
amplitude is equal to the input. When | H (ω )| is positive, the
output’s amplitude is greater than the input, and the circuit is
C 1
said to have gain. When | H (ω )| is negative, the output’s ampli- Cs

tude is less than the input, and the circuit is said to attenuate
the signal.
For a linear circuit, the transfer function is obtained using
complex impedances for capacitors and inductors. A capacitor L Ls
with capacitance C has impedance 1/(sC ), and an inductor with
Figure 5: Passive linear components and their
equivalent Laplace-domain impedances.
 introduction 15

inductance L has impedance sL. Once components are replaced

by their equivalent impedances, they can be analyzed as though
they were resistors where the resistance values are polynomials
in s.

Example 1 (Low-pass RC circuit).

The low-pass configuration is like a simple voltage divider. The

impedances are Z1 = R and Z2 = 1/sC. Then R
  VIN (s) VOUT (s)
Z2
VOUT (s) = VIN (s)
Z1 + Z2 1/sC
VOUT (s) 1/sC
⇒ H (s) = =
VIN (s) R + 1/sC
Figure 6: Low-pass configuration.
1
=
1 + sRC
The low-pass transfer function is commonly represented as

1
H ( jω ) =
1 + jω/ω3dB

. The magnitude response is then

  
2 1 1
| H (ω )| =
1 + jω/ω3dB 1 − jω/ω3dB
!
1
= 2
1 + ω 2 /ω3dB

At low frequencies where ω  ω3dB , the magnitude response is flat, approximately equal to one. At
higher frequencies where ω  ω3dB , the magnitude drops rapidly. At these high frequencies, since
ω/ω3dB  1, we can make an approximation:

ω/ω3dB + 1 ≈ ω/ω3dB
⇒ | H (ω )| ≈ ω3dB /ω (high frequencies above ω3dB )

When represented in decibels, we find that

ω 
3dB
| H (ω )| ≈ 20 log10
ω
= 20 log10 ω3dB − 20 log10 ω.

So as ω increases, the magnitude decreases by 20 dB per decade.

16 ece3410 lecture notes

Example 2 (High-pass RC circuit).

The high-pass configuration has impedances are Z1 = 1/sC and Z2 =

R. Then 1/sC
VIN (s) VOUT (s)
 
Z2
VOUT (s) = VIN (s)
Z1 + Z2
R
VOUT (s) R
⇒ H (s) = =
VIN (s) R + 1/sC
sRC Figure 7: High-pass configuration.
=
1 + sRC
The high-pass transfer function is commonly represented as

jω/ω3dB
H ( jω ) =
1 + jω/ω3dB

. The magnitude response is then

− jω/ω3dB
  
jω/ω3dB
| H (ω )|2 =
1 + jω/ω3dB 1 − jω/ω3dB
!
ω 2 /ω3dB
2
= 2
1 + ω 2 /ω3dB

At high frequencies where ω  ω3dB , the magnitude response is flat, approximately equal to one. At
lower frequencies where ω  ω3dB , the magnitude drops rapidly. Since ω/ω3dB  1, we can make
an approximation:

ω/ω3dB + 1 ≈ 1
⇒ | H (ω )| ≈ ω/ω3dB (low frequencies below ω3dB )

When represented in decibels, we find that

 
ω
| H (ω )| ≈ 20 log10
ω3dB
= 20 log10 ω − 20 log10 ω3dB .

So as ω increases from very low frequencies, the magnitude increases by 20 dB per decade.

A note on approximations: in these examples we used a

If A  B then:
very common method of large-value approximation. We will
use this procedure many times. Suppose two quantities A and A+B ≈ A
1 1 1
B differ greatly in value, so that A  B. The notion of “much + ≈
A B B
greater than” is somewhat fuzzy, but in this course we will A
≈1
define it as more than a 10× difference between two quantities. A+B
B B
≈
A+B A
and so on...
 introduction 17

Rout
Ideal Amplifier Models + +
+
An ideal linear amplifier is a circuit which receives an input vin Rin Av vin − vout
signal X and produces an output signal Y = AX. In other
− −
words, the output is larger than the input by a constant multiple
Figure 8: Ideal linear voltage amplifier model at low
A, called the gain. The input/output signals can be either or mid-band frequencies.
current or voltage, which introduces four possible amplifier
configurations:

Input Output Amplifier Type Gain Name and Symbol

Voltage Voltage Voltage Amplifier Gain Av
Current Current Current Amplifier Gain Ai
Voltage Current Transconductance Amplifier Transconductance Gm
Current Voltage Transresistance Amplifier Transresistance Rm

In order to use an amplifier, it has to be connected to its

signal source on the input side and its load on the output side.
This creates a coupling interaction between the amplifiers
internal resistances and the neighboring signal resistances. In
the voltage amplifier, we see a voltage-divider effect at both the
input and output interfaces:

Rsig Rout
+ + 
Rin

vIN = vSIG
+ Rin + Rsig
vsig +
− vin Rin Av vin − vout RL  
RL
vOUT = Av vIN
Rout + R L
− −

Figure 9: Coupling interactions in voltage amplifiers.

Resistive voltage dividers appear at the input and
output interfaces.
As a result the complete system is described by the gain
equation in combination with the coupling divider ratios. To
describe this effect, we distinguish the open-circuit gain from
the loaded gain:

vOUT
open-circuit gain: Avo , = Av
vIN
  
v Rin RL
loaded gain: AvL , OUT = Av .
vIN Rin + Rsig Rout + R L

To maximize the amplifier’s gain, we want to eliminate the

coupling ratios by making them very close to one. This is Maximum gain in voltage amp: Rout  R L and
achieved when the amplifier has large input resistance and a Rin  Rsig . In the limit, a truly ideal voltage amp has
Rin → ∞ and Rout → 0.
small output resistance.
18 ece3410 lecture notes

EveryCircuit Demonstration 2 (Ideal Voltage Amplifier).

This demonstration implements the ideal voltage amplifier model from Figure 9 with Rsig , Rin , Rout and
R L all equal to 1 kΩ, and a voltage gain Av = 10 V/V. The simulation traces show an attenuation by
half at each signal port due to the voltage-divider couplings.

Exercise: Increase Rin to 10 kΩ and then 100 kΩ, and observe what happens to the amplitude of vin
compared to vsig for these values. Then do the same for R L . You should notice that the coupling
effects disappear when R L  Rout and Rin  Rsig . Verify that your observations match the value of the
loaded gain predicted by our analysis in this section.
 introduction 19

iin iout
The ideal linear current amplifier is very similar to the
voltage amplifier, except that we get current dividers instead of
voltage dividers at the input and output terminals. In a current vsig Rin Ai iin Rout load
divider, the opposite resistance appears in the numerator, so the
conditions for achieving maximum are reversed.
For current amplifiers, the most ideal gain is called the short-
circuit gain Ais , since we can eliminate the coupling ratios by Figure 10: Ideal linear current amplifier model at low
setting R L to zero, hence short-circuiting the output. The gain or mid-band frequencies.
expressions for a current amplifier are:

iOUT
short-circuit gain: Ais , = Ai
iIN
  
i Rsig Rout
loaded gain: AiL , OUT = Ai .
iIN Rin + Rsig Rout + R L
Maximum gain in current amp: Rout  R L and
To maximize the current amplifier’s gain, we want to elimi- Rin  Rsig . In the limit, a truly ideal current amp has
nate the coupling ratios by making them very close to one. This Rin → 0 and Rout → ∞.

is achieved when the amplifier has small input resistance and

a large output resistance, the opposite of what we found for
voltage amplifiers.

iin iout
 
Rsig
iIN = vSIG
Rin + Rsig
isig Rsig Rin Ai iin Rout RL 
Rout

iOUT = Ai iIN
Rout + R L

Figure 11: Coupling interactions in current amplifiers.

Resistive current dividers appear at the input and
output interfaces.
20 ece3410 lecture notes

The remaining amplifier types are mixtures of voltage and

current amplifiers. The transconductance amplifier takes Transconductance amplifiers are especially important
voltage input and delivers a current output. Then we see a since they are the basis of transistor device models.

voltage divider at the input interface and a current divider at

the output interface/

Rsig iout
+ 
Rin

vIN = vSIG
Rin + Rsig
vsig +
− vin Rin Gm vin Rout RL  
Rout
iOUT = Gm vIN
Rout + R L
−

Figure 12: Coupling interactions in transconductance

amplifiers. A resistive voltage divider appears at the
For the transconductance amplifier, the gain expressions are:
input interface and a current divider at the output
iOUT interface.
short-circuit gain: Gms , = Gm
vIN
  
i Rin Rout
loaded gain: GmL , OUT = Gm .
vIN Rin + Rsig Rout + R L
Maximum gain in transconductance amp: Rout  R L
To maximize the transconductance amplifier’s gain, we want and Rin  Rsig . In the limit, a truly ideal transconduc-
to eliminate the coupling ratios by making them very close tance amp has Rin → ∞ and Rout → ∞.

to one. This is achieved when the amplifier has large input

resistance and a large output resistance.
Lastly, The transresistance amplifier takes current input and
delivers a voltage output. Then we see a current divider at the
input interface and a voltage divider at the output interface/

iin Rout
+ 
Rsig

iIN = vSIG
+ Rin + Rsig
isig Rsig Rin Rm iin − vout RL 
RL

vOUT = Rm iIN
Rout + R L
−

Figure 13: Coupling interactions in transresistance

amplifiers. A resistive current divider appears at the
For the transresistance amplifier, the gain expressions are:
input interface and a voltage divider at the output
vOUT interface.
open-circuit gain: Rmo , = Rm
iIN
  
vOUT Rsig RL
loaded gain: RmL , = Rm .
iIN Rin + Rsig Rout + R L
Maximum gain in transresistance amp: Rout  R L
To maximize the transresistance amplifier’s gain, we want to and Rin  Rsig . In the limit, a truly ideal transconduc-
eliminate the coupling ratios by making them very close to one. tance amp has Rin → 0 and Rout → 0.

This is achieved when the amplifier has small input resistance

and a small output resistance, the opposite of what we found
for transconductance amplifiers.
 introduction 21

Real Amplifiers Ideal Linear Amplifier

Real amplifiers are affected by nonlinear transfer characteris- 100 Output

tics between the input and the output.
Input
The ideal transfer characteristic is a straight line, extend-
−10 10
ing from −∞ to +∞ with a constant slope. The gain of this
amplifier is the slope of its transfer characteristic: −100
Figure 14: DC transfer characteristic of an ideal
dv amplifier.
Gain , OUT .
dvIN

Real amplifiers do not exhibit such ideal behavior. A more real-

istic transfer characteristic is a curve that saturates at maximum
and minimum values of vOUT , with a non-constant slope in
between.

100 Output 100 Gain

Input Input
−15 −10 −5 5 10 15 −15 −10 −5 5 10 15

−100 −100

Figure 15: Non-linear transfer characteristic showing

non-constant slope. The amplifier saturates when the
Since the slope varies, the gain is non-constant. This introduces gain falls below 1 V/V.
distortion into the signal being amplified. Due to this nonlinear
behavior, we are unable to use linear circuit methods to analyze
the amplifier system. As a result, analysis and design can
become very complex tasks. To simplify our understanding of
nonlinear systems, we rely on the concepts of linearization and
small-signal analysis.
A linearized model is a direct application of the first-order
Taylor series approximation. For a non-linear function f ( x ), the
Taylor approximation is defined around an offset x0 as

∂ f 
f ( x ) ≈ f ( x0 ) + ( x − x0 ) .
∂x  x0
= f 0 + A ( x − x0 )

This approximation is only valid for small variations, i.e. when

| x − x0 | is small (the meaning of “small” here is fuzzy; the
variation is considered small enough if the approximation is
sufficiently accurate for our needs). The Taylor approximation
can be interpreted as zooming-in on the original function, such
that the zoomed portion is a nearly straight line:
22 ece3410 lecture notes

Real Non-Linear Amplifier Zoomed Non-Linear Amplifier

10
Output Output
100
5
Input Input
−15 −10 −5 5 10 15 −1 −0.5 0.5 1
−5
−100
−10
Figure 16: Zoomed transfer characteristic showing
approximately linear behavior for small signal
Small-signal equivalent circuit models variations.

The Taylor linearization reveals an extremely useful aspect of

linearized circuits: thanks to the principle of superposition, we
can separate the circuit’s behavior into two parts: the DC offset
or bias point x0 , f 0 and the small signal variation ( x − x0 ). In
the circuit context, the transfer characteristic shows the large-
signal relationship between two signals vIN and vOUT . We
VOUT Q Point,
refer to these as the total instantaneous signals, i.e. the precise Bias Point,
physical signal value at an instant in time. DC Offset
For non-linear circuits, it is often difficult to analyze the total VIN
instantaneous signal, so we split it into a superposition of two
parts:

DC offset – the central or average value of a signal; what you

would measure on an oscilloscope as the signal’s MEAN. We Figure 17: Offset point of a non-linear transfer
write DC offsets using all capital letters, as in VIN or VOUT. characteristic.

Small-signal – the amount by which the signal varies from the

offset; what you would measure on an oscilloscope set to AC
vOUT = VOUT + vout
Coupling. We write small-signal quantities in all-lowercase,
as in vin or vout .
Total Instantaneous Small Signal
Total instantaneous signal – the superposition of the offset and Signal DC part part
small signal; what you would measure on an oscilloscope
set to DC coupling. We write the total instantaneous signal
using lowercase letters with uppercase subscripts, as in vIN or
vOUT .
vout
The uppercase/lowercase notation is useful to keep track of
our separate analysis domains, but is not entirely perfect. For
example, we also use uppercase symbols to represent sinusoidal
amplitudes, which can sometimes create ambiguity. To help
distinguish these quantities, we will try and use calligraphic vin
font for sinusoidal amplitudes, as in VA .

Figure 18: Small-signal activity overlaid on the

nonlinear transfer characteristic.
 introduction 23

Procedure for small-signal analysis

When analyzing a linearized circuit, we often want to analyze
just the signals, without being distracted by their DC offsets.
We want to know, for example, the AC amplitude and phase
shift of signals at various points in a circuit. The principle of
superposition allows us to extract the small-signal behavior by
following these steps:

1. Solve the circuit’s DC operating point. In many cases we

may only need to find part of the DC solution in order to do
the next step.

2. Linearize the circuit by applying a Taylor approximation

centered at the DC operating point.

3. Replace any non-linear components with their linearized

equivalents.

4. Set all DC independent sources (both current and voltage)

to zero. Voltage sources become short-circuits, and current
sources become open-circuits. Note: do not modify any
time-varying or dependent sources.
24 ece3410 lecture notes

Example 3 (Linearization of a sensor).

A temperature sensor provides a change of 2mV per ◦ C, connected to a load of 10kΩ. The output
changes by 10mV when T is changed by 10◦C. What is the source resistance of the sensor?
The sensor model is linearized:

dvS  RS
vs = VS + ∆T +
dT  T0

where T0 is the reference temperature and ∆T is the variation vs

from that temperature. To consider only the variation in vOUT ,
we isolate the small signal portion: RL vOUT
 0
dvS 
∆T
+
vout = VS −
dT  T0

The problem statement tells us that −

 Figure 19: Linear temperature sensor model.
dvS 
= 2mV/◦C The DC offset VS is set to zero (i.e. shorted
dT  T0 out) for small-signal analysis.

It also tells us that vout = 10 mV, so we can solve for RS :

RS
RL +
vout = vs
R L + RS
RL
= (2 mV/◦C) (10 ◦C) vs RL vout
R L + RS
(2 mV/◦C) (10 ◦C) R L
→ RS = − RL −
vout
Figure 20: Small-signal equivalent tempera-
= 10 kΩ ture sensor model. The lower-case signals
vs and vout represent the variations in the
corresponding physical signals.
 introduction 25

Example 4 (Linearization of a thermistor model).

A thermistor is modeled by the Steinhart-Hart equation:

 
−B 1 1
T0 − T
R = R0 e

where R0 and T0 are reference measurements, T and

T0 are in Kelvin, and B is a device-specific parame- ·104
1.02
ter. For small temperature changes (e.g. changes in a Actual
room’s temperature), we can approximate this using a Linearized
linearized model centered around T0 : 1.01

R (Ω)
1
   
d − B T1 − T1
R ≈ R0 + ∆T

R0 e 0 
dT 
T =T
    0 
1
−B T − T 1 d 1 1 0.99
= R0 + ∆T R0 e

0 −B − 
dT T0 T 
T = T0
! 280 290 300 310 320
B
= R0 − ∆TR0 T (Kelvin)
T02
Figure 21: Linearized approximation of thermistor
resistance for temperatures near 300 K
So if T0 = 300 K , R0 = 10 kΩ and B = 50 K−1 , then for
temperatures near 300 K we have

R ≈ 10 kΩ − ∆T × 5.5 Ω

So we should see a difference of about 5.5 Ω/K. To

check the accuracy of this approximation, we can compare the actual (nonlinear) equation to the
linearized result, as shown in Figure 21. Note that the accuracy is best for very small ∆T, and the
error begins to grow as |∆T | increases.
26 ece3410 lecture notes

Equivalent small-signal resistance and impedance

In example 3 we determined the series internal resistance of a

temperature sensor. Since this resistance affected the sensor’s
incremental or differential behavior, we can refer to it as a
small-signal resistance. By definition, a small-signal resistance
is the ratio of the small change in current in a branch that
results from a small change in voltage across the corresponding
terminals. This can be stated mathematically in a few different
ways:

∂v X 
large-signal definition: r X =
∂i X DC
vx
small-signal definition: =
ix

From this definition we can define an analysis procedure for

determining a circuit’s small-signal equivalent resistance:

1. Linearize the circuit and obtain the small-signal equivalent

model.

2. Set any independent signal sources to zero.

3. Insert a test voltage source v x across the terminals of interest.

4. Solve the current i x that flows through the test source v x .

vx
5. The equivalent resistance is r x = ix .

Note that this procedure only works for small-signal models.

Do not use the large-signal ratio v X /i X !

Frequency Response of Amplifiers

Every circuit has a frequency response. At the very least, there

is a hidden capacitance between every pair of nodes, called the
parasitic capacitance. These capacitances introduce multiple
poles and zeros into the circuit’s frequency response.

Rsig Cf
Rout
+ +
+
vsig +
− vin Cin Rin Av vin − Cout vout RL

− −

Figure 22: An example amplifier model showing

parasitic capacitances.
 introduction 27

The general “ZPK” form of the transfer response is

∏k (1 − s/ωzk )
H (s) = K
∏m 1 − s/ω pm

where ωzk are the zeros, indexed by k and ω pm are the poles, + +
indexed by m. In this course we will concern ourselves almost
VY (s) vy
exclusively with “simple” poles and zeros in the left half-plane. vX H (s) = VX (s)
In other words, we’ll assume that all poles and zeros are real-
valued (not complex or imaginary), are all well separated (they − −
do not overlap in value), and are negative valued. If these
conditions are satisfied, then we can use a simplified “stick- Figure 23: General “black-box” model of a linearized
amplifier circuit. Zeros are roots of s in the numera-
figure” method to produce approximate magnitude and phase tor and poles are roots in the denominator.
response diagrams, which are called Bode plots.
28 ece3410 lecture notes

Low-pass systems
For every pole ω pm , the magnitude decreases by 20 dB per
decade at frequencies above the pole. The phase response
decreases by 90° between the frequencies 0.1ω pm and 10ω pm ,
and crosses −45° at ω pm .

100
ω p0
Gain Magnitude (dB)

-20dB/decade
50

100 101 102 103 104 105 106 107 108 109

0
45◦ Phase Loss
Phase (°)

−50

−100
100 101 102 103 104 105 106 107 108 109
Frequency

Figure 24: Bode plot of a low-pass system with

transfer function
1
H (s) = K ,
1 + s/ω p0
with a single pole at ω p0 and no zeros, and with gain
constant K = 104 corresponding to 80 dB. In this
example the pole is at 100 rad/s. The phase response
begins to decrease at 10 rad/s, loses 45° per decade,
and the phase change concludes at 1 × 103 rad/s.
 introduction 29

High-pass systems
For every zero ωzk , the transfer function increases by 20 dB
per decade at frequencies above the pole. The phase response
increases by 90° between the frequencies 0.1ω pm and 10ω pm ,
and crosses −45° at ω pm .
In high-pass systems, there is usually a zero at the origin.
In that case, there is no phase response associated with the
zero (it occurs at infinitely low frequency on the logarithmic
scale), and the zero must be canceled by one or more poles at
higher frequencies. On the Bode plot, the magnitude response
reaches its maximum value and becomes constant after the first
pole, ω p0 . For frequencies below ω p0 , the magnitude response
decreases by 20 dB per decade.

100
ω p0
+20dB/decade
Gain Magnitude (dB)

50

100 101 102 103 104 105 106 107 108 109

0
45◦ Phase Loss
Phase (°)

−50

−100
100 101 102 103 104 105 106 107 108 109
Frequency

Figure 25: Bode plot of a high-pass system with

transfer function
s
H (s) = K ,
1 + s/ω p0
which has a single zero at the origin, and a single
pole at 100 rad/s. The gain constant is K = 104 ,
corresponding to 80 dB. The phase response is due to
the pole; the zero contributes no phase change since
it occurs at the origin.
30 ece3410 lecture notes

Band-pass systems

Many circuit’s exhibit a mix of high-pass and low-pass char-

acteristics. We will especially see this in circuits that use ca-
pacitive coupling to separate the DC offset from an AC small
signal. In a bandpass system, the transfer function’s magnitude
is highest for middle frequencies between two pole frequencies
ω L and ω H . This zone is referred to as the circuit’s mid-band or
pass band.
A typical band-pass amplifier model is shown below. The
signal source has a DC offset voltage VSIG , which is usually
undesirable since it will be amplifier along with the signal. In
order to amplify just the signal, the offset is rejected by using
a coupling capacitor CC1 to create a high-pass response at the
input. The amplifier’s output similarly has an undesired DC
offset VOUT , which is rejected using the coupling capacitor CC2 .

Rsig CC1 Rout

+ +
+
vsig Av vin −

vin Rin Cout vout RL

+ +
VSIG − VOUT −

− −

Figure 26: Bandpass amplifier model where coupling

capacitors CC1 and CC2 are used to reject or replace
To analyze the bandpass circuit, we replace capacitors by the DC offsets VSIG and VOUT .
their Laplace domain equivalent impedances. We then have
 
sCC1 Rin
vin = vsig
1 + sCC1 ( Rin + Rsig )
 
RL
vout = Av vin
R L + Rout + sCout Rout R L
  
sCC1 Rin RL
= vsig Av
1 + sCC1 ( Rin + Rsig ) R L + Rout + sCout Rout R L

The transfer function is

vout
H (s) =
vsig
  
RL sCC1 Rin
= Av
R L + Rout (1 + sCC1 ( Rin + Rsig )) (1 + sCout ( R L k Rout ))

In this case there is a zero at the origin and two poles located at
 introduction 31

two frequencies:

1
ω p0 =
CC1 ( Rin + Rsig )
1
ω p1 =
Cout ( R L k Rout )

Under ideal conditions, the voltage amplifier should have

very high Rout which places ω p0 at a low frequency, and it
should have a very low Rout which places ω p0 at a high fre-
quency. Since there is a zero at the origin, the magnitude rises
by 20 dB per decade for frequencies below ω p0 , and then be-
comes flat between ω p0 and ω p1 . For frequencies higher than
ω p1 the magnitude falls by 20 dB per decade.

100
ω p0 ω p1
Gain Magnitude (dB)

+20dB/decade -20dB/decade

50
midband

100 101 102 103 104 105 106 107 108 109
0
45◦ Phase Loss
→ 90◦ Phase Loss
−50
Phase (°)

−100
135◦ Phase Loss

−150
→ 180◦ Phase Loss

100 101 102 103 104 105 106 107 108 109
Frequency

Figure 27: Bode plot of a band-pass system with a

single zero at the origin, and two poles at 100 rad/s
and 1 × 106 rad/s . The gain constant is K = 104 ,
corresponding to 80 dB. The phase response is
due to the two poles, approaching −180° at higher
frequencies.
32 ece3410 lecture notes

EveryCircuit Demonstration 4 (Ideal Band-Pass Amplifier Model).

This demonstration shows an implementation of the band-pass model from Figure 26. Examine this
circuit and perform both AC simulations (frequency mode) and transient simulations (time mode).
Try increasing and decreasing both CC1 and Cout by 10× (for a total of four different cases), and
observe how the pole frequencies change. Verify that the observations match the predictions from our
analysis in this section.

EveryCircuit Demonstration 6 (Capacitive Coupling).

This capacitive coupling demonstration shows how we can remove a signal’s DC offset and replace
it with a different offset. The circuit works through superposition of high-pass and low-pass signal
paths. The input AC signal has an offset of 10 V and a zero-to-peak amplitude of 1 V. At the out-
put, the original offset is rejected by the coupling capacitor. A new offset of 1 V is provided by an
independent DC voltage source, and is superimposed through the 1 kΩ resistor on the output side.
 introduction 33

Harmonic distortion
40
When a pure sinusoid is input to perfectly linear amplifier, the

VS (s) (dB)
output is expected to be a pure sinusoid, and its magnitude
spectrum should have a single impulse. Real amplifiers are not
20
perfectly linear though, so the output is usually not a perfect
sinusoid.
As a result, unexpected features called harmonics appear
0
in the output magnitude spectrum. Harmonics are spuri- 103 104
ous impulses that appear at integer multiples of the original ω (rad/sec)
fundamental signal frequency. So if the input sinusoid has a Figure 28: Harmonic “spurs” appear at integer mul-
fundamental frequency component at f 0 , the distorted output tiples of the fundamental frequency, and represent
distortion.
sinusoid has harmonic components spaced at integer multiples
fk = k f0 .

Aliasing
Since the harmonic components can extend to very high fre-
quencies, they may contribute to aliasing effects in a digital
oscilliscope’s FFT display. Aliasing occurs when a signal vio-
lates the Shannon-Nyqvist Sampling Theorem, which states that
the sampling rate must be at least twice the highest frequency
present in the signal. On a typical digital oscilloscope, we must
be aware of the following considerations:

• The Sec/Div knob sets the sampling rate f S .

• If the signal frequency f > f S /2, then the scope will show an
image at f − f S /2. So if you increase f beyond f S /2, the signal
peak on the FFT will appear to move backwards.

• When many high-frequency harmonics are present, their

images will overlap again and again over the FFT display,
creating an erroneous and confusing plot.

• Higher frequency harmonics can be suppressed by activating

an internal bandwidth limit on the oscilloscope’s input
channel.

• When zooming in to see more detail on the FFT display, do

not use the Sec/Div knob. Instead, look for a digital zoom
setting in the FFT menu.
Operational Amplifier Circuits

v−
− −
Amplifiers with finite open-loop gain
vid vOUT

Operational amplifiers (op amps) are nearly ideal differential v+

+ +
amplifiers. This means that their output is proportional to the
difference of their inputs, and is governed by the characteristic
Figure 29: An op amp has two input terminals and
equation one output. The input signal is differential, with
vid , v+ − v− . The output is single-ended, with
vOUT = A v+ − v− ,


vOUT = Avid .

where gain is the amplifier’s voltage gain. Since op amps are

nearly ideal, we expect them to have very high Rin and very low
Rout . Furthermore, there should be zero current passing into the
op amp’s input terminals.
Op amps are almost always used in negative feedback con-
figurations where there is some path for current to flow be-
tween the amplifier’s output and its inverting input terminal.
To analyze realistic op amp circuits with feedback, we need to
introduce some more refined notation:

G ? = The desired or ideal or nominal closed-loop gain

⇒ Gi? = for an inverting configuration
?
⇒ Gni = for a non-inverting configuration
G = The actual achieved closed-loop gain.
A = The op amp’s finite open-loop gain, in volts per volt.
e = The error coefficient
⇒ G = G? e

Notice that the concept of “open-loop gain” is distinct from

the “open circuit gain,” but in this chapter we will consider
them to be approximately the same. The open-loop gain refers
to the amplifier’s gain without feedback, whereas the open-circuit
gain refers to the gain without a load. Since an op amp is ex-
pected to have a very low Rout , we will assume that loading
effects are negligible.
36 ece3410 lecture notes

Inverting amplifier

The standard inverting configuration includes an input resistor

R1 and a feedback resistor R2 . Whenever an op amp is con-
R2
nected in a negative feedback configuration, it will exhibit a
virtual short effect that forces v− to be approximately equal to i2
v+ . The virtual short occurs because the op amp’s open-loop
R1
gain tends to be very large. We can prove the virtual short effect v−
vIN −
under the most ideal condition: that the op amp’s open loop i1
vOUT
v+
+
gain is so large it effectively approaches infinity.
Figure 30: Inverting op amp configuration. No
current flows into the op amp’s terminals, so i2 = i1 .
Proof. First suppose v− > v+ . Then we expect to see a large Summary: This configuration’s characteristics are:

negative voltage at vOUT . By superposition, R2

G? = −
    R1
R2 R1 G = eG ?
v− = vIN + vOUT .
R1 + R2 R1 + R2 A
e= R2
1+A+ R1
But if the op amp’s gain A → ∞, then vOUT → −∞ and
consequently v− → −∞. This creates a contradiction, since
we supposed that v− > v+ . On the other hand, if v− < v+ ,
then vOUT → ∞ and consequently v− → ∞, which is another
contradiction. The only non-contradictory scenario is if v− =
v+ .

Thanks to the virtual short effect, we can say that ideally

v− = 0, so the current passing through R1 is

vIN
i1 = .
R1

Since there is no current passing into the op amp’s input termi-

nals, the entire current i1 must pass through R2 . Then i2 = i1
and vOUT = −i1 R2 = −vIN ( R2 /R1 ). This result is based on The closed-loop gain is the ratio vOUT /vIN when a
ideal assumptions, so we can say that the ideal closed-loop negative feedback connection is present.

gain is
R2
Gi? = − .
R1

The ideal analysis assumes that the op amp’s open-loop gain

goes to infinity. We can perform a more realistic analysis by
accounting for the op amp’s finite open-loop gain. In this case,
the op amp has an inexact virtual short, so we should not rely
on it in our analysis. Instead, we can solve for the closed-loop
gain beginning from the op amp’s characteristic equation:
 operational amplifier circuits 37

vout = A v+ − v−

⇒ vout = A 0 − v−

vout
⇒ v− = −
A
vout − v−
i2 = i1 =
R2
−
v − vin
=
R1

Then we have

    v
1 out

R1 vout 1 + = R2 − − vin
A A
 
1 R2 R2
⇒ vout 1 + + = − vin
A R1 A R1
  
vout R2 A
⇒ Gi = = −
vin R1 A + 1 + R2 /R1

Notice that, in this form, we can express the circuit’s actual

gain as the product of two terms:

Gi = Gi? × e
R2
Gi? = −
R1
A
e=
A + 1 + R2 /R1

The first term, G ? , is the gain expected if we used an ideal op

amp. The second term, e, is an error coefficient that quantifies
the effect of using an op amp with finite open-loop gain A.

EveryCircuit Demonstration 8 (Inverting configuration).

This circuit implements an inverting configuration where the op amp’s open-loop gain is A = 10 V/V
(i.e. 20 dB). The resistor values are R1 = 1 kΩ and R1 = 2 kΩ, so we expect an ideal closed-loop gain
of G ? = −2 V/V. The input signal has a zero-to-peak amplitude of 1 V, so the output amplitude
should be 2 V. Simulate this circuit and observe the output amplitude. It should be 1.54 V. To verify
that this matches the prediction from our theory, solve for e and G using the methods described in
this section. Then, try increasing the op amp’s open-loop gain to 20 V/V and repeat your calculations
to verify that the theory holds up.
38 ece3410 lecture notes

Non-inverting amplifier R2

The non-inverting configuration is similar to the inverting

configuration, except the input signal is applied at v+ . Under R1
i2
v−
ideal assumptions, we may appeal to the virtual short so that −
vOUT
v− = vIN , and i2 = i1 . Then i1 v+
+

+
vIN − vIN
i1 = −
R1
vOUT = vIN − i1 R2
Figure 31: Non-inverting amplifier configuration.
The “virtual short” effect causes the op-amp’s
R1 input terminals to have nearly equal potentials, so
= vIN + vIN v− ≈ v+ .
R2 Summary: This configuration’s characteristics are:
? R1
⇒ Gni = 1+
R2 R2
G? = 1 +
R1

To obtain the more realistic gain accounting for finite open- G = eG ?

A
loop gain, we begin from the characteristic equation as before: e= R2
1+A+ R1

vout = A vin − v−

vout
⇒ v− = vin −
A
vout − v−
i2 = i1 =
R2
v−
=
R1

Rearranging we get:

R1 vout − v− = R2 v −


 vout   vout 
⇒ R1 vout − vin + = R2 vin −
 A  A
1 R2
⇒ vout 1 + (1 + R2 /R1 ) = vin 1 +
A R1
G?
 
?
⇒ vout 1 + ni = vin Gni
A
 ? 
A + Gni ?
⇒ vout = vin Gni
A
 
vout ? A
⇒G= = Gni ?
vin A + Gni
 
? A
⇒ G = Gni
A + 1 + R2 /R1
 operational amplifier circuits 39

Once again we may express the result in two parts, G ? and e:

? R2
Gni = 1+
R1
A
e=
A + 1 + R2 /R1
?
Gni = Gni ×e

Notice that the error coefficient, e, is the same for both the
inverting and non-inverting configurations.

Generalized Result
Since the error coefficient is the same in both configurations, the
closed-loop gain can be generally expressed as

G = G? × e
 
? A
=G
A + 1 + R2 /R1

EveryCircuit Demonstration 10 (Non-inverting configuration).

Make a copy of the inverting configuration circuit and modify it to implement a non-inverting config-
uration. Keep the parameters from the original exampe, R1 = 1 kΩ, R2 = 2 kΩ and A = 10 V/V, and
set the input signal amplitude to 1 V. For these parameters, calculate the expected values of G ? , e and
G. Simulate the circuit and verify that the output amplitude agrees with your calculations.
40 ece3410 lecture notes

Voltage Follower
−
The voltage follower represents a slightly different case, since
vOUT
there are no resistors. vIN +
In this configuration, we have the following device equations:
Figure 32: Voltage follower configuration. Due to the
vOUT = A v+ − v−


“virtual short” effect, vOUT ≈ vIN .
Summary: This configuration’s characteristics are:
= A (vIN − vOUT )
v A
⇒ G = OUT = G? = 1
vIN A+1
G = eG ?
In this case, the gain can be expressed as A
e=
1+A
Gv? f = 1
A
ev f =
A+1
Gv f = Gv? f × ev f

EveryCircuit Demonstration 12 (Voltage follower configuration).

Make a copy of the inverting configuration circuit and modify it to implement a voltage follower
configuration. Keep the same op amp gain from the original example, A = 10 V/V, and set the input
signal amplitude to 1 V. Calculate the expected values of G ? , e and G. Simulate the circuit and verify
that the output amplitude agrees with your calculations.
 operational amplifier circuits 41

Difference amplifiers

To make an amplifier with fully-differential input, we can com-

bine inverting and non-inverting configurations. This gives us
two gains: R2

? R2
Gni = 1+
R1
− −
R2
Gi? = − vIN R1 vOUT
R1 + +
R3

To achieve proper differential operation, the inverting and R4

non-inverting gains must be balanced, i.e. Gni = | Gi |. In their
usual configurations, this is not the case. In order to balance the
inverting and non-inverting gains, we insert the voltage divider Figure 33: Difference amplifier configuration for
R3 , R4 , so that: amplifying a differential signal. Inverting and non-
inverting configurations are superimposed. The
resistor-divider R3 − − R4 is used to ensure the same
gain for the inverting and non-inverting signal paths.
  
? R2 R4
Gni → 1+
R1 R3 + R4
R2
=
(condition for balance)
R1
  
R4 R2 R
⇒ 1+ = 2
R3 + R4 R1 R1

Then solving for R4 /R3 we find that

  
R3 R2 R1
=
R3 + R4 R1 R2 + R1
R2
=
R1 + R2

Then we can invert both sides:

R3 R
1+ = 1+ 1
R4 R2
R3 R1
⇒ =
R4 R2

So the resistor ratios need to be matched.

42 ece3410 lecture notes

EveryCircuit Demonstration 14 (Difference amplifier (differential mode)).

This circuit implements a difference amplifier with

both differential and common-mode input circuits. R2
In the initial setup, you should see that the two dif-
ferential input signals, vip and vin , have zero-to-peak
amplitudes of 1 V and a frequency of 1 kHz. One of
the sources, vip , has a phase of 180° in order to have −
opposite polarity from vin . The common-mode signal R1 vOUT
+
vCM is shared by both of the input signals, i.e. they vin R3
share this signal component; it is common to both vip
R4
of them. In the example design, vCM has a small
amplitude of 100 mV and a frequency of 300 Hz. We
expect the common-mode signal to be canceled out, vCM
so it should not appear at all in the output signal.
To verify this, increase the amplitude of vCM to 5 V,
so it will be clearly visible. Notice that the output
waveform doesn’t change.
Next, modify the value of R4 by increasing it to 4 kΩ. Keep the amplitude of vCM at 5 V, and let the
simulation run for a while. You should observe that a 300 Hz fluctuation is superimposed onto the
output signal. The common-mode is no longer canceled.

The importance of matching

If the inverting and non-inverting gains are imbalanced, then
the common-mode signal is not perfectly cancelled. To see this,
we now consider the actual gains Gi and Gni , which may differ
due to imprecision in actual resistor values:
1 +
vIN + = v + vCM
2 sig
1 −
vIN − = vsig + vCM
2
1
⇒ vOUT = ( Gni + | Gi |) vsig + ( Gni − | Gi |) vCM
2
The latter part of this result is called the common-mode gain,
ACM = ( Gni − | Gi |). The Common Mode Rejection Ratio
(CMRR) is the ratio of the effective differential gain, Ad =
1
2 ( Gni + | Gi |), to ACM :

Ad
CMRR =
ACM
This figure is often specified in dB. Ideally it should be infinite.
 operational amplifier circuits 43

Input resistance in the difference amplifier

One source of mismatch in the difference amplifier is that the
input resistances are unmatched between the two input legs. To
evaluate the input resistance, we apply the method described in
?? separately for each leg of the input signal.
At the inverting input, we find that the input resistance is
equal to R1 , since vip = 0, so that v+ = 0 and, due to the virtual
short, v− = 0. At the non-inverting input, the equivalent resis-
tance is equal to R3 + R4 . If the input signals have a significant
series resistance, we will see signal attenuation due to resistive
coupling effects, which modifies the gain. Let us assume that
both vip and vin are both connected in series with a resistance
equal to Rsig . Then this resistance is effectively added in series
with R1 and R3 , so that after accounting for this loading effect
the gain becomes
R2
GL? = .
R1 + Rsig
In other words  
R1
GL? =G ?
.
R1 + Rsig
If we repeat this analysis on the non-inverting signal path,
we will find the same ratio. Finally, accounting for finite gain
together with the loading effect:
 
? R1
GL = G e,
R1 + Rsig

where e is now modified due to the presence of Rsig :

A
e= R2
.
1+ A+ R1 + Rsig
44 ece3410 lecture notes

Instrumentation amplifiers

vi1 + R3 R4
vx

Advantages over difference amplifiers: − ix

• Very high input resistance (Rin → ∞).

R2

• Gain controlled by a single resistor (2R1 ). −

2R1 i x − iy vout
• CMRR increased by the gain of the pre-amp stage. +

R20
Disadvantages:
• Needs three op amps.
− iy
R3 R4
• Higher power consumption. vy
vi2 +

Instrumentation amplifier A D analysis. Figure 34: Instrumentation amplifier configuration

for amplifying differential signals. Since both inputs
are connected to the op amps’ non-inverting termi-
We have three amplifiers. The first two are non-inverting con-
nals, they should both have high input resistance
figurations. Together they are described as a fully-differential and matched electrical characteristics. Compared
pre-amplifier. The third op amp is configured as a difference am- to difference amplifiers, this configuration is less
sensitive to resistor mismatch and has improved
plifier. The differential gain may be analyzed as a superposition CMRR.
of two non-inverting configurations:

 
R2 R
v x = vi1 1 + − vi2 2
R1 R1
 
R2 R
vy = vi12 1 + − vi1 2
R1 R1
The overall gain of the pre-amplifier stage is then
v x − vy
A D1 =
vi1 − vi2
2R
= 1+ 2
2R1
R
= 1+ 2.
R1
The difference amplifier contributes a gain of R4 /R3 , so the
total differential gain is
  
R2 R4
AD = 1 + .
R1 R3

Instrumentation amplifier ACM analysis.

We expect to obtain a net improvement in CMRR through
this configuration, compared to the difference amplifier. In
fact, the instrumentation amplifier achieves the following two
advantages:
 operational amplifier circuits 45

• Eliminates sensitivity to R1 in the non-inverting configura-

tions by sharing R1 between the two circuits.

• Eliminates sensitivity to mismatch in R2 .

To analyze the Common-Mode case, we set the two differen-

tial inputs equal: vi1 = vi2 = vicm . Then, due to the virtual short
effect, the op amp’s inverting terminals are also equal to vicm .
Therefore the voltage drop across R1 is zero, so that

i x − iy = 0
⇒ v x = vy

Note that this result does not depend on the matching

between R2 and R20 . We may conclude that the pre-amplifier’s
common-mode gain is

ACM1 = 0V/V.

This would mean that the instrumentation amplifier has a

theoretically infinite CMRR. In practice, the op amps them-
selves will contribute second order imperfections (“second order”
means they contribute smaller effects than resistor mismatch),
resulting in some residual imbalance and a finite CMRR.
46 ece3410 lecture notes

Non-Ideal Op Amp Characteristics

We have already discussed finite open-loop gain, finite input

resistance and common-mode gain as non-ideal features of op
amp circuits. Now we will examine two additional features:

• Input bias current

• Offset voltage

Input Bias Current

Every op amp has a small but non-zero bias current flowing
into its input terminals; a typical value might be 10 µA, but this
can vary across a wide range for different products. The bias
current is typically a fixed current that can be modeled as a DC
current source.

Example 5 (Bias current in inverting configuration).

In this example we analyze the effect of bias current on an inverting configuration.

The theorem of superposition allows us to set vin = 0 to
analyze the contribution of Ibias . In this case, we see that R2

v− = 0 (virtual short) ⇒ vout = Ibias R2

By superposition, we can add in the contribution from vIN −

R1 v− vOUT
vin , resulting in Ibias +
 
R2
vout = vin − + R2 Ibias .
R1

Based on this example, we can see that the effect of Ibias Ibias
is to introduce a DC offset voltage on vout . This places Figure 35: Inverting configuration showing bias-
current sources.
a limitation on the size of R2 that can be used. Suppose,
for instance, that we have
Ibias = 10µA R2 = 1MΩ VR = 5V
and the op amp’s power rails are at ±VR . In this case, the bias current induces an output offset
voltage equal to
Ibias R2 = 10V,

which is greater than the rail of the op amp. As a result, the op amp will simply saturate.
 operational amplifier circuits 47

Example 6 (Maximum resistance due to Ibias ).

Given Ibias , an input signal vIN and a desired closed-loop gain G, how can we determine the maxi-
mum allowable value for R2 ? Suppose vmax is the maximum value of vIN , and vmin is the minimum
(note that vmin can be a negative voltage). Then our circuit must satisfy

VR + Gvmin
Ibias R2 + Gvmin < VR ⇒ R2 < .
Ibias

So returning to our example where Ibias = 10 µA and VR = 5 V, and let G = −10 V/V and vmin =
−0.1 V, we find
(5 V) + (1 V)
R2 < = 600 kΩ.
10 µA
48 ece3410 lecture notes

Offset Voltage

Every op amp has a DC offset voltage so that its equation is

vout = A v+ − v− + Vofs .

When used in high-gain circuits, this offset voltage gets ampli-

fied, which may lead to erroneous signal processing in some
circuits.
Vofs is random, usually varying in the range ±10mV. Vofs can
also change slowly over time, making it difficult to zero it out
by design.

Example 7 (Inverting configuration with offset voltage).

R2

R1
vin −
v− vout
+

Vofs

−
+
Suppose an inverting op amp configuration
Figure 36: Inverting configuration showing input
has supply rails equal to +5V and −5V, and offset voltage source.
is configured to have a closed loop gain Effect of Vofs
G = − R2 /R1 = −100V/V. The input signal
is a sinusoid with peak-to-peak amplitude 5 ∗
vout
Output Voltage [V]

45mV, and the op amp has an offset voltage vout

Vofs = 10mV. Draw the output waveform.

Answer: the output amplitude is 4.5V, but 0

since the offset voltage is also amplified,
the output will contain a DC offset equal to
1.01V, hence the output waveform is −5
0 5 10
vout = 1.01 + 4.5 sin (2π f t) .
Time [s]
This will result in clipping of the waveform. Figure 37: Waveform saturation caused by unde-
sired amplification of the op amp’s input offset
voltage.
 operational amplifier circuits 49

EveryCircuit Demonstration 16 (Non-inverting circuit with bias and offset).

This circuit implements models of both Ibias and VOFS in a non-inverting op amp configuration. Since
the EveryCircuit op amp model is very ideal, a slight circuit trick is used to model the bias current by
steering it into ground instead of into the op amp terminal. This trick doesn’t change anything at all
about the circuit’s behavior. The model uses typical values of 10 µA and −10 mV for the bias current
and offset voltage, respectively.
We see that the output waveform has a significant DC offset due to the bias and offset effects, and
part of the waveform is saturated. To get some experience with these effects, you can experiment
with larger and smaller values of each, and with positive and negative values of VOFS . Occasionally
the simulation will halt and complain that it can’t find a solution. Usually in these cases you can just
restart the simulation and will proceed without any problems.
Design question: how can the circuit be modified to minimize the undesirable offset and avoid
saturating the output waveform?
50 ece3410 lecture notes

Frequency Response of Op Amps

General-purpose op amps are said to be internally compen-

sated devices, meaning they are deliberately designed to have
a single-pole frequency response with a very low cutoff fre-
quency:
A0
A (s) =
1 + s/ωc
where

ωc = The low cutoff frequency

A0 = The DC open-loop gain, in V/V

The frequency response looks like this:

100
Gain Magnitude (dB)

ωc

50

ωt
0
100 101 102 103 104 105 106 107 108
0

−50
Phase (°)

−100

−150 PM

100 101 102 103 104 105 106 107 108

Figure 38: Standard op amp frequency response. In

The phase response loses 45° about the dominant pole ωc . this example, ωc = 100 rad/s, ωt = 1 × 106 rad/s,
and Av0 = 80 dB. In real op amp products these
There are typically additional poles at frequencies above ωt , parameters can vary significantly for different
which can cause additional phase loss just prior to ωt . The products. For a given product, ωt typically shows
low part-to-part variation and is a useful figure-of-
Phase Margin (PM) measures how much phase is lost at ωt . merit.
Specifically,

PM = 180° + ∠ A ( jωt )

(note that ∠ A ( jωt ) is negative).

For our (introductory) purposes, we will assume that PM =
90°.
 operational amplifier circuits 51

Unity-Gain Frequency
A typical op amp has a a very large DC open-loop gain, often
greater than 80 dB or 10 000 V/V. Then the magnitude response
can be approximated as
s
A20
| A (ω )| =
1 + ω 2 /ωc2
| A0 | ω c
≈
ω

The unity-gain frequency ωt is where the gain magnitude is

equal to unity, i.e. 1 V/V:
| A0 |
1 = ωc
ωt
⇒ ω t = ω c | A0 | Note | A0 | is in V/V

Because of this result, the unity-gain frequency is often referred

to as the Gain-Bandwidth Product (GBP). We can also write the
transfer function in terms of ωt as follows:
A0
A (s) =
1 + s | A0 | /ωt

Closed-Loop Frequency Response

Consider the inverting configuration using an op amp with a
one-pole response:
  
R2 A (s)
ACL (s) = −
R1 A (s) + 1 + R2 /R1
A 0
!
1+s/ωc
⇒ ACL (s) = G ? A0
1+s/ωc + 1 − G?
 
A0
⇒ ACL (s) = G ?
A0 + 1 − G + s (1 − G ? ) /ωc
?
 
A0
≈ G? since A0  1 − G ?
A0 + s (1 − G ? ) /ωc
 
1
= G?
1 + s (1 − G ? ) /ωt
We can re-write this as a single-pole transfer function with pole

ωCL = ωt / (1 − G ? )
= ωt / (1 + R2 /R1 ) .

This result introduces the universal Gain-Bandwidth Trade-

off. By using feedback, we can convert between bandwidth and
52 ece3410 lecture notes

closed-loop gain according to an approximate one-to-one ratio.

Note that for a given op amp, all configurations have the same
unity-gain frequency. Hence we consider ωt to be the universal
parameter of an op amp’s frequency response.
The closed-loop frequency response looks like this:

100
Gain Magnitude (dB)

ωc

50

ωCL
ωt
0
100 101 102 103 104 105 106 107 108

Figure 39: Closed-loop magnitude response (in

red) for an op-amp feedback configuration. The
open-loop response is also shown (in blue). For fre-
quencies greater than ωCL , the closed-loop response
approximately matches the open-loop response.

Example 8 (Closed-loop frequency response, low-gain).

Consider the following parameters:

ωt = 10MHz
R2 /R1 = 10

What are the closed-loop DC gain, the 3dB cutoff frequency, and the unity-gain frequency for these
parameters?

V
ACL = −10
V
ωt = 10MHz
ωc = 909kHz
 operational amplifier circuits 53

Example 9 (Closed-loop frequency response, high-gain).

Consider the following parameters:

ωt = 10MHz
R2 /R1 = 100

What are the closed-loop DC gain, the 3dB cutoff frequency, and the unity-gain frequency for these
parameters?

V
ACL = −100
V
ωt = 10MHz
ωc = 99kHz

Notice that as the desired gain G grows to be very large, the cutoff frequency approximates to ωt /G.

EveryCircuit Demonstration 18 (Closed-loop frequency response).

This circuit models an op amp with a single-pole transfer function connected in a non-inverting
configuration. Since EveryCircuit’s built-in op amp model is basically ideal, we have to insert extra
components to introduce a pole at the op amp’s output node. This is accomplished using an RC
low-pass network followed by a voltage buffer comprised of a dependent voltage source with a gain
of 1 V/V.
Perform a frequency simulation of the closed-loop system and observe the major parameters: the
DC gain ACL (in dB), the 3 dB cutoff frequency ωc , and the unity-gain frequency ωt . Next, increase
the value of R2 by 10× and then 100×, and observe how it changes ACL and ωc . Convert ACL to
V/V in order to test the predictions from the theory presented in this section. Verify that ωt remains
constant and is approximately equal to ACL ωc .
54 ece3410 lecture notes

Slewing

Slewing is very different from ordinary transfer-function based A signal affected by slewing
0 , i.e.
behavior. Slewing can be thought of as saturation of vout
a second-order saturation effect. As such, it is fundamentally 1

non-linear and introduces harmonic distortion into the signal.

vout
SR = max vout given in V/µs. 0
dt
Slewing tends to turn the output signal into a triangle wave.
If the op amp’s input signal is a pure sinusoid, then we can
−1
determine if the output will be affected by slewing:
0 2 4 6 8 10
∗ Time
vout = | ACL | VA sin (2π f t)
Figure 40: Slew-rate distortion in an op amp circuit.
d ∗
⇒ v = 2π f | ACL | VA cos (2π f t)
dt out
where VA is the input signal amplitude. This tells us that slew-
ing may occur if VA is large, or if the frequency f is large, or if
the closed-loop gain | ACL | is large. The maximum rate of signal
change must be less than the slew-rate:

2π f | ACL | VA ≤ SR

Example 10.

Slew-rate limiting Suppose an amplifier has the following characteristics:

SR = 1V/µs
ACL = 2 V/V
f = 100kHz

What is the maximum input amplitude VA which can guarantee no slewing?

SR
VA max =
2π f | ACL |
= 0.796V.

Clearly the slew rate can present real limitations for a circuit.

Although slewing distortion occurs commonly in op amp

circuits, there is no easy way to model it in simple simulators
like EveryCircuit. To get an accurate prediction of slew-rate
 operational amplifier circuits 55

limiting, we need to use a more advanced simulator like SPICE.

This is one of the first instances where we can see the need for
sophisticated engineering software.
56 ece3410 lecture notes

Full Power Bandwidth (FPBW)

The FPBW is the maximum frequency at which an op amp

can deliver its full-swing output signal (i.e. rail-to-rail output
amplitude). If the op amp has rails at ±VR , then the maximum
output amplitude is VO = VR . Then

SR
FPBW =
2πVR

If the op amp is single-supply, then the maximum amplitude

is VR /2, so

SR
FPBW =
πVR

The circuit will process any frequency less than the FPBW
distortion-free. For higher frequencies, you may begin to see
spurious harmonics in the output spectrum.
Once the FPBW is known, the slewing limit can be predicted
as follows:
FPBW
VO max = VR
f

Hence if you know the FPBW and the rail voltage, you can
estimate the maximum allowable amplitude at a given high
frequency.
 operational amplifier circuits 57

Z2
Op Amp Integrators and Differentiators

If the circuit is analyzed in the Laplace domain, we can con- Z1

sider arbitrary impedances to behave as through they were vin −
vn
resistors. Then vout
vout (s) Z (s) +
ACL = =− 2
vin (s) Z1 (s)
Figure 41: Generalized inverting configuration with
complex impedances.
Differentiator: Z1 is a capacitor
If Z1 is a capacitor C1 , and Z2 is a resistor R2 , then

1
Z1 (s) =
sC1
⇒ ACL (s) = −sC1 R2 .

In this transfer function, −C1 R2 is just a scale constant. The

signal is multiplied by s, resulting in differentiation in the
C2
time-domain.

Integrator: Z2 is a capacitor R1
vin −
vn
If Z2 is a capacitor C2 , and Z1 is a resistor R1 , then vout
+

1
Z2 (s) = Figure 42: Ideal Miller integrator.
sC2
R
⇒ ACL (s) = − 1 .
sC2
In this transfer function, − R2 /C1 is just a scale constant.
The signal is multiplied by 1/s, resulting in integration in the C2
time-domain.

C1
Z1 and Z2 are both capacitors
vin −
vn
If both of the impedances are capacitors, then the behavior is vout
+
similar to an inverting configuration.

1 Figure 43: Idealized capacitive inverting configura-

Z1 (s) = tion.
sC1
1
Z2 (s) =
sC2
C
⇒ ACL (s) = − 1 .
C2
In this transfer function, −C1 /C2 is the amplifier’s gain. The s
terms cancel out, resulting in no integrating or differentiating
behavior.
 58 ece3410 lecture notes

Practical Considerations RF

In practice, capacitors cannot simply be left floating at the C2

op amp terminals. Consider the circuit shown in Figure 43.
Node vn is left floating, which means there is nothing to define
C1
its potential. It could literally be anything, which could be
vin −
disastrous. vn
vout
Additionally, there is no path for the op amp’s DC bias +

current to flow. To address these problems, we have some

options: Figure 44: Practical capacitive configuration with DC
bypass resistor.

(a) Include large resistances to passively clear the charge on v− .

(b) Use ideal switches to periodically reset charge on v− . C2

Method (b) is commonly used in integrated circuits, where

capacitors are easier to make than resistors, and switches are C1
made using MOSFET transistors. One of the key advantages vin −
vn
to the circuit in Figure 45 is that it can cancel out the op amp’s vout
+
offset voltage. When used for this purpose it is often called an
auto-zeroing circuit. We can analyze the auto-zeroing circuit
Figure 45: Practical capacitive configuration with
in two phases. In Phase 1, the switches are configured to short switched DC bypass.
across C2 and to connect the top plate of C1 to ground. In this
phase, the op amp is basically in a voltage-follower configura-
tion. Due to the virtual short effect, vn should be equal to VOFS ,
so C1 gets charged up to a voltage equal to VOFS . Meanwhile C2
is discharged to a voltage of zero.

C2 C2

C1 C1
vin − vin −
vn vout vn vout
+ +

+ +
− VOFS − VOFS

Phase 1 Phase 2
Figure 46: The two switching phases of a capacitive
inverting configuration.
In Phase 2, the input is connected, and node vn is left float-
ing, so that no charge can be added or removed from vn . So
any charge added to the outside plate of C1 has to be balanced
by an opposite charge on the outside plate of C2 . The charge
Q1 = vIN /C1 must be balanced by Q2 = vOUT /C2 = − Q1 .
 operational amplifier circuits 59

Therefore
vOUT v
= − IN
C2 C1
vOUT C2
⇒ =− .
vIN C1

This interpretation allows us to build practical op amp configu-

rations using only capacitors. There’s a good reason for doing
this: resistors are big but capacitors are small. When making
circuits at the micro or nano scale, it is usually preferred to use
capacitors and avoid resistors whenever possible.
60 ece3410 lecture notes

Miller Integrator

When Z2 is a capacitor and Z1 is a resistor, as in Figure 42,

the circuit is called a Miller integrator. The ideal circuit from
Figure 42 suffers from a few practical difficulties:

1. What determines the Initial Condition of the integrator?

Usually we want vout = 0 at some starting time t = 0.

2. When vin = 0, we expect vout = 0 for all t > 0. However the op

amp’s systematic offset voltage creates a “ghost input” that
gets integrated, so the charge on C2 will go to ∞.
RF

3. There is no reset mechanism to zero the charge on C2 . If vin C2

is a sinusoid centered at 0, the offset will keep charging C2

without limit.
R1
vin −
vn
To resolve these difficulties, there are two common solutions. vout
The first solution is to use a large passive bypass resistor R F +

connected in the feedback path, as shown in Figure 47. The

Figure 47: Miller integrator with DC bypass resistor
bypass resistor serves to zero the DC charge on C2 . If R F is RF .
sufficiently large, then it will have minimal influence on the
frequency response above DC, however it may contribute to
offset effects due to the op amp’s bias current and offset voltage.
It will also tend to amplify any DC offset present in the input
signal. At very low frequencies, we can treat the capacitor C2
as an open-circuit, i.e. we simply remove it from the circuit.
C2
This reveals the circuit’s DC behavior, an inverting integrator
with gain − R F /R1 . Similarly at higher frequencies where
(ωC2 )−1  R F , we can ignore the presence of R F and the circuit R1
should behave like an ideal integrator. vin −
vn
vout
The second solution is to use a switching reset in the feed-
+
back path. We use a switch which is closed periodically to
zero the charge on C2 . This method has the advantage of being Figure 48: Miller integrator with switched DC
insensitive to the op amp’s bias current, and is only weakly bypass.
sensitive to the input offset voltage. The main drawback is that
the switch also resets the signal integration result, so it is not
possible to integrate over a long period of time.

Frequency Analysis

The Miller Integrator introduces an interesting frequency re-

sponse. We can solve the unity-gain frequency by evaluating
 operational amplifier circuits 61

the magnitude:

1
ACL ( jω ) =
ωR1 C2
1
⇒ ωt = .
R1 C2

We can draw the magnitude response by placing a point at ωt ,

then draw backwards adding 20dB per decade at frequencies
below ωt . The response grows toward ∞ as the frequency
approaches DC.
Introduction to Diodes

+ vD −
A diode is like a valve that lets current flow one direction
vA vB
but not the other. It is a nonlinear device, which means the
traditional linear analysis techniques cannot be directly applied.
iD
We begin with some simplified models that are useful for
Figure 49: Diode symbol and notation.
building intuition about diode circuits. After that, we’ll build up
to more accurate (but difficult) models and techniques. We’ll see
that accurate simulation using SPICE (or a similar software tool)
is essential for designing nonlinear circuits.

Ideal switch model

The simplest way to understand a diode is to consider it as an

ideal switch.

• When v D > 0, the switch is closed and i D can be any positive

value.

• When v D ≤ 0, the switch is open and i D = 0.

Using the switch model, we first make a hypothesis as to

whether the diode is ON or OFF. Then, we analyze the circuit
to verify it is consistent with that hypothesis. This approach
introduces our first iterative procedure: If the circuit contains
multiple diodes, we initially assume that all diodes are OFF
and then analyze the circuit. Any diode with a forward voltage
is then turned ON. After changing the diode’s state, we must
re-analyze the circuit to see if any additional devices need to be
turned ON.
64 ece3410 lecture notes

Example 11 (Max-Value Circuit).

Analysis steps:
D1
1. Suppose both diodes are OFF. Then vC = 0. But then both vA
D1 and D2 have positive potentials across their terminals,
so they cannot both be off. v A = 4V
2. Observe that D2 has the larger forward potential across D2 v B = 7V
its terminals. Based on this, suppose that D2 is ON while vB vC
D1 remains OFF. In this case, vC = v B = 7V, hence the
potential across D1 is vC − v A = −3V, which is consistent R
with the hypothesis.

In this example, we find that D1 is OFF while D2 is ON.

Figure 50: Diode max-value circuit.
Based on our analysis, we can generalize the result and
describe this circuit by the function

vC = max (v A , v B ) .

Example 12 (Min-Value Circuit).

Analysis steps:
VDD
1. Suppose both diodes are OFF. Then vC = VDD .

2. Observe that D1 has the larger forward potential across

its terminals. Based on this, suppose that D1 is ON while R
D2 remains OFF. In this case, vC = v A = 4V, hence the v A = 4V
potential across D2 is v B − vC = −3V, which is consistent
va vC v B = 7V
with the hypothesis.
D1
In this example, we find that D2 is OFF while D1 is ON.
Based on our analysis, we can generalize the result and
describe this circuit by the function vb
D2
vC = min (v A , v B ) .
Figure 51: Diode min-value circuit.
 introduction to diodes 65

Exponential model

A more accurate model of the diode is given by this expression: Diode physical device parameters:
    IS = Scale current, typ. ≈ 1pA to 1nA
vD
i D = IS exp −1 n = Grading coefficient, typ. ≈ 1
nUT
kB T
UT = Thermal voltage, ≈ 26mV at room temp.
Notice that when v D = 0, the current is also zero. When q

v D > 0, the exponential part rapidly becomes much greater than k B = Boltzmann constant = 8.6173 × 10−5 eV/K
T = Temperature (K) ≈ 300K at room temp.
one. When v D < 0, the exponential part rapidly becomes much
q = Elementary charge = 1eV/V
smaller than one. This splits the diode into two different modes:
called forward bias and reverse bias, respectively.
10
 
vD
Forward bias i D ≈ IS exp nU T
.
8
Reverse bias i D ≈ − IS .
6

i D (mA)
Constant voltage-drop model 4

From the physical model, we can see that the i D curve becomes
2
very steep when v D ≥ 0.7V, so we can say this is approximately
the ON voltage of the diode. When a diode is turned ON, it 0
0 0.2 0.4 0.6 0.8 1
should have a nearly constant forward voltage drop equal to
vD
0.7V.
Figure 52: Diode transfer characteristic. The current
increases very rapidly when v D ≈ 0.7 V.

Example 13 (Min-value circuit with 0.7V drop model).

Analysis steps:

1. Complete the analysis using the ideal switch model. We find that D1 is ON and D2 is OFF.

2. Estimate a more accurate result by adding a 0.7V forward drop to every diode that is ON, hence

vC = v A + 0.7V = 4.7V

Based on our analysis, we can generalize the result and describe this circuit by the function

vC = min (v A , v B ) + 0.7V.

Important Note: If |v A − v B | < 0.7V, then this method does not yield any valid solution. In that case,
we must use the full physical model with iterative analysis to arrive at the correct solution.
66 ece3410 lecture notes

Iterative Analysis

The constant voltage drop model gives us an approximation

that is useful for back-of-the-napkin analysis. For a more precise
analysis, we must solve the voltages and currents using the
full physical model. The resulting equations do not often have
closed-form solutions, so we must apply an iterative method
based on this procedure:

1. Obtain an initial solution using the switch model.

2. Improve the solution using the constant voltage drop model.

3. Based on that solution, calculate the resulting currents that

should flow through linear elements (resistors).

4. From those currents, estimate a more exact voltage drop for

each diode.

5. Repeat steps 3 and 4 in a loop until the answers converge to

a stable answer.

Convergence: How to know when the iterations are finished

Most of the time, we do not carry out iterative analysis by
hand; we use SPICE or a similar simulator to perform these
calculations for us. “Under the hood,” SPICE performs iterative
calculations to predict a circuit’s behavior. These simulators use
two criteria to decide when iterations are complete: absolute
tolerance (abstol) and relative tolerance (reltol), defined as:

• abstol – Simulation continues until all voltages and currents

satisfy
|∆x | < abstol

• reltol – Simulation continues until all voltages and currents

satisfy
 ∆x 
 
 x  < reltol
 

Most simulators will allow you to adjust the abstol and reltol
parameters. Smaller values result in better accuracy, but will
take more time to finish.
introduction to diodes 67
68 ece3410 lecture notes

Example 14 (Iterative analysis).

In this example, the current i is described by two

equations:
R vB
v − vB vA v A = 3V
i= A
R  R = 1kΩ
vB
 i
i = IS exp i
nVT D
Because of the exponential term, there is no easy
solution. We may solve the circuit by iteration:

1. Using the ideal switch model, we see that D must

Figure 53: Iterative solution for resistor-diode series
be ON. configuration.

2. Using the 0.7V model, we obtain an initial guess

(0)
v B = 0.7V
i(0) = 1mA

3. Using the resistor equation, we obtain a new

estimate for the current:
3 − 0.7
i (1) = = 2.3mA
1kΩ

4. From the diode equation, we can obtain a new

estimate for the voltage:
!
(1) (0) i (1)
v D = v D + nVT ln (0) = 0.72166V.
i

5. We repeat these analyses using the generalized

equations
(k)
v A − vB
i ( k +1) =
R !
( k +1) (k) i ( k +1)
vB = vB + nVT ln
i (k)

By following this procedure, we obtain the following sequence of results:

k i [mA] v B [V] ∆i [mA] ∆v B [V]
0 1 0.7 - -
1 2.3 0.72166 1.3 0.02166
2 2.2783 0.72141 −0.021656 −2.5 × 10−4
3 2.2786 0.72141 2.4596 × 10 − 4 2.8067 × 10−6
Notice that the changes ∆i and ∆v B become smaller with each iteration. This means that the calcula-
tions are converging onto the correct answer, where all equations find perfect agreement.
 introduction to diodes 69

iD
Linearized Model
+
id
Yet another way of modeling the diode is to use a linear approxi- +

mation. vd rd
Recall the definitions of small-signal notation, ID and VD are
the operating point values, id and vd are small variations, and i D −
and v D are the actual physical signal values. Hence vD ID

i D = ID + i d
+
− VD
v D = VD + vd

Looking at this circuit, it is easy to see that rd = vd /id . Since

vd and id represent small variations, we can interpret rd as the −
Figure 54: Linearized diode model.
derivative:
dv D
rd =
di D
di D −1
 
≈
dv D
  −1
IS VD
= exp
nVT nVT
nVT
=
ID
If we use the 0.7V model, and assume room temperature
operation with n = 1 (so nVT = 0.026V), then the values for this
model are

VD = 0.7V
ID = 1mA ( k +1)
iD
rd = 26Ω +
id
+
Iteration with the linearized model
(k)
vd rd
Iterative analysis can be combined with small-signal analysis by
repeatedly recalculating rd . In this version, the diode’s circuit −
( k +1) (k)
model looks like this: vD iD

The analysis procedure is as follows:

+ (k)
1. Use the constant 0.7V model to obtain an initial guess for all − vD
(0)
voltages and currents, and for rd .
( k +1) −
2. Using linear circuit analysis, find the solution for v D .
Figure 55: Iterative solution of linearized model
3. Using the non-linear device current equation, calculate the parameters.
( k +1) ( k +1)
current i D and the small-signal resistance rd :
( k +1) (k)
!
( k +1) (k) vD − vD
iD = i D exp
nVT
70 ece3410 lecture notes

4. Repeat the calculations until the answer is sufficiently con-

verged.
(0) (0)
Beginning from the initial conditions i D = 1mA, v D = 0.7V
(0)
and rd = 26Ω, we may solve new values for the voltages and
currents. Those new values may then be used to improve the
calculation of rd .
The chief advantage of using small-signal iteration is that
it provides stable convergence for most circuits, whereas the
method of direct iteration can sometimes fail. This method is
mathematically equivalent to the Newton-Raphson method,
and is the most common type of algorithm used in circuit
simulators like SPICE.

Example 15 (Iteration with linearized model).

For example, we may reconsider our resistor-diode circuit:

R i ( k +1)
vA
+ id
+
R vd (k)
rd
vA
−
≈ ( k +1)
vB i (k)

+ (k)
− vB

Figure 56: Iterative solution of the resistor-diode series configuration using the linearized model.

In this example, the iterative procedure yields the following table of results:
k i [mA] v B [V] rd [Ω] id [mA] vd [V]
0 1 0.7 26 2.25504 0.032943
1 3.5504 0.73294 7.3232 −1.0705 −0.009330
2 2.4799 0.72361 10.4843 −0.1934 −0.002112
3 2.2865 0.7215 11.3713 −0.0000079 −0.00009
4 2.2786 0.72141 11.4106 0 0
Diode Circuits

vin vout
Half-Wave Rectifier
R

The 1/2-wave rectifier circuit passes current only when vout >
0.7V. In this case, the diode’s forward voltage drop is close to
0.7V, regardless of the current that flows, so that vout ≈ vin − 0.7V. Figure 57: Half-wave rectifier circuit.
When the diode is OFF, no current flows, so vout ≈ 0V. This
behavior is approximately described by the expression

vout ≈ max (0, vin − 0.7V) .

vin
1
vout (ideal)
Voltage

vout (0.7V drop)

0

−1

Time
Figure 58: Behavior of the half-wave rectifier. The
ideal switch model is compared to the more accurate
constant-0.7 V drop model.

Example 16 (Half-wave rectifier with vin < 0).

In this example, let vin = −1V and R = 1kΩ. We want to solve for vout . First, we assume the diode is
OFF and check for consistency. We find that vout = 0 and therefore the diode’s forward drop is v D =
−1V. Since v D is negative, the diode must be OFF, so vout = 0V.
72 ece3410 lecture notes

Example 17 (Half-wave rectifier with vin = 1V).

In this case the diode is clearly ON. Using the con-

stant voltage drop approximation, we can estimate 1mA
that vout ≈ 0.3V. A more precise estimate may be
obtained using the small-signal model:
vin vout
vout + 0.7V − vin vout
+ − 1mA = 0
26Ω 1kΩ

−
+
1 kΩ
vin − 0.7 26 Ω
 
1 1 0.7 V
⇒ vout + = 1mA +
26 1kΩ 26

Figure 59: Linearized model of half-wave rectifier.

Now solving for vout :

vin − 0.7
⇒ vout = (1mA) (26Ω k 1kΩ) + (26Ω k 1kΩ)
26
Now notice that (26 k 1000) ≈ 26 (try it). Then we can simplify the approximation:

vout ≈ 26mV + vin − 0.7V

≈ vin − 0.684V.

This provides a more accurate approximation when the resistor R is large. In the case where vout =
1V, we find that

vout ≈ 0.343V
i D ≈ 343µA
 diode circuits 73

Resistor-diode regulator

The regulator circuit is similar to the 1/2-wave rectifier, only vin vout
it interchanges the positions of the diode and resistor. In this
circuit, when vin < 0.7V, the diode is either OFF or only weakly
ON, so the current is close to zero. In that case, the voltage drop
across R is nearly zero, so vout ≈ vin . When vin > 0.7V, the diode
is clearly ON. Using the constant voltage drop model, we find
Figure 60: Single-diode regulator circuit.
that vout ≈ 0.7V, so the waveform is “clipped” at 0.7V.

0.7V Regulator Behavior

1
vin
0.8 vout
Voltage

0.6
0.4
0.2
0
Time
Figure 61: Behavior of the single-diode regulator
circuit with R = 100. The results from SPICE
simulation are more accurate than hand analysis.
A more accurate analysis is obtained using the linearized
diode model. By applying the node-voltage method at vout , we
find that

vout − vin vout − 0.7V R

+ + 1mA = 0 vin vout
R 26Ω
 
1 1 vin 0.7V
⇒ vout + = +
R 26Ω R 26Ω
26Ω R
⇒ vout = vin + 0.7V 26Ω
26Ω + R R + 26Ω

1 mA
As the name implies, regulators are used to produce sta-
ble DC voltages. Ideally, a regulator should produce 0.7V re- +
gardless of vin (so long as vin > 0.7V). The preceding analysis 0.7V −

revealed a slight dependency between vin and vout :

 
26Ω
∆vout = ∆vin . Figure 62: Linearized model of the single-diode
R + 26Ω regulator.

In practice, the residual ∆vout signal can introduce interference

into the circuits that are interfaced with the regulator. Accord-
ing to this analysis, the regulation works best when R is large.
74 ece3410 lecture notes

Peak rectifier

The peak rectifier (or peak detector) circuit is like a rectifier

that uses a capacitor in place of the resistor. This circuit can
vin vout
be interpreted as an integrating rectifier. Unlike the usual
diode circuits, the 0.7V approximation can be misleading when
applied to the peak rectifier. C

This is because the capacitor integrates all of the current that

passes through it:

Z tF
1
vout = i D (t) dt.
C 0

When the diode is OFF, a small current still flows, and that
current is steadily accumulated by the capacitor’s integrating
behavior.
Consider the output from a SPICE simulation where C =
1nF, shown below. In this simulation, we can see that vout rises
initially to 0.263V, which is approximately vin − 0.437V. Clearly
the 0.7V model is not working.

Peak Detector Circuit with 0.7V Input Amplitude

vin
0.5 vout
Voltage

−0.5

Time

To understand why the 0.7V model fails, we may examine

the diode current, shown in the figure below. Although the
current never exceeds 1µA, the small pulses are sufficient to
charge C.
In each cycle of the input waveform, the peak current gets
smaller, so the output waveform marches in smaller and smaller
steps toward the peak value of the input voltage. Given enough
time, vout will eventually rise very close to the actual peak. This
effect can be used to create AC-to-DC converters.
 diode circuits 75

Peak Detector Current

·10−8
3
i

2
Current

0
Time
Figure 63: Current delivered into the capacitor in the
peak detector circuit.
Envelope detector

The peak detector circuit can also be used in a variety of ap-

plications for instrumentation and communication. In these
applications, we usually want to detect the envelope of some vin vout
waveform, which requires that vout be allow to drop when vin de-
creases. This is accomplished by adding a resistor R in parallel C R
with C, resulting in an envelope detector:
An example SPICE simulation result is shown in the plot
below. This simulation used the following values:
Figure 64: Envelope detector circuit.
C = 10µF
R = 10kΩ
f = 10Hz

In this circuit, the diode is able to rapidly charge the capaci-

tor C, which is then slowly discharged by R.

Envelope Detector
4
vin
vout
2
Voltage

−2

Time
Figure 65: Behavior of the envelope detector circuit.
When the didoe is OFF, the output waveform is described by
76 ece3410 lecture notes

the standard RC discharge equation

vout (t) = vpeak (1 − exp (− RC (t − t0 ))) ,

where t0 is the time when the diode turns OFF.

Netlist 1: envelope_detector.sp
* envelope detector circuit

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)

* The input is a damped 10Hz sine wave that

* looks like an impulse:
Vin 1 0 SIN(0 5 10 0.25 8)

* Peak detector circuit:

D1 1 2 diode
C1 2 0 10uF
R1 2 0 10k

* Transient simulation:
.tran 1m 1.5

.end
 diode circuits 77

Bridge Rectifier

A bridge rectifier circuit, shown below, provides full-wave

rectification. Node numbers in the figure are indicated in blue,
corresponding to the example SPICE description.

D2
1
D

− load +
vIN +
0 3
D3

4
D

vOUT

−
Figure 66: Full wave bridge rectifier circuit.
Analysis:
Case 1: vIN > 0. In this case, we see that the most
positive potential appears at the anode of
D2 . Based on this, we may predict that D2 is
ON while D1 is OFF. Since the most negative
potential appears at the anode of D4 , we may
conclude that D4 is OFF.
Based on this reasoning, we infer that the
current flows in a zig-zag through D2 , then the
load, then D3 . The potential appearing across
the load is
vOUT ≈ vIN − 1.4V.

Case 2: vIN < 0. In this case the most positive potential

appears at the anode of D4 , and the most nega-
tive potential appears at the cathode of D1 . We
may conclude that the current flows in a zig-zag
through D4 , then the load, then D1 . In this case
the potential appearing across the load is
vOUT ≈ |vIN | − 1.4V.
78 ece3410 lecture notes

The bridge arrangement ensures that the polarity across the

load is always oriented right-to-left, regardless of the input
polarity.

Bridge Rectifier Circuit with 10V Input Amplitude

10
vin
vout
5
Voltage

−5

−10
Time

SPICE simulation example for the bridge rectifier:

Netlist 2: bridge_rectifier.sp
* bridge rectifier circuit

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)

* The input is a 120Hz sine wave:

Vin 2 1 SIN(0 10 120)

* Bridge rectifier:
D1 0 2 diode
D2 2 3 diode
D3 0 1 diode
D4 1 3 diode

* Load resistor:
Rload 3 0 1k

* Transient simulation:
.tran .1m 0.02

.end
 diode circuits 79

VDD
Voltage Regulators
R
We previously considered a 0.7V regulator circuit. We can
vOUT
extend this concept to produce other regulated voltages by
connecting multiple diodes in series. For example, we may
connect four diodes in series to create a 2.8V regulator circuit:

Ripple Analysis: Line Regulation

The regulator is able to reject ripple waveforms that appear in
the supply voltage, however the rejection is not perfect. A close
inspection reveals that a small ripple is injected into vOUT :
The regulator’s quality is measured by the amount of ripple
that appears in vout . More precisely, we want to know the ratio
of output ripple amplitude to input ripple amplitude. This
quantity is called the line regulation, defined as
Figure 67: A four-diode voltage regulator.
∆vOUT
LR =
∆VDD
To predict this, we must calculate the small-signal gain of
AC signals that are transferred from vin to vout . We previously vdd
introduced a small-signal model that allows each diode to
be replaced by a linear approximation. Now we introduce R
the concept of an AC Equivalent Circuit which we can use to vout
analyze the non-DC behavior.
rd

Deriving the AC Equivalent Circuit

rd
Step 1 To obtain the linear circuit approximation,
replace all non-linear devices (e.g. diodes)
rd
with their linearized companion models, as in
previous examples.
rd
Step 2 To obtain the AC equivalent circuit, set all
independent DC sources to zero. This means
that independent current sources are replaced
by open-circuits, and independent voltage Figure 68: Small-signal equivalent circuit model of
the four-diode 2.8 V regulator.
sources are replaced by short-circuits.

After obtaining the AC equivalent circuit, we use all-lower-

case notation to indicate the ripple waveforms vin and vdd . Using
the AC equivalent circuit, we can solve for the line regulation as
the ratio of these small signals: Reminder: The lower-case signal vout represents the
vout small ripple signal appearing in the output. The
LR ≈ all-upper-case notation VOUT is used to represent
vdd the DC (average) value. The actual physical signal is
vOUT (t) = VOUT + vout (t) .
80 ece3410 lecture notes

Example 18 (Four-diode voltage regulator design).

Let

vin = 10V + (0.5V) sin (2π f t) .

Basic analysis
Find R to get an average current of 1mA, resulting in vout = 2.8V.
vin − vout
1mA = I =
R
vin − vout
⇒R=
I
= 7.2kΩ

The behavior of this circuit is investigated using SPICE simulation. The results shown below include
a supply ripple with zero-to-peak amplitude of 0.5V at 120Hz. From SPICE simulations, we see
that the actual output voltage is 2.7863V, which is slightly less than the intended value. The ripple
amplitude is also found to be 14.158mV.
By using the small-signal model, we can obtain a reasonable estimate of vout , the small ripple wave-
form that is superimposed on the regulator’s output:

vin = (0.5V) sin (2π f t)

4rd
vout = vin
R + 4rd
 
104
= vin
7200 + 104
= vin (0.014239)
= (7.12mV) sin (2π f t)

Then the line regulation is

vout
LR =
vdd
7.12mV
=
500mV
= 0.014239
= 1.4239%
 diode circuits 81

Netlist 3: basic_regulator.sp
* 2.8V regulator circuit

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)

* The input is a 120Hz sine wave with a 10V offset.

* The supply ripple amplitude is 0.5V
Vin 1 0 SIN(10 0.5 120)

* Regulator circuit
* The output is at node 2
R1 1 2 300
D1 2 3 diode
D2 3 4 diode
D3 4 5 diode
D4 5 0 diode

* Transient simulation:
.tran .1m 0.02

.end

Regulator Circuit with 120Hz Supply Ripple

10 vin
vout
Voltage

0
Time
Figure 69: Behavior of the four-diode regulator from
SPICE simulation.
82 ece3410 lecture notes

Regulator Output Ripple

2.79
Voltage

2.79

2.78

Time
Figure 70: Zoomed view of the ripple voltage on
vOUT .

General Analysis

In general, for a diode circuit comprised on N diodes with bias

current ID , generated by an input voltage VIN and resistance R,
we can produce a regulated voltage VOUT = NVD , where VD is
the individual diode voltage associate with ID . Then the line
regulation is

NVT /ID
LR =
R + NVT /ID
NVT
=
RID + NVT
NVT
= .
VDD − VOUT + NVT

The smaller we make this value, the better quality we will

provide on the regulator output. Things that achieve good
quality regulation include:

• A large voltage drop RID , i.e. vin should be significantly

greater than the regulated vout .

• A small number of diodes N.

 diode circuits 83

Example 19 (Two Diode Regulator with Op Amp Buffer).

Another approach is to use two diodes at 1mA to create

a 1.4V reference, which is then multiplied using a non- VDD R2
inverting op amp configuration to yield 2.8V:
For this configuration, the line regulation is: R1
R −
2VT vOUT
LR = ( G )
(10V − 1.4V) + 2VT +
= 0.01202 (V/V) .
D1
So it appears that this solution is slightly better, although it
may be affected by the tolerances on R1 and R2 , as well as D2
the op amp’s input bias current and finite gain.

vin +

Super Diode, Precision Rectifier va

−
This circuit operates in two modes. When the diode is forward
biased, it is a unity-gain follower. Note that in this configura-
tion v D can be very near zero, because little current is required vout
to regulate the op amp’s inverting terminal.
When the diode is reverse biased, the op amp is discon- Rload
nected from the output node. Therefore it delivers no current
to the load, and vout = 0. Note that in this configuration, the
op amp’s loop is open, which will cause v a to rail negative. Be-
Figure 71: Precision rectifier circuit with op amp
cause of this issue, this circuit is best used with a single-sided
feedback.
power supply.

Superdiode With Single-Rail Supply

4
vin
2 vout
Voltage

0
−2
−4
Time
84 ece3410 lecture notes

Netlist 4: superdiode.sp
* super-diode precision rectifier simulation

* Include model for 741 op amp:

.include 741.sp

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)

VIN 1 0 SIN(0 4 10)

VDD 10 0 DC 10V

* 741 instance
* Pin order: v+ v- VR+ VR- vo
X1 1 2 10 0 3 uA741

D1 3 2 diode
RL 2 0 1k

.tran 1m 0.5

.end

The superdiode netlist uses a SPICE model for the uA741 op

amp. The model is provided by the vendor, and the usage is
documented in the model file:

Netlist 5: 741.sp (top lines showing port order)

* SPICE model for uA741 op amp
*
* To use a subcircuit, the name must begin with ’X’. For example:
* X1 1 2 3 4 5 uA741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt uA741 1 2 3 4 5
 diode circuits 85

C
vin vout
DC Restoration, Clamped Capacitor

In this circuit the behavior depends on the capacitor’s charge q.

q
vout = vin +
C
Figure 72: Clamped capacitor circuit.
When the diode is forward biased, the capacitor is able to be
charged via current flowing through the diode. When the diode
is reverse biased, no current flows, so that capacitor holds its
charge.
To analyze the circuit, consider the initial condition q (t = 0) =
0, so that initially vout = vin . Suppose vin is initially zero, and in-
creases above zero. Then the diode will stay reverse biased, and
q doesn’t change.
But if vin decreases below zero, then the diode will begin to
switch on. The capacitor will accumulate charge equal to

q (t) = i D t
−vout
 
= IS exp t.
VT

This current will be greater than zero as long as vout < 0.

Consequently, the capacitor will collect charge until vout = 0.
As a result of this process, the capacitor will store a voltage
equal to the minimum value of vin .
Result: vout is a shifted version of vin , such that its minimum
value is equal to zero.

DC Restorer Circuit with 1V Input Amplitude

vin
vout
2
Voltage

−2
Time
Figure 73: Behavior of DC restorer (clamped capaci-
tor) circuit simulated in SPICE.
86 ece3410 lecture notes

Netlist 6: dc_restorer.sp
* DC restoration circuit

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)

* The input is a 10Hz sine wave:

Vin 1 0 SIN(0 2 10)

* Peak detector circuit:

D1 0 2 diode
C1 1 2 10uF

* Transient simulation:
.tran 1m 2

.end
L
VIN VOUT

Boost converter iL
C
Diodes are frequently used in power conversion circuits. In this
appendix we look at one important step-up DC-to-DC converter
circuit, known as the boost converter. The boost converter con- Figure 74: Idealized boost converter circuit.
sists of an inductor, a diode, a switch and a load capacitance, as
in the schematic shown in Figure 74.
When the switch closes, the inductor is shorted to ground,
resulting in a large current. When the switch opens, the induc-
tor’s current cannot change instantly, so the current is forced
through the diode into the capacitor. This establishes a large
potential across the capacitor.
More precisely, suppose that the switch is initially open and
the current i L is zero. Then, at time t = 0, the switch closes
abruptly. The current is then
Z t
1 VIN
i L (t) = VIN dτ = × t.
L 0 L
Then if the switch opens again at some time t1 , the inductor will
possess a stored energy equal to

1 2
E ( t1 ) = LI .
2
Since the current must continue flowing through the inductor,
most of this energy is transferred into the capacitor, and some
of the energy is dissipated in the diode. For our purposes, we’ll
use the ideal switch model and ignore losses in the diode, hence
we will assume all the energy is transfered to the capacitor.
 diode circuits 87

If the switch is toggled very rapidly, with period T, then the

current i L will “ripple” up and down, transferring packets of
energy in each cycle. Suppose the switch is closed for a time
DT, where D is the duty cycle of the switching clock. Then the
switch is open for a time (1 − D ) T. At steady state, the current
should grow and shrink by the same amount:

DT
∆i L (on) = VIN
L
(1 − D ) T
∆i L (off) = − (VIN − VOUT )
L
If we set the rise and fall equal to each other (as required for
steady-state operation), then we can solve for VOUT :
50
VIN
VOUT =

vOUT (V)
1−D 40

Note that this analysis only works if the switching is very fast,
30
so that the inductor current never drains completely to zero.
If the switching clock has a 50% duty cycle, then the circuit
20
acts as a voltage doubler. An example SPICE simulation follows
0 0.5 1 1.5
with VIN = 20 V and a switch frequency of 5 MHz with a duty
Time (s) ·10−3
cycle of 62%. The expected output is VOUT = 52.6 V. The simula-
Figure 75: Output voltage from the boost converter
tion output, shown in Figure 75, approaches the expected limit when initialized at zero.
after about 1 ms, which corresponds to five thousand switching
cycles in this example. Note that the simulation does account for
energy lost in the diode. The main effect of diode losses is that
the circuit takes longer to approach the steady state condition.
But just like with the peak detector circuit, the diode’s loss gets
smaller in each cycle, and some energy is delivered to the capac-
itor in each cycle, so the circuit asymptotically approaches the
ideal limit.

Netlist 7: boost_converter.sp
* Boost converter simulation

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)

* switch model:
.model switch sw(Ron=5, Roff=100000, Vt=0.001, Vh=0.0001)

* The input is 10V DC

Vin 1 0 DC 20V
88 ece3410 lecture notes

* The switch control voltage is a high-frequency pulse waveform

Vswitch 4 0 PULSE(0 1 0 1n 1n 125n 200n)

* Boost converter circuit:

* Inductor:
L1 1 2 100u

* Diode, load capacitor and switch:

D1 2 3 diode
CL 3 0 10u
S1 2 0 4 0 switch

.tran 100n 1500u

.end
Memristors

+ v (t) −
The “memristor” refers to a nonlinear two-terminal device for
which the resistance changes in response to an applied voltage
or current signal, and in which the resistance stays constant for Figure 76: Memristor symbol. The device acts like a
some period of time when the signal is removed. This behavior time-varyingR resistor, where the resistance changes in
response to v (t) dt.
is described as a “memory resistor,” hence the abbreviated
name, “memristor”. A device which exhibits resistance memory
is said to be a “memristive” device or system.
Memristive devices were first observed more than a century
ago, but they lacked a general theory to understand and apply
their behavior in the context of circuit engineering. The first
general theory was articulated by Leon Chua in two papers,
written in 1971 and 1976 2 . Chua’s theory began as a somewhat 2
Leon O Chua. Memristor-the missing circuit
speculative hypothesis. Interest surged in memristors after a element. Circuit Theory, IEEE Transactions on, 18(5):507–
519, 1971; and Leon O Chua and Sung Mo Kang.
group from HP Labs published a paper titled “The missing Memristive devices and systems. Proceedings of the
memristor found,” which showed that nano-scale resistance- IEEE, 64(2):209–223, 1976
switching devices have the characteristics predicted by Chua’s
theory 3 . 3
Dmitri B Strukov, Gregory S Snider, Duncan R
Stewart, and R Stanley Williams. The missing
memristor found. nature, 453(7191):80–83, 2008
Axiomatic Circuit Theory

Memristor theory grew out of Chua’s axiomatic formulation

of nonlinear circuit theory, which accounts for conservation
laws (i.e. Kirchoff’s Voltage and Current Laws) in networks of
nonlinear devices. There are four “fundamental” quantities
which must be conserved in any circuit:

• Voltage v (KVL)

• Current i (KCL)

• Charge q (conservation of matter)

• Flux linkage φ (conservation of energy)

Among these quantities, flux linkage (we’ll call it “flux” for

short) tends to cause a lot of confusion, which has led to some
90 ece3410 lecture notes

serious debates over the interpretation of memristor theory.

We’ll briefly examine the theoretical foundations in order to
prevent any confusion later.
In a coil inductor, the flux is associated with the magnetic
field flux through the plane of a wire loop. In the general theory
of circuits, however, flux linkage is a broader concept, and does
not always have a magnetic field interpretation. In the theory of
circuits, the flux is defined strictly as the integral of voltage over
time: Z
φ, v (t) dt.

This definition does not need to invoke any concept of a mag-

netic field. In fact, the theory of circuits does not reference Some recent research hints at a genuine link between
any electric or magnetic field quantities at all; it is concerned magnetic fields and memristor flux within a specific
type of resistance-switching memristor . The
strictly with the relationships between current, voltage, charge correctness and applicability of this theory are not
and flux in a network of interacting components. This theory yet established. It could help to clear some of the
confusion about flux, but such an explanation is not
represents physical laws that are as fundamental as electromag- strictly necessary, since the circuit theory definition
netism, and are valid irrespective of the presence of electric or of flux stands on its own.
magnetic fields. E. Gale. The memory-conservation theory of
memristance. In Computer Modelling and Simulation
We could say that it is a sufficient theory for circuit interac- (UKSim), 2014 UKSim-AMSS 16th International
tions, meaning it is a set of laws or axioms which suffice to Conference on, pages 599–604, March 2014
account for all of the applicable facts within a specified domain.
For example, we can state a sufficient theory of addition on the
natural numbers (0, 1, 2, . . . ) without considering the concepts of
multiplication, division, fractions, rational or irrational numbers,
prime numbers, etc. Those additional concepts have no impor-
tance to the theory of adding natural numbers. In a similar way,
the full theory of electromagnetism is mostly unnecessary for
studying circuit networks.
So what is the theory of circuits really about? The theory
treats every physical device as a black box, defined only by the
activity of v, i, q and φ on its terminals. It it assumes there are
no significant field interactions between devices or wires, and
addresses two basic questions:

1. What types of device behavior are allowed under the physi-

cal laws?

2. How do the devices interact when connected together via

wires?

The answers to these questions dictate what kinds of circuits are

possible to build, and also provide the foundation for analyzing
and simulating those circuits. In effect, this theory forms the
basis for SPICE and other circuit simulation methods.
 memristors 91

capacitor
Constitutive Relations dq = C dv
voltage charge
In order to define the behavior of “black box” devices, we begin v q
with a standard format, called the constitutive relation, that
can be used to describe any passive two-terminal device. A

dv
=
constitutive relation is an expression that defines a conservative

φ
dt
relationship between two of the fundamental quantities. The resistor
dv = R di memristor
traditional linear components are defined by familiar relations,
dφ = M dq
expressed in both their usual and differential forms

t
id
=
dq
usual form differential form
current flux
v = Ri dv = R di
i φ
inductor
q = Cv dq = C dv dφ = L di
φ = Li dφ = L di Figure 77: An illustration of the constitutive relation-
ships corresponding to standard components and
In addition to the three standard passive elements, we may definitions. One relation is missing in the classical
define two more constitutive relations based on the definitions theory: the memristor.

of current and flux:

integral form differential form

Z
q= i dt dq = i dt
Z
φ= v dt dv = φ dt

This brings us to a total of five relations among the four quan-

“The memristor is not an invention.
tities, as illustrated in the diagram in Figure 77. Chua noticed Rather it is a description of a basic
that one relation is missing: the relationship between φ and phenomenon of nature that manifests
q. All other relationship pairs are defined, so why is this one itself in various dissipative devices,
absent? He named the hypothetical missing element the mem- made from different materials, internal
structures and architectures.”
ristor and proceeded to analyze what kind of characteristics it
should have, according to the physical laws of circuit theory. – Prodromakis, Toumazou & Chua,
“Two centuries of memristors”
Nature Materials
Nonlinear Devices vol. 11, 478–481 (2012)

The memristor is an inherently nonlinear device. In order to

understand it, we first need to examine the fundamentals of
nonlinear constitutive relations. Nearly all real-world devices
exhibit some degree of nonlinearity. The format of constitutive
relations allows us to define arbitrary nonlinear behaviors
which can then be analyzed using computer simulations.
We begin with nonlinear versions of the standard elements.
Since computer simulators will typically work by analyzing
small-signal linearized models of nonlinear circuits (similar to
the methods we used to analyze diodes), nonlinear constitutive
92 ece3410 lecture notes

relations are represented in differential form:

dv = R(v, i ) di non-linear resistor

dq = C (v, q) dv non-linear capacitor
dφ = L(i, φ) di non-linear inductor

Notice that in these nonlinear relations, the R, C and L values

are not constant; they functions of their electrical state. This the-
ory represents a wide generality of phenomena – for example, a
diode can be considered as a nonlinear resistor.

Example 20 (Diode as a nonlinear resistor).

Consider a forward biased diode with the standard equation

i = IS ev/nUT .

We can define the small-signal resistance of this diode as

  −1
di
R(v, i ) = I ev/nUT
dv S
nUT
=
IS ev/nUT
nUT
=
i
So, for small changes in the current and voltage around the neighborhood around (v, i ), we can say
that the diode’s constitutive relation is
nUT
dv = di.
i
In a transient computer simulation for a circuit containing diodes or other nonlinear devices, we
begin with an initial state using an iterative technique. Then we slowly advance time in very small
steps, each time solving for the small changes dv, di, dq and dφ at all points in the circuit. We add the
changes to the circuit’s state and repeat, until reaching the simulation’s stop time.

Now the memristor’s constitutive relation is given by

dφ = M (φ, q) dq.

In order to understand this relation, it is helpful to translate it

into the domain of voltage and current:
dφ dq
= M(φ, q)
dt dt
⇒ v = M(φ, q) i.
 memristors 93

That looks like a resistor equation, except the resistance is a

function of φ and q. And since φ and q are defined as the time- 4

integral over voltage and current, respectively, we can say that

the resistance in M is a function of the entire history of v and q 2

applied to the memristor. This long-term memory effect is the

Current
0
reason behind the name “memory resistor.”

−2
Memristor Properties
−4
Chua authored several papers exploring the possible attributes
−4 −2 0 2 4
of a memristor device. The most important features can be
Applied Voltage
deduced from the constitutive relation itself. First of all, since
Figure 78: Pinched hysteresis in a memristor, driven
the memristor behaves like a time-varying resistance, we expect by a sinusoidal voltage across its terminals. In this
that when zero volts are applied, its current should also go model, we assume resistance increases when a rising
to zero, just as it would for any resistor. Second, if a positive positive voltage is applied (blue curve). As the
resistance increases, the blue curve’s slope becomes
voltage is applied, the flux and charge should begin to change, flatter. When the positive voltage begins to decrease
and we therefore expect the resistance to change over time. (red curve), the current is lower due to the increased
resistance in this portion of the curve. When the
Third, if a negative voltage is applied, it should reverse the voltage reaches zero, the current also goes to zero.
changes in the flux and charge, and so the resistance should When the applied voltage swings negative (green
change in the opposite direction. curve), the resistance decreases so the curve becomes
more steep. When the applied negative voltage
The above reasoning predicts what is known as pinched rises toward zero again (black curve), the current
hysteresis, which is the key attribute of any memristor device. is stronger (more negative) due to the decreased
resistance. Once the applied voltage returns to
Pinched hysteresis is observed on a type of plot called the Lis- zero, the memristor’s resistance should return to its
sajous figure, which displays the device’s current and voltage original value.
when being driven by a period source. For an ordinary resistor,
the Lissajous figure should be a straight line. For capacitors and
inductors, the Lissajous figure is a circle or ellipse. For a mem-
ristor, we see the “bow tie” pattern shown in Figure 78. This
pattern is not observed for any other device, and is considered
a “fingerprint” of memristance.
A second property of memristance is non-volatility: when A Real Memristor

the applied voltage is zero, the current is also zero, therefore 4

the flux and charge should remain constant. In other words, the
memristor remembers its internal resistance for some period of 2
Current (mA)

time when held at zero volts. This property is potentially very

0
useful for memory and storage applications, and is now one of
the top priorities in memristor research. −2
A third property is lobe narrowing at higher frequencies.
−4
When a high-frequency voltage signal is applied, the positive
and negative voltages appear for shorter periods of time, so the −1 −0.5 0 0.5 1
Voltage (V)
flux does not change as much. This should squeeze the hystere-
Figure 79: Measured data of a resistance-switching
sis curves closer together. At progressively higher frequencies,
device reported by HP Research. The HP group was
the Lissajous pattern should converge to a single line or curve the first to identify these devices as memristors.
with no hysteresis at all — like an ordinary resistor. This prop-
94 ece3410 lecture notes

integrator
erty can be useful, for example, in reconfigurable radio circuits,
where low-frequency signals can be used to “tune” the device’s C

resistance, whereas radio-frequency signals will see a stable

resistance. +
−
A final property is that memristors are purely passive de-
R +
vices. Unlike capacitors and inductors, a memristor does not +
store any energy. The memory effect in a memristor is usually v (t) B vφ
due to a chemical or structural change, such as a migration of
molecules within a solid material. Work must be done to induce −
−
those changes, and they cannot be reversed without additional Figure 80: A memristor model based on an op amp
work from an external source. integrator and a voltage-controlled nonlinear resistor.

Simulating Memristors

Memristor models are an active area of research, and there

is not yet any standard model for simulations, nor is there a
memristor device built into SPICE or other simulators. We can
nevertheless get some experience with memristive behavior by integrator
creating behavioral models in SPICE. This is a tricky problem; vofs
several behavioral models are available but all of them are

+
−
sensitive to simulation parameters and may crash the simulation
if conditions are not just right. Furthermore memristor models C
often become invalid outside of a limited range of voltage and
frequency, so they are not necessarily general-purpose models.
+
One of the simplest models uses an op amp integrator to − ro
model the flux in the memristor, as shown in Figure 80, where R +
B +
the integrator’s output voltage vφ should be proportional to vφ
v (t)
the flux φ. Then, to model the changing resistance, we have to co
utilize a special nonlinear dependent current source provided rs

by NGSpice. The syntax for a nonlinear source is −

−
Bxxx n+ n- i={expr}
Figure 81: A stabilized and bounded memristor
where {expr} is the mathematical expression used to define the model. The zener diode and offset voltage vofs are
device’s current. We could use a simple expression like this: used to constrain the maximum and minimum
resistance in the device.
i = −K v (t) vφ (t)

where K is a scale constant with units of V/Ω, and the resis-

tance is assumed to decrease with higher values of φ. The
expression is negative since the Miller integrator circuit is invert-
ing, so we have to invert the sign.
There are a couple of problems with this model: first, we
can’t allow vφ to ever be positive, since that would turn the
memristor into an impossible energy source. This problem is
fixed by inserting a diode across the terminals of C. We add an
 memristors 95

offset voltage source as shown in Figure 81 to compensate for

the diode’s forward drop. In addition, by using a zener diode,
the diode’s reverse breakdown voltage limits the maximum flux
in the memristor, so the memristor model should saturate at
maximum and minimum resistances. It is realistic to assume
limits on the device’s flux, since physical quantities generally
don’t extend to infinity in real devices.
A second problem is more subtle: this model can sometimes
induce numerical instability in SPICE simulations. There are
some tricks that improve stability, like inserting small-valued
resistors and capacitors around the op amp and the nonlinear
current source. These stabilizing devices appear as ro , co and
rs in Figure 81. To verify the qualitative behavior of this model,
the simulation below tests the model for a 5 V sinusoidal input
at three different frequencies. It should produce six plots rep-
resenting the Lissajous figure and the integrator state for each
case.

memristor_integrator_model.sp
* Memristor integrator model

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1, BV=200)

* Memristor subcircuit model:

.subckt memristor nplus nminus
R1 nplus n2 100
C1 n2 n3a 10n ic=0

* Ideal op amp model (dependent v source):

E1 n3 nmin nmin n2 10000

* Stabilizing RC network at op amp’s output:

R2 n3a n3 1
C2 n3a nmin 10f

* Zener diode to constrain integrator bounds:

D1 n3a n2a diode
V1 n2a n2 DC -0.8V

* Nonlinear current source:

B1 nplus nmin i={-0.001*(v(n3)-v(nmin))*((v(nplus)-v(nmin)))}

* Stabilizing series resistance:

R3 nmin nminus 1
.ends
96 ece3410 lecture notes

memristor_integrator_simulation.sp
* Memristor simulation based on integrator model

.include memristor_integrator_model.sp

V1 nplus 0 SIN(0 5 100k)

X3 nplus 0 memristor

.control
* Medium-frequency simulation:
tran 10n 50u uic
plot -i(v1) vs v(nplus)
plot v(X3.n3)
wrdata integrator_mid_freq v(nplus) i(v1) v(X3.n3)

* Low-frequency simulation:
alter @V1[sin]=[ 0 5 1k ]
tran .01m .0025 uic
plot -i(v1) vs v(nplus)
plot v(X3.n3)
wrdata integrator_low_freq v(nplus) i(v1) v(X3.n3)

* High-frequency simulation:
alter @V1[sin]= [ 0 5 1MEG ]
tran 1n 5u uic
plot -i(v1) vs v(nplus)
plot v(X3.n3)
wrdata integrator_high_freq v(nplus) i(v1) v(X3.n3)

.endc
.end
 memristors 97

The simulation results are shown in Figure 84 on the follow-

ing page. In the mid-frequency case (at 100 kHz) we see the
typical pinched hysteresis that represents memristive behav-
ior. The integrator state shows that the device’s flux oscillates,
corresponding to the integral of the sinusoidal input.
For the low-frequency results (at 1 kHz), the Lissajous figure
shows “peaks” on each side of the hysteresis lobes. The peaks
represent resistance saturation in the memristor device, which
is verified by noting the saturation in the integrator state. If we
examine the behavior at even lower frequencies, the hysteresis
lobes will almost disappear, and all we will see is a curved line.
This is because the resistance saturates early in the sinusoidal
period, so the device behaves sort of like a diode, with low
resistance for positive voltages and high resistance for negative
voltages.
Figure 82: Davy’s arc lamp exhibits memristive
Lastly, in the high-frequency case (at 1 MHz), we see the pre- behavior, and is believed to be the first human-made
dicted lobe narrowing. The integrator state shows why: the flux memristor device.
amplitude is reduced at high frequencies. This phenomenon has
an easy theoretical explanation: the flux is
Z
φ= VA sin (2π f t) dt
VA
 
= cos (2π f t)
2π f

so as f increases we expect the amplitude to drop.

The model used in this example is an idealization. Real mem-
ristors can exhibit a variety of complex nonlinear behaviors,
but all of them possess the essential characteristic of pinched
hysteresis and resistor memory. Memristor theory is now under-
stood to encompass many historical and contemporary devices,
including 19th century devices like the arc lamp (Figure 82) and
coherer (Figure 83). Chua’s theory has also been expanded to
encompass modern devices like the thermistor, various point
contact devices, fluorescent tubes, among others. As a physical
Figure 83: Branly’s coherer, basically a tube filled
theory, memristance is increasingly observed in biological and with iron filings, is another early memristor device.
chemical systems such as synaptic ion channels in neurons, The tube’s resistance changes in the presence of
leaves, blood, and even slime molds 4 . radio waves. This device was widely used in wireless
telegraph receivers from 1890 to 1920. In 1901, Bose
reported the first observation of pinched hysteresis in
a coherer device.
4
Themistoklis Prodromakis, Christofer Toumazou,
and Leon Chua. Two centuries of memristors. Nature
materials, 11(6):478–481, 2012; and D. Lin, L. Chua,
and S. Y. Hui. The first man-made memristor: Circa
1801 [scanning our past]. Proceedings of the IEEE,
103(1):131–136, Jan 2015
98 ece3410 lecture notes

Lissajous figure for the mid-frequency case Integrator state (flux) for the mid-frequency case

100 0

50
Current (mA)

−5

vφ (V)
0
−10
−50

−15
−100
−6 −4 −2 0 2 4 6 0 10 20 30 40 50
Voltage (V) Time (µs)
Lissajous figure for the low-frequency case Integrator state (flux) for the low-frequency case

0
800

600 −50
Current (mA)

400
vφ (V)

−100
200

0 −150

−200
−200

−6 −4 −2 0 2 4 6 0 500 1,000 1,500 2,000 2,500

Voltage (V) Time (µs)
Lissajous figure for the high-frequency case Integrator state (flux) for the high-frequency case

60
0
40

−0.5
Current (mA)

20
vφ (V)

0
−1
−20

−40 −1.5

−60
−6 −4 −2 0 2 4 6 0 1 2 3 4 5
Voltage (V) Time (µs)
Figure 84: Simulation results for the integrator-based
memristor model at three different frequencies.
 memristors 99

Memristor Applications

Memristors are now known to have been used in many applica-

tions before there was a unified theory to describe them. One Anode
of the earliest practical uses was in radio receivers based on the
coherer device, that exploited the memristor’s diode-like behav-
ior. The coherer was eventually replaced by simpler vacuum
tube and solid-state diodes, and for most of the past century
memristive behavior was either ignored or expressly avoided.
Thanks to the development of Chua’s theory, we can now
identify several important applications for memristive behavior.
Today, the most promising applications are seen in Resistive Cathode
RAM (RRAM) memories and in neuromorphic circuits, which
Figure 85: Formation of a metal filament within the
mimic the activity of biological neurons. Applications are also
resistance-switching memristor.
being considered for high-speed computing, and for new types
of logic-in-memory architectures which blur the distinction
between processors and RAM.

H
RRAM

Researchers are currently studying new semiconductor memory

technologies that exploit the non-volatility of memristor de-
vices. These are based on a type of memristor called resistance
switching devices. Resistance-switching memristors are simple L
structures, often only a few nanometers across. The device has
metal plates on the top and bottom, separated by an insulator.
The top plate contains a different metal composition from the
bottom plate, which allows metal ions to migrate into the insu-
lating material. In this section, we present a simple version of H
RRAM based on resistance-switching devices. Many other types
of memristive RAM are now being researched, so this should be
viewed as an introductory example.
Thanks to the migration of metal ions, when voltage is ap- H
vs
plied in one direction, a metal filament tends to grow into the
insulator, which lowers its resistance. When the voltage is re- Figure 86: Portion of an RRAM array showing the
bias conditions for a SET operation.
versed, the filament breaks up and restores the high-resistance
state of the insulator. Due to the small dimensions of the ma-
terial, this process can occur very rapidly, so the device tends
to switch quickly between maximum and minimum resistance
levels, hence the name “resistance switching device.”
In order to read and write data from an RRAM array, we can
use a simple diode addressing scheme as shown in Figure 86.
Each memristor is connected in series with a diode. At the
nanoscale, it’s possible to make the diode “for free”, as it can be
100 ece3410 lecture notes

made from the wire connections around the memristor. Under

normal conditions, all row wires are biased at a “high” voltage
level, and all column wires are biased at a “low” voltage, so that
L
every diode is reverse-biased.
To drive a forward voltage across the memristor (called a
SET operation), we activate one single memristor by driving
its column voltage high and its row voltage low. This forward
biases the diode in that cell only, and exposes the memristor
H
to non-zero forward voltage, which drives it to its maximum-
resistance state.
To drive a reverse voltage across the memristor (called a
CLEAR operation), we bias one column connection low, while
all other columns are biased high. We then drive the cell’s row
L
voltage to a very high level, sufficient to exceed the diode’s
reverse breakdown voltage. This exposes the memristor to a
non-zero reverse voltage and drives it to its minimum-resistance
state.
To READ the data from a cell, we apply a small forward volt- L
vs
age on the column wire. The memristor then forms a voltage
Figure 87: Portion of an RRAM array showing the
divider with the column’s series resistance, allowing us to mea-
bias conditions for a CLEAR operation.
sure the memristor’s state by sampling the divider output at vs .
A high value implies high-resistance, and a low value implies
low-resistance.
It is possible that the small voltage applied during a READ
operation could alter the resistance state within the cell. For-
tunately, many resistance-switching memristors are found to
exhibit a threshold effect, so that their resistance remains undis-
turbed as long as the applied voltage remains less than some
threshold. With that type of device, we can use a READ volt-
age less than the threshold to perform a non-destructive read:
defined as measuring the device’s state without disturbing it.
To simulate an RRAM example, we first modify our memris-
tor model by adding a threshold effect. One way to do this is
to insert diodes in series with the integrator’s input. Then the
input voltage will have to exceed the diode’s 0.7 V drop in or-
der to influence the integrator’s state. The modified memristor
model, and an RRAM demonstration, are given in the netlists
below. The demonstration considers only a single RRAM cell.
The simulation results are shown in Figure 88, which
presents three transient signal traces. The top plot shows
the column voltage (red), the row voltage (green), and the
voltage seen across the memristor (blue). During a SET oper-
ation, the memristor voltage spikes to a high value, but then
quickly curves downward as the memristor switches into a
 memristors 101

high-resistance state. During the CLEAR operation, the memris-

tor shows a small negative voltage at first, but then transitions
to a larger negative voltage as the device switches to a low-
resistance state.
In between the SET and CLEAR operations, a small, brief
pulse is used to READ the memristor’s state. The pulse is kept
small in order to stay below the memristor’s threshold, so that
the state will not be disturbed. This type of small pulse is often
called a sub-threshold pulse. The middle plot in Figure 88
shows a zoomed view of the READ signals. We see that the
voltage across the memristor is higher when it is in a low-
resistance state. By measuring the voltage output, we can
deduce whether the memristor is in a high or low resistance
state, hence revealing the stored value of zero or one.
The bottom plot in Figure 88 shows the integrator state
within the memristor model, representing the device’s resis-
tance state. We see that the device switches quickly between
saturated high and low levels, and is not disturbed by the sub-
threshold READ signal.
102 ece3410 lecture notes

memristor_integrator_model_with_threshold.sp
* Memristor integrator model with threshold

* Generic diode model:

.model diode d(Is=2.0298e-15, n=1, BV=200)

* Memristor subcircuit model:

.subckt memristor nplus nminus
D2 nplus nth diode
D3 nth nplus diode
R1 nth n2 100
C1 n2 n3a 10n ic=0

* Ideal op amp model (dependent v source):

E1 n3 nmin nmin n2 10000

* Stabilizing RC network at op amp’s output:

R2 n3a n3 1
C2 n3a 0 10f

* Zener diode to constrain integrator bounds:

D1 n3a n2a diode
V1 n2a n2 DC -0.8V

* Nonlinear current source:

B1 nplus nmin i={-0.0001*(v(n3)-v(nmin))*((v(nplus)-v(nmin)))}

* Stabilizing series resistance:

R3 nmin nminus 1
.ends
 memristors 103

RRAM_threshold.sp
* Memristor resistive RAM demo

* Zener diode model:

.model zdiode d(Is=2.0298e-15, n=1, BV=5)

* Load the external memristor model:

.include memristor_integrator_model_with_threshold.sp

* Circuit for one RRAM cell:

R1 1 2 100
X1 2 3 memristor
D1 3 4 zdiode

* VH is the write-1 pulse

* VL is the write-0 pulse
* Vrd is the read pulse
VH 1 5 DC 0 PULSE (0 10 00u 10u 10u 400u 2400u)
VL 4 0 DC 0 PULSE (0 10 1200u 10u 10u 400u 2400u)
VRd 5 0 DC 0 PULSE (0 1 660u 10u 10u 30u 1200u)

* Simulation control commands:

.control
tran 100u 20m uic

* Plot write/read/memristor signals:

plot v(1) v(4) ’v(2)-v(3)’

* Plot model integrator state:

plot v(X1.n3)-v(X1.nmin)

* Plot read response:

plot ’(v(2)-v(3))*v(5)/3’ v(5)

wrdata RRAM_threshold_demo v(1) v(2) v(3) v(4) v(5) X1.n3 X1.nmin

.endc
.end
104 ece3410 lecture notes

RRAM Simulation

SET CLEAR Vcolumn

10
Vrow
Vmemristor
Voltage (V)

5
READ

−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Time (s) ·10−3

RRAM Memristor Voltage During Read

1 Vread
Voltage (V)

Vmemristor
high low
0.5 res res

0
−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time (s) ·10−3

RRAM Memristor Integrator State

0
vφ (V)

−100

−200
−0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
Time (s) ·10−2

Figure 88: RRAM simulation results using the

integrator model with threshold. This is only a
hypothetical model, but real RRAM circuits show
qualitatively similar behavior.
 memristors 105

Exploring Memristor Controversies

“A significant part of the scientific process is to vet
Since memristors are a relatively new addition to electronics descriptions of new ideas or objects, and the bigger
and circuit theory, there is naturally a fair amount of debate the potential impact of a concept, the more rigorous
that scrutiny should be. However, intertwined
among researchers and practitioners over how the theory with this process are many human issues of desire
should be interpreted. Students might be interested in hear- for recognition and priority of discovery, as well
as an often strong bias to reject anything new
ing about some of this controversy. This section provides an without actually understanding it. There are a
overview of some of the major criticisms. lot of misconceptions about memristors floating
While most researchers have accepted the basic science and around that are difficult to correct with only a few
explanatory pages. Real understanding requires a
historical narrative presented in this chapter, there are a few crit- great deal of hard work, and the resources essential
ics who remain unconvinced. Criticisms appear mainly among to achieve that understanding already exist in the
literature.”
practitioners in private industry, writers and commenters in R Stanley Williams. Aftermath of finding the
popular magazines and newspapers, and online discussions. memristor. In Memristor Networks, pages 15–19.
For example, critics have been active in editorializing their Springer, 2014

views on the Wikipedia entry for memristors. A small number

of peer-reviewed articles (less than ten) have challenged various
aspects of memristor devices and theory, compared to thou-
sands that have adopted, expanded and successfully applied the
theory. A number of very critical articles have been published in
the notorious pseudoscience server known as “vixra” (don’t be
fooled by the academic appearance of some vixra articles).
Criticisms can be divided into the following major categories:
claims of credit (i.e. who really discovered or invented it); pedan-
tic arguments (e.g. real memristors are not “ideal” enough);
philosophical disputes; and pessimism about applications.
Other arguments may be seen, including outright denial that
memristance exists, allegations of fraud, and other crankish
fringe complaints. But any worried readers can satisfy such
extreme doubts by simply purchasing a memristor array sam-
ple chip (currently $199 from Bio-Inspired Technologies) and
observing it directly.

Claims of Credit

1. Resistance-switching devices existed before Chua’s theory,

and before HP Lab’s device. They didn’t invent anything.
Since it’s now understood that memristive devices were used in
the 19th century, some critics argue that Chua’s theory “doesn’t
count” as a legitimate discovery. Critics have also questioned
the novelty of HP Lab’s discovery, since various types of thin-
film resistance-switching devices were studied going back to the
1960s. Furthermore, 1995 an Indian research group described a
device very similar to HP’s 5 . 5
HM Upadhyaya and Suresh Chandra. Polarity-
Some criticisms also mention older theories that resemble or dependent memory switching effects in the
ti/cdxpb1-xs/ag system. Semiconductor Science
and Technology, 10(3):332, 1995
106 ece3410 lecture notes

overlap with Chua’s theory on memristors. A device called the

“memistor” was studied in the 60’s, and was similarly given a
name based on “memory resistance.” It is fairly common for
competing theories to emerge in science, and subtle differences
can cause one theory to prevail while another is forgotten. The
“memistor vs memristor” argument is examined and resolved in
an article by Kim and Adhikari6 . 6
H. Kim and S. Prasad Adhikari. Memistor is not
memristor [express letters]. IEEE Circuits and Systems
Answer: So why do Chua and HP deserve so much atten-
Magazine, 12(1):75–78, Firstquarter 2012
tion? The reason is that they articulated a unifying theory.
Chua’s contributions was to express nonlinear circuit theory
as a rigorous and closed mathematical system. The major
contribution from HP Labs was to link Chua’s theory with
resistance-switching devices. As a result, researchers have been
able to refine and improve on Chua’s original theory. Critics
often claim that the Indian researchers believe that resistance-
switching devices are not memristors, but their personal beliefs
are not especially relevant to the bigger scientific question.
Thanks to contributions from hundreds of other researchers,
we now know that “memristance” is a rich concept with broad
descriptive power. It covers numerous devices and behaviors
that are awkward to describe using traditional circuit concepts,
and are absent from electronic simulators like SPICE. In the
past, useful circuit techniques may have been missed due to a
simple lack of description for these behaviors.

Pedantic Arguments

2. The memristor definition has evolved over time. There

is no “ideal memristor” matching the one first proposed by
Chua in 1971. All known memristors have some differences that
disqualify them as ideal. Real memristors are a closer match to
the expanded definition of “memristive systems” developed by
Chua in 1976. Researchers now use the term “memristor” when
they really mean “memristive system.” Critics argue that you
can’t redefine a term like that.
Answer: Sure you can. This is the process of science. A
scientific theory is not like a contract or a piece of legislation;
we expect theories and definitions to evolve as they are refined
by continuing evidence and reasoning. When critics say “there “Mathematics is an experimental science,
is no real memristor,” they are simply being dishonest. If we and definitions do not come first, but
allowed their reasoning, we could also claim there is no real later on.”
capacitor, inductor or resistor. An ideal capacitor, for example, “I do not refuse my dinner simply be-
should be able to store an arbitrary amount of charge, and it cause I do not understand the process of
should retain that charge forever if its terminals are left open. digestion.”

– Oliver Heaviside, answering criticisms of his

Laplace transform method for circuit analysis
 memristors 107

But a real capacitor will experience dielectric breakdown if it

stores too much charge. A real capacitor will slowly discharge
through leakage currents. Ergo, there is no such thing as a
capacitor, right?
The concept of memristance continues to evolve, and re-
searchers are not yet settled on the best meaning of “ideal”
memristor behavior. What it means to be “ideal” is ultimately
decided based on what is most useful for circuit analysis and
design. We haven’t yet figured everything out, and that’s just
fine. That’s what makes memristors interesting as a topic of
research.

Philosophical Disputes

3. Argument from radical empiricism: All genuine science

must originate from empirical observation, and mathematics is
useful only for the subordinate role of description. “Today’s scientists have substituted mathematics for
experiments, and they wander off through equation
Answer: As engineers, we may be tempted to embrace this
after equation, and eventually build a structure
philosophy, since the final proof always appears in the real which has no relation to reality... The scientists of
world. But if we really thought this way, it would invalidate today think deeply instead of clearly. One must be
sane to think clearly, but one can think deeply and be
most of the methods used in our profession, and in all the hard quite insane.”
sciences. A scientific theory is more than just a handy descrip-
– Nikola Tesla, arguing against Einstein’s theory of
tion of observations. The value of a theory lies in its predictive general relativity
utility: if a theory’s axioms correspond to confirmed physical
laws, then mathematical predictions from those laws should
hold true. Otherwise we have to reject or modify the theory. We are “Who the h— is still believing that memristors
therefore obligated to accept Chua’s prediction of memristors, or might exist in physical reality? By now, it should
be clear that the ‘memristor’ is nothing else but a
else we have to explain what’s wrong with the theory of circuits. mathematical curiosity. The above discussed findings
For a scientific skeptic, It’s not enough to just reject mathe- are exclusively related to resistance switching
materials (ReRAM).”
matical predictions; we have to correct the underlying theory.
Memristor critics have not proposed any changes to the theory; – “A Physicist” (online comment)
in effect, they are simply rejecting mathematics as a legitimate
foundation for hard science.
4. Argument from reductionism. Here there are two sub-
arguments: (A) that we cannot legitimately separate the def-
inition of flux in circuit theory from its magnetic field interpre-
tation; and (B) that we cannot study devices at the circuit level,
they can only be understood by studying the specific physics
and chemistry that apply within a real device.
Answer: Sub-argument (A) is elaborated in a peer-reviewed
article by Vongehr and Meng, published in Scientific Reports
with the title, “The Missing Memristor has Not been Found.”
This article postulates an elaborate scenario involving an alter-
nate universe where magnetic fields and inductors don’t exist,
108 ece3410 lecture notes

and imagines an alternative Chua (perhaps wearing a goatee

in this universe) who predicts, through mathematical analysis,
that there should be a missing device called an “inductor” that
relates current and flux. But since their universe doesn’t have
magnetic fields, it would be impossible to discover a “real” in-
ductor, even if they discovered some devices deemed similar,
those devices would not represent true inductors because they
would not possess true magnetic fields. “whatever devices would be discovered
This “thought experiment” aims toward concluding that without magnetism, none can be the real
there can be no legitimate concept of “flux” except the one EM inductor, but the latter is the grounds
associated with magnetic fields, and therefore the discovered on which the original real memristor
memristors are not “real” memristors. The authors furthermore device hypothesis sits.”
speculate that a “true” memristor is impossible, but offer no Sascha Vongehr and Xiangkang Meng. The missing
memristor has not been found. Scientific reports, 5,
concrete evidence for this conclusion, other than to speculate 2015
that we may be living the wrong universe.
Sub-argument (B) is a more generalized attack, but similar
in spirit to Vongehr and Meng’s alternate universe theory.
Proponents of this criticism argue that it’s meaningless to
define devices at the circuit level, because (i) circuit theory was
developed to study networks of already-existing devices, (ii)
generic Schottky
we can’t produce a successful device unless we understand the
detailed physics internal to that device, and (iii) the original
theoretical conception of the memristor gave no indication as to
how such a device could be realized.
Zener Tunnel
To answer these arguments, we must first observe the value
of circuit theory as an independent and complementary disci-
pline from device physics. Circuit theory is not about making
devices, it is about making complex systems. A device is only
Photodiode LED
useful to the extent that it can exist in an electronic system, so
the theory of circuits is not somehow subordinate to device
physics. As mentioned in the beginning of this chapter, circuit
theory rests directly on physical laws; it is not “derived from” Tube
Varactor
Maxwell’s electromagnetic theory. It is more correct to say that
circuit theory is the subset of electromagnetic theory that is
indifferent to fields in space. In the context of circuit theory, we
define devices by what they do at their terminals, not how they are Figure 89: Many types of diodes, with distinct inter-
nal physics. All are classified by a single unifying
made or how they work internally. concept.
A perfect example is the diode. Historically, the name
“diode” referred to a vacuum tube device that worked on the
basis of thermionic emission from a heated metal plate, facili-
tating directional conduction between two electrodes. The term
was purportedly coined by William Eccles in 1919 as a port-
manteau of “di” (two) with “electrode.” The same name was
soon used to refer to solid-state rectifying semiconductor de-
 memristors 109

vices, which operate from different physical principles. It would

be counterproductive to argue that we need different names,
or to complain that the definition of “diode” was changed to
something more broad than its original meaning. To this day,
we continue to use the name “diode” for a variety of vacuum
tube and the solid-state devices (a short list is shown in Fig-
ure 89), even though they have very different constructions and
different underlying physics. Their behavior is qualitatively the
same, and that’s what matters most for the purpose of circuit
engineering.
A more subtle example is the phenomenon of diode reverse
breakdown. When Zener hypothesized the reverse breakdown
effect, he proposed that it would be caused by quantum tun-
neling in the device 7 . When diodes are used in their reverse 7
Clarence Zener. A theory of the electrical breakdown
breakdown mode, they are commonly called “Zener diodes” to of solid dielectrics. Proceedings of the Royal Society of
London. Series A, Containing Papers of a Mathematical
honor his purely mathematical discovery. We now know when the and Physical Character, 145(855):523–529, 1934
breakdown voltage is greater than about 5 V, avalanche ioniza-
tion is the primary mechanism, not quantum tunneling. This
distinction may be relevant for optimizing a particular design
for a particular application, but from the standpoint of circuit
theory they both deliver the same qualitative behavior, and
for most purposes there’s nothing wrong with using the name
“Zener diode” to refer indifferently to both physical effects. It
would be silly to declare that “Zener was wrong” or to insist
that avalanche diodes are not “true” Zener diodes; it’s much
more useful to describe tunnel devices and avalanche devices as
subtypes of the general diode class.
Finally, to answer Vongehr and Meng’s alternate universe
scenario, imagine that we discovered a device that relates φ to
i — it stores energy and resists a sudden change in current —
but is found to contain no internal magnetic fields of any kind.
Perhaps the device is governed by electrochemical reactions or
by tiny molecule-sized demons; it doesn’t matter. What matters
is if the device’s behavior is indistinguishable from an inductor,
then for all practical purposes it is an inductor. It would be
meaningless to say that it isn’t a “true” inductor, just as it would
be meaningless to say that only vacuum tubes are “true” diodes.

Pessimism

5. Non-volatile memristors are impossible. Some researchers

have argued that memristors’ internal states could be disrupted
by noise processes. If that’s true, then it will not be possible
to store information indefinitely in a memristor memory cell,
110 ece3410 lecture notes

and RRAM will not work as a replacement for Flash devices.

This argument is put forward by Meuffels and Soni in a draft
available at the arxiv server8 (note that arxiv papers are not peer 8
Paul Meuffels and Rohit Soni. Fundamental issues
reviewed). and problems in the realization of memristors. arXiv
preprint arXiv:1207.7319, 2012
The article has been cited by a few peer-reviewed articles,
and may have some validity. But several critics have also
claimed this analysis as evidence that memristors are “im-
possible” as real devices. Their reasoning is that a memristor is
supposed to be non-volatile, meaning it should remember its
resistance state indefinitely. If Meuffels and Soni showed that
permanent memory is unlikely, then the memristor must be
impossible, right?
Answer: We already used an identical argument to prove
that capacitors are impossible, since their charge tends to leak
away. This argument describes the same kind of problem that
we see in DRAM: stored information is temporary. For this
reason, DRAM memories require a refresh operation to periodi-
cally re-write the stored information. Perhaps memristor-based
RRAMs will also require a refresh operation. Perhaps that will
make RRAMs less competitive compared to other memory
technologies. That could all be true, but at most it means that
memristors will be disappointing in the RAM market. It doesn’t
have anything to do with memristors being “impossible” de-
vices. It just means that the non-volatility property is temporary
in ressitance-switching devices.

Conclusion

Memristors are a fascinating area of current research in both the-

ory and experiment. This chapter has introduced only the most
basic facts about memristors. We examined and answered a few
of the major arguments that have generated some controversy
on the topic. One can find many more arguments circulating
in the wild, but the ones listed here are deemed by the author
to be the strongest criticisms. The current scientific consensus
is that memristors comprise a legitimate theory bolstered by
numerous real devices and phenomena. The reader can gain
direct experience by purchasing a resistance-switching sample,
or by constructing a replica coherer device, or by studying one
of the biochemical substances that are now known to exhibit
memristive behavior. More advanced resistors are dangerous to
manufacture without proper facilities, so students are urged to
exercise caution in their explorations.
 iD
Drain (D)

Introduction to MOSFETs +

Gate (G) v DS
+

Why do we need transistors? vGS

−
−
Source (S)
Diodes can perform logic operations, but they cannot perform:
iD
• NOT, NAND or NOR operations – diode logic gates are not
universal! Figure 90: NMOS device symbol, showing the
device’s three major terminals. Current flows
• Amplification – signals attenuate as they pass through diode between the drain (D) and source (S) terminals,
networks, so large-scale systems are impossible with diodes and is controlled by the gate (G), like a valve. A
fourth terminal. known as the bulk, body, or substrate,
alone. is not shown. The substrate is usually shared by
many devices, and for NMOS devices it should
Amplification is the fundamental characteristic needed for be connected to the circuit’s most negative potential
logic circuits – the device must be able to deliver more energy at (usually ground or VSS .
its output than provided at its input.

MOSFET as switch
The MOSFET has three terminals, source, gate and drain. We iD

may first understand the MOSFET as a logic switch. In this Source (S)
+
model, the terminal potentials are interpreted as logic val- +
|vGS |
ues, i.e.the logic set {0, 1} is mapped to the potential values
{0, VDD }. Under this model we may consider all signals to be −
Gate (G) |v DS |
either HIGH or LOW. Then the behavior is as follows:
Device Type vG Device State v DS
NMOS HIGH ON small −
Drain (D)
LOW OFF large
iD
PMOS HIGH OFF large
LOW ON small
Figure 91: PMOS device symbol, which is comple-
Notice two things: mentary to the NMOS device. The drain and source
terminals are flipped (current is understood to flow
• The NMOS and PMOS have complementary behavior, i.e. they vertically downward from the source to the drain). A
“bubble” is commonly drawn at the gate to indicate
have opposite states in response to the gate voltage. that the device responds to the logical complement
of the gate signal. For PMOS devices, the substrate
• When the device is ON, the drain-source voltage v DS must be is usually connected to the circuit’s most positive
quite small. When the device is OFF, the drain-source voltage potential (usually VDD .
can be large. This is the behavior we expect from a switch.
112 ece3410 lecture notes

MOSFET as a current source

The MOSFET is an analog device, meaning it does not merely

have “OFF” and “ON” states, but has a continuous range of
in-between states. If a MOSFET is balanced in an “almost-on”
state, known as its saturation mode, it produces an approx-
imately constant current. Therefore we can use a MOSFET
device to implement a DC current source.
In practice, an NMOS device first begins to switch ON when
its VGS crosses a device-specific threshold voltage, VTh . When VGS
is just slightly above VTh , the device enters its saturation mode.
If VGS is increased, the current increases. If VGS is held constant,
the current stays constant. If we keep increasing VGS , the device
eventually turns fully ON, at which point it no longer acts like a
current source, and behaves more like a small resistor.
In the PMOS case, the device first begins to switch ON when
its VSG voltage exceeds the device’s VTh , which places the device
in its saturation mode. The behavior is again complementary
to the NMOS: as VG is lowered, VSG increases, and the cur-
rent increases. Eventually, when VG becomes low enough, the
PMOS device turns fully ON and no longer works like a current
source.
If the MOSFET is balanced in its saturation mode, and a
time-varying signal is applied to the gate, the device’s current
will change in response to the gate signal. Hence the MOSFET
in saturation is considered to be a transconductance amplifier:
it produces a current output (at the drain) in response to a
voltage input (at the gate).
One of our key design tasks will be to balance the MOSFET
in the appropriate mode for our intended application. When
making switching circuits, we want the MOSFET to be toggle
between ON and OFF states. When making a current source or
an amplifier, we want the MOSFET to be suspended in between,
in its saturation mode, with a relatively small value of VGS (for
NMOS) or VSG (for PMOS).
R

Electrical Characteristics
vOUT

The MOSFET is of course more complicated than the switch

vIN
model implies. To get a more detailed picture of MOSFET be-
havior, we may consider an alternative invterter circuit known
as the resistor-transistor logic (RTL) configuration. The RTL
circuit is inferior to the CMOS configuration in that it draws
Figure 92: NMOS RTL inverter configuration.
static power when the NMOS device is ON. This is because
 introduction to mosfets 113

5
the MOSFET must pull a constant current through the resistor
R in order to maintain a low output voltage. It is nevertheless
helpful to study the RTL inverter, because its properties are 4 I II

somewhat easier to analyze than the CMOS design.

The RTL inverter’s DC transfer characteristic is split into 3

vOUT
three regions, representing the different modes of the NMOS
device: 2 VTh

I Cutoff— When vIN is below the devices threshold, VTh , it is

1 III
considered OFF and behaves like an open circuit between the
Drain and Source.
0
II Saturation — When vIN is slightly greater than VTh , the de- 0 1 2 3 4 5
vIN
vice is partially turned ON. The output voltage is determined
Figure 93: Transfer characteristic of the RTL inverter
by the current through the MOSFET, which depends strongly obtained from a SPICE simulation, showing the
on vIN . operating modes (I) Cutoff, (II) Saturation and (III)
Triode.
III Triode — The device is considered fully ON when vOUT <
vIN − VTh . In this mode, the Drain and Source are almost
short-circuited.
The precise behavior of a MOSFET device is modeled by
three different equations corresponding to three operating
modes. The equations are qualitatively different, but they
should be piecewise continuous (i.e. they should connect at the
boundaries between each mode). These equations relate the
device’s drain current, iDS , to the gate-source and drain-source
voltages vGS and vDS , respectively. To simplify the equations, we
define the Overdrive Voltage as
vOV , |vGS | − |VTh | .
Then the device equations are:
I Cutoff — vOV ≤ 0:
iDS = 0

II Saturation — vOV > 0 and |vDS | > vOV :

1 2
iDS = kv .
2 OV
III Triode — vOV > 0 and |vDS | ≤ vOV :
 
1 2
iDS = k vOV |vDS | − |vDS | .
2

In these equations, k is a scale constant with units µA/V2 ,

and is typically on the order of 100 µA/V2 to 1 mA/V2 . The
threshold voltage is a manufacturing parameter that varies
widely between different technologies. It is typically between
0.4 V and 2 V.
114 ece3410 lecture notes

NMOS RTL Inverter Analysis

Considering the NMOS RTL inverter shown above, suppose

VTh = 2 V, k = 100µA/V 2 , R = 100kΩ and VDD = 5 V. Given the
model equations above, solve for the DC transfer characteristic 5
of vOUT as a function of vIN .
Solution: We may divide the analysis into the three regions, 4 I II
and determine the points where these regions meet. Since the
MOSFET’s source terminal is tied to ground, we observe that 3

vOUT
vGS = vIN and vDS = vOUT . If we imagine that vIN is initially
zero, and is slowly increased toward VDD , then we have three 2 VTh
subproblems:

I Cutoff— When vIN < VTh , verify that vOV < 0, therefore 1 III
iDS = 0. In that case, there is no current flowing through R, so
vOUT = VDD = 5 V. 0
0 1 2 3 4 5
vIN
II Saturation — When vIN > VTh , then vOV > 0 and the device’s
Figure 94: Comparison of analysis and simulation re-
current is given by the square-law equation. Then vout is sults in the three operating modes, cutoff, saturation,
determined by the voltage drop across R: and triode.

1
vOUT = VDD − Rkv2OV
2
= 5 V − 5 (vIN − 2 V)2
As vIN increases, vOUT will decrease until the MOSFET enters
the triode mode. That transition happens when vOUT = vOV ,
i.e.
1
vOV = 5 V − Rkv2OV
2
1
⇒ 0 = Rkv2OV + vOV − 5
2
Since the result is a quadratic equation, we can apply the
standard formula and solve:
r  
−1 ± (1)2 − 4 12 Rk (−VDD )
vOV =
√ Rk
−1 ± 1 + 2RkVDD
=
r Rk
2VDD
if 2Rk  1 : vOV ≈
Rk
Note that we chose the positive result in the quadratic equa-
tion, since vOV has to be positive in both saturation and triode,
otherwise these equations wouldn’t apply. The results are:

exact: vOV = 0.905 V

approx: vOV ≈ 1 V
 introduction to mosfets 115

And the corresponding values of vIN are:

exact: vIN = 2.905 V

approx: vIN ≈ 3 V

III Triode — When vIN > 2.5188 V, the device should enter
triode, and the new device equation is
 
1 2
iDS = k vOV vOUT − vOUT
2
 
1 2
⇒ vOUT = VDD − Rk vOV vOUT − vOUT
2

Once again we can arrange this in the form of a quadratic

equation:

1
0= Rkv2OUT − (1 + RkvOV ) vOUT + VDD
2 q
(1 + RkvOV ) ± (1 + RkvOV )2 − 2RkVDD
vOUT =
q Rk
(1 + RkvOV ) − 1 + ( RkvOV )2
=
Rk
Note that if RkvOV  1 the equation simplifies to vOUT = 0.
116 ece3410 lecture notes

PMOS RTL inverter analysis

In the PMOS version of the RTL inverter circuit, the circuit is
“flipped upside down” and the behavior is transposed. The vIN
circuit’s logical behavior is the same as the NMOS version, but
the fine details are changed. We see that the cutoff, saturation vOUT
and triode regions now appear in different places:
In this configuration, we start by solving for |vGS |, |vDS | and
R
vOV in terms of the terminal signals:

|vGS | = VDD − vIN

|vDS | = VDD − vOUT
Figure 95: PMOS RTL inverter configuration.
vOV = |vGS | − |VTh |

We may then proceed with the same analysis steps as before,

only this time we imagine that vIN starts at VDD and is slowly
decreased down to zero.
5
I Cutoff— When vOV < 0, the MOSFET is OFF so that iDS = 0.
In that case, there is no current flowing through R, so vOUT =
4 III VDD − |VTh |
0. This describes the region where vIN > VDD − |VTh |.

II Saturation — When vOV > 0 and |vDS | > vOV , the device’s 3
vOUT
current is given by the square-law equation. This corresponds
to the case when: 2

VDD − vOUT > VDD − vIN − |VTh |

1 II I
⇒ vOUT < vIN + |VTh |

In this region, vout is determined by the voltage drop across R: 0

0 1 2 3 4 5
1 vIN
vOUT = Rkv2OV
2 Figure 96: DC transfer characteristic obtained from a
= 5 (VDD − vIN − 2 V)2 SPICE simulation of the PMOS RTL inverter.

As vIN decreases, vOUT will decrease until the MOSFET

enters the triode mode. That transition happens when VDD −
vOUT = vOV , i.e.
1
vOV = 5 V − Rkv2OV
2
1
⇒ 0 = Rkv2OV + vOV − 5
2
Notice that this is the same quadratic equation we obtained
for the NMOS circuit, so we can borrow the results from
before:

exact: vOV = 0.905 V

approx: vOV ≈ 1 V
 introduction to mosfets 117

5
And the corresponding values of vIN are:

vIN = VDD − vOV − |VTh | 4 III VDD − |VTh |

exact: vIN = 5 V − 2.905 V = 2.095 V

3
approx: vIN ≈ 5 V − 3 V = 2 V

vOUT
2
III Triode — When |vDS | < vOV , the device enters triode. This
corresponds to the case where
1 II I
VDD − vOUT < VDD − vIN − |VTh |
⇒ vOUT > vIN + |VTh | 0
0 1 2 3 4 5
vIN
or when vIN < vOUT − |VTh |
Figure 97: Comparison of analysis and simulation
results for the PMOS RTL inverter.
In this region, the device’s current and output voltage change
as follows:
 
1
iDS = k vOV |vDS | − v2DS
2
 
1
⇒ vOUT = Rk vOV |vDS | − v2DS
2
 
1 2
⇒ VDD − |vDS | = Rk vOV |vDS | − vDS
2

Once again we can arrange this in the form of a quadratic

equation, but this time we will simplify the equation by
leaving it in terms of vDS , so we get:

1
0= Rkv2DS − (1 + RkvOV ) |vDS | + VDD
2 q
(1 + RkvOV ) ± (1 + RkvOV )2 − 2RkVDD
|vDS | =
q Rk
(1 + RkvOV ) − 1 + ( RkvOV )2
=
Rk
Notice that this is the exact same result as before, only it’s
“upside down.” We can next get the solution for vOUT :

vOUT = VDD − |vDS |

q
(1 + RkvOV ) − 1 + ( RkvOV )2
= 5V−
Rk

Finally, if we suppose RkvOV 1  1 then vOUT → VDD .

118 ece3410 lecture notes

Comparison of NMOS and PMOS versions

4
Our results show that both the NMOS and PMOS configura- NMOS

vOUT
tions have the same qualitative behavior. They both function
2 PMOS
as logic inverters. If we were to balance one of these circuits
right in the center of its saturation region (II), where the slope
is very steep, we could use it as an inverting amplifier. We will 0
0 2 4
soon introduce linearized amplifier models that apply in the vIN
saturation region; it will be important to recognize that both Figure 98: Overlay of the NMOS and PMOS RTL
NMOS and PMOS devices have the same linearized models in inverter transfer characteristics. Both devices behave
as an inverter. They differ slightly in the offset
saturation, just as they show the same behavior in the RTL in- voltage at which they “tip” from high to low.
verter configurations, even though they exhibit complementary
iDS
logical behavior.

Behavior in Saturation +
vDS −
+
We may now go one level deeper and examine the MOSFET’s −
behavior in the saturation mode. First, let’s understand why it’s
called “saturation.” Suppose we hold the gate potential fixed so
that vGS = 1 V and perform a DC sweep on vDS while measuring Figure 99: An experiment in which vGS is held
the current. constant while sweeping v DS .
According to the triode equation, the current should be a
parabola:  
1 2
iDS = k (1)vDS − vDS .
2
But if that were true, the current would begin to decrease when
60
vDS > 1 (dashed curve below), and eventually the current would
swing negative, creating an impossible free-energy device. 40
Obviously this doesn’t happen, instead the device current rises
iDS (µA)

monotonically until it reaches the peak of the parabola, and 20

then flattens out at higher vDS (solid curve). This is why it’s
0 free
called “saturation”: when vDS is swept from zero, iDS increases energy!
until it saturates at a maximum value. −20
0 1 2 3
Since the saturation current is approximately constant, we vDS
may interpret the MOSFET as a nonlinear voltage controlled Figure 100: The triode equation predicts decreasing
current source that depends on the gate voltage. For a first- current when vOV > vDS (dashed line). Physical laws
dictate that the current should be non-decreasing as
order circuit analysis, we can replace the MOSFET symbol with vDS is increased, so the current saturates at a nearly
a dependent current source. When a small signal is applied at constant value.
the gate, we can write the gate voltage as a superposition of the
DC signal (VG ) and the small signal (v g ). In that case we can
linearize the current source by solving the first-order Taylor
approximation:
 !
d i D 
i D ≈ VGS + vgs .
d vgs VGS
 introduction to mosfets 119

It will often be useful to analyze the small-signal equivalent

circuit, which is obtained from the linearized model by zeroing
Drain
out DC independent sources. For this purpose we may simplify
the expression: Gate
 ! +
d i D 
id ≈ vgs . vGS gm vgs
d vGS VGS

Since the MOSFET takes a voltage as input and produces a −

current as output, it is conventionally interpreted as a transcon-
ductance amplifier. The amplifier’s transconductance gain, Source
conventionally denoted as gm , is defined as the derivative of i D
Figure 101: The MOSFET behaves like a dependent
with respect to vGS :  current source controlled by the gate-source voltage.
d i D 
gm ,
d vgs VGS 200

Then we can write the device’s small-signal behavior as simply

150
id = gm vgs .
vOV = 1.5V

iDS (µA)
Channel Length Modulation 100

In a real MOSFET device, the saturation current is not perfectly

vOV = 1.0V
constant with increasing vDS . Instead, we see an approximately 50
linear increase with vDS , which can be partially explained as
vOV = 0.5V
a variation in the MOSFET’s channel dimensions. From the
circuit perspective, this behavior is modeled by augmenting the 0
0 1 2 3
square-law equation with a “fudge factor” λ: vDS (V)

1 2 Figure 102: Transfer characteristic of i D vs vDS for

iDS = kv (1 + λ |vDS |) .
2 OV an NMOS device at three different values of vOV .
The slope is not completely flat in the saturation
Typically λ is in the range from 0.01 V−1 to 0.1 V−1 . When region. This means the device should have a finite
including channel length modulation (CLM), the curves are not differential resistance when in saturation.

completely flat in saturation. Drain

Since we consider the MOSFET to be a transconductance
amplifier, we can interpret the slope due to CLM as the output Gate
+
resistance:   −1
gm vgs

d i D  vGS ro
ro , .
d vDS DC
−
In this definition, the derivative is evaluated at the DC operat-
ing point, which encompasses all the DC values of VGS , VDS and Source
ID .
Figure 103: When CLM is included, it appears as an
output resistance in the transconductance amplifier
Calculating gm and ro model.

The transconductance and output resistance can be calculated

in a few different ways. We could measure these parameters
experimentally by using an ammeter to observe the changes
120 ece3410 lecture notes

in i D that result from small variations in vGS and vDS . For hand
analysis, we can directly integrate the device equations:
 
d iD d 1
k (vGS − VTh )2 

=
d vGS d vGS 2 DC
= k (VGS − VTh )
= kVOV

This tells us that the transconductance gain is directly propor-

tional to the DC overdrive voltage. Summary, Saturation Mode
In practice, it is often easier to select a DC bias current ID ,
Large Signal:
rather than to directly control VOV . In that case, it is useful to
vOV = |vGS | − |VTh |
express gm in terms of ID :
1 2
iD = kv
2 OV
q
kVOV = k (k VOV 2)
when |vDS | > vOV
p
= 2k ID and vOV > 0.
Small-Signal:
This expression tells us that the transconductance gain is pro-
gm = k VOV
portional to the square root of the DC bias current. p
= 2k ID
Lastly, to calculate the output resistance we need to consider
r o = ( λ ID ) −1
CLM:
   −1
d 1 2 
ro = kvOV (1 + λ vDS ) 
d vDS 2 DC
  −1
1 2
= kv λ
2 OV
1
=
λ ID
This expression tells us that the output resistance is inversely
proportional to the bias current. Since the transconductance
√
increases with ID , there is a tradeoff between transconduc-
tance and output resistance. This tradeoff will have important
consequences for practical circuit design.

Some important DC configurations

There are a few patterns that appear frequently in MOSFET VDD

circuits, and it will be useful to have their solutions available for
reference. The two major cases are the diode connection and the ID
passive resistor bias network. The third case is a combination R
of the first two. Additional configurations can be understood as
VD
special cases of these three configurations.
Diode connection: When the MOSFET’s gate is directly
connected to the drain terminal, it is referred to as a “diode
connection.” In this configuration, the drain terminal provides

Figure 104: Diode-connected NMOS device.

 introduction to mosfets 121

a negative feedback loop to the gate terminal, so that the circuit

settles into a stable DC state. Since vGS is determined by the
voltage drop across R, which is in turn determined by the
current ID , the solution is governed by feedback:

VGS = VD = VDD − ID R
1 2
ID = kV
2 OV
1
= k (VDD − ID R − VTh )2
2
√
To complete the solution, we define a variable x = ID , and The diode connection is guaranteed to always be in
then arrange the above equation into a quadratic equation: the saturation mode, since VDS = VGS it is always
assured that VDS > VOV .
r r
k 2 k
R x +x− (VDD − VTh ) = 0
2 2
Applying the quadratic formula:
p
−1 ± 1 + 2kR (VDD − VTh )
x= √
R 2k
 p 2
−1 + 1 + 2kR (VDD − VTh )
⇒ ID = x 2 =
2kR2

EveryCircuit Demonstration 20 (Diode connected NMOS device).

A diode connected configuration is implemented with VDD = 5 V, R = 50 kΩ, and the MOSFET param-
eters are k = 500 µA/V2 , VTh = 0.5 V and λ = 0.05 V−1 . The analysis from this section predicts a bias
current of ID = 78.8 µA, which is quite close to the simulated value. We can also verify that the gate
voltage should be VG = 1.06 V, which is again quite close to the simulated result.
122 ece3410 lecture notes

Passive bias network: In this very general case, resistors are VDD
placed adjacent to both the source and drain terminals, and the
gate is biased at some constant voltage, such that the device is RD
held in its saturation mode. There are interactions at both the VD
drain and source terminal: ID
VG
VD = VDD − ID R D
VS = ID RS
VS
1
ID = k (VG − ID RS − VTh )2 RS
2
we solve this case in much the same way as the diode-connected
√
circuit. By defining x = ID , we can obtain a quadratic polyno-
mial:
r r
k 2 k
0 = RS x +x− (V − VTh )
2 2 G
p
−1 ± 1 + 2kRS (VG − VTh )
⇒x= √
RS 2k
and ID = x2 .

EveryCircuit Demonstration 22 (NMOS bias network).

A NMOS passive bias configuration is implemented with VDD = 5 V, R D = 50 kΩ, RS = 20 kΩ,

VG = 1.25 V, and the MOSFET parameters are k = 500 µA/V2 , VTh = 0.5 V and λ = 0.05 V−1 .
The analysis from this section predicts a bias current of ID = 22.5 µA, which is quite close to the sim-
ulated value. We can also verify that the source voltage should be VS = 0.45 V, and the drain voltage
should be VD = 3.875 V. We can then verify that the device is biased in saturation since VDS = 2.44 V
whereas VOV = VG − VS − VTh = 0.3 V. All of these calculations are very close to the simulation results.
 introduction to mosfets 123

VDD
MOSFETs as Switches

Many digital and mixed-signal applications use MOSFET

devices as logic switches. Like all devices, MOSFETs make
imperfect switches, but with careful design they can be used to vD
realize complex and efficient logic circuits. When operated as
a switch, we will primarily use the triode and cutoff operating
modes, corresponding to ON and OFF states, respectively.
vG
Cutoff is easy to understand: the device is OFF, no current flows
between the source and drain terminals, and we can treat it like
an open circuit. (a)
The ON behavior is more complicated. When a MOSFET VDD
switches ON, it usually transitions into the saturation mode first
before settling into the triode mode. In some configurations,
the MOSFET may be prevented from entering triode, making it
“stuck” in saturation, where it performs poorly as a switch. As
vS
an example, consider the two scenarios shown in Figure 105.
vG
The pull-down configuration is basically identical to the
NMOS RTL inverter circuit. We now include the presence
of a parasitic capacitance at the MOSFET’s drain node. This (b)
capacitor must be charged or discharged in order to change the
Figure 105: An NMOS device in (a) pull-down
drain voltage. As a result, the circuit’s transient behavior will configurration, and (b) pull-up configuration.
look somewhat like the DC behavior we saw before. Suppose
the device is initially OFF, and the capacitor at v D is initially
charged to VDD . Then, when vG transitions from zero to VDD , the
NMOS device is initially in cutoff. Once vG crosses the device’s
threshold voltage, it enters the saturation region and begins to
draw current that discharges the capacitor at v D . After some
time, the capacitor is discharged enough so that the device
enters triode, and eventually it may be discharged to zero.
The pull-up configuration doesn’t work as well. Suppose
that the NMOS device in Figure 105(b) is initially OFF, and the
capacitor is initially fully discharged so that vS = 0 V. Then
when vG switches from zero to VDD , the NMOS device begins
to turn on. But since v D = VG = VDD , it will never cross into
triode because vDS > vGS − VTh , regardless of what happens
at vS . Therefore as the device tries to pull up vS , its current is
governed by the square law, i D = k v2OV . As the capacitor charges
up, vOV eventually goes toward zero. In the end, the capacitor
cannot be charged any higher than

vs, max = VDD − VTh ,

because this is the voltage where vOV becomes zero, and device
switches OFF.
124 ece3410 lecture notes

The behavior of a PMOS device is similar but complementary.

PMOS devices pull-up well, but are not able to pull down.
When a PMOS device is used to pull down a signal, the best
it can achieve is a source voltage equal to |VTh |. The PMOS
analysis is identical to the NMOS analysis.

EveryCircuit Demonstration 24 (NMOS RTL inverter).

This example shows the NMOS RTL inverter configuration. THe transient simulation shows that
when the NMOS device is ON, the active pull-down is very fast and effective. When the NMOS
device is OFF, however, the passive pull-up operation is very slow due to the RC delay. Note that this
example uses a manual switch to change the input signal. You have to click it to change the state.

EveryCircuit Demonstration 26 (NMOS pull-up and pull-down).

This circuit shows a combination of the pull-up and pull-down configurations shown in Figure 105.
The two configurations are folded together, so there is no resistor current to overcome. The simula-
tion shows that the NMOS device pulls down very well, but the pull-up operation is both slow and
incomplete. A PMOS pull-down example is also available, showing the complementary behavior.

Ideal CMOS Inverter VDD

MOSFET switching behavior is exemplified by the CMOS

inverter circuit, which is the simplest logic gate. When the
input (gate) voltage is high, the NMOS device is ON while
the PMOS device is OFF. The NMOS device pulls the output in out
low while the PMOS device does nothing. When the input is
low, the NMOS device switches OFF while the PMOS device
switches ON, pulling the output high. This results in a very
clean logic inverter behavior. More importantly, when the gate
is idle (not switching), there is no current through either the
NMOS or PMOS device, so we say there is zero static power Figure 106: Standard CMOS inverter circuit.
dissipation. Power is only dissipated during switching, when a
small amount of energy must be expended to change the output
voltage.
 introduction to mosfets 125

Static CMOS Logic

The most successful and widespread application of MOSFET

devices is CMOS logic, which is the foundation of modern dig- A
A B
ital electronics. The majority of CMOS logic circuits are based B
on the static CMOS gate structure, which uses a PMOS pull-up Q
Q
network in parallel with an NMOS pull-down network.
A
Static CMOS gates are based on four basic principles:
A

• Series (stacked) MOSFETs implement an AND operation B

B

• Parallel MOSFETs implement an OR operation

Figure 107: CMOS NAND gate and its logic inter-

• NMOS devices invert their outputs (i.e. place a bubble at the
pretation. The PMOS pull-up network uses two
network’s output port) devices in parallel, representing an OR function with
inverted inputs. The NMOS pull-down network uses
two devices in series, representing an AND function
• PMOS devices invert their inputs (i.e. place bubbles at the with inverted output. By de Morgan’s Laws, these
network’s input ports). functions are equal, but complementary.

By using De Morgan’s Laws, we can transform any logic

function into a PMOS network and an NMOS network, then
NAND
short their outputs together. According to de Morgan’s Laws, a ⇐⇒
NAND gate is equivalent to an OR gate with inverted inputs,
A+B ( AB)
and a NOR gate is equivalent to an AND gate with inverted
inputs.
So to produce a gate with some desired function F, we start
with a logic gate implementation, and then apply transforma-
NOR
tions to create two versions: one with a single bubble at the
⇐⇒
output (for the NMOS network), and another with bubbles on
all the top-level inputs (for the PMOS network). In both net- ( A)( B) ( A + B)

works, there should be no bubbles in the connections between

Figure 108: De Morgan’s Laws: ( AB) = A + B and
gates. We can also insert inverters onto the inputs and outputs ( A + B) = ( A)( B).
in order to complement them as needed.
In the process of obtaining the PDN and PUN circuits, sev-
eral circuit transformations are allowed. The basic gate conver- AND
sions from de Morgan’s Laws are always permitted, as are the ⇐⇒
alternative transformations shown in Figure 109. If a bubble
A+B ( AB)
is present on a connection, it can be moved to the other end of
the connection, where it might be useful for applying a gate
transformation. We can also insert “double bubbles” by placing
a bubble at the start and end of a connection. Double bubbles
OR
can also be removed if needed, since they cancel each other out. ⇐⇒
( A)( B) ( A + B)

Figure 109: Alternative version of de Morgan’s Laws:

AB = A + B and ( A + B) = ( A)( B).
126 ece3410 lecture notes

Example 21 (Static CMOS logic design).

Suppose we are given a four-input logic function F = A( B + CD ). To synthesize a static CMOS imple-
mentation, we begin with a classic logic circuit, and then apply de Morgan’s laws to transform it:

C
D
B F C
A
1A. PMOS PUN: Using de Mor- D
B F
gan’s Laws, make gate transforma- A
tions to insert bubbles at the signal
inputs.

C
D
B F
A A B
1B. Cancel the double-bubbles and add an
inverter to eliminate the output bubble. D
Now there should be bubbles on all input
signals, but no interior bubbles. C

C
D
B F
A
2. NMOS PDN: Since there are already no interior bubbles,
simply place a bubble on the output signal and cancel it with
an inverter. Now both the PUN and PDN have inverters at A
the output; for the transistor implementation, we ignore the F
inverters. An inverter will be attached to the gate’s output after
we are finished.

4. Transistor implementation: For both networks, begin on the

left-most gate and compose a heirarchical structure. OR means
a parallel connection, AND means a series (stacked) connection.
C
Once the structures are built, connect the PMOS and NMOS
networks together in the middle. Connect VDD to the top of B
the PMOS network, and ground to the bottom of the NMOS D
network. Lastly, insert any needed inverters to complete the
circuit.
 introduction to mosfets 127

Example 22 (Static CMOS XOR gate).

The Exclusive OR (XOR) function is crucial for many logic and arithmetic circuits. The function is
F = A ⊕ B = AB + AB. To synthesize a static CMOS XOR gate, we begin with a classic logic circuit,
and then apply de Morgan’s laws to transform it as follows:

A
B 1. PMOS PUN: Just com-
F plement two of the input A
A signals to get bubbles on B
B all of them. F
A
B

2A. NMOS PDN: Transform one gate

to get a bubble on the output.
A
B
F
A A
A
B
A A
B B
2B. Move the nuissance bubbles, and
complement two input signals so
the left-side AND gates are fully
surrounded with bubbles. F
A
B
F
A A B

2C. Transform the left-side AND B B

gates to eliminate the bubbles.
A A B
B
F
A
B
3. To complete the transistor implementation, we proceed as before and implement AND gates as
stacked connections, while OR gates are parallel connections. The PUN consists of two stacks (from
the left-side AND gates) connected in parallel. The PDN consists of two parallel connections, stacked.
Inverters are inserted to produce A and B (all of the signal wire connections are not shown). In total,
12 transistors are needed.
128 ece3410 lecture notes

Transmission Gates φ

In order to make a general-purpose switch that can be used for

both pull-up and pull-down operations, we can simply connect
PMOS and NMOS devices in parallel. This circuit is commonly a b
called a transmission gate. It acts as a passive switch, meaning
it cannot directly provide energy to its terminals, it can only
transfer energy.
φ
Transmission gates are useful for efficiently realizing several
types of logic gates. For example, transmission gates provide Figure 110: A CMOS transmission gate acting as
one of the simplest realizations for the exclusive-OR (XOR) a switch between nodes a and b. The switch is
gate. Transmission gates also provide a natural realization for controlled by a logic signal φ ∈ {0, VDD } . The switch
is ON when φ is high. An inverter is required to
multiplexor (MUX) gates. produce φ, which is needed to switch the PMOS
device.

Analog Switching
A
In addition to digital applications, transmission gates are useful
for switching analog signals. One common application is the
track and hold (T/H) circuit, which serves as the front-end for B
many sampling circuits, such as analog-to-digital converters.
The most basic T/H circuit contains only a capacitor and switch.
When the switch is ON, the capacitor “tracks” the voltage of Q
the input signal. When the switch is OFF, the capacitor is left
floating. In this condition, no charge can be added or removed
from the capacitor, so it “holds” whatever voltage it contained
at the moment when the switch turned OFF.
When a T/H circuit is used to sample a slow-changing ana-
log signal, then there will usually be a small signal difference
between each sampling event. As a result, |vDS | will tend to be Figure 111: XOR gate based on transmission gates.
small each time the transmission gate is switched ON, so the The logic function is Q = AB + AB. This circuit
devices start out in triode rather than saturation. This scenario requires a total of eight MOSFETs.

is an example of small-signal switching. When the devices are

ON, it is useful to think of them as approximate resistors, where
the resistance is
d i D −1
 
rON ,
d vDS DC, triode
  −1
d 1 2
= k vOV vDS − vDS
d vDS 2 DC
= [k (VOV − VDS )]−1
When the device is fully ON, VDS may be very small. In switch-
ing applications, VOV is always VDD − VTh , so for a fully-ON device
we can say that the small-signal equivalent resistance is
1
rON = .
k (VDD − VTh )
 introduction to mosfets 129

Lastly, for a transmission gate, the equivalent resistance is

the parallel combination of the rON values for the NMOS and
PMOS devices.

EveryCircuit Demonstration 28 (Transmission gate track-and-hold circuit).

This circuit implements a passive T/H circuit based on the transmission gate switch. The circuit has
supply voltage VDD = 5 V and a 100 nF hold capacitor. The device parameters are as follows:

NMOS PMOS
kn = 500 µA/V2 kp = 250 µA/V2
VThN = 0.5 V VThP = 0.5 V
λn = 0.05 V−1 λp = 0.1 V−1

Based on these parameters, the triode ON resistance should be

rON, n = [k n (VDD − VThN )]−1

= 444 Ω
  −1
rON, p = k p (VDD − VThP )
= 888.9 Ω

In parallel, the total ON resistance for this switch should be rON = 296 Ω. When the switch is turned
ON, the output signal’s rise time is determined by the time constant formed by rON and C, which
works out to be τ = 29.63 µs. Then the 10–90% rise time is tr = 2.2τ = 65.2 µs. This gives an indica-
tion as to the minimum switching period for this T/H circuit. In practice, 10–90% is not sufficient to
obtain a high-precision sample, so a switching period five to ten times slower may be required.
The simulation example shows an input signal at 100 Hz with a switching period of 500 µs, which is
almost 10× higher than the calculated rise time. By zooming in on the waveform, you can see that
the tracking accuracy improves gradually with more time in the tracking phase. The slow conver-
gence is a direct consequence of the ON resistance in the transmission gate.
130 ece3410 lecture notes

MOSFETs as Amplifiers

We saw previously how the MOSFET device can be interpreted

R
as a transconductance amplifier: the input signal is vGS , and the
output signal is i D . We can build on this concept by configuring
vOUT
the MOSFET in several ways to make different types of ampli-
fiers. In all cases, we will deliberately operate the device in its vIN
saturation mode, balanced between its ON/OFF states.
vin

Common-Source Configuration
+
VIN −
As a first example, we consider the RTL inverter circuit, only
now we will try and balance the circuit at the point where
its transfer characteristic is steepest. We refer to this as the vout
quiescent point, Q point, bias point, or DC operating point.
vin
We then superimpose a small AC signal on top of the DC +
operating point. Amplifier design is therefore divided into two
vgs = vin gm vgs ro R
tasks: biasing and small-signal analysis. We’ll consider biasing
strategies later. In this section we focus on basic small-signal
−
analysis techniques, as they dictate amplifier behavior and
potential applications.
To begin with, we consider the common-source configura-
tion and assume it is appropriately biased at a suitable DC Figure 112: NMOS common-source amplifier config-
uration and its small-signal equivalent model. Since
operating point. To analyze the small-signal behavior, we re- VDD is shorted out in the small-signal model, the
place the MOSFET with its small-signal equivalent model (the bias resistor R appears in parallel with the device’s
internal resistance ro .
transconductance amplifier model). Second, we zero-out any
DC independent sources. This means that the VDD node gets
shorted to ground, so any devices connected to it are “folded
over” onto the ground node. Summary: CS amp
To analyze the amplifier characteristics, we use the small-
signal equivalent circuit to solve for the gain and output resis- • Inverting amplifier

tance. From the model in Figure 113, we see that the amplifier • Output resistance: ROUT = ro k R

consists of a current source and two resistors. Since the two • Gain: Av = − gm ROUT

resistors appear in parallel, we can merge them as R0o = ro k R.

Then the output voltage is simply the voltage drop across R0o .
Since the current is drawn upward through R0o , the voltage drop
is negative. Solving for the gain:

vout = − ( gm vin ) R0o

vout
⇒ Av = = − gm R0o
vin
To solve the output resistance, we set the input signal to zero
and solve for the equivalent resistance seen looking into the
output node. Since there is a literal resistance of R0o at that node,
the output resistance is clearly R0o .
 introduction to mosfets 131

EveryCircuit Demonstration 30 (NMOS Common-Source Amplifier).

This example shows a basic common-source configuration for an NMOS device with k n = 500 µA/V2 ,
λn = 0.05 V−1 and VThN = 0.5 V. The supply voltage is 5 V. The gate is biased with a DC operating
voltage of VIN = 0.9 V, and the bias resistor is R = 50 kΩ. Capacitive coupling is used at the gate to
separate the DC bias voltage from the AC small-signal input. Capacitive coupling is also used at the
drain to remove the DC offset from the output signal.

Based on these parameters, we can calculate the device’s small-signal characteristics, and then obtain
the gain and output resistance as follows:

VOV = 0.9 V − 0.5 V = 0.4 V

1 2
ID = k n VOV = 40 µA
2
VOUT = VDD − ID R = 3 V
gm = k n VOV = 200 µA/V
ro = (λn ID )−1 = 500 kΩ
ROUT = ro k R = 45 kΩ
Av = − gm ROUT = −9 V/V

Run the transient simulation and verify that the predicted gain and output offset are correct. You will
probably notice that the simulated output offset is 2.727 V. Can you explain this discrepancy? (Hint:
consider the effect of CLM with VDS = 2.727 V, then calculate new values for ID and VOUT ).
132 ece3410 lecture notes

PMOS Common-Source Configuration

Now let’s consider the complementary PMOS version of the vIN
common-source circuit. This circuit is obtained by swapping
the vertical positions of the MOSFET and resistor. In the PMOS
device, the drain current has an inverse response to the gate vOUT

voltage: when vIN rises, i D falls. Since the resistor is positioned vin
R
between the drain and ground, a smaller current means a
+
smaller output voltage at the drain. The result is that the small- VIN −

signal behavior is the same for both the NMOS and PMOS
versions.
vout
To obtain the small-signal equivalent circuit, we zero-out
VDD and VIN , so that the PMOS source terminal is connected to vin
+
small-signal ground. Even though the PMOS device current has
an inverse response to the gate voltage, we can flip the device vgs = vin gm vgs ro R
upside down so that the source terminal is folded back onto the
ground node. We then obtain the exact same model as we had −

for the NMOS version. What this means is that every NMOS
circuit configuration should have a complementary PMOS
version with the exact same behavior. The only differences will Figure 113: PMOS common-source amplifier configu-
be in the device’s k, VTh and λ parameters. ration. Its small-signal equivalent model is the same
as the NMOS version.

EveryCircuit Demonstration 32 (PMOS Common-Source Amplifier).

This example shows a PMOS version of the common-source amplifier. The parameters very similar to
the NMOS case: k p = 250 µA/V2 , λ p = 0.1 V−1 and VThP = 0.5 V. The supply voltage is 5 V. The gate
is biased with a DC operating voltage of VIN = VDD − 0.9 V, and the bias resistor is R = 50 kΩ. Then:

VOV = 0.9 V − 0.5 V = 0.4 V

1 2
ID = k p VOV = 20 µA
2
VOUT = ID R = 1 V
gm = k p VOV = 100 µA/V

−1
r o = λ p ID = 500 kΩ
ROUT = ro k R = 45 kΩ
Av = − gm ROUT = −4.5 V/V

Run the transient simulation and verify that the predicted gain and output offset are correct. You will
probably notice that the simulated output offset is 1.364 V. Can you explain this discrepancy? (Hint:
consider the effect of CLM with |VDS | = VDD − 1.364 V, then calculate new values for ID and VOUT ).
 introduction to mosfets 133

Common-Source with Active Bias

In the previous examples, we considered CS amplifiers where
MOSFET is coupled with a resistor. It is often more useful ID

to consider the active bias configuration, where the resistor is

replaced by an ideal current source. This removes R from the vOUT

small-signal model. Since the bias current is forced by an ideal

vIN
DC independent current source, in the small-signal model
contains an open-circuit at the MOSFET’s drain node. As a vin
result, this configuration achieves the highest possible gain
magnitude for a given MOSFET device. The gain and output +
VIN −
resistance are

Avo = − gm ro
vout
Rout = ro
vin
+
The gain magnitude of this configuration, gm ro , is commonly
referred to as the intrinsic gain of the MOSFET, since it is the vgs = vin gm vgs ro
highest gain achievable with a single MOSFET device. When
−
the circuit is analyzed with no load attached, it is referred to as
the “open-circuit gain” and the subscript letter ‘o’ is added in
Avo to signify this.
In practice, a nearly-ideal current source can be implemented Figure 114: NMOS active-bias common-source am-
using a MOSFET device with a constant gate voltage. For plifier configuration and its small-signal equivalent
model. The current source directly forces a DC bias
example, a PMOS device can be substituted in place of the current of ID in the NMOS device. Since the bias
current source. The PMOS gate voltage, VGP , should be chosen current is forced by a DC independent source, it
is zeroed out in the small-signal model, leaving an
so that the device is biased in its saturation mode. In that open-circuit at the output node.
configuration, the PMOS device is insensitive to the voltage
at its drain terminal, so its constant gate voltage maintains a
constant bias current ID .
Since the PMOS device is not perfectly ideal, it contributes a VGP
load effect due to its intrinsic resistance ro . In the small-signal
ro,p
model, the NMOS and PMOS ro ’s will appear in parallel, so the vOUT
output resistance and gain are slightly modified: ro,n
vIN
Rout = ro,n k ro,p
Av = − gm Rout vin

By using a PMOS device the circuit’s gain is roughly cut in half VIN
+
−
due to the interaction of ro ’s. In general, an amplifier’s output
node is connected to two branches, one “going up” toward VDD
and another “going down” toward ground. The total output Figure 115: NMOS active-bias common-source
resistance is taken as the parallel combination of equivalent amplifier configuration with PMOS bias device. The
PMOS device acts as a current source.
resistance looking up with the resistance looking down, i.e.
Rout = Rup k Rdown .
134 ece3410 lecture notes

Common-Source with Source Degeneration

The active-bias CS amplifier is extremely sensitive to its bias
point. If the DC gate voltage is off by a small error, then the ID

circuit is easily driven to its rail voltages and rendered useless.

In order to relax the bias sensitivity, we can insert a degeneration vOUT

resistor under the source terminal.

vIN
To solve the gain for this configuration, we first observe that
the output node is open-circuited in the small-signal equivalent
circuit model, since DC bias current source was zeroed out. In vin

that case, the current flowing into the output branch must be
+ RS
zero. If a portion of the circuit is enclosed by the dashed box VIN −

shown in Figure 116, then the total current flowing into the box
has to equal the total current flowing out of the box (this is a
version of Kirchoff’s current law). The MOSFET does not allow id = 0 A
vout
any current at its gate terminal, so the gate current is zero. The
output terminal is open-circuited, so the drain current is also vin
+
zero. The only remaining branch is the source terminal, which ig = 0 A
must be zero since there is no other route for current to flow vgs = vin − vs gm vgs ro
into the box. Since is = 0, there is no voltage drop across RS , so
the source voltage is also zero. −
As a result of this analysis, the model for solving the gain of vs
this circuit is identical to the model in Figure 114, so the gain is
must be exactly the same, Av = − gm ro . Where the models RS
differ is in the output resistance. To find Rout for this circuit, we
zero out the input signal and apply a test voltage at vout . Then
we solve for the current that flows through the output branch. Figure 116: NMOS active-bias common-source
Since the output node is no longer open-circuited, a non-zero amplifier with source degeneration resistor RS . The
current flows through the drain and source terminals, with effect of RS is to reduce the amplifier’s gain while
improving error tolerance in the bias point.
id = is = iout . Also, since vin = 0, the gate-source voltage is
vgs = −vs = −is RS . Based on these considerations, we obtain
the circuit shown in Figure 117. is
To solve for the output resistance, we consider the voltage
drop across ro . Two downward currents are superimposed on
+
ro :
vgs = 0 − vs gm v s ro
vout = vs + ro ( gm vs + is ) +
− vout
= i s R S + r o ( gm i s R S + i s ) −
vout vs
⇒ Rout = = R S + r o + gm r o R S
is is
RS
So although the active-bias open-circuit gain is the same when
source degeneration is present, the output resistance is much
higher. This should result in a more significant coupling effect
when a load is connected. Figure 117: Finding the output resistance for the
degenerated amplifier.
 introduction to mosfets 135

Common-Source Amplifier with Passive Bias and Degeneration

In the passive-bias configuration, we can leverage our previous RD
analyses to solve the small-signal behavior without repeating
the entire process. This circuit can be viewed as a superposi-
Rup = R D
tion of the active-bias open-circuit configuration with the bias
resistor R D applied as a load. The gain can be considered as the vOUT

loaded-gain of the active-bias version: Rdown = RS + ro + gm ro RS

RD
AvL = (− gm ro )
R D + Rout vIN
− gm r o R D
=
R D + R S + r o + gm r o R S
vin
Another way of looking at it is that the resistance R D summa-
RS
rizes the circuit’s “up” branch, and the open-circuit amplifier
+
VIN −
summarizes the circuit’s “down” branch. The two branches can
be analyzed separately, and then joined together via a coupling
analysis. After coupling, the new overall output resistance is Figure 118: NMOS CS amplifier with passive bias
0 = R k R . and source degeneration.
Rout out D

Common-Source Amplifier with PMOS Bias and Degeneration

VGP
When a PMOS device is used to supply the amplifier’s active
bias current, we can adopt the same approach as in the passive
Rup = ro,p
case. We now consider the amplifier to be loaded by the ro of
the PMOS device: vOUT

ro,p Rdown = RS + ro,n + gm ro,n RS

AvL = (− gm ro,n )
ro,p + Rout
− gm ro,n ro,p
= vIN
RS + ro,n + ro,p + gm ro,n RS

In both the passive and PMOS biased circuits, we make use of vin
the idealized amplifier model shown below.
+ RS
VIN −

open-circuit amplifier model

Rdown Figure 119: NMOS CS amplifier with passive bias
vin and source degeneration.

+
Rin → ∞ − − gm ro,n vin Rup

Figure 120: Amplifier model separating the upper

bias portion (modeled as a load) from the lower
portion (modeled as an open-circuit amplifier
configuration).
136 ece3410 lecture notes

Example 23 (Passive-biased CS amp with source degeneration).

Consider a passive-biased common-source amplifier like the one shown in Figure 119. The NMOS
device has parameters k = 500 µA/V2 , VTh = 0.5 V and λ = 0.05 V−1 . The bias resistor is R D = 50 kΩ
and the degeneration resistor is RS = 20 kΩ. If the input offset voltage is VIN = 1.25 V, what is the
circuit’s gain?

To solve this problem, we first solve the DC operating point and then calculate the small-signal pa-
rameters. Referring back to the bias configurations studied earlier in the chapter, we see that this
circuit is already covered by the passive bias network analysis. In a previous example, we found that
√
the bias current should be ID = 22.5 µA. Then gm = 2kID = 150 µA/V2 , ro = (λID )−1 = 889 kΩ,
gm ro = 133 V/V, and Rdown = 3.58 MΩ. The high intrinsic gain looks pretty promising, but the
resistive coupling effect is going to ruin it. Putting all this together, the amplifier’s loaded gain is
 
RD
AvL = (− gm ro )
R D + Rdown
= −1.83 V/V.

With the large source degeneration resistance, the circuit does not make a very good amplifier.
If the degeneration resistance could be removed (while keeping the bias current the same), then the
output resistance would be a much smaller value of ro , and in that case the loaded gain would be
much better:  
RD
AvL = (− gm ro ) = −7 V/V.
R D + ro
 introduction to mosfets 137

Benefits of source degeneration

From the preceding analysis, it sounds like source degeneration
4
is purely harmful, since it significantly reduces the gain. There
are three good reasons for understanding source degeneration:

1. It is sometimes an unavoidable feature of some circuits. 2

2. It models the coupling behavior when multiple MOSFET

amplifiers are folded together into a complex circuit.
0
3. It provides a looser error tolerance for biasing the common- 0 2 4
source amplifier.
Figure 121: DC transfer characteristic of a CS ampli-
Of these reasons, the third point is the most practical con- fier with no source degeneration. The amplifier will
sideration at this stage in our study of MOSFET amplifiers. not function if the input offset strays outside the red
box, leaving little tolerance for error.
A high-gain CS amplifier can be difficult to successfully bias
in practice. Since the transfer characteristic is very steep, a
slight error can cause the amplifier to rail, making it useless.
By inserting a degeneration resistor, we can flatten the transfer 4

characteristic and make it more tolerant to bias error.

A collection of simulated DC transfer characteristics is shown
in Figure 122. The degeneration resistance is varied from zero 2
up to 20 kΩ. With increasing values of RS , two drawbacks are
visible. First, the gain is diminished, which is evident from the
flatter slope in curves with higher RS . Second, the output signal 0
range is diminished, since the transfer characteristic flattens out 0 2 4
at a higher voltage. This limits the minimum output voltage
Figure 122: DC transfer characteristic of a CS am-
that can appear, so we can’t produce a full 5 V rail-to-rail signal plifier with several values of source degeneration.
in this example. The degenerated amplifier is more forgiving of bias
errors, but has a flatter slope and therefore lower
gain.
Using a bypass capacitor
For applications where only high-frequency signals need to
be amplified, a win-win solution is possible by inserting a RD
bypass capacitor across the degeneration resistor. The bypass vOUT
resistor has the effect of shorting out RS when processing high- vIN
frequency signals. But at DC, the capacitor has no effect on the
vin
circuit.
At a given frequency f , the bypass capacitor CB behaves RS
+ CB
approximately like a resistance of magnitude (2π f CB )−1 . At VIN −

higher frequencies this resistance tends toward zero, hence

“bypassing” RS . The amplifier’s gain will then tend toward the
Figure 123: NMOS CS amplifier with passive bias,
loaded gain without degeneration: source degeneration and bypass capacitor.
 
RD
AvL → − gm ro .
R D + ro
138 ece3410 lecture notes

Netlist 8: DC sweep of common-source degeneration resistances

* Common-Source amplifier with source degeneration
.model ntype NMOS(KP=100e-6,VTo=0.5,LAMBDA=0.05)

VDD ndd 0 DC 5V
VIN ndc 0 DC 1V
vsig nsig 0 SIN(0 0.1 1k)

RDC ng ndc 1Meg

Cin nsig ng 10uF

RL nout 0 1Meg
Cout nd nout 10uF

M1 nd ng ns 0 ntype W=1u L=200n

RD ndd nd 50k
RS ns 0 1

.control
* Foreach loop to scan through RS values:
foreach RSval 0 500 1000 5000 10000 20000

alter RS = $RSval
dc VIN 0 5 0.05

end

plot dc1.nd dc2.nd dc3.nd dc4.nd dc5.nd dc6.nd

wrdata cs_degenerated_dc dc1.nd dc2.nd dc3.nd dc4.nd dc5.nd dc6.nd
.endc
.end

EveryCircuit Demonstration 34 (CS amplifier with bypass capacitor).

This example implements the NMOS common-source amplifier described in the SPICE netlist above,
with a passive bias resistor R D = 50 kΩ, a degeneration resistor RS = 20 kΩ, and a bypass capacitor
CB = 10 µF. With the bypass capacitor in place, the gain is close to −7 V/V as we predicted in exam-
ple 23. If you remove the bypass capacitor, you should notice that the gain drops to about −1.8 V/V
as predicted.

The circuit is highly tolerant of different DC input bias voltages. Try adjusting the DC gate voltage
source between 1 V and 1.8 V. The circuit continues to function throughout this range, while main-
taining a gain close to the −7 V/V target. Try repeating the simulations with RS and CB removed (i.e.
shorted out). The results will not be as robust for different gate offset voltages.
 introduction to mosfets 139

Amplifier analysis: general principles Rdrain

We’ve now seen several different ways to configure the common-

source amplifier. All of these configurations can be unified into
a general-purpose small-signal analysis procedure. To analyze
any configuration, we only need the following information:
RS

1. The ideal amplifier model is obtained by analyzing the open-

circuit gain of an active-bias configuration.
Figure 124: General resistance into the drain terminal:
Rdrain = RS + ro + gm ro RS .

2. The ideal output resistance is equal to the equivalent resis-

tance looking into the corresponding terminal of the ideal
active-bias configuration.

3. To account for the circuit’s real bias source (whether passive,

PMOS, or something else), we consider the bias device to
RD
be a load resistance which forms a voltage divider at the
amplifier’s output.

This general framework is suitable for analyzing all MOSFET

amplifier configurations. To solve the terminal resistances, Rsource
we only need two general-purpose theorems that reveal the
Figure 125: General resistance into the source
resistance looking into the drain and source terminals.
terminal: Rsource = 1R+Dg+mrroo .
Resistance into the drain: In any configuration, we can
quickly solve Rdrain , the equivalent small-signal resistance look-
ing into the drain terminal of a MOSFET device. To do this, we is
first summarize any circuitry present under the source terminal,
and treat it as a single equivalent resistance RS . Then the circuit
+
is reduced to the exact same model as the CS amplifier with
source degeneration. We found that vgs = 0 − vs gm v s ro

RD
−
Rdrain = RS + ro + gm ro RS
vs

is +
This result covers all possible cases. When the source terminal vs −
is connected directly to ground, RS = 0, then Rdrain = ro . If
there is an ideal current source under the source terminal, then
RS → ∞, in which case Rdrain → ∞.
Figure 126: Model for solving the resistance looking
Resistance into the source: To find the resistance looking into the source terminal.
into the source terminal, we summarize any circuitry present
above the drain as an equivalent resistance, R D . We then apply
a test voltage at the source and solve for the current that flows
140 ece3410 lecture notes

into the source terminal:

vd
is = ID
RD
v d = v s + r o ( gm v s − i s )
vOUT
⇒ i s ( R D + r o ) = v s (1 + gm r o )
vs R + ro
⇒ Rsource = = D . vIN
is 1 + gm r o

In the coming sections we will apply these general principles RS

to an expanding array of configurations. VG

+
−

vin
Common-Gate amplifier configuration
+
VIN −
In the common-gate (CG) configuration, the input signal is
applied to the source terminal, the output is sampled from the
drain terminal, while the gate terminal is held at a constant
bias voltage. In the small-signal equivalent model, the gate vout

voltage is zeroed-out to small-signal ground, and the bias

current source is zeroed-out so that it becomes an open-circuit. +
Since no current flows out of the open-circuited drain terminal,
there must also be no current flowing through RS , i.e. is = 0. vgs = 0 − vs gm v s ro

Therefore vs = vin . Then vout is determined by the voltage drop

−
across ro :
vs

vout = vin + gm ro vin is = 0

vout RS
⇒ Avo = = 1 + gm r o .
vin
The output resistance for this configuration is the resistance vin
+
−
looking into the drain, which we already know is:

Rout = Rdrain = RS + ro + gm ro RS .
Figure 127: NMOS Common-Gate amplifier config-
uration with ideal active bias, and its small-signal
The input resistance is the resistance seen looking into the
equivalent circuit model. The signal source is as-
source terminal. Since there is an ideal current source connected sumed to have a series resistance of RS .
above the drain, the effective resistance above the drain is
Rd → ∞, so for this configuration,

Rin = Rsource = ∞.

Passive-bias configuration: If the ID current source is re-

placed by a resistor R D , we can consider R D as a load resistance.
Then the amplifier’s gain is revised by considering the coupling
ratio:
RD
AvL = (1 + gm ro ) .
R D + R S + r o + gm r o R S
 introduction to mosfets 141

Capacitive coupling: When the CG amplifier is used to

amplify AC signals, we can use a procedure similar to the
bypass method that we applied in the CS amplifier with source ID
degeneration. In this configuration we can similarly leverage RS
to provide a more tolerant bias point at DC, while bypassing RS vOUT
to mask its effect at higher frequencies.
An ensemble of DC transfer characteristics are shown in vIN
Figure 129. The steepest curve corresponds to an RS near zero.
The steepest curve offers the best gain, but the flattest curve
offers the most tolerant bias point. By using capacitive coupling, +
VG −
the circuit will “see” the flatter high-RS curve at DC, but will RS
“see” the steeper low-RS curve at high frequencies. vin
Input resistance: In some applications, we are specifically +
VIN −
interested in the input resistance coupling for the passive-bias
configuration. The CG input resistance is defined as the resis-
tance looking into the source terminal, Rsource , which depends
Figure 128: NMOS Common-Gate amplifier with
on the value of R D together with any load resistance that might capacitive input coupling to bypass RS .
be present. This creates a tricky situation: we can either account
for R D via the input coupling OR account for it via the output
coupling. If we model input and output coupling effects at the 4
same time, R D will be double-counted.
In our previous output-side analysis, we considered the open-
circuit analysis and later inserted R D as a load. In the input-side 2
analysis, we consider the short-circuit configuration with RS
removed, then insert it as a coupling resistance on the front side.
In that case, the solution changes a little:
0
R + ro 0 2 4
Rin = D
1 + gm r o
Figure 129: DC transfer characteristic of a CG
Rout = R D k ro amplifier with different values of RS . A higher RS
provides a flatter characteristic, and is therefore more
RD tolerant to bias error.
Avs = + gm ( R D k r o )
R D + ro
 
RD Rin
AvL = + gm ( R D k r o ) is
R D + ro Rin + RS vout
 
RD R D ro
R D +r o + gm R D +r o ( R D + r o )
=  
+
(1 + gm ro ) 1R+Dg+mrroo + RS
R D + gm R D r o vgs = 0 − vs gm vin ro
=
R D + r o + R S + gm r o R S RD
RD −
= (1 + gm r o ) vs = vin
R D + r o + R S + gm r o R S
is
The same result we obtained before. vin
+
−

Figure 130: Short-circuit model for input-side

coupling analysis, with RS removed while R D
remains.
142 ece3410 lecture notes

Example 24 (Common-gate configurations).

Consider a CG amplifier with passive-bias where R D = 50 kΩ, RS = 10 kΩ, VG = 2.5 V and VIN =
1.6 V. The NMOS device parameters are k = 500 µA/V2 , VTh = 0.5 V and λ = 0.05 V−1 , and the supply
voltage is VDD = 5 V. What gain and output resistance will be achieved in the series configuration (??)
and the bypass configuration (??)?
To begin with, we solve the DC operating point, then the small-signal parameters, and the open-
circuit characteristics of this amplifier:

VOV = VG − VS − VTh
VS = VIN + ID RS
1 2 1
ID = kV = k (VG − VTh − VIN − ID RS )
2 OV 2
√
By defining x = ID , we can express a quadratic equation:
r r
k 2 k
R x +x− (V − VTh − VIN ) = 0
2 2 G
then solve using the quadratic formula:
p !2
−1 + 1 + 2kR (VG − VTh − VIN )
ID = √ = 15.3 µA
R 2k

Then the small-signal parameters are:

p
gm = 2kID = 123.6 µA/V
ro = (λID )−1 = 1.3 MΩ
1 + gm ro = 162.6 V/V

From this point, the two circuits will diverge in the value of Rdrain at higher frequencies. In the by-
pass configuration, RS is masked for AC signals, so Rdrain = ro . For the series configuration, however,
RS has a big effect:

Rdrain (series) = RS + ro + gm ro RS = 2.9 MΩ

Then the gain for the two configurations is

 
RD
AvL = (1 + gm ro )
R D + Rdrain
= 2.73 V/V (series version)
= 6.0 V/V (bypass version)
 introduction to mosfets 143

EveryCircuit Demonstration 36 (Common-Gate configuration).

This demonstration shows a basic common-gate amplifier with a passive bias resistor R D = 50 kΩ.
The NMOS device has the familiar characteristics: k = 500 µA/V2 , VTh = 0.5 V and λ = 0.05 V−1 . The
supply voltage is VDD = 5 V, the NMOS gate is biased at a constant VG = 2 V, and the input signal has
a DC offset of VIN = 1.1 V, and the input AC small signal vin has an amplitude of 100 mV. The input
signal has zero series resistance.

To determine the DC operating point and small-signal characteristics, we can start by directly calculat-
ing VOV since there is no resistor below the source terminal:

VOV = VG − VS − VTh
= VG − VIN − VTh = 0.4 V

Then the DC bias current, output offset, and small-signal parameters are:

1 2
ID = kV = 40 µA
2 OV
VD = VDD − ID R D = 3 V
VDS = VD − VIN = 1.9 V > VOV
gm = k VOV = 200 µA/V
ro = (λID )−1 = 500 kΩ

Finally the gain and output resistance are

 
RD
Avo = (1 + gm r o )
R D + ro
 
50
= (101 V/V) = 9.18 V/V
550
Rout = R D k ro = 45.45 kΩ

Now measure the amplitude of the output signal in EveryCircuit, and verify that the gain is a little
over 9 V/V, as predicted by our analysis.

As an exercise, try removing R D and replace it with an ideal current source (pointing down) sup-
plying 40 µA. Predict the effect this will have on the circuit, and verify your prediction in the Ev-
eryCircuit simulation (note: for this exercise you will need to reduce the amplitude of vin to 1 mV, and
carefully increase the DC offset to VIN = 1.11 V).
144 ece3410 lecture notes

EveryCircuit Demonstration 38 (Common-Gate bypass configuration).

This circuit implements the passive-bias CG configuration described in example 24. The bypass
version is shown. Run the transient simulation and verify that the results align with the predictions
from example 24. As an exercise, remove the bypass capacitor and reposition the AC input in series
between the DC offset and RS . Repeat the simulation, and verify that the gain decreases to a value
close to what was predicted.
 introduction to mosfets 145

Source Follower configuration

If the input signal is applied to the gate while the output is sam- vIN

pled from the source terminal, the circuit is called a common-

drain configuration, more popularly known as a source follower vin
since the source terminal “follows” the gate signal with a small- vOUT

signal gain close to one.

For the ideal active-biased open-circuit configuration, the +
VIN − ID
small-signal model is quite simple. We see immediately that
vout = gm ro (vin − vout ), so the open-circuit gain is simply

gm r o
Avo = . vout
1 + gm r o

The output resistance is a little more subtle. Since the resistance vin − vout ro

is looking into the source terminal, we should have Rout =

Rsource with R D = 0. Then
Figure 131: Source follower configuration with ideal
ro 1 active bias, and its small-signal equivalent model.
Rout = ≈ .
1 + gm r o gm

The 1/gm approximation is accurate when gm ro  1, which is

usually true.
Passive-loaded configuration: If a resistor RS is used instead
of the ideal current source, we can treat it as a load applied to
the ideal open-circuit configuration. Then the loaded gain is

gm r o gm R S
AvL =
1 + gm r o 1 + gm R S
gm R S
≈
1 + gm R S

This approximation applies when gm ro  gm RS , which is often

the case when using a passive bias. Finally the output resistance
is
1
Rout = k RS .
gm

This tends to be much lower than the output resistance of the

CG and CS configurations. For that reason, the SF configuration
can be useful as an output buffer to drive small-resistance loads
without suffering signal attenuation due to output resistance
coupling.
146 ece3410 lecture notes

Example 25 (Source Follower output resistance).

Suppose a CS configuration has an open-circuit gain of Avo = 20 V/V an output resistance Rout =
500 kΩ, and needs to drive a load R L = 10 kΩ. If the CS amplifier is connected directly to the load,
the gain will be attenuated so that AvL = 20 × 10/(10 + 500) = 0.392 V/V. Now suppose a SF
configuration is inserted in between the CS output and the load resistor, and the SF circuit has gm =
200 µA/V, ro = 500 kΩ, and the load itself acts as a passive bias resistance of RS = 10 kΩ. Then the
overall gain of this two-stage circuit will be
  
gm r o gm R L
AvL = 20 V/V = 19.99 V/V,
1 + gm r o 1 + gm R L

so there is almost no attenuation at all.

vIN RL vIN
RL
 introduction to mosfets 147

Biasing MOSFET amplifiers

In the previous examples, we considered the DC solution for

passive resistor-biased amplifier configurations. Passive bias
designs are convenient in that they can be fully analyzed, and
can be made tolerant to bias errors and parametric variation.
But there are several drawbacks to passive-bias designs:

• Bias resistors load the amplifier and significantly lower the

gain.

• Due to the DC voltage-drop across each bias resistor, the

dynamic range is limited; for example, with VDD − 5 V, a

load
passive-biased CS amplifier may deliver an output amplitude ID
no greater than 1 V.

• For integrated circuit applications, resistors are physically iOUT

large and expensive to fabricate on-chip.

To address these limitations, there are two major alternatives:

+ +
current-mode biasing and feedback biasing. There are other, vGS vGS
− −
more advanced, bias solutions, but for now we will focus our
attention on these two methods.
Figure 132: MOSFET current mirror. The input
current (on the diode connected side) is copied at the
Current-mode biasing output branch.

One of the most important bias strategies is based on the cur- + |v |

GS 2 |vGS 2 | +
rent mirror configuration shown in Figure 132. The current mir-
− −
ror consists of two devices, both biased in saturation, connected ID
with the same gate and source voltages. Since the saturation Rref
current depends only on vGS , and both devices have the same
vGS , they should both have the same current. On the input side,
a current is forced into the drain terminal of a diode-connected

amplifier
device. The diode connection regulates vGS to support the forced
current ID . On the output side, the device can be used as a
current source that delivers iout = ID to a load connected at its + +
vGS 1 vGS 1
drain terminal. − −
Current mirrors can be used to generate bias currents, and
to source multiple copies of a reference current. This can be Figure 133: Example showing two current mirrors. In
the NMOS mirror, the reference current is setup by
quite useful for amplifier biasing. In the structure shown in the interaction between R and the diode-connected
Figure 133, the reference current (i.e. the input) is initially NMOS device. The PMOS mirror then generates a
determined by a resistor R. The current in this configuration new copy of the reference current, which is used to
bias an amplifier.
was previously found to be
 p 2
−1 + 1 + 2kR (VDD − VTh )
ID = .
2kR2
148 ece3410 lecture notes

Example 26 (Current-mirror active bias).

Consider the CS-SF configuration from the previous example. By using current mirrors, we can
convert this to an active-bias configuration, replacing the resistors with MOSFETs as shown below.

Device MCS is in a common-source configuration with output v X .

Device MSF is in a source-follower configuration with input v X and
ID
output vOUT . Both devices are biased with the same DC current, ID .
Capacitive coupling is used to separate the DC gate offset for MCS vX
MSF
Design problems: vOUT

• Generate the correct offset voltage at VIN . MCS ID

• Implement the ID current sources. +

VIN −
vin

In the expanded circuit below, current mirroring is used to generate both the VIN offset voltage and
the current sources for ID . There are two current mirrors, an NMOS mirror producing three copies of
ID via vGS 1 , and a PMOS mirror producing one copy of ID via |vGS 2 |.

+ |vGS 2 | |vGS 2 | + To keep MCS in satu-

− − ration, it’s DC current
ID should be equal to ID . If
Rref all the NMOS devices
are matched, and if they
MSF
all have the same VGS ,
then they should all have
vout the same current. Hence
by setting VIN = vGS 1 ,
ID
MCS the current mirror pro-
+ +
vGS 1 vGS 1 vides both the gate offset
− −
voltage and the current
sources.

vin
 introduction to mosfets 149

Symmetry in current mirrors

When using a current-mirror bias network, the output signal’s + |v | |vGS 2 | +
GS 2

DC offset is not obvious. We usually want an amplifier’s DC − −

offset to be balanced in the center of its operating range, but ID

how can we control this? The answer lies with symmetry. Rref
vY vX
In the two-mirror bias structure shown in Figure 134, the
NMOS mirror is used to set the gate offset voltage, and the
PMOS mirror is used to source the active bias current. For this
setup to work, all devices must be perfectly matched, i.e. they
must have the same physical parameters (k, VTh , λ, etc) and the MCS
+ +
same geometry (W and L). They must furthermore all operate vGS 1 vGS 1
− −
in saturation, so that the sensitivity to their drain voltages is
minimized. Then they should all have the same device current,
Figure 134: Two current mirrors used to bias a
ID . common-source amplifier. By symmetry, we can infer
Using the square-law device equation, we can solve for that v X = vY .

all the voltages in this circuit except for one: v X . To obtain

a solution for v X , we note that the PMOS devices have the
exact same gate and source voltages, and the same device
current. In that case, we may make an argument from physical
symmetry: if two devices are known to have exactly the same
electrical state in all variables except one, then they must
also be matched in the remaining unknown variable. In other
words, v X = vY = VDD − |vGS 2 |. In the next example, we find that
this isn’t always the best bias point.

Example 27 (Output offset with current-mirror bias).

Suppose the circuit of Figure 134 is constructed with the following parameters: k n = 5 mA/V2 , k p =
3 mA/V2 , VThN = VThP = 0.5 V, λn = 0.01 V−1 , λ p = 0.05 V−1 , Rref = 50 kΩ and VDD = 5 V. What is the
circuit’s complete DC operating point?
Using the previous analysis of the diode-connected MOSFET, we calculate ID and then vGS 1 and vGS 2
 p 2
−1 + 1 + 2kR (VDD − VTh )
ID = = 86.3 µA
2kR2 s
s 2ID
as 2ID VOV 2 = = 0.24 V
VOV 1 = = 0.186 V kp
kn
|VGS 2 | = VOV 2 + VThP = 0.74 V
VGS 1 = VOV 1 + VThN = 0.686 V

Then the value of vY and v X is

vy = v X = VDD − |vGS 2 | = 4.26 V
150 ece3410 lecture notes

In the result from Example 27, notice that the output offset
is very close to the maximum output voltage. It is near the top
of its range. That means the positive leg of an output signal
will be clipped. To resolve this problem, we need to break the
symmetry by a small amount. One option is to slightly increase
the k of device MCS (by increasing its width), so that its device
current is slightly greater than ID . That will pull down the
output offset. A second option is to slightly decrease the gate
bias voltage at MCS . Both of these methods are risky, since it
can be challenging to calculate the exact variation required. Real
MOSFETs may deviate slightly from our model equations, and
manufacturing variations can result in physical parameters that
are slightly different from the ones on the data sheet.

EveryCircuit Demonstration 40 (Two stage amp with current mirror bias).

This demonstration implements the current-mirror bias network from Example 26. In order to correct
for the output bias problem discussed in Example 27, the width of device MCS is slightly increased.
Based on the parameters from Example 27, we found that the bias current is ID = 86.3 µA. Continu-
ing this analysis, we find the small-signal parameters are
p
gm = 2k n ID = 929 µA/V
ro,n = (λn ID )−1 = 231.7 kΩ
ro,p = (λ p ID )−1 = 115.9 kΩ

Then the expected gain is AvL = − gm (ro,n k ro,p ) = −71.77 V/V.

In the demonstration, since MCS is slightly wider, its k increases to 5.85 µA/V2 . Using an ammeter
in the simulation, we can see that this increases the bias current to about 110 µA, hence gm becomes
1.13 mA/volt, ro,n = 181.8 kΩ and ro,p = 90.9 kΩ. Then the loaded gain should be −68.5 V/V. In the
simulation, the gain is observed to be −83.8 V/V, somewhat higher than the prediction.
As an exercise, try setting the width of MCS to 10, so that it matches the widths of all other devices
in the circuit. You should see that the output waveform saturates due to the output offset being near
the upper edge of saturation for the PMOS device.
 introduction to mosfets 151

Feedback biasing
In order to achieve a more reliable bias solution that is highly −
LPF

tolerant to both manufacturing variation and model inaccuracy, VX?

+
− +

we can exploit the power of negative feedback. Since our goal is

to achieve an output bias near the center of its dynamic range,
we can directly enforce this condition by using an error ampli- vX
fier loop like the one shown in Figure 135. The idea is that if VX
deviates from the desired value, VX? , then the amplifier responds
by pushing VX strongly in the opposite direction.
vIN
At this point you may ask, “if I have an op amp, why don’t
I just use it as the amplifier instead of using it to bias a MOS-
FET circuit?” In practice, we don’t need to use a full fledged
op amp for this bias configuration. A simpler MOSFET-based Figure 135: An error amplifier loop is used to
differential amplifier is adequate. There are several configura- regulate the DC offset at VX so that it stays close
to the desired value VX? . This configuration adapts
tions that can be used for error amplification. One example is to changes in the gate offset at VIN . Note that the
the circuit shown in Figure 136, in which a CS configuration feedback signal is connected to the op amp’s non-
is superimposed onto a SF configuration. When two amplifier inverting input. This is because the PMOS device acts
as an inverting amplifier, so there is a net negative
stages are superimposed in this manner, it is referred to as a sign around the feedback loop.
folded configuration.
The new circuit in Figure 136 now has three devices that will
act as CS amplifiers. The primary amplifier is NMOS MCS1 , and
the error amplifier bias network has PMOS amplifiers MCS2
and MCS3 . In the small-signal domain, MCS2 has an open-circuit
gain of − gm ro , but is loaded by the 1/gm source resistance of (v− )
MCS2
MSF2 . So the loaded gain of MCS2 is + LPF
Vreg − vz
  MCS3
1/gm
ACS2 = − gm ro ≈ −1,
1/gm + ro
where the approximation is due to the fact that ro  1/gm ,
so the 1/gm term is removed from the denominator, allowing MSF2 vX
(v+ )
both gm and ro to be canceled. Next, since MSF2 is a source
follower, its gain is approximately one. So the small-signal
voltage arriving at the gate of MCS3 is vY ≈ (v+ ) − (v− ). Finally vIN MCS1
the error signal vy is amplified by MCS3 with a gain of − gm ro ,
which supplies the amplification in this feedback loop.
The purpose of the error amplifier is to make small adjust-
ments in the current of MCS3 in order to precisely control the Figure 136: A differential error amplifier made by
folding together a PMOS common-source amplifier
offset voltage at v X . The device current in MCS3 should still be with a PMOS source-follower. In the small-signal
very close to ID , and its gate voltage should therefore be very model, we see that the SF device loads the CS
configuration, so that the overall gain is close to one.
close to s
2ID
v Z ≈ VDD − VThP − ,
kp
where ID is the DC bias current in MCS1 and MCS3 . Further-
more, the DC currents in MCS2 and MSF2 should be equal to
152 ece3410 lecture notes

each other, so
1
2 1
k p VDD − Vreg − VThP = k p (v Z − v X − VThP )2
2 2 s !

2ID
⇒ VDD − Vreg − VThP = VDD − VThP − − v X − VThP .
kp

So, in order to achieve v X = VX? , we should set the control

voltage at s
? 2ID
Vreg = VX + VThP + .
kp
If k p  ID , then
Vreg ≈ VX? + VThP .
The feedback bias methods discussed here are introductory.
A variety of more sophisticated bias techniques can also be
used, but are beyond the scope of this chapter.

EveryCircuit Demonstration 42 (Two-stage amplifier with ideal feedback bias).

This example modifies the design from Example 27 to use feedback bias with an ideal op amp as the
error amplifier, like the solution shown in Figure 135. In this configuration, all devices are matched,
so there is no need to manipulate the width of MCS .

EveryCircuit Demonstration 44 (Two-stage amplifier with PMOS feedback bias).

This example modifies the design from Example 27 to use feedback bias with an error amplifier like
the one from Figure 136. In this design, the control voltage is Vreg = 3.0 V, corresponding to VX? + VThP .
All NMOS devices are matched, and the error amplifier feedback is achieved without using an op
amp.
 introduction to mosfets 153

Frequency response of CMOS amplifiers

Rsig Rout
In this section we will introduce the basic concepts of CMOS
amplifier frequency response and bandwidth. All circuits have vsig
+
Cin Rin − Avo vin Cout RL
a maximum operating frequency, beyond which they exhibit
rapid signal attenuation. Frequency limitations arise from the
parasitic capacitances that exist on every node in a physical
circuit. Capacitance arises from the wire connections at a node, Figure 137: High-frequency amplifier model showing
from the substrate and insulation materials of a wire, a printed input and output capacitances.
circuit board or chip, and from the internal junction physics of
the MOSFET itself. In this section, we will focus on the analysis
of capacitive effects and not concern ourselves with calculating
specific capacitance values around MOSFET devices (we will
assume the capacitance values are known or given).
In an amplifier circuit, it is usually sufficient to assume that
a “lump” capacitance is connected to each node that summa-
rizes all the neighboring parasitic effects. We therefore insert
lump capacitors connected from the input and output nodes to
ground, called Cin and Cout , respectively. By representing these
capacitors in the Laplace domain, we can treat them as part of
the input and output impedances, and their effect is captured
by the resistor-divider coupling ratios at the input and output
nodes. Then the amplifier’s frequency response is

Rin k sC1in R L k sC1out

! !
Av (s) = Avo
Rsig + Rin k sC1in Rout + R L k sC1out
  
Rin RL
= Avo
Rsig + Rin R L + Rout
  
1 1
×
1 + s( Rsig k Rin )Cin 1 + s( Rout k R L )Cout

This implies there are two poles:

ω p1 = [Cin ( Rin k Rsig )]−1

ω p2 = [Cout ( Rout k R L )]−1

It will often be the case that one pole is much larger than the
other. In that case may consider the smaller pole to be domi-
nant, and treat the circuit as a one-pole system governed by the
dominant pole.
154 ece3410 lecture notes

Frequency response of the common-source configuration

The common source configuration benefits from an infinite

input resistance, so the input pole is determined solely by Rsig ID
and Cin . The output pole is quite sensitive to the amplifier’s Cfb
output and load resistances.
Input-dominant pole. If Rsig is significant, then the input
node may dominate the frequency response. In that case, the Rsig
vin Cout RL
circuit’s cutoff frequency is approximately ωin ≈ ( Rsig Cin )−1 .
Cin
Miller effect. If the input pole is dominant, then it may be
necessary to account for any feedback capacitance, Cfb , that
may bridge between the input and output terminals. In practice
Figure 138: Common-source configuration showing
feedback capacitances are usually much smaller than the lump input and output capacitances. In some cases there
capacitances at the input and output terminals. Due to the may be a feedback capacitor Cfb , which can affect the
bandwidth if the input pole is dominant.
negative feedback path in the common-source configuration, the
effect of Cfb is amplified, and may alter the frequency response.
The Miller effect appears in the small-signal equivalent 100 Ω
impedance seen looking into the input terminal. Using the
0
simplified circuit model in Figure 140, we find that

| H ( f )| (dB)
312.5 kΩ

vout = − Av vin −50

iin = (vin − vout ) sCfb = (vin + Av vin ) sCfb
vin
⇒ Zin = = [(1 + Av ) sCfb ]−1
iin
101 103 105 107 109
Frequency (Hz)

This result shows that the effective capacitance is (1 + Av ) Cfb ,

Figure 139: Simulated transfer functions for a
i.e. the feedback capacitor is “amplified” by the gain of the CS configuration with input-dominant pole for
inverting configuration. A similar analysis shows that there is Cin = 1 pF. Each curve represents a different Rsig ,
starting from 100 Ω and increasing by 5× up to
no such effect on the output side. 312.5 kΩ. The cutoff frequency varies from the order
Thanks to the Miller effect, in a high-gain amplifier a small of GHz down to a few hundred kHz.
feedback capacitance could prove to dominate the bandwidth.
Cfb
Sometimes this is a nuisance, but it can also be desirable for
special applications. iin iout
Output dominant pole. If Rout k R L is very large, and Rsig is
vin − Av vout
comparatively small, then the output pole will tend to dominate
the frequency response. In that case, it is sometimes desirable
to load the amplifier with a smaller R L , in order to increase the Figure 140: Simplified circuit model for analyzing the
bandwidth. Since this also decreases the amplifier’s gain, there Miller effect.
will be a strong tradeoff between gain and bandwidth.
Gain/Bandwidth Tradeoff. For the output-dominant case,
the tradeoff between gain and bandwidth manifests in multiple
ways. When using a small load resistance, R L  Rout , the
 introduction to mosfets 155

tradeoff is clear:
 
RL
AvL = Avo
R L + Rout
 
RL
≈ Avo ID
Rout
f c = [2π ( Rout k R L )Cout ]−1 vOUT
−1
≈ [2πR L Cout ]
vIN Cout
We see that there is a one-to-one exchange between gain and
bandwidth. In other words, the gain-bandwidth product is
constant: GBW = Avo /(2πRout Cout ).
For a larger load, or when no resistive load is present, we Figure 141: Active-bias CS configuration, when the
output pole is dominant,
√ shows a strong gain/BW
also see the tradeoff as a property of the bias current. The −1
tradeoff: AV ∝ ID , whereas f c ∝ ID .
amplifier’s open-circuit gain is

Avo = − gm ro
p  1 
=− 2kID
λID
s
2k
=−
λ2 ID R

Meanwhile the cutoff frequency is vOUT

f c = (2πRout Cout )−1

vIN
λID
= Cout
2πCout
As a result, a higher ID means higher bandwidth but lower R
gain. To put it another way, a high-bandwidth amplifier con-
sumes more power and has less gain than a low-bandwidth
amplifier. Figure 142: Passive-bias CS configuration, when the
output pole is dominant,
√ shows a similar gain/BW
In the case of a passive-biased CS amplifier, we again see the tradeoff: AV ∝ R, whereas f c ∝ R−1 .
same tradeoff. Suppose the amplifier has a source degeneration
resistor such that RS = R D with a source bypass capacitor, and
the gate offset is at VDD /2. Then, using the quadratic formula,
we find that the DC solution, open-circuit gain, and bandwidth
are
p !2
−1 + 1 + 2kR (VDD /2 − VTh )
ID = √
R 2k
VDD /2 − VTh
≈
R p
Avo ≈ − gm R = − 2kID R
q
≈ − 2kR (VDD /2 − VTh )
f c = (2πRCout )−1
156 ece3410 lecture notes

So once again we see the same tradeoff between gain and

100 kΩ
bandwidth. This scenario was simulated using Listing 10 with 20
results shown in Figure 143. The observed gain and −3 dB
bandwidth are close to what is predicted by our analysis.

| H ( f )| (dB)
10
The table below summarizes the results. From the data, we
see that the prediction is more accurate for larger R. The netlists 5 kΩ
used to simulate the input-dominant frequency response and 0
the gain-bandwidth tradeoff are shown after the data table.

−10
101 103 105 107 109
Predicted Simulated Frequency (Hz)
R (kΩ) ID (µA) Av (dB) f c (MHz) ID (µA) Av (dB) f c (MHz)
Figure 143: Simulated transfer functions for the CS
5 400 7 31.8 223 8 32
configuration from Figure 142. The NMOS device
10 200 10 15.9 131 11.6 15.7 has k = 500 µA/V2 , VTh = 0.5 V, VDD = 5 V and
25 80 14 6.4 61 16 12.7 VIN = 2.5 V. R is varied from 5 kΩ up to 100 kΩ.
50 40 17 3.18 33 19.5 3.7
100 20 20 1.59 17.5 22.7 1.86

Netlist 9: AC simulation of CS configuration

* Common-Source amplifier with source degeneration
.model ntype NMOS(KP=100e-6,VTo=0.5,LAMBDA=0.05)

VDD ndd 0 DC 5V
VIN ndc 0 DC 2.5V
vsig nsig 0 DC=0 AC=1 SIN(0 0.01 1k)

Rsig nsig nin 10

RDC ng ndc 1Meg
CC1 nin ng 10uF
Cin ng 0 1pF

RL nout 0 1Meg
CC2 nd nout 10uF
Cout nd 0 1fF

M1 nd ng ns 0 ntype W=1u L=200n

RD ndd nd 50k
RS ns 0 50k
CS ns 0 1uF
.control
* INPUT DOMINANT CASES:
* Foreach loop to scan through RSig values:
foreach RSigval 100 500 2500 12500 62500 312500
alter Rsig = $RSigval
AC dec 10 10 10G
end

* OUTPUT DOMINANT CASES:

 introduction to mosfets 157

* Foreach loop to scan through Cout values:

alter Rsig=10
foreach Coutval 10f 50f 250f 1.25p 6.25p 31.25p 10p
alter Cout = $Coutval
AC dec 10 10 10G
end

plot db(ac1.nd) db(ac2.nd) db(ac3.nd) db(ac4.nd) db(ac5.nd) db(ac6.nd)

plot db(ac7.nd) db(ac8.nd) db(ac9.nd) db(ac10.nd) db(ac11.nd) db(ac12.nd)
.endc
.end

Netlist 10: Gain/BW tradeoff in CS configuration

* Common-Source amplifier gain/bw tradeoff
.model ntype NMOS(KP=100e-6,VTo=0.5,LAMBDA=0.05)

VDD ndd 0 DC 5V
VIN ndc 0 DC 2.5V
vsig nsig 0 DC=0 AC=1 SIN(0 0.01 1k)

Rsig nsig nin 10

RDC ng ndc 1Meg
CC1 nin ng 10uF
Cin ng 0 1pF

RL nout 0 1Meg
CC2 nd nout 10uF
Cout nd 0 1pF

M1 nd ng ns 0 ntype W=1u L=200n

RD ndd nd 50k
RS ns 0 50k
CS ns 0 1uF
.control

* Sweep R values to see Gain/BW tradeoff:

foreach Rval 5k 10k 25k 50k 100k
alter RD=$Rval
alter RS=$Rval
DC VIN 0 5 0.1
AC dec 10 10 10G
set gm=@m1[gm]
set rv=$Rval
let av=$gm*$rv
let avp=sqrt(2*5e-4*$rv)
let avdb=20*log10(av)
let fc=1.0/(2*3.1415*$rv*1e-12)
echo $rv
print @m1[gm] @m1[id] av avp avdb fc
end
158 ece3410 lecture notes

plot db(ac1.nd) db(ac2.nd) db(ac3.nd) db(ac4.nd) db(ac5.nd)

wrdata cs_gbw db(ac1.nd) db(ac2.nd) db(ac3.nd) db(ac4.nd) db(ac5.nd)
.endc
.end
 Collector
vC

Introduction to BJTs Base

iC = βi B = αi E

vB
iB +

v BE i E = i B + iC
The bipolar junction transistor was the first practical transistor −
vE
device for mass production, and defined the semiconductor
Emitter
industry from the 1950s into the 1980s. Today, BJTs are not as
widespread as MOSFETs, but are still very important for niche Figure 144: The NPN BJT device, showing its be-
havior in the active mode (when v BE ≈ 0.7 V and
applications. Some areas where BJTs excel include high-voltage vCE > 0.3 V). In this mode, the device can be de-
applications, and radio-frequency power amplifiers, where scribed as a current amplifier with constant gain
BJTs are able to drive antennas and transmission lines with β.

very good linearity and, hence, low distortion. BJTs also have a
Emitter
high transconductance, and it is usually easier to make a good vE
+
discrete BJT amplifier, whereas MOSFETs may need several i E = i B + iC
v BE
devices in order to achieve a good bias configuration, making
them more suited for integrated circuit designs. −
The chief drawbacks to BJT devices are high power consump- iB vB
Base
tion (BJT bias currents must usually be on the order of 1 mA
iC = βi B = αi E
to 100 mA), and comparatively high voltage overhead (unlike
vC
MOSFETs, the BJT’s overdrive voltage is not adjustable and
Collector
cannot be reduced for low-voltage applications). In addition,
BJT devices cannot be miniaturized to nano-scale dimensions, Figure 145: The PNP BJT device, showing its be-
havior in the active mode (when v EB ≈ 0.7 V and
so they cannot achieve the same performance enhancements or v EC > 0.3 V). The PNP device’s behavior is comple-
cost improvements that come with MOSFET scaling. Lastly, BJT mentary to the NPN.
devices pass current through their base terminals (comparable
to the MOSFET’s gate), which makes them inefficient for logic
circuits, and complicates amplifier analysis and design.
BJTs are built out of PN junctions (diodes), and normally
have three operating modes corresponding to the diode states: Active Mode Summary:

• cuttoff: both junctions are not forward biased, i.e. v BE < 0.4 V 
v BE

i B = IS exp
and vCB > −0.4. Note that the junctions do not have to nUT

be reverse biased; a very weak forward bias is sufficient iC = βi B

to shutoff the junction for most applications. This mode = αi E

β
roughly corresponds to the MOSFET’s cutoff mode, and is α=
β+1
the appropriate OFF mode for switching circuits.

• active: emitter-base junction forward biased, v BE ≈ 0.7 V,

collector-base junction not forward biased, vCB > −0.4 V.
160 ece3410 lecture notes

Note that these conditions imply that vCE > 0.3 V. In this
mode, the base-current is defined by the forward-bias diode
equation, i B = IS exp (v BE /nUT ), and the collector current
is iC = βi B , where β is the device’s current gain, n is the
forward emission coefficient (usually close to 1.0), UT is
the thermal voltage (26 mV at room temperature), and IS
is a scale current on the order of pA. This mode roughly
corresponds to the MOSFET’s saturation mode, and is the
appropriate DC bias mode for amplifier circuits. Collector Emitter

• saturation: both junctions are forward biased, v BE ≈ v BC ≈

N P
0.7 V. This mode roughly corresponds to the MOSFET’s triode
mode, and is the appropriate ON mode for use in switching Base P Base N
circuits.
N P
In most of our designs, the BJT will used as an amplifier,
and will be operated in its active mode. In atypical situations, Emitter Collector
there are two additional modes that may arise in BJT circuits:
Figure 146: Physical concept of the BJT device. By
applying a forward bias across the base-emitter
• Reverse active: when the collector and emitter terminals diode, a proportionally larger current is induced
are swapped, the device can be used with the base-collector between the collector and emitter.
junction in forward bias while the base-emitter junction is
not forward biased, i.e. v BC ≈ 0.7 V and v EC > 0.3 V. In this
configuration, the device functions similarly to the forward
active mode, but with a much smaller current gain, β. This
can easily happen by accident when connecting discrete
devices in lab experiments, and highlights a key difference
between BJTs and MOSFETs: whereas MOSFETs are often
symmetric devices, BJTs are not. You cannot interchange
the collector and emitter terminals.

• Avalanche breakdown: since the BJT is built from diode

junctions, reverse-breakdown can occur in one or both of
the junctions. The breakdown voltages are usually large
enough that they are not encountered in ordinary BJT circuits.
In some applications, a BJT can be deliberately forced into
avalanche breakdown, which can be useful for high-speed
switching of large currents as may be needed in pulse-based
instrumentation or radio frequency transmitters. When a BJT
is operated in its avalanche breakdown mode, it is referred
to as an avalanche transistor. Some specialty devices may be
built specifically for avalanche operation, but ordinary BJTs
can also be operated in the avalanche mode.
 introduction to bjts 161

DC passive bias configurations VCC

BJTs are primarily used as amplifiers, so we will consider active-

mode bias configurations. Since the device is extremely sensi- RC
tive to the base-emitter voltage, it is usually necessary to place R B1
resistors in series with the base and emitter terminals. These VC

resistors provide “elastic” voltage drops that help maintain an

VB
appropriate v BE .
Two common passive bias configurations are shown in Fig-
ure 147 and Figure 148. In both cases, we will begin by choosing VE
R B2
a desired bias current for IE (usually on the order of 1 mA),
RE
assume that v BE ≈ 0.7 V, and follow a Kirchoff voltage loop
across the emitter-base junction. The values of RC and R E can
be chosen based on gain analysis (which will be addressed later;
they will typically be on the order to 10 kΩ), so our bias task Figure 147: Voltage-divider bias configuration.
will be to calculate the R B values.
Voltage-divider bias: for the configuration in Figure 147, VCC
Ohm’s Law indicates that VE = IE R E , and the Kirchoof voltage
loop indicates that VB = IE R E + v BE = VE + 0.7 V. The resistors
R B1 and R B2 should be chosen to achieve this voltage. If we ass- RC
sume that IB is small enough that we can ignore its contribution RB
to the voltage divider, then
VC
R B2
VCC = IE R E + 0.7 V VB
R B1 + R B2
VB
R B2 = R B1
VCC − VB VE

On the collector side, VC = VCC − IC RC . The circuit should be RE

biased so that the minimum expected voltage at vC is at least
0.3 V greater than VE .
Feedback bias: for the configuration in Figure 148, Ohm’s
Law again indicates that VE = IE R E . In this case, we take the Figure 148: Feedback bias configuration.
Kirchoof voltage loop from the emitter, to the base, then across
the collector and up to VCC . Note that the feedback connection
merges the base current together with the collector current, so
the total current in RC is IE . Then

VCC = IE R E + v BE + IB R B + IE RC
IE R B
⇒ VCC = IE R E + 0.7 V + + IE R C
β+1
β+1
⇒ RB = (VCC − 0.7 V − IE ( R E + RC ))
IE
162 ece3410 lecture notes

Example 28 (Voltage divider bias).

A voltage-divider network like the one in Figure 147 has VCC = 5 V, RC = 2 kΩ, R E = 0.5 kΩ,
R B1 = 10 kΩ, and the device has β = 100 A/A. If the desired emitter current is 1 mA, what is the cor-
rect value for R B2 ?
Based on the given parameters, we can directly calculate VE = IE R E = 0.5 V, and VB = VE + 0.7 V =
1.2 V. Then
R B2
VCC = 1.2 V
R B1 + R B2
⇒ VCC R B2 = 1.2 V ( R B1 + R B2 )
1.2 V
⇒ R B2 = R B1
VCC − 1.2 V
= 3.16 kΩ

Example 29 (Feedback bias).

A voltage-divider network like the one in Figure 148 has VCC = 5 V, RC = 3 kΩ, R E = 0.5 kΩ, and the
device has β = 100 A/A. If the desired emitter current is 1 mA, what is the correct value for R B ?
As in Example 28, we can directly calculate VE = IE R E = 0.5 V, and VB = VE + 0.7 V = 1.2 V. Then

β+1
RB = (VCC − 0.7 V − IE ( R E + RC ))
IE
= 80.8 kΩ.

On the collector side, we may estimate the collector voltage as VCC − IE RC = 5 V − 1 mA × 3 kΩ = 2 V.

 introduction to bjts 163

BJT small-signal characteristics ib ic

vb vc
The small-signal characteristics are obtained using the same
differential techniques that we employed for MOSFET devices. rπ gm vbe ro
As with MOSFETs, the most important characteristics are the
transconductance gain gm and the intrinsic resistance ro . Un-
like MOSFETs, the BJT also has a resistance associated with the
ie
base emitter junction, called rπ .
We first obtain the transconductance by applying the differen-
ve
tial definition:
 Figure 149: Standard ‘Π’ model of the BJT device.
d iC  The base-emitter diode induces a differential resis-
gm ,
d v BE DC tance named rπ .
 
d v BE
= βIS exp
d v BE nUT
 
1 v BE 
= βIS exp
nUT nUT DC
I
= C .
nUT
Small-Signal Summary:
Early effect resistance: the BJT’s ro parameter is due to a
phenomenon called the Early effect, which is very similar to IC
gm =
Channel Length Modulation in MOSFET devices. The Early nUT
V
effect accounts for a slight sensitivity between the collector ro = A
IC
current and the collector-emitter voltage: β
rπ =
   gm
v BE vCE
iC = βIS exp 1+
nUT VA

where VA is called the Early voltage, with units of V. The Early

effect is algebraically identical to CLM if we recognize that
VA = λ−1 . Then the ro resistance is
   −1
d iC 
ro ,
d vCE DC
    −1
d v BE vCE 
= βI exp 1+
d vCE S nUT VA DC
V
= A.
IC

Lastly, the differential base-emitter resistance is defined as

   −1
d i B 
rπ , .
d v BE DC

Recall that i B = iC /β. In that case this derivate is the same

as the one that defines gm , except for the constant β factor.
Therefore rπ = β/gm .
164 ece3410 lecture notes

BJT amplifiers with passive bias

VCC
The BJT configurations are very similar to their MOSFET coun-
terparts. One crucial difference is that the BJT allows some
current to flow through the base terminal. This often means RC
that BJT amplifiers have finite input resistance, which can create R B1 CC2
VC
resistive coupling effects at the input terminals. We’ll begin our Rbase
vOUT
study with a simplified analysis and then consider the terminal Rcoll.
vIN
resistances afterward. VB
CC1
In order to simplify our analyses, we’ll assume that the
VE
resistance seen looking into the BJT’s collector terminal is very
R B2
large, much larger than RC . We’ll furthermore assume that the RE
input resistance looking into the base is very large compared
to the equivalent series resistance of the signal source, and
that β is very large so ie ≈ ic , and that gm is very large so that
gm R E  1. With all of these assumptions, the gain is found by Rsig  Rbase
vout
vin ic
the following analysis

vout = − gm vbe RC rπ gm vbe

vout R E
vbe ≈ vin − ie R E = vin + RC  Rcoll.
RC
 
vout R E ie ≈ ic
⇒ vout ≈ − gm RC vin + RE
RC
vout − gm R C
⇒ ≈
vin 1 + gm R E
R Figure 150: Common-Emitter configuration based on
≈ − C. the voltage-divider bias network, and its simplified
RE
small-signal model.
In the feedback-biased case, we may reach a similar conclu-
sion if the value of R B is much larger than RC and also much VCC
larger than Rsig . In that case, the negative feedback loop created
by R B will have little impact on the small-signal analysis, and
we arrive at the same result for the gain. RC
CC2
RB
vOUT
VC

VB
vIN
CC1
VE

RE

Figure 151: Common-emitter configuration based on

the feedback bias network.
 introduction to bjts 165

EveryCircuit Demonstration 46 (Common-Emitter with feedback bias).

Using the bias network from Example 29, we introduce input and output signals using the capacitive-
coupled connections shown in Figure 151. A bypass capacitor is used to eliminate the AC influence of
R E , so the AC gain should be − gm R E . Since IC ≈ 1 mA, the transconductance and gain should be

1 mA
gm = = 38.46 mA/V
26 mV
⇒ − gm RC = −115 V/V

The simulation verifies a gain of 104.5 V/V, which is close to our prediction. The small discrepancy is
due to the assumptions and approximations made in our analysis.
Basic Electronic Device Theory
Si C

Some relevant chemistry

Most modern electronic devices are solid-state, meaning they are

B P
built from solid materials as opposed to gas, liquid or plasma
(in contrast to vacuum tubes, for instance). Solid materials can
be crystaline, where atoms are arranged with highly uniform ge-
ometry (e.g. diamond); or amorphous, where no uniform struc- Figure 152: Electron orbit illustration. The valence
ture is discernible (e.g. glass); or they can be poly-crystaline, electrons are shown as red circles. The atoms shown
are silicon (Si, 4), carbon (C, 4), boron (B, 3) and
where small crystal grains are mashed together (e.g. granite). phosphorus (P, 5).
The electronic properties of solids are determined by two
key concepts: charge balance between an atom’s protons and
electrons, and the octet rule which governs stability of electrons Si
occupying an atom’s valence shell (i.e. the outermost orbit). In
order for an atom to be electrically neutral, it should possess Si Si Si Si
a number of electrons equal to the number of protons in its
nucleus, which is equal to its atomic number. Si
But the octet rule dictates that the most stable electronic
configuration is when there are precisely eight valence electrons. Figure 153: Lewis dot diagram notation showing the
valence electrons around a silicon atom (on left), and
An atom can add to its valence shell in two ways: first, by
the joining of neighboring valence electrons to form
participating in covalent bonds, which allow two electrons to four covalent bonds (on right). When neighboring
be shared between neighboring atoms. Second, if the atom atoms are brought together, they can share valence
electrons to satisfy the octet rule. In this example, the
has fewer than eight valence electrons, it can capture a free- center silicon atom (in red) has a complete octet by
moving (i.e. mobile) electron from its environment. A captive sharing one electron from each neighbor.
electron contributes a surplus negative charge bound to the
atom’s location, since there is no matching proton to balance it
out. Note on Electron Volts (eV): energy levels are
usually specified in eV, defined as voltage multiplied
In the converse scenario, if an atom has more than eight into the electronic charge q. So 1 eV/q = 1 V. To put
valence electrons, the surplus electrons are easily removed. it another way, one eV is equivalent to 1.6 × 10−19 J.
The energy needed to separate a surplus electron is much The most common context is when a voltage V is
applied across some material, thereby inducing a
less than what is normally required for a valence electron. shift of qV eV in electon energy levels within the
These electrons may be removed by thermal fluctuations in the material.
material, or by kinetic collisions with mobile electrons. Once a
surplus electron is separated from its atom, it becomes mobile
and is available to conduct current.
168 ece3410 lecture notes

Energy band theory

E

The processes of separating and binding electrons to atomic

orbits is often described in terms of energy bands. At the atomic conduction band

level, electrons have quantized energy states determined by quan-

tum physics. In a sufficiently large volume of solid material,
there can be a truly huge number of electrons and energy states Eg

which we can approximate as a continuous band of energy states.

As an analogy, picture a cup of water. The cup contains a finite
number of molecules, and each molecule has a specific position valence band
in the cup. But since there are so many molecules, it is more x

useful to think of it as a continuous fluid with a statistical den- insulator

sity of molecules per unit volume. We will similarly address E

the statistical density of energy states per unit volume within
energy bands.
conduction band
All solids have two bands, called the valence and conduction
bands, representing the allowed energy states of electrons
Eg
within the material. In an insulator, there is a large gap between
the valence and conduction bands, which means the electrons
valence band
are tightly bound to their atomic orbits and require high energy
x
to remove. In a metal, the conduction band overlaps with the
semiconductor
valence band so that electrons can easily change states and
move around in the material. E
In a semiconductor, the valence and conduction bands are
separated by a relatively small band gap Eg . Thermal excita-
conduction band
tions can provide enough energy for electrons to jump the gap.
At ordinary temperatures, this results in a small number of valence band
electrons in the conduction band, so the material is slightly x
conductive. Electrons can also be excited by photons or other metal
particles if they have energy greater than Eg , so semiconductors
Figure 154: Band structure of insulators, semicon-
are responsive to light and radiation. ductors and metals. A semiconductor has a smaller
Band theory is a consequence of statistical mechanics; in a band gap than an insulator, allowing some electrons
to transition into the conduction band, where they
volume containing a very large number of atoms and electrons, become mobile. The band structure is commonly de-
the electrons’ energies are accounted for by a statistical distri- picted along a lateral position x within the material.
bution called the Fermi-Dirac distribution. In a specific material
at thermal equilibrium, the distribution is centered around an
energy called the Fermi Level, EF , defined as the median electron
energy in the system. In other words, half of all electrons will
have energy below EF , and the other half above EF .
In practice, we usually won’t need to know the precise value
of EF . It is more important to know how close EF lies relative
to the valence or conduction band energies. To analyze these
energy relationships, we will make use of the Fermi-Dirac
 basic electronic device theory 169

distribution equation:
1
f ( E) =  .
1 + exp Ek− ETF
B

This equation is also called the Fermi function for short. The
Fermi function gives the probability that an energy state S at
energy E is occupied by an electron. We could say the Fermi
function has units of electrons per state. Some common bandgap energies (eV):
The Fermi function is completely general, and applies to Material Eg
Silicon (Si) 1.12
any solid material in thermal equilibrium. To understand the Gallium Arsenide (GaAs) 1.424
distribution of charges in a specific material, the Fermi function Germanium (Ge) 0.664
Indium Antimonide (InSb) 0.230
must be joined together with a function for the material’s
Indium Phosphide (InP) 1.344
Density of States. In a semiconductor or insulator, not every Indium Arsenide (InAs) 0.354
energy level is allowed. For example, there are no allowed states Zinc Oxide (ZnO) 3.3
Zinc selenide (ZnSe) 2.822
within the forbidden gap, as illustrated in the figure below.
Energy states within the gap are excluded; they are “chopped
out” from the distribution. Then the amount of mobile charge is
determined by the distribution’s “tail” , the amount surviving
in the conduction band.

E E E

−
−
− − −
− − −
EC
− −
− − − − − − EF − − − − − − EF EF
− − − − − − − − − −
− − − − − − − − − − − − − − − − − − EV
− − − − − − − − − − − − − − − − − −
− − − − − − − − − − − − − − − − − −
− − − − − − − − − − − − − − − − − −
− − − − − − − − − − − − − − − −
f ( E) f ( E) f ( E)
T = 0 K (absolute zero) T ≈ 300 K (room temperature) T ≈ 300 K (room temperature)

Figure 155: Fermi-Dirac distribution at absolute zero

(left), room temperature (middle), and with band-gap
In a solid with numerous atoms, a large number of states removed (right). Notice that the surviving electrons
appear at energy levels very close to each other. We approxi- in the conduction band all have energies close to EC .
mate these states as a continuous "band" and imagine that an
"energy level" is a vanishingly small energy interval of width
dE. The density of states, N ( E), has units of states per energy
level per volume, and is the fraction of all allowed states that
lie within a small segment between E and E + dE. The solution
of N ( E) is simplified by observing that nearly all electrons in
the conduction band will “barely make it”, so they have energy
barely greater than EC . Then N ( E) can be approximated as an
impulse function called the effective density of states, NC , which is
170 ece3410 lecture notes

known to be
 3/2
NC = 2 2π η me k B T/h2

where η is a material-dependent constant, me is the electron rest Physical constants for electrons (e− ):
mass in free space, and h is Planck’s constant. The effective mass
η me is an adjustment that accounts for a variety of material- me = 9.1 × 10−31 kg
specific effects, such as bond lattice geometry and random h = 6.626 070 04 × 10−34 m2 kg/s
collisions with other particles. In general, a lower effective mass k B = 1.380 648 52 × 10−23 m2 kgs−2 K−1
indicates that the material can be used to make faster devices.
Material η
If we consider “number of electrons” as a physical unit, then
Silicon (Si) 1.09
we can interpret the Fermi function as “number of electrons Gallium Arsenide (GaAs) 0.067
per state” in the material. The density of states reveals the Germanium (Ge) 0.55
Indium Antimonide (InSb) 0.013
“number of states per energy level per volume.” Hence when Indium Phosphide (InP) 0.08
we multiply N ( E) and f ( E) together, the resulting units are Indium Arsenide (InAs) 0.023
Zinc Oxide (ZnO) 0.29
Zinc selenide (ZnSe)
e− states e− 0.17
× = ,
state energy level × volume energy level × volume

where “e− ” is shorthand for “electrons.” To find the total den-

sity of mobile electrons in the material, we integrate f ( E) N ( E)
over energies from EC up to the vacuum energy E0 (If an electron
has energy greater than E0 , it will completely escape the mate-
rial and fly off into space). The result reveals a great deal about Note on effective mass: III-V alloy semiconductor
materials like Gallium Arsenide, and specially
the material’s electrical characteristics:
structured lattices like graphene, can have a much
Z E0 lower effective electron mass than IV semiconductors
n= f ( E) N ( E) dE like Silicon. Therefore Si is not the fastest technology,
EC but is currently preferred due to its low cost and ease
Z E0 of manufacturing.
≈ f ( E) NC δ ( EC ) dE
EC
NC
=  
1 + exp ECk −TEF
B

If EC − EF > 4k B T, then we may further simplify the result: Physical constants for holes (h+ ):
Material ηh
E − EF Silicon (Si)
  0.55
n ≈ NC exp − C . Gallium Arsenide (GaAs) 0.45
kB T Germanium (Ge) 0.37
Indium Antimonide (InSb) 0.4
When an e− transitions into the conduction band, it leaves Indium Phosphide (InP) 0.64
behind a hole (h+ ) in the valence band. Holes are able to move Indium Arsenide (InAs) 0.4

around by being exchanged between neighboring valence

shells in the material. A hole is therefore considered to be a Effective density of states for Si at room tempera-
ture:
virtual particle capable of conducting current in the opposite
direction to e− current. Since mobile e− and h+ are available NC = 2.86 × 1019 cm−3
to carry current, they are often referred to as “carriers.” To NV = 1.04 × 1019 cm−3
determine the density of mobile h+ in a material, we again
make use of the Fermi function. This time, we want to calculate
 basic electronic device theory 171

the probability that a state is empty in the valence band, given by

 
exp Ek− ETF
1 − f ( E) = B .
1 + exp Ek− ETF
B

Once again, we approximate the density of states as an impulse

function at the valence band edge, where the effective den-
sity of states is NV . We repeat the integrate-and-approximate
procedure from above to obtain
E − EV
 
p ≈ NV exp − F ,
kB T
where NV has the same form as the expression for NC :
 3/2
NV = 2 2π ηh me k B T/h2

Semiconductor materials Figure 156: Unit-cell structure of the diamond lattice.

Single-crystal structures for carbon and silicon follow
Single-crystal Si is an uninterrupted lattice of pure atoms, which this pattern.

acts as a semiconducting solid. Polycrystaline Si is a random

assembly of crystal grains which act as a resistive material. In
micro- or nano-scale geometries, poly-Si behaves like a conduc-
tor. Today, most electronic devices are made by manipulating
pure Si and/or poly-Si. There are other semiconducting mate-
rials in use besides Si, but the basic principles are mostly the
same, so for now we’ll limit our attention to Si-based devices.
Single-crystal Silicon (Si) is comprised of a repeated crys-
taline lattice with few dislocations. Single-crystal Si comes in
two forms: Figure 157: Scanning electron micrograph of single-
crystal Si. Individual atoms are visible in their
• Intrinsic – one uninterrupted lattice of Si molecules. diamond arrangement.
• Extrinsic – mostly uninterrupted, with periodic insertion of
dopant ions that replace Si atoms at isolated lattice points.
In all types of materials, the mobile charge density is governed
by the mass action law, which dictates that the product of mo-
bile e− and h+ concentrations should be constant. We use the
special symbol ni to denote the e− concentration of an intrinsic
Figure 158: SEM micrograph of poly-crystaline Si,
material in thermal equilibrium. We expect equal concentrations showing the composition of irregular grains rather
of e− and h+ , so pi = ni . Then, using the solutions from energy than a uniform lattice.

band theory, we find

n p = n2i At room temperature:
EC − EV
 
p
where ni = NC NV exp −
2k B T ni = 1.45 × 1010 carriers/cm3
− Eg
 
p k B T = 25.7 eV
= NC NV exp
2k B T k B T = 4.11 × 10−21 J
172 ece3410 lecture notes

This result allows us to conveniently determine carrier concen-

trations without actually knowing the material’s Fermi level.
Random mobile charges are generated by heat energy. In an
− +
intrinsic material, the charges exist in equal numbers. Extrinsic
material is doped with one of two types of impurities:
B P
• Donors – have one excess e− in the valence shell (i.e. five
total), so they donate one surplus mobile e− to the material,
but leave behind one immobile h+ at the lattice point where
the dopant atom resides. Figure 159: To make complete covalent bonds with
Si neighbors, an acceptor (Boron) steals a mobile
• Acceptors – have one too few valence e− (i.e. there are three electron (e− ) to achieve a valence shell of four,
total), so they tend to “steal” or accept a mobile e− from the leaving behind a mobile hole (h+ ). Conversely, a
donor (Phosphorus) donates a mobile e− , leaving
surrounding material, leaving a mobile h+ in the material, behind a fixed h+ at the donor site.
and a fixed e− at the dopant site.

The presence of dopant ions tends to increase the relative

proportion of mobile charges:

• Donors create N-type material, with a suplus of mobile e−

compared to mobile h+ .

• Acceptors create P-type material, with a suplus of mobile h+

compared to mobile e− .

In an extrinsic material, we usually assume that the dopants

positive mobile carriers h+
are dispersed uniformly throughout the crystal structure. The
negative mobile carriers e−
concentration of dopants is usually given with units of “dopant
ions per cm3 .” For an N-type material, we consider the donor Figure 160: Intrinsic single-crystal Si with thermally
concentration, ND , whereas for a P-type material we consider generated mobile carriers.

the acceptor conentration, NA . The amount of doping is usually

Extrinsic Material (P-type)
much larger than the thermally generated concentration, so we
can say that the majority carrier concentration is approximately
equal to the dopant concentration. We then apply the mass
action law to determine the minority carrier concentration:

majority minority
n2i
N-type (donors) n = ND p= ND
n2i
P-type (acceptors) p = NA n= NA

Now let’s take a closer look at the P-type material illustrated positive mobile carriers h+
in Figure 161. The sum of all charges must balance to zero at negative mobile carriers e−
equilibrium (i.e. when no external energy is applied). Athough negative fixed charges
the P-type material has fewer mobile e− , there are correspond-
Figure 161: Extrinsic P-type single-crystal Si doped
ingly more fixed negative charges at the dopant sites, so the with acceptors, yielding a surplus of mobile h+
material has zero net charge. The situation is the same for balanced by fixed negative charges at the acceptor
sites.
N-type material, where the charge polarities are swapped.
 basic electronic device theory 173

Example 30 (Charge density in doped semiconductors).

A typical N-type silicon material might have a donor density of ND = 1016 dopants per cm3 . In this
material, at thermal equilibrium (with no externally applied potential and no net current flow), the
equilibrium charge concentrations will be

dopants
nn ≈ ND = 1016
cm3
n2i
pn ≈
nn

2
1.5 × 1010 carriers per cm3
=
ND = 1016 carriers per cm3
= 2.25 × 104 carriers per cm3 .
174 ece3410 lecture notes

Energy Bands and the Fermi Level in Doped Semiconductors

Doping alters the balance of mobile carriers in a semiconductor.

This means that the statistical distribution of electron energies
is changed, primarily due to a shift in the material’s Fermi
level EF . Recall that the Fermi level is the median energy of
all electrons in the system; half of electrons have energy above
EF , and half have energy below (this description applies before
chopping out the band gap). In an undoped semiconductor,
the intrinsic Fermi level Ei is roughly halfway between the
conduction band and valence band edges. When the material’s
Fermi level is disturbed by doping, the mobile carrier densities
are related to the change in the Fermi level as follows:

EF − Ei
 
n = ni exp
kT −
−

Ei − EF
 
−
p = ni exp − −
EC
kT EF

− − − − − − EV
− − − − − −
− − − − − −
− − − − − −

a To put it more simply, when the Fermi level is closer to the − − − − −

f ( E)
conduction band edge, it means there are more mobile electrons N-Type Material with Donors
in the material. When the Fermi level is closer to the valence E
band edge, it means there are more mobile holes in the material.
For typical doped semiconductors, where the doping concentra-
tion is much greater than ni , the Fermi level is predicted by a
simple approximation:
EC

EF
− − − EV
− − − − −
  − − − − − −
ND − − − − − −
(N-type) EF = Ei + kT ln − − − − − −
ni f ( E)
 
NA P-Type Material with Acceptors
(P-type) EF = Ei − kT ln
ni
Figure 162: How doping affects the Fermi level. Note
the presence of conduction-band electrons in the
N-type case, and the presence of valence-band holes
(empty spots) in the P-type case.
 basic electronic device theory 175

Example 31 (Fermi levels in doped silicon).

Part A: A piece of single-crystal Si is doped with Phosphorous (a donor species) with a dopant den-
sity of ND = 1016 dopants per cm3 . Calculate the concentration of majority carriers (electrons) and
minority carriers (holes) in this material at room temperature. Also calculate the change in Fermi
level due to doping, and compare it to the bandgap.
Solution A: For moderately high doping concentration (greater than 1010 dopants per cm3 ), the den-
sity of majority carriers approximately equals the doping concentration. The mass-action law dictates
that n × p = n2i , and for Si at room temperature, ni ≈ 1.45 × 1010 carriers per cm3 . Then the densities
are

n ≈ ND = 1 × 1016 carriers/cm3
n2i
p= = 2.1 × 104 carriers per cm3
n
Compared to intrinsic Si, the Fermi level is moved by this amount:
 
ND
∆EF = EF − Ei = kT ln
ni
 
= (25.7 meV) ln 6.5 × 105
= 345.5 meV

Since Si has a bandgap of Eg = 1.12 eV, the Fermi level is shifted toward the conduction band edge
by 0.3455
1.12 , or about 30% of the band gap. Part B: A piece of single-crystal Si is doped with Boron (an

acceptor species) with a dopant density of NA = 1016 dopants per cm3 . Calculate the concentration of
majority carriers (holes) and minority carriers (electrons) in this material at room temperature. Also
calculate the change in Fermi level due to doping, and compare it to the bandgap.
Solution B: This problem is completely symmetric to Part A, only the carrier’s polarity is reversed.
The majority carriers are now holes, and the Fermi level will be moved downward toward the valence
band. The calculations are otherwise identical:

p ≈ NA
n2i
n= = 2.1 × 104 carriers per cm3
p

 
NA
∆EF = EF − Ei = −kT ln
ni
 
= − (25.7 meV) ln 6.5 × 105
= −345.5 meV

So in this case the Fermi level is shifted downward by about 30% of the band gap.
176 ece3410 lecture notes

Mechanisms of Current Flow

Acs
There are two major mechanisms for current flow in physical
systems: Drift current is motion of charge due to an electric
field (E field). Diffusion current is random motion of charge e−
Idrift
that tends to flow from areas of high charge concentration h+
toward areas of low concentration.
To begin with, we consider the drift velocity of charge car-
+ E −
riers in a solid material. Any charged particle will accelerate
under the influence of an externally applied E field. In free Figure 163: Illustration of drift current induced by an
electric field. The current Idrift flows from the left to
space, a particle can be accelerated toward the velocity of light the right through the volume. The total current is
(called ballistic transport). In a solid material, the particle reaches proportional to the cross-sectional area ACS .
a lesser velocity vdrift as determined by the material’s mobility
(µ), which has units of velocity per electric field. The mobility
describes the terminal velocity of a particle as it moves through
a solid, sort of like the terminal velocity of an object falling
through air. As a particle moves through a solid, it tends to
follow an irregular path disturbed by collisions with other par-
ticles, and with atoms in the crystal lattice. The average effect
of all those collisions is lumped together in the mobility param-
eter. We usually consider mobility to be a constant, but it does
1,500
have some dependency on temperature and on the total charge µn
density. µp
Given the average e− velocity, the current density (Jdrift ) is
1,000
the product of vdrift with the carrier density (n or p) and the
elementary charge per carrier (q). To obtain the total current, we
multiply the current density into the total cross-sectional area
(Acs ) through which the current flows. 500

Property for Electrons for Holes units

vdrift = −µn E µpE cm/s 0
Jdrift = µn E qn µ p E qp A/cm2 14 16 18 20
Idrift = − Acs µn E qn Acs µ p E qp A Figure 164: Mobility in Si as a function of dopant
Note that there is a double-negative in the expression for elec- concentrations for electrons and holes when doped
with Phosphorous (N-type) and Boron (P-type).
tron flow; the electron velocity is negative (motion against the E
field), but the electronic charge is also negative, so the current
L
flows in the positive direction (with the E field). Putting all this
together, the total drift current in a material is given by


Idrift = AµE q pµ p + nµn .
+ E −

Resistivity
The drift current mechanism supplies the electronic theory
underlying the classical lineary property of resistivity. If the
material is homogeneous, meaning it has the same composition
+
−

Figure 165: Illustration of resistivity in a homoge-

neous semiconducting material.
 basic electronic device theory 177

throughout its volume, then the drift current should usually be E

proportional to an applied voltage. Suppose a voltage V is ap-
E
plied across a section of material with length L. This will induce
a constant electric field in the material, E = V/L. Combining
- -
this with the expression for Idrift , we obtain - - -

Idrift = Acs qE µ p p + µn n
V
x (position)
= Acs qµ p p + µn n
L
V A 1 Figure 166: Energy bands are tilted in the presence
⇒R= = CS
of an E -field. Electrons tend to “roll” down the
Idrift L q µ p p + µn n
slope from higher energies toward lower energies.
Finally we can see that the expression has the same form as Note that the same process will cause holes to be
transferred up the hill. Since a current is flowing, the
classical resistivity, R = ρACS /L, where the ρ is the material’s
system is not in equilibrium. The Fermi level is only
resistivity defined as well-defined for systems in equilibrium, so there is
no EF here.
1
ρ=
.
q µ p p + µn n

Example 32 (Drift current in a homogeneous material.).

Suppose a piece of single-crystal silicon with dimensions 1 mm × 1 mm × 1 cm is doped P-type with

acceptor concentration NA = 1015 donors per cm3 . The material is homogeneous, which means it
has uniform composition throughout its volume. It has a mobility for holes of µ p = 462 cm2 /Vs. A
potential of 1 V is applied the long way across the material. Calculate the resulting electric field and
the drift current that will flow in response.

Solution: First note that the electric field has units of V/cm. Since 1 V is applied across the “long
dimension” of 1 cm, the electric field should be E = 1 V/cm. Since the material is P-type, the majority
carriers are h+ . We can ignore the negative carriers with little consequence. Then the h+ velocity and
drift current density are

vdrift ≈ µ p E = 462 cm/s

Jdrift ≈ q ND vdrift = 0.074 A/cm2

Lastly, the cross-sectional area is 1 mm × 1 mm. Since material units are most often given in terms of
centimeters, we must take care to convert all dimensions to centimeters and ensure that the units
properly balance. Then the cross-sectional area and total drift current are:

ACS = 0.1 cm × 0.1 cm

= 0.01 cm2
Idrift = ACS Jdrift
= 740 µA.
178 ece3410 lecture notes

Diffusion closed chambers, at equilibrium

Diffusion is the process by which randomly moving particles

establish a net flow along a concentration gradient. To visualize
diffusion, consider a box with three chambers as shown in Fig-
ure 167. The box is full of particles represented by little flies that
move randomly. The left-most chamber has the most flies, and
the right-most has the least. We suppose that the concentration
of flies, N ( x ) [particles per cm3 ], changes uniformly so that opened chambers, disturbing equilibrium
there is a constant ∆N , N ( x ) − N ( x + 1). Also imagine that the
chambers continue indefinitely to the left and to the right, so we
are looking somewhere in the middle of a large system.
If the partitions are suddenly removed then the flies will
freely migrate between chambers. Suppose that after a short
time ∆t all flies have moved either −∆x (to the left) or +∆x
(to the right). Each fly has equal probability of moving either
direction. So half the flies from N (0) move to the right into Figure 167: Illustration of diffusion with flies in a
terrarium. The three chambers are initially closed.
chamber 1, and half of N (1) move to the left into chamber 0. So
When the doors are opened, flies tend to migrate
after ∆t, the net movement across the boundary is randomly into neighboring chambers. Chambers
with higher concentration simply contribute more
N (0) N (1) flies than those with low concentration. Hence the
N0→1 = − average flow tends to be from high concentration
2 2
towards low concentration.
∆N
=
2
The net particle flux is then equal to the net number of trans-
ferred particles times their average velocity, ∆x/∆t:

∆N ∆x
   
φdiff = × (1)
2 ∆t
!
∆N (∆x )2
 
= × (2)
∆x 2∆t
= ∇ N (x)D (3)

Here we have introduced two important concepts: the gradient

∇ N ( x ) [particles per cm], defined as the spacial derivative of
concentration with respect to position:

∂N ( x )
∇ N (x) , .
∂x
This tells us that the diffusion current is proportional to the
concentration gradient; particles flow from regions of high
concentration toward regions of lower concentration.
The second new concept is the diffusivity D, with units
cm2 /s. Diffusivity indicates the speed with which particles
move under thermal excitation. It is a property of Brownian
 basic electronic device theory 179

motion, an important branch of thermodynamics that was illu-

minated in one of Einstein’s first papers. Diffusivity is strongly
related to both temperature and mobility, and is quantified in
the famous Einstein relations:
kB T
D=µ .
q
= µUT ,

where UT is the highly important “thermal voltage” that arises

in many device equations. At room temperature, UT = 27 mV.
This quantity is ubiquitous in electronics since most devices
rely in some way on diffusion, and UT determines the speed of
diffusion via the Einstein relations.
Now let’s suppose that the flies are electrons. To obtain the
current density from the particle flux, we include the charge −q.
In a semiconductor, holes are also able to diffuse with charge
+q. So there are two components of diffusion current:

Jdiff (e− ) = −q∇n( x ) Dn

Jdiff (h+ ) = q∇ p( x ) D p

In these expressions we included the position x since the gradi-

ent can change at different positions in the material.
180 ece3410 lecture notes

Combined Expression for Diffusion and Drift

From the analyses above, we know there are two mechanisms
of current flow (drift and diffusion) and two species of charge
carriers to carry current (electrons and holes). The total current
in a semiconductor is the superposition of all four:


Jdrift = qE µ p p + µn n


Jdiff = q ∇ pD p − ∇nDn
J = Jdiff + Jdrift
I = ACS J

In equilibrium these current mechanisms can occur, but the

total current must balance out to zero. To have a non-zero net
current, there must be an excess in at least one mechanism.

Example 33 (Drift and diffusion currents).

A piece of N-type Si has a “built-in” uniform E -field of 1 V cm−1 and a cross-sectional area of
0.01 cm2 . At a point x = 0 along the direction of current flow, the electron concentration is
n (0) = 16 − 3
10 e /cm . If the material is in thermal equilibrium, solve an expression for n( x ). As-
sume that the electron mobility is constant at µn = 1200 cm2 /Vs, and the thermal voltage is
UT = k B T/q = 27 mV. Furthermore assume that the minority carriers (holes) are negligible. Lastly,
calculate the drift and diffusion currents at a position of x = 1 µm, and state the electron concen-
tration at that position. How can the material be in equilibrium if an electric field and currents are
present?

Solution: Since the material is in equilibrium, the drift and diffusion currents must cancel each other
out. Therefore:

qE µn n = q∇nDn
µn
⇒ ∇n = nE
Dn
E
=n
UT

A differential equation of this form has only one non-trivial solution: n( x ) must be exponential with
respect to x:
Ex
 
n( x ) = n(0) exp .
UT
At the position x = 1 µm = 0.001 cm, the electron concentration is n( x ) = 1.037 73 × 1016 e− /cm3 .
Then the drift current is 19.95 mA and the diffusion current is −19.95 mA. In spite of all this activity,
the material is in equilibtrium since the net current from all contributors balances out to zero.
 basic electronic device theory 181

Velocity saturation and high-field effects

At first glance, the electronic theory seems to merely replicate
the classical concept of linear resistivity. In fact the electronic
theory reveals a much more complex family of nonlinear phe-
nomena. Electronic theory agrees with the classical theory only
under some key conditions: bulk material: there must be a
huge number of atoms and charge carriers in the material; con-
stant mobility: the mobility must not be affected by changes
in carrier concentration, electric field or current; homogeneity:
the material should have uniform characteristics throughout;
closed system: the material must be isolated from any exotic
interactions (e.g. photons or particle radiation). We will see that
there are lots of useful cases where these conditions don’t apply.
In this course, we will usually assume that mobility is con-
stant, but electronic devices are increasingly affected by a
phenomenon known as a velocity saturation. When the electic
field strength is strong enough, the average particle velocity is
no longer simply proportional to the E -field. In this “high-field”
regime, carrier velocities saturate at a maximum velocity that no
longer increases with a rising E -field. In Si, the saturation velocity is vsat ∼ 1 × 107 cm/s.
The PN Junction

As the name implies, a PN junction is formed when a section of

P-type material is joined to a section of N-type material. This
simple junction has myriad consequences which form the basis
of all semiconductor electronic devices. We will first examine
the PN junction in equilibrium, with no externally applied bias
and no net current in the material. Then we will study what
happens when equilibrium is disturbed due to reverse bias
(VN > VP ) and forward bias (VP > VN ).

Neutral bias

P xp xn N

E
− +

positive mobile carriers h+ positive mobile carriers h+

negative mobile carriers e− negative mobile carriers e−
negative fixed charges positive fixed charges

Figure 168: PN junction in equilibrium. Mobile car-

riers combine near the junction, forming a depletion
When N-type and P-type materials are joined together, their
region of width W.
mobile charges tend to diffuse across the junction. Mobile e−
and h+ are attracted to each other, so they tend to meet and
annihilate. As a result, the space near the junction becomes
depleted of mobile carriers. This region is called a depletion
184 ece3410 lecture notes

region or space charge region. As indicated in Figure 168, the

depletion region extends a distance of xn [cm] into the N side,
and x p [cm] into the P side, with total width W [cm]. We will
use electrostatic theory to determine the precise dimensions.
Although the mobile carriers are stripped away in the de-
pletion region, dopant ions remain. On the P-type side, each
acceptor ion retains a surplus e− in its orbit, resulting in an
immobile negative charge. On the N-type side, each donor ion
retains an immobile h+ . There is consequently a net positive
charge Q P on the P-type side and a net negative charge Q N on
the N-type side within the depletion region. Since there is a
non-zero net charge, there is a built-in electric field E oriented
from the N side toward the P side. And since there is an E -field
present, there is also a built-in potential V0 across the junction. P depletion N
The remaining material outside the depletion region is called
the quasi-neutral region. This region behaves like a homoge-
nous extrinsic material: mobile charges balance out the fixed
dopant ions, so there is zero net charge. At equilibrium, there EC
should be no E -field and no potential drop across the quasi- EF
neutral region. With no E -field present, the drift and diffusion
currents should also average to zero.
Because the material is in equilibrium, the Fermi level is
well-defined and we can use energy band theory to predict V0 .
As indicated in Figure 169, the conduction and valence band
EV
energies can “bend” in the depletion region. The Fermi level,
on the other hand, is a statistical constant for the entire system.
This means that EC and EV must curve in order to accomodate a
constant EF . On the P-side, EF is below Ei by kT ln ( NA /ni ) eV. Figure 169: Energy band bending in the depletion
On the N-side, EF is above Ei by kT ln ( ND /ni ) eV. In order for region. At equilibrium, the bands bend so that EF is
constsant between the N and P sides.
EF to join on both sides, the bands have to bend by the sum of
these differences:

∆E = kT ln ( NA /ni ) + kT ln ( ND /ni )
!
NA ND
= kT ln [eV]
n2i

This result has units of electron volts. We convert this to volts

by dividing out the elementary charge q, which gives us the
built-in potential:
!
kT NA ND
V0 = ln
q n2i
!
NA ND
= UT ln [V]
n2i
 the pn junction 185

Since the junction has a built-in potential drop V0 across the

junction, there must be a corresponding E -field. By applying ρ( x )
Maxwell’s equations in one dimension, we can determine the qND
relationship between V0 , E ( x ) and the fixed charges Q N and Q P .
First, let’s state the boundary conditions: QN

• The net charge density, ρ( x ) [C/cm3 ], is equal to zero in the −x p x

quasi-neutral regions. In the depletion region there are two xn
QP
sides:
−qNA
– P side (− x p < x < 0): ρ( x ) = qNA
– N side (0 < x < xn ): ρ( x ) = −qND

• At equilibrium, the net charge must balance to zero, so the

total charge on the N side must be opposite the total charge
E (x)
on the P side. Therefore Q P = − Q N . Since the charge density
is constant in the depletion region, this means that
Emax
Q P = − x p × qNA
Q N = xn × qND
⇒ x p NA = xn ND

• The E -field is only present in the depletion region where a

net charge is present; in the quasi-neutral regions it must
drop to zero. x
−x p xn
• Since the charge density is negative on the P side and posi-
tive on the N side, the E -field should be oriented N-to-P, and
V (x)
should be maximum at the junction (x = 0).

• Since the potential drop V0 is relative, we define the quasi-

V0
neutral potential on the P side to be 0 V, and on the N side as
−V0 V.

From these boundary conditions, we can apply Poisson’s

equation to obtain the E -field and potential difference across the
junction:
Z x x
−ρ( x )
E= dx ( x < 0) −x p xn
−x p e
Z x
ρ( x )
= Emax − dx ( x > 0) Figure 170: Net charge density, electric field strength
0 e
Z xn and potential drop across the depletion region at the
V0 = E dx PN junction. Note that the doping concentrations
−x p differ on each side, in this example ND > NA (which
is typical in digital semiconductors). Since the total
where ρ( x ) is the charge density in the material and e is the ma- charge is the same on each side, the depletion depth
must be shallower on the N side, i.e. xn < x p .
terial’s permittivity. The charge density is equal to the dopant
186 ece3410 lecture notes

concentration, which is constant on each side, therefore the E

field takes a triangle shape, and the potential is found as the
area under the triangle:
qNA x p
Emax =
e
qND xn
=
e
1
V0 = W Emax ,
2
Therefore:
 
W qND xn
V0 =
2 e
Now recalling the charge balance between Q N and Q P , we
can further simplify the expression:

W = xn + x p ,
ND
x p = xn
N
A 
ND
⇒ W = xn 1 +
NA
W NA
⇒ xn =
NA + ND
Now we can substitute for xn into the solution for V0 :
 
qW ND W NA
V0 =
2e ND + NA
  
2 1 NA ND
=W
2e NA + ND
s  
2e 1 1
⇒W= + V0
q NA ND

Up to this point, we know V0 from energy band theory, and

we know W from Maxwell’s equations. We will add to this
discussion one important special case: if the doping on one
side of the junction is much greater than the other, then the
depletion region extends almost totally into the weakly doped
side. This case is called a one-sided junction. Since Si wafers
are commonly weakly doped p-type, junctions are formed on
the surface with much stronger N-type doping. Then ND  NA ,
and the depletion depths are:
ND
xn = x p
NA
N
x p = xn A
ND
 the pn junction 187

So if ND is 104 × greater than NA , we expect x p to be 104 ×

greater than xn , so in the common case of a one-sided junction
on the P side:

W ≈ x p (one sided, ND  NA ).

Reverse Bias

Next let’s consider what happens when a “reverse” potential

is applied to the junction, so a positive bias VR is applied to
the N side relative to the P side. The applied voltage must be
absorbed by the junction, and adds directly on top of V0 . As P ←− E N
a result, the E -field strength must increase and the depletion
region must grow wider:

1
W Emax
V0 + VR =
2
s  
2e 1 1
⇒W= + (V0 + VR )
q NA ND
++++
2 (V0 + VR )
Emax =
W − − − − EC

From this we see that the E -field strength increases with VR1/2 ,
which enhances the opposition to current flow. The energy band
interpretation is illustrated in Figure 171.

EV
Leakage Current

In reverse bias, the junction current is not precisely zero. Even

though carriers are blocked from entering the depletion region,
Figure 171: Energy bands in reverse bias. The barrier
a few carriers are continually present due to spontaneous
is increased against mobile charge flow, since e−
thermal generation in the depletion region. From time to time, would prefer to flow downhill from the N side, and
an e− /h+ pair spontaneously appear and are swept apart by h+ like to flow up hill from the P side. But the hill is
now steeper.
the E -field, allowing a small current to flow in the device. At
neutral bias, these charges simply generate and recombine in
an equilibrium process. When a reverse bias is applied, the
minority charges are attracted to the device’s terminals, which
disturbs equilibrium and sets up a net current. Since the rate
of generation and recombination is uniform throughout the
material (including the quasi-neutral regions), the leakage
current is approximately constant and usually far below a micro
ampere. In practical diodes, the leakage current may show a
very slight dependence on VR due to surface conduction, caused
by material changes on the outer surfaces of the diode.
188 ece3410 lecture notes

Junction Capacitance in Reverse Bias A

P N
The depletion region behaves like a parallel-plate capacitor
with a variable capacitance. This concept is illustrated in Fig- depletion
ure 172. Since the reverse-bias potential alters the depletion
width, we can alter the separation between the two “plates” of
the capacitor, thereby changing the capacitance:
W
s
Figure 172: Illustration of the reverse-biased junction
 
2e 1 1
W= + (V0 + VR ) as a parallel-plate capacitor.
q NA ND
where VR is the applied reverse-bias voltage. Then W is the For Si:
inter-plate spacing and the capacitance is:
s   eR = 11.9
e qe NA ND 1 e0 = 88.5 fF/cm2
Cdep = A =A
W 2 NA + ND V0 + VR
Cj0
=  m
VR
1+ V0

where Cj0 is a summary constant and m is the junction grading

coefficient, nominally m = 0.5 for a perfectly abrupt junction. In
real junctions, the P and N regions are often blended, and better
physical accuracy is obtained by using a different m.

Example 34 (Junction capacitance due to depletion).

A Si PN junction has NA = 1016 dopants/cm3 , ND = 1018 dopants/cm3 , the cross-section area is

ACS = 1 × 10−4 cm2 , and the grading coefficient is m = 1/2. Assuming romo temperature, calculate
the zero-bias depletion width W and the junction capacitance Cj0 . How does the junction capacitance
change when a reverse bias of 2 V is applied?
Solution: Si has relative permittivity of 11.9, and the vacuum permittivity is e0 = 8.85 × 10−14 F/cm2 ,
so the total permittivity is e = 1.05 × 10−12 F/cm2 . At zero bias (i.e. at equilibrium), the built-in po-
tential and depletion width are given by
! s  
NA ND 2e 1 1
V0 = UT ln = 0.85 V W = + V0 = 0.122 cm
n2i q ND NA

Then the junction capacitance is Cj0 = ACS e/W = 86.4 fF. When a 2 V reverse bias is applied:

Cj0
Cj =  1/2 = 47.2 fF,
VR
1+ V0

So the capacitance is reduced by about half when applying a 2 V bias.

 the pn junction 189

Reverse Breakdown

When the reverse bias potential VR exceeds a critical threshold,

the junction is said to “break down” and behaves like a low-
valued resistance. The current can suddenly become quite large
and can damage the junction unless some limits are externally
imposed. There are two mechanisms behind this breakdown.
The first mechanism is called the avalanche effect, in which elec-
trons’ average kinetic energy exceeds the ionization energy
within the depletion region, leading to a huge increase in mo-
bile carriers. The second mechanism is quantum tunelling, also
called the Zener effect after Clarence Zener. When a junction is
designed as a “Zener diode,” it means it is intended to be used
at or near its breakdown point. If the breakdown point occurs
below 5.6 V, the tunneling mechanism most likely applies. For
breakdown points beyond 5.6 V, the avalanche mechanism usu-
ally applies. Avalanche and tunelling mechanisms also occur in
other electronic structure and applications.

Avalanche Breakdown

The avalanche breakdown mechanism is caused by electron

collisions in the semiconductor lattice. If the electron is very
energetic, then it may transfer enough impact energy in the
collision to bridge the bandgap Eg . This will occur when the
maximum E -field in the junction exceeds a critical strength, Ecrit .
The E -field is related to the junction potential by the expression
we solved previously

2 (V0 + VBR )
Ecrit =
s W  
2e 1 1
W= + (V0 + VBR )
q NA ND
2 (V0 + VBR )
⇒ Ecrit = r  
2e 1 1
q NA + ND (V0 + VBR )
2 
qEcrit

1 1
⇒ VBR = + − V0 .
2e NA ND

This indicates that the breakdown voltage is inversely propor-

tional to the weaker doping between NA and ND . So to achieve
a low breakdown voltage (as is usually the case in Zener diodes),
relatively strong doping is needed on both sides of the junction.
190 ece3410 lecture notes

Example 35.

Avalanche breakdown voltage. Suppose a juntion is doped with NA = 1015 dopants/cm3 on the P
side and ND = 1017 dopants/cm3 on the N side. The reverse breakdown potential is found to be
VBR = 300 V. Now suppose another junction is fabricated with NA increased to 101 6 dopants/cm3 .
How will VBR change in the new junction?
 
Solution: In the first case, the built-in potential is V0 = UT ln NAnN
2
D
= 0.725 97 V. Let V00 and VBR
0 be
i
the built-in potential and breakdown potential for the second case, respectively. Since the doping on
the P side is now equal to NA0 = 1016 dopants/cm3 , we find that V 0 = 0.788 14 V Then, since V + V
0 0 BR
1 1
is proportional to N + ND , we can say that
A

1 1
V00 + VBR
0
NA0 + ND
= 1 1
V0 + VBR NA + ND
 
1 1
NA0 + ND
0  − V00
⇒ VBR = (V0 + VBR )  1 1
NA + ND

= 31.96 V

P ←− E N
Tunneling Breakdown
When the doping concentration is especially high, the built-in
potential increases and the depletion width decreases. This re-
sults in a steep energy band transition, as shown in Figure 173.
At the level where Ec aligns with Ev , separated by a small
distance L, it is possible for electrons to undergo quantum me- −−−−
chanical tunneling across the barrier. Quantum theory reveals ++++
that the tunneling current density is given by EC
!
4L 2m∗ Eg
p
Jtunnel = qv R n exp − ,
3h̄

where m∗ is the effective electron mass, and v R is an average

velocity constant known as the Richardson velocity. Since the
current is exponential in L, the diode switches on it a manner EV

similar to the forward bias ON current.

Figure 173: Illustration of the tunelling process

in strongly doped junctions. When the doping
concentration is especially high, the depletion region
is very thin. If the conduction band energy on one
side aligns with the valence band edge on the other,
then electrons can tunnel through the barrier without
actually crossing it. Once through the barrier, the
electrons freely recombine with holes on the other
side, supporting a current.
 the pn junction 191

·10−4
In practical terms, the main difference between tunneling and
avalanche mechanisms is in their response to temperature. In
5
each case, temperature effects are measured via the temperature
coefficient parameter, defined as

dVBR
TC , ,
dT 0

with T being the temperature in Kelvin. For Zener breakdown,

the temperature coefficient is negative, so VBR tends to shift to
lower values at higher temperatures. For avalanche breakdown,
the temperature coefficient is positive, so VBR tends to increase −5

with rising temperature. These effects can have significant con-

sequences for some sensitive circuits. For critical applications, 4 6 8 10
the two mechanisms can be made to balance each other out Figure 174: Typical temperature coefficients of
Zener diodes, superimposing the contributions from
when VBR is around 5.6 V, so it is possible to obtain a Zener
avalanche and tunneling mechanisms.
diode with nearly zero temperature coefficient at that voltage.
Typical temperature coefficients for Si Zener diodes are shown
in Figure 174.

Example 36 (Zener temperature coefficients.).

A Zener diode with a nominal breakdown voltage of 4.5 V has a temperature coefficient TC =
−0.3 mV/K. If the diode’s temperature rises to 400 K, how will that alter the breakdown voltage?
Solution: Since the nominal breakdown voltage is defined for room temperature, 300 K, the change
in temperature from nominal conditions is ∆T = 100 K. Then the change in breakdown voltage is
∆VBR = TC × ∆T = −40 mV. Then the actual breakdown voltage should shift to 4.46 V.
192 ece3410 lecture notes

Forward Bias

At last we can examine the junction’s behavior in forward bias. P ←− E N

Since the full analysis is quite complex, in this section we will
just summarize the relevant mechanisms that contribute to −
current flow in forward bias. Starting from zero bias, where
there is zero net current, the junction is in equilibrium. In the q (V0 − VF )
−−−− EC
equilibrium condition, the drift and diffusion currents balance
perfectly at the edges of the depletion region. If a forward
voltage is applied across the junction, something must occur to
create an imbalance between drift and diffusion, so that a net
current appears. Furthermore, since the potential across the ++++
junction is reduced, the depletion width must shrink. In order
EV
for this to happen, extra mobile carriers must be generated +
at the edges of the depletion zone. Newly generated carriers
appear as electron/hole pairs. On each side of the depletion
zone, the majority carriers are rejected from the depletion Figure 175: Energy bands in forward bias. The
region by the strong E -field. But diffusing minority carriers are barrier is decreased but there is still opposition to
majority carriers. Minority carriers (indicated in red)
accelerated by the field and swept into the depletion zone, are generated at the edges of the depletion zone.
where they establish a current. They diffuse into the zone where they are swept up
by the E -field.
Based on this reasoning, we conclude that the forward-
bias current is due to diffusion of minority carriers, electrons
on the P side and holes on the N side. The full analysis is
quite complex, but we can obtain an approximate solution by
revising the Fermi level theory. On the P side, let n p0 be the
minority carrier concentration at equilibrium (here the n refers
to electrons, the subscript p refers to the P-type side, and the
subscript 0 indicates equilibrium). Similarly on the N side, let
pn0 be the minority carrier concentration at equilibrium. We
know from before that
EF − EC
 
n0 = NC exp
kT
EV − EF
 
p0 = NV exp
kT
n0 p0 = n2i

When equilibrium is disturbed due to a forward voltage VF , the

Fermi level is no longer well defined, however a new pair of
quasi-Fermi levels can be defined separately for electrons and
holes. The separation between the respective quasi-Fermi levels
(n) ( p)
is EF − EF = qVF . Quasi-Fermi levels represent the disturbed
balance between minority and majority carriers, and can vary at
different positions in the material. The quasi-Fermi levels also
disturb the mass-action law, as governed by the so-called Law
 the pn junction 193

of the Junction:  
VF
np = n2i exp .
UT
Since the majority concentration is set by the dopant concen-
tration, the increased concentration appears mainly in the
minority carriers. As a very rough approximation, we suppose
those new carriers appear as an impulse function at the very
edge of depletion, so the minority carrier gradient is equal to
the impulse height. Minority carriers will diffuse due to this
sharp gradient in a process called minority carrier injection.
Then the diffusion current should be
 
VF
I = IS exp ,
UT
where IS is a scale constant. It so happens that IS is equal to the
reverse bias leakage current. A full analysis of generation and
recombination reveals the scale current to be
Dn n p0 D p pn0
 
IS = qACS + ,
Ln Lp
where Ln and L p are the mean diffusion length parameters for
electrons and holes, respectively. The diffusion length refers
to how far a particle diffuses, on average, before it recombines.
The diffusion lengths are obtainable from the diffusivity and the
average carrier lifetime τ:
√
Ln = Dn τn
q
L p = D p τp ,

where τp and τn are the recombination lifetimes of holes and

electrons, respectively. Calculating the lifetimes is not simple,
and they are usually measured empirically. The concept of
carrier lifetime is important for several effects and applications.
Since the diffusing carriers last for some time in the material,
there is a limit on how quickly the diode can be switched
between OFF and ON states. The current does not immediately
shutoff when the bias is reversed.This limitation is linked to
the scale current by the expression above: a larger scale current
implies smaller lifetimes and therefore faster switching, but
also implies higher leakage when the diode is OFF. This is also
called a hysteresis effect and can pose significant limitations in
radio-frequency (RF) circuits.

Capacitive Behavior in Forward Bias

Since diffusing minority carriers occupy the junction for some
time, we can say they are stored in the junction during their
194 ece3410 lecture notes

lifetime τ. This results in a diffusion capacitance that is distinct

from the reverse-bias junction capacitance. For strong forward
bias, the diffusion capacitance becomes larger than the depetion
capacitance, and increases exponentially with the applied
forward voltage. This capacitance is defined differentially as

dQ
Cdiff =
dV
d
= Iτ
dV
I
= D τ,
UT
hence the capacitance is directly proportional to the forward-
bias current ID . Note that in a one-sided junction, where the
depletion region extends mostly into the weakly doped side
(usually that’s the P side), the characteristics are dominated by
the weaker doping. In that case, the average lifetime is τ = τp .

The “Ideal” Diode Model

The physics underlying forward and reverse bias, excluding

breakdown, can be merged into a single expression commonly
called the “ideal” diode model. The model includes an ad-
ditional parameter n, knowns as the emission coefficient or
ideality factor, which corrects for additional physical effects
that were left out of the analysis. The combined expression is
  
vD
i D = IS exp −1 ,
nUT

where the parameter IS accounts for both the forward bias

scale current and the reverse leakage. This model is justified by
idealized analysis of the PN junction, but doesn’t account for
everything. Some additional phenomena that have relevance in
real applications are recombination current, high-injection (i.e.
high-current) effects, and temperature sensitivity.

Recombination Current
In strong forward bias, the diode’s current is primarily driven
by minority carrier diffusion. Parameters like IS and n are
defined to accurately model the forward bias current, but they
don’t always provide the best model for weak forward bias
or reverse bias. In these cases, a much smaller drift current is
present, caused by thermal generation of mobile charge pairs
in the depletion region. A small amount of mobile pairs appear
 the pn junction 195

spontaneously and are immediately swept apart by the E -field.

When the carriers reach the edge of depletion, they recombine
with other charges in the quasineutral region, resulting in a
small generation-recombination current, or just “recombination
current” for short. The recombination current behaves like a
second diode connected in parallel with the bulk junction, and
is modeled by a similar exponential expression:
  
vD
i DR = ISR exp −1 ,
n R UT
where n R is a distinct ideality factor for recombination. The
diode’s total current is equal to the superposition of “normal”
and recombination currents:
     
vD vD
i D = IS exp − 1 + ISR exp −1 .
nUT nSR UT

Sidewall or Surface Currents

In practice, a diode is not usually a perfect junction in the bulk
of two semiconducting regions. Additional effects happen
around the diode’s outer surfaces which can create a bypass
path for carriers to move and recombine, giving rise to a “side-
wall” or surface recombination current that can be significant.
The word “sidewall” refers to a layer of insulation used to iso-
late diodes in integrated circuits. The insulation also contributes
some additional capacitance around the diode’s perimeter. This
has the effect of increasing IS , however the sidewall current is
proportional to the junction’s perimeter, unlike the bulk scale
current which is proportional to the junction’s area.

High-Injection Effects
When the junction is placed in a sufficiently strong foward bias,
the minority carrier concentrations exceed the material’s doping
concentration. In order to preserve net charge neutrality in the
quasi-neutral regions, the concentration of majority carriers
must also increase. This sets up a process of diffusion and
recombination that partially cancels out the minority diffusion
current, hence the diode’s current starts to flatten out with
increasing voltage. This effect is well modeled by setting the
ideality factor to n = 2 when the forward current exceeds a
critical threshold called the high-injection knee current, IKF .
The modified diode expression is
 
vD
i D ≈ IS exp (when i D > IKF ).
2UT
196 ece3410 lecture notes

In practice, the high-injection effect is often masked by the

series resistance in the quasi-neutral regions, RS . At high
forward currents, a large voltage drop can appear across the
“parasitic” RS resistors on either side of the diode, making it
increasingly difficult to increase the actual forward voltage
at the junction. In many diodes the series resistance sets the
dominant limitation on the diode’s maximum current, and the
high-injecton region is never really reached.

Temperature Dependence
The ideal diode model contains UT in its exponent, giving it a
strong temperature dependence. We have also seen that mobil-
ity, diffusivity and the minority carrier concentrations are all
sensitive to temperature, and they all contribute to the diode’s
scale current. All of these combined effects can overpower the
contribution of UT in the exponent. In most datasheets, the
scale current IS is measured at room temperature T0 . If the tem-
perature (in K) is changed by ∆T, the resulting change in IS is
approximately given by

IS ( T0 + ∆T ) ≈ IS ( T0 ) exp ( xti ∆T ) ,

where xti is a parameter called the temperature exponent. For

most Si diodes, xti = 2.0. Other types of diodes may have
different exponents.
 the pn junction 197

Example 37 (Realistic and Approximate Diode Models).

Suppose a diode has ideal characteristics IS = 6 nA and n = 1.9 measured at room temperature, T0 =
300 K. In addition, it has non-ideal characteristics ISR = 11 nA, n R = 5, RS = 0.33 Ω, IKF = 43 mA and
xti = 4.0. Consider the following cases.

 VF= 0.8 V, calculate the diode’s current using both the ideal forward bias
(A) In forward bias, with
vF
model, i D ≈ IS exp nU T
, and again using the complete model including recombination current.
How do they compare? Solution: Computing the two expressions yields the approximate result of
i D ≈ 1.112 98 mA and the more accurate model gives i D = 1.113 08 mA. In forward bias, the difference
is about 0.09%. We may conclude that the simplified exponential formula is sufficiently accurate for
“normal” forward bias conditions.
(B) In what range of voltages does the recombination current become a significant influence? Solution:
Recombination is significant when
   
vD vD
IS exp ≤ ISR exp
nUT n R UT
   
1 1 I
⇒ vD − ≤ ln SR
nUT n R UT IS
 
nn R UT ln IISR
S
⇒ vF ≤
nR − n
= 0.048 V

It’s easily verified that at this voltage, both the diffusion current and recombination current are
around 16 nA. For voltages less than this and for reverse bias, recombination will play a significant
role.
(C) What will be the reverse leakage current? Solution: In reverse bias, the total leakage current
should be sum of diffusion and recombination currents, IS + ISR = 17 nA.
(D) What forward voltage is required to exceed the high-injection knee current? Solution: This is a
more challenging question. The knee current is IKF = 43 mA, and using the exponential forward-
bias model we can solve for the forward voltage as VKF ≈ nUT ln ( IKF /IS ) = 0.779 78 V. But if
the current is 43 mA then we should see a combined voltage drop in the quasi-neutral regions of
2RS IKF = 0.0258 V, which reduces the forward voltage and drops the current down to 25.5 mA. But
the lesser current also reduces the voltage drop across RS ... To get the real answer we need to iterate.
After iterating a few times, the solution converges to 29.9 mA when VF = 0.779 78 V, which does not
actually surpass the knee current. Using the iterative method, we can search by increasing v F until
the iterated solution exceeds IKF . This occurs when v F ≈ 0.805 V.
198 ece3410 lecture notes

SPICE Diode Models

Simulators based on (or similar to) SPICE are able to account

for all the physics described above, plus a good deal more. To
obtain more accurate simulation results, we can supply SPICE
with additional parameters to model the built-in potential,
junction capacitance, resistance in the quasi-neutral region,
reverse breakdown behavior, diffusion capacitance, etc. Some
of the major parameters recognized by SPICE are as follows,
showing default values (used by SPICE when the parameter is
unspecified) and example values for the popular 1N914 signal
diode:

Name Description Default Units 1N914

IS Scale Current 1 × 10−14 A 6.2229 × 10−9
RS Series Resistance 0 Ω 0.336 36
N Emission Coefficient 1 N/A 1.9224
TT Transit Time 0 s 2.8854 × 10−9
CJO Zero-Bias Junction Capacitance 0 F 764.38 × 10−15
VJ Built-in Potential 1 V 9.9900
M Grading Coefficient 0.5 N/A 0.1001
EG Bandgap Energy 1.11 eV 1.11
XTI Temperature Exponent 3.0 N/A 4
BV Reverse Breakdown Voltage ∞ V 100.14
IBV Current at BV 1 × 10−3 A 0.259 51
ISR Recombination Scale Current 0 A 11.526 × 10−9
NR Emission Coefficient for Recombination Current 2.0 N/A 4.9950
IKF High-Injection Knee Current ∞ A 42.843 × 10−3

Most of these characteristics are NOT modeled in a simple

simulator like EveryCircuit. To capture the full range of junction
behaviors, a more sophisticated simulator like SPICE is required.
Most SPICE simulators account for additional behaviors with
more parameters than the ones listed above. Some simulators
do not recognize all the parameters listed above; for example,
NGSpice does not account separately for recombination current,
+
so it does not recognize ISR or NR. Furthermore, diode models − VIN D DR
are typically extracted by automated test equipment, and differ-
ent sets of parameter values may provide equally good fit to the
same physical diode.
Figure 176: Circuit to model recombination current
When high accuracy is needed, you should review the model in NGSpice. A parallel diode (indicated in blue) is
information in your simulator’s manual and make adjustments inserted having the recombination characteristics in
its model. This degree of accuracy is not necessary
if needed. For instance, since NGSpice doesn’t account for ISR for all applications, but sometimes a little “model
hacking” is needed to expand the capabilities of your
simulator.
 the pn junction 199

and NR, we can model these effects by defining a separate

diode model with the recombination parameters. The recombi-
nation diode can be connected in parallel with normal diodes
in the circuit. An example DC simulation of this model is per-
formed by the listing below. Simulation results are shown in
??, which compares the transfer characteristic with (black) and
without (red) recombination. We can see that the recombination
current causes a small deviation in weak forward bias, but has a
larger influence on the reverse bias leakage current.

Netlist 11: diode_dc.sp

** Diode DC Transfer Characteristic

* Model for 1N914 diode:

******
.MODEL 1N914 D ( IS=6.2229E-9, N=1.9224, RS=.33636
+ IKF=4.843E-3, CJO=764.38E-15, M=.1001
+ VJ=9.9900, ISR=11.526E-9, NR=4.995
+ BV=100.14, IBV=.25951,TT=2.8854E-9 )
******
.MODEL 1N914R D ( RS=0
+ VJ=9.9900, IS=11.526E-9, N=4.995)
******

* Simple Diode Circuit:

Vin 1 0 DC 0
D1 1 0 1N914
D1R 1 0 1N914R

* DC Simulation:
.control
DC Vin -1.0 1.25 0.001
plot ylog ylimit 1e-10 10 abs(i(Vin))
.endc
.end
200 ece3410 lecture notes

100
Diffusion only
10−1 Diffusion and Recombination High-Injection

10−2

10−3

as
Bi
10−4
| i D | [A]

d
ar
w

n)
r

io
Fo
10−5

us
iff
(d
Recombination
10−6

10−7
Reverse Bias
10−8

10−9
−1.2 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4
v D [V]

Optoelectronic Behavior of PN Junctions

P ←− E N
When a photon interacts with a semiconducting material, it can
pass completely through the material, or it can be reflected away −
from the incident surface, or it can be absorbed in the bulk of
the material. Photon absorption can occur when the photon’s
EC
energy coincides with the semiconductor’s bandgap energy.
ν
In this case, when the photon with energy Eg strikes a valence
electron with energy close to EV , the electron can absorb the
photon’s energy thereby boosting its own energy level up to
−
EC , resulting in the generation of a mobile electron/hole pair. If
the photon has energy less than Eg , then the electron is unable
+ EV
to absorb it since the combined energy would place it in the
fobidden gap, so the photon passes through unabsorbed. Pho- ←− E
tons with energy above Eg can be absorbed, but with increasing
energy they are much more likely to be absorbed or reflected Figure 177: Illustration of photon absorption in the
near the material surface rather than in the bulk. depletion region. A photon with energy > Eg is
Optoelectronic interactions have several important applica- absorbed by a valence electon, promoting a mobile
pair of charge carriers which are swept up by the
tions. The simplest is the photo resistor: when many photons are E -field to establish a drift current.
absorbed, the mobile charge concentration increases, causing
increased conductivity in the material. This phenomenon can be
used in basic circuits that respond to bright sources such as sun-
light or lasers. Beyond the photoresistor, there are many more
 the pn junction 201

sophisticated applications which all rely on junction physics,

especially the physics of the depletion region. These applica-
tions include solar cells, photodiodes, digital cameras, LEDs and
lasers, among others. To understand these, we’ll begin with a
close look at the junction.

P depletion N
Photons in the Depletion Region
When a photon is absorbed in the quasi-neutral bulk regions of
T
a PN diode, it adds to the pool of mobile carriers and slightly al- W

ters the conductivity, which is a fairly weak interaction. When a Figure 178: Photons pass through the top surface of
photon is absorbed in the depletion region, the result is more in- this junction. They are able to be usefully collected in
teresting: a new pair of mobile carriers is generated, which are the depletion region, which has width W. The junc-
tion has thickness T, so the total area for collecting
immediately swept apart by the electric field, setting up a net photons is W × T.
reverse current through the junction. This current is called the
photo current, and is directly proportional to the rate of photon
absorption in the depletion region. The photon flux Φ is de-
fined as the rate of photons of a particular wavelength passing
through a material section, usually with units ofphotons/scm2 .
As illustrated in Figure 178, photons incident on the surface
plane are “eligible” to be absorbed as they pass through the
bulk. If the junction thickness is T and the depletion width is W,
then the photocurrent should be

Iph = qηΦTW,

where η is a wavelength-dependant scale constant called the

quantum efficiency that indicates the probability of a photon
being absorbed before passing all the way through the material.
The underlying physics lumped into η can be complex: smaller
wavelengths (in the blue or ultraviolet range) have higher
energies and are more likely to be reflected or absorbed near the
material surface. Larger wavelengths have lower energies (in the
red or infra-red range) and tend to penetrate deeper and may
pass all the way through without being absorbed.
The photo current is commonly expressed as a function
of the total radiant flux φ, defined as the total optical power
incident upon the material’s surface, with units of W. The
irradiance is related to the photon flux by φ = Φhc/λWT,
where h is Planck’s constant, c is the speed of light and λ is the
photons’ wavelength. Then the photocurrent can be expressed
as
Iph = Rλ φ

where Rλ is the material’s spectral responsivity with units

202 ece3410 lecture notes

A/W, given by
qλη
Rλ = .
hc
 the pn junction 203

Photodetector Circuits
A photo detector can be made from a single photodiode and a Iph
biasing circuit. In Figure 179, a resistor is used to achieve the
reverse bias. Since the photocurrent is directly proportional
to the incident optical power, and the resistor’s voltage drop vOUT
is proportional to the photocurrent, overall this is a linear
photodetector. Linear detectors are not necessarily the best
option for all applications. Considering that the difference in
irradiance between outdoor and indoor lighting can span four
orders of magnitude, it is not feasible to design a passive linear
photodetector for general use. Figure 179: A linear resistor-diode photodetector.
The resistor and power supply are used to setup a
An alternative design is the active pixel sensor (APS) shown
reverse bias condition in the diode, with an output
in Figure 180. In this design, a MOSFET switch (M1) is first voltage close to VDD . When light is present the
switched ON to drive node v x up to VDD − VTh , placing the diode photocurrent induces a drop across R, giving an
output vOUT = VDD − Iph R.
in reverse bias. Then M1 is switched OFF, leaving v x floating on
the capacitor CP . The photocurrent discharges CP , causing v x to
drop in proportion to the time integral of Iph . The output signal
is isolated by a source-follower (M2). Suppose M1 is turned M1
rst
OFF at time 0, and the signal at vOUT is sampled after a short
time ∆t. Then the change in output voltage should be
Z ∆t M2
∆vOUT = − Iph dt. Iph
0 CP vOUT

If the sampling time is very small so that Iph is nearly constant,

then the expression simplifies to

∆vOUT = − Iph ∆t.

The detector’s sensitivity is therefore a function of ∆t, which

Figure 180: An active pixel sensor (APS). In this
can be easily adjusted on the fly using digital methods. This version, only N-type MOSFETs are used since they
gives APS cameras the ability to adapt to a wide variety of permit smaller pixel cells than P-type devices.
lighting conditions without requiring mechanical accessories.
The sensitivity of APS circuits is limited by the diode’s re-
verse leakage current, which in this context is called the dark
S1
current. It is also limited by sources of noise within the photo- t=0
diode and its surrounding circuit. All circuits are affected by Av
low-frequency noise. Digital camera sensors are additionally af- CR
+
fected by so-called fixed pattern noise, which is a combination vOUT ∆vOUT
−
of pixel-to-pixel variation in the chip’s fabrication, combined
with self-illumination from photons emitted by neighboring
S2
circuits. A result of fixed-pattern noise To reduce these effects,
most APS imagers use correlated double sampling with a read- t = ∆t

out circuit similar to the one shown in Figure 181. In this circuit, CS

switch S1 is opened at time 0, sampling vOUT (0) on the top

plate of CR . Then after time ∆t, switch S2 is opened to sample
Figure 181: Basic concept of correlated double-
sampling. The starting and ending values of vOUT
are sampled onto two capacitors. Their difference,
∆vOUT , is amplified by a differential amplifier with
fixed gain Av .
204 ece3410 lecture notes

vOUT (∆t) on the top plate of CS . The differential output is then

a direct measurement of ∆vOUT .

EveryCircuit Demonstration 48 (Correlated Double Sampling).

This example circuit models an active pixel sensor with correlated dobule sampling. Since EveryCir-
cuit doesn’t have any models for photonic signals, we simulate the photocurrent by superimposing
a parallel current source with the reverse-biased diode. There are three different MOSFET configu-
rations here: switching mode (in red), amplifiers (blue) and bias transistors (green). The reset switch
is used to initialize the charge on capacitor CP . We don’t need to know the precise initial value, just
that it is the same after each reset. The sampler switches are used with capacitors as track-and-hold
(T/H) circuits: when the switches are ON, the capacitors are connected to their respective signals.
When the switches are OFF, the capacitors are floating, and the remember whatever signal value was
present at the time of switch-off. The amplifier configurations are Common-Source (CS) gain stages
and Source-Follower (SF) buffers. We previously studied all of these configurations, but this is one of
our first examples showing a system with multiple configurations working together.

CS Amp. CS Amp.

Diff. Sampler

Vbias M7 M9
Reset
+ ∆vOUT −
SF Buffer φ2
S/E Sampler
M10 M11
φ1 M1
VP CO
M6
M2 M4 φ4 φ4
CS
Iph
M3
VSF M5
M8
Photodiode Model
CE
φ3
 the pn junction 205

The point of the example CDS circuit is to sense Iph with

adjustable precision. The precision is tuned by altering the
timing of the switching signals φ1 (reset), φ2 (start), φ3 (end) and
φ4 (sample ∆vOUT ). The signal timing events are shown below
in Figure 182.

∆t
M1 ON
φ1
M4 ON
φ2
M5 ON
φ3
M10 , M11
φ4
ON
/ R
Reset Int ( )
VP

Track / Hold
VS

VE /
Track Hold

∆vOUT Track / Hold

Figure 182: Timing diagram for Correlated Double

Sampling. The output signal, ∆vOUT , is not valid
When φ1 goes high, the reset switch is turned ON, which until the track/hold signal φ4 goes high (track) and
initializes the charge on capacitor CP , and pulls VP up to a high then low again (hold). The output signal can be used
value (we know from a previous chapter that the maximum (e.g. for analog-to-digital conversion) during the hold
interval.
value is VDD − VTh ). Once φ1 goes low, the photocurrent begins
to discharge CP , and VP starts to drop linearly with time, at
a rate determined by the photocurrent. A Source Follower is
used to buffer the output signal so that the charge on CP is not
altered by downstream circuits. The Source Follower’s output is
2 T = 10 µs, ∆t = 5 µs
VSF = VP − VGS , where VGS is a constant voltage (you may recall T = 1 µs, ∆t = 0.5 µs
that the Source Follower is commonly called a Level Shifter
since it shifts the signal offset at its output). Signal φ2 is pulsed
∆vOUT [V]

to record the initial voltage on VSF . Then, after a time-interval 1

∆t, φ3 is pulsed to record the final voltage on VSF . These signals
are amplified and their difference is sampled onto another
capacitor.
The cell’s sensitivity can be changed by adjusting the gap 0
between pulses φ2 and φ3 . An example is shown in Figure 183. 10−6 10−5 10−4
When Iph is large, CP discharges rapidly, so ∆t must be small Iph [A]
in order to avoid fully discharging the capacitor. Conversely,
Figure 183: Transfer characteristics of the CDS circuit
when Iph is small, a large ∆t is needed in order to observe a
for two different values of ∆t. Shorter ∆t can be
significant change in the charge on CP . Since the track/hold used to measure larger current ranges, and hence
pulses are all digital, the timing can be adjusted using digital brighter scenes. Longer ∆t can be used to sense
fainter currents associated with dimmer scenes.
techniques like a clock divider circuit.
206 ece3410 lecture notes

P-I-N Diodes
Since the photocurrent only responds to photons collected
within the depletion region, to make a sensitive photodetector
we should make W as large as possible. Recall the expression
for W in reverse bias: P I N
s  
2e 1 1
W= + (V0 + VR ). Figure 184: Structure of a PIN diode. The large
q NA ND intrinsic region in the middle is fully depleted. In
√ some versions, the P-type surface is exposed to
We see that W ∝ 1/NA + 1/ND . Suppose we let NA or ND go photons. If the P region is kept very thin, the photons
to zero. In that extreme limit, W goes to infinity, so the weakly will pass through it to be absorbed in the thick I
region below.
doped side of the junction will be fully depleted throughout
its volume. By placing an undoped region of intrinsic semicon-
ductor in between the P and N regions of a normal diode, a P N
very wide depletion zone is created, resulting in a highly sensi-
tive photodetector. The wide depletion width also reduces the
junction capacitance and gives it a high-bandwidth in reverse I

bias, making for a fast photodetector. A couple of common PIN

diode structures are shown in Figure 184 and ??.
PIN photodiodes respond very quickly, and can be used in
Figure 185: Alternative structure of a PIN diode. P
high-speed optical data links. Their quantum efficiencies can and N regions are implanted into an intrinsic (or
exceed 90%. Their wavelength response depends strongly on weakly doped) wafer substrate. A fully depleted
surface stretches between them. This structure is
their material composition. In fiber optic cables, optimal trans-
good for collecting high-energy photons (in the blue
mission is achieved for a wavelength of 1550 nm, making this range, for example) that are absorbed closer to the
the world’s most widely used wavelength for telecommunica- material’s surface.

tion. PIN diodes made from Germanium or from alloys such

as Indium-Gallium-Arsenide (InGaAs) have a good response in
this region, since their bandgap energy is lower than the pho-
tonic energy at that wavelength. Silicon’s bandgap corresponds
to a wavelength of about 1100 nm, making it a poor detector
for fiber optic applications. Si is still a relatively good detector
for infrared and visible light, providing the basis for low-cost
and high-resolution digital photoghraphy that is well integrated
with other Si electronics.
The PIN diode is also interesting for RF applications. The
low junction capacitance makes it very good for rejecting RF
frequencies when reverse biased. When forward biased, the
large depletion region tends to linearize the diode’s transfer
characteristic at high frequencies. It can be used as a variable
resistor, with the resistance tuned by the forward bias current.
Since the small-signal resistance can be made very low, PIN
diodes make high-quality RF switches. Their main limitation
in this use is that they cannot be rapidly switched between ON
and OFF states, due to the large charge stored in the intrinsic
region.
 the pn junction 207

Avalanche Photodiodes

If a photodiode is biased close to the edge of its reverse break-

down point, absorbed photons can provide enough energy to
stimulate avalanche multiplication. This method can be used P ←− E N
to create highly sensitive photon detectors used in scientific
applications. In order to achieve a good gain, the junction must
++++ EC
have a very large breakdown voltage and a large reverse bias −−−−
(typically exceeding 100 V). Single-photon sensitivity can also
be achieved if the diode is biased slightly beyond its breakdown VD = 0 EV
point, referred to as Geiger mode since the diode will emit short P ←− E N
pulses of current in response to individual photons, much like a
Geiger counter. EC
++++ −−−−

Tunnel Diodes EV
VD = VP
When a junction has very high doping, so that the depletion P ←− E N
region becomes very thin, there can be quantum tunneling
−−−− EC
during forward bias operation as well as in reverse breakdown.
The concept is illustrated by the energy band diagrams in Fig- ++++
EV
ure 186. The forward tunnel current comes to a maximum at
the peak voltage VP , where the conduction and valence bands are VD > VP
aligned. This is because the allowed energy states are mostly
squeezed in very close to EC and EV . Most of the mobile elec- Figure 186: Energy bands in a weakly forward
biased tunnel diode. When VD is slightly above zero,
trons are sitting at EC , and they need valid energy states near electrons can tunnel across the thin depletion region.
EV in order to tunnel. The tunnel current is maximum at the peak voltage
VP , where the valence band on one side aligns with
When the diode’s foward voltage is increased higher than
the conduction band on the other side, since the
VP , the bands are moved out of alignment so that the tunneling available energy states are concentrated near the
current actually decreases with increased forward bias. This band edges. When VD > VP , the available states are
poorly aligned so the tunnel current decreases.
causes a behavior called negative differential resistance – the
slope di/dv swings negative. This means that in the small-signal
10−1
equivalent circuit, the tunnel diode behaves like a negative resis-
tor. Negative resistance has a variety of exotic applications, but
the most important use is in high-frequency RF and microwave 10−2

oscillators. These applications were important enough to earn

| ID | [A]

Nobel prizes for the tunnel diode’s inventor, Leo Esaki (tunnel 10−3
diodes are often called “Esaki diodes” in his honor). “peak”
The tunnel diode’s current consists of a primary tunneling
current, superimposed with secondary or “excess” tunneling 10−4

currents, and also superimposed with a normal exponential “valley”

diode current. The tunneline current follows an exponential 10−5

model around a peak voltage: 0 0.1 0.2 0.3 0.4 0.5
  m  VD [V]
VD VD
Itun = exp − ,
R0 V0 Figure 187: Example tunnel diode DC transfer
characteristic for the MBT1057 tunnel diode. Note the
log scale on the vertical axis.
208 ece3410 lecture notes

where R0 is the linear resistance in the junction’s quasi-neutral

regions, V0 is a parameter in the range 0.1 V to 0.5 V, and m is
an emperical parameter in the range 1 to 3. From this expres-
sion we can show that the peak current is obtained when the
voltage is
 m
1
VP = V0 .
m
The excess tunneling current determines the “valley” and is
given by a similar exponential expression:

VD − VV
 
VD
Iex = exp ,
RV Vex

where VV is the valley voltage where ID is minimum, and RV

and Vex are emperical parameters.

Modeling and Simulating Tunnel Diodes in SPICE

Most SPICE simulators do not natively support models for
tunnel diode devices. For this reason, many engineers use poly-
nomial voltage-controlled current-sources to provide an emperical
approximation to the diode’s transfer characteristic. Here we
examine this method for simulating tunnel diodes, but this
strategy can be applied to a huge variety of atypical devices
and materials. Think of this as an exercise in expanding the
capabilities of SPICE, which will have unexpected uses in the
future.
In NGSpice, a non-linear source has the form
BX N1 N2 I=<expr>

where X is a unique identifier for the device, N1 and N2 are the

source’s terminals, and <expr> is some valid mathematical
expression. An example tunnel diode model is shown below, us-
ing polynomial coefficients fit to emperical data via a standard
curve-fitting method. This model was provided by Metelics
Corporation as a model of the MBD1057 tunnel diode:

Netlist 12: tunnel_diode_model.sp

.SUBCKT MBD1057 1 2
B1 1 2 I=0.007358*V(1,2)-0.08607*V(1,2)^2+0.2911*V(1,2)^3+0.03922*V(1,2)^4-1.693*V(1,2)^5
C1 1 2 0.3E-12
.ENDS

Using this model, we can simulate tunnel diode circuits within

a limited signal range. The model is not accurate for large for-
ward bias or for reverse bias, since the polynomial fit was done
 R1 the pn junction 209
n1 n2 n3

+
to minimize error around the negative differential resistance − R2 C L
(NDR) portion of the transfer characteristic.
A typical tunnel diode application is in RF oscillators like the
one shown in Figure 188. A voltage source and resistor pair are
used to bias the tunnel diode in the middle of the NDR region. Figure 188: Tunnel diode oscillator circuit. Node
numbers corresponding to the SPICE netlist are
In a classical RLC circuit, the resistor dissipates energy with indicated in blue.
each period of the oscillation. If the resistor is negative, however,
then the dissipation is also negative. This means that energy
is added with each period of the oscillation. The tunnel diode
can therefore be used to deliver energy into a resonant LC tank
oscillator, so long as the signal oscillations occur within its NDR
region of operation. The resulting frequency is approximately 0.1
that of the LC tank,
1
ω= √ .

v(2) [V]
0
LC
In the example SPICE netlist shown below, the parameters −0.1
are L = 100 µH and C = 100 pH, yielding a resonant frequency
of about 1.5 MHz. The diode is biased so that its differential
−0.2
resistance is about rd = −1 kΩ. Simulation results are shown
in Figure 189. The waveform is distorted due to the diode’s
0 0.2 0.4 0.6 0.8 1
nonlinear transfer characteristic, but the waveform can be made
Time [s]
·10−5
more sinusoidal by adding resonant filters to the circuit.
Figure 189: Transient SPICE simulation results for a
tunnel diode oscillator.

Netlist 13: tunnel_diode_oscillator.sp

* Tunnel Diode Simulation
*Macromodel for MBD1057 tunnel diode
.SUBCKT MBD1057 1 2
B1 1 2 I=0.007358 ∗ V (1, 2) − 0.08607 ∗ V (1, 2)∧ 2 + 0.2911 ∗ V (1, 2)∧ 3
+ + 0.03922 ∗ V (1, 2)∧ 4 − 1.693 ∗ V (1, 2)∧ 5 + 2.099 ∗ V (1, 2)∧ 6
C1 1 2 0.3E-12
.ENDS

V1 1 0 DC 1.5V
X1 2 3 MBD1057
R1 1 2 200.0
R2 2 0 20
C1 3 0 100p
L1 3 0 100u
.nodeset v(3)=0.1

.control
tran 1n 10us uic
plot v(3)
.endc
.end
210 ece3410 lecture notes

LEDs and Direct vs Indirect Bandgaps

Light Emitting Diodes are like reverse photodetectors. When

a mobile charge pair recombines in forward bias, a photon
is emitted. The energy of this photon is set by the material’s
bandgap Eg . The first observations of photon emission from
a semiconductor – a phenomenon called electroluminescence –
was in 1907. Commercially viable LEDs with visible emission
appeared in 1962, and a telecom-grade LED was first produced
in 1976. The first commercial LEDs were made from a Gallium
Arsenide (GaAs) alloy, which provides high electroluminescence
due to its direct bandgap. We previously glossed over some of the
physics that underlies energy band transitions. An electron’s
energy level is a scalar quantity, but the transition is also af-
fected by the electron’s momentum, which is a vector quantity.
In an indirect-bandgap material like Si, electrons cannot change
energy levels unless they also change the direction of their mo-
mentum vector. A photon by itself cannot provide the needed
change in momentum; that change has to come from a thermal
interaction with the crystal lattice. For that reason, Si diodes dis-
sipate most of their transition energy as heat. These transitions
are called non-radiative since most of the energy goes into heat,
but a small fraction of recombinations do yield photons, it’s just
a very inefficient process.
Direct bandgap materials, on the other hand, can undergo
energy level transitions without heat dissipation. This allows
production of highly efficient bright light sources. Today LEDs
are made from diverse materials and can emit light across the
whole visible spectrum, ranging from infrared to ultraviolet.
Various flourescent coatings have also been introduced to im-
itate the look and feel of incandescent lights, which has sped
the adoption of LED-based lighting in homes and commercial
buildings. LED lighting has also benefitted from advances in
solid-state AC/DC conversion, which can now be done with ef-
ficiency above 99%. Thanks to microelectronic fabrication, these
devices can all be integrated into a light-bulb sized package and
used as an in-place upgrade for century-old lighting systems.
Another crucial application of LEDs is the laser. A typical
LED undergoes a process of random recombination called
spontaneous emission. Einstein discovered (mathematically)
that the probability of recombination/emission is increased if
another photon of the same energy is present. In this process,
called stimulated emission, a photon induces a recombination
event leadining to a second photon emitted with the exact
 the pn junction 211

same wavelength, direction and phase as the original photon.

The idea of a diode laser is to put reflective surfaces on each
side of an LED junction, so that more emission is continually
stimulated by the reflected photons. A small hole is provided
to allow a narrow column of photons to escape, creating a laser
beam. Since some of the reflected photons are re-absorbed by
the material, the device reaches a saturation level of photon
emission. The LED laser is now the basis of optical storage
media (e.g.] CDs, DVDs, BlueRay discs), fiber optic transmitters,
and lecture pointers. They are also widely used to entertain cats
and create a nuissance around airports.

Diodes as Particle Detectors and Geiger Counters

High-energy particles are produced by a variety of phenomena.

X-rays and gamma rays are very high-energy photons that may
be produced by radioactive decay or from cosmic sources. Other
common particles include alpha decay (which emits a high-
energy helium nucleus with two protons and two neutrons),
beta decay (which emits a high-energy electron or positron),
and the high-energy collision byproducts produced in particle
accelerators. All of these rays and particles interact with semi-
conductor junctions. As a high-energy particle passes through
the material, it delivers ionization energy to a large number of
charges. This is similar to photon absorption except a very large
number of mobile charge pairs can be created along the parti-
cle’s path as it passes through the material. In a reverse biased
PN junction, this creates a big current pulse with a slow de-
cay due to the ongoing diffusion of carriers from the particle’s
“charge wake.”
As an example application, at CERN’s Large Hadron Collider
(LHC) facility, specialized “pixel detector” chips are arranged
around the exterior of a tube. Protons are accelerated within
the tube and smashed together at extremely high energies in Figure 190: Layered arrangement of pixel detector
“staves” in LHC experiments.
order to break them into their constituent elementary particles.
The collision byproducts are scattered out of the tube, passing
through an array of several hundred million pixel detectors on
the way. The pixel detectors are fairly large by silicon standards
– 50 µm by 400 µm – and are packaged in thin columns called
“staves” containing several pixels each. The staves are layered in
a ratchet-like orientation so that they can detect particles’ paths
in three dimensions as they fly out of the collider.
 gate

Field Effect Transistors SiO2

tox

n+ source n+ drain
L

The Field Effect Transistor (FET) was first described by Julius p− substrate
Edgar Lilienfeld in a 1926 patent. The basic concept is the same
as modern FET devices, but the devices could not be manufac- Figure 191: Cross section of a standard bulk MOSFET.
tured in Lilienfeld’s day since they require highly perfect crystal Devices are most often fabricated on a P-type
substrate with weak doping, indicated as p− . The
structure, precise doping control, and microscopic dimensions. Source and Drain regions are implanted with strong
The first modern Metal Oxide Semiconductor (MOS) FET device N-type doping, indicated as n+ . A layer of insulation,
was demonstrated at Bell Labs in 1960 by Atalla and Kahng. usually comprised of silicon dioxide (SiO2 , often
called the “glass” layer), is grown or deposited on
One of the key innovations in fabricating successful MOSFETs the surface. The region between the Source and
was to grow a layer of insulating Silicon Dioxide on the device’s Drain terminals is called the channel with length L.
Suspended above the channel is the Gate terminal,
surface, thereby controlling surface imperfections that had es- which is a deposited layer of poly-crystaline Si
sentially created a short-circuit between the switching terminals (“poly” for short).
in older devices. The basic structure of the 1960 MOSFET is
still used up to the present day. Variations on this structure
Gate
have been at the cutting edge until very recently. Today we see
competition from alternative nano-wire and “fin” based FET
structures which will be discussed later; first we’ll study the
classic bulk MOSFET device that is used in nearly all integrated
Source Drain
circuits produced since the 1980s.

W
Physical Structure

The standard MOSFET device, shown in the cross-sectional

illustration in Figure 191, consists of a silicon wafer (called
the substrate or bulk). In many cases the wafer is doped P-type
with a relatively weak dopant concentration (weak doping L

is indicated as P− ). On the surface of the wafer is a layer of

Figure 192: Overhead layout of a standard bulk
insulating SiO2 called the oxide or glass. A short distance above MOSFET device. The width W is usually larger than
the wafer surface, the oxide is thinned to deposit a layer of poly- the channel length L. Metal interconnects access the
Source, Drain and Gate layers via contacts indicated
silicon (poly for short) which forms the device’s gate terminal. as black squares. The contacts are usually chemically
The oxide thickness below the gate establishes an incremental etched openings in the SiO2 layer, allowing metal to
gate capacitance: be deposited down to the material beneath.

eox
Cox0 = [F/µm2 ],
tox
214 ece3410 lecture notes

and the total capacitance depends on the area under the gate,
which can be adjusted by an integrated circuit designer. One
of the main benefits of a capacitive gate is that it prevents any
current from flowing into the device’s gate terminal. This makes
the MOSFET nearly ideal for use as a voltage amplifier, and is
a crucial property for energy efficient large-scale logic circuits.
For some very small devices, with channel lengths below 90 nm,
tox is small enough to permit quantum tunneling through the
oxide. This phenomenon, often called “gate leakage,” is one of
many problems that has led the industry to modify or abandon
the classic bulk MOSFET structure. More complex structures,
like the FinFET, are increasingly favored in new technologies.
We will examine the FinFET structure in a later chapter.
On either side of the gate, strong N-type doping (indicated
as N + ) is implanted into the wafer to form the source and drain
terminals of the device. Terminal contacts are created by etching
small holes in the oxide where metal can be deposited. By
alternately depositing oxide, etching oxide, depositing metal,
and so forth, complex circuits can be constructed across the
wafer’s surface. A device with a P-type substrate and N-type
source/drain terminals is referred to as an N-type MOSFET.
We will discuss the complementary P-type MOSFET in a later
section.
Manufacturers and process designers determine many of
the device’s properties, like the doping concentrations, oxide
thickness below the gate, minimum dimensions and spacings
of objects, depth of the source and drain implants, and so on.
But chip-level designers have the freedom to manipulate two
important dimensions: the device’s length L, defined as the
spacing between the source and drain terminals, and the width
W. These dimensions are determined by the device’s physical
layout. An example layout is shown in Figure 192. A layout
designer has considerable freedom to manipulate the device
geometry so long as the basic process design rules are obeyed.
 field effect transistors 215

MOSFET at Zero Gate Bias

To understand the operation of the MOSFET device, we begin

with the case of zero gate bias. This means that the gate and
gate
substrate are at the exact same potential. Since the device is
physically symmetrical, there is no special distinction between
the source and drain terminals other than that the drain is SiO2
n+ source n+ drain
assumed to be at a higher potential than the source. We will
assume that VS ≥ 0 and VD > VS , but VD can exceed VS by
any amount. The source and drain regions form PN junctions
with the substrate. Since the substrate is weakly doped, the
p− substrate
junctions are one-sided, and a depletion region extends around
the terminals into the bulk. Generally the depletion is thicker
Figure 193: MOSFET cross section with the Gate and
around the drain, and can extend all the way across the surface Bulk at 0 V. A depletion region is present around
connecting between the source and drain. In this condition, the the Source and Drain terminals. Since VD > VS , the
depletion layer is larger around the Drain.
device acts like a capacitor. To a first approximation, no current
flows between the source and drain when the gate voltage is
zero. More accurately, a small leakage current flows due to
generation/recombination and other effects in and around the
depletion region.
216 ece3410 lecture notes

MOSFET in Weak Inversion

When VG is slightly greater than zero, but less than the device’s
threshold voltage, majority carriers (holes) are repelled from
gate
the region beneath the gate. Minority carriers (electrons) are + + +
attracted from the bulk. The minority carriers aggregate at the
Si surface, just beneath the oxide layer, resulting in an inversion SiO2
n+ source − − − n+ drain
of mobile charge polarity in the MOSFET channel between the
source and drain. In this mode, the potential along the channel
is nearly constant, and the voltage drop between VD and VS − − −
occurs close to their junctions. Hence there is no net E -field in
p− substrate
the channel, and no drift current flows. The excess minority
charges tend to diffuse into the Source and Drain junctions,
Figure 194: MOSFET cross section with weakly
in a process similar to a weakly forward biased diode. Since inverted channel.
the weak inversion current flows primarily by diffusion across
junctions, the device has an exponential current similar to a
diode. The Source and Drain diffusion currents are
φ − VS
 
Isource = I0 exp
UT gate
φ − VD
 
Idrain = I0 exp
UT Cox

n+ source − − − n+ drain
where I0 is a scale current and φ is the channel potential.
As Figure 195 shows, a capacitive divider forms between the Cdep

oxide capacitance under the gate and the depletion

 capacitance
under the channel. Let κ , Cdep / Cox + Cdep be the divider
p− substrate
ratio, then the channel potential is φ = κVG . Most often κ ≈ 0.7,
but it can vary considerably since Cdep is a function of the
Figure 195: In weak inversion, the channel potential
channel charge. Then the total current is the difference between depends on the capacitive divider formed between
the Drain and Source currents: Cox and Cdep .

κVG − VS κVG − VD
   
I = I0 −
UT UT
κVG − VS −VDS
   
= I0 exp 1 − exp
UT UT
For a bulk MOSFET device, the scale current I0 can be shown to
be ! 
0 U2
−κVTh
 
2µn Cox T W
I0 = exp .
κ L UT
When VDS is greater than about 100 mV, the current becomes
insensitive to VDS and the device is said to be in substhreshold
saturation. In this mode we can use the approximate expression

κVG − VS
 
ID ≈ I0 exp .
UT
 field effect transistors 217

Example 38 (Subthreshold operation).

A MOSFET device has parameters κ = 0.7, µn = 700 cm2 /Vs, Cox 0 = 5 fF/µm2 , V
Th = 0.5 V, W =
0.4 µm and L = 0.06 µm. What is the device’s current when VS = 0 V, VD = 1 V and VG = 0.2 V?

Solution: First, the device’s scale current is found to be I0 = 228 nA (note: remember to reconcile the
units cm2 in µn with µm2 in Cox 0 !). Since V
DS  100 mV, we can use the approximate expression for
subthreshold saturation. In that case, the current is ID ≈ 40.7 µA.

Example 39 (Subthreshold leakage current).

One of the most important consequences of subthreshold operation is that it sets up a DC leakage
current in digital circuits, which creates static power dissipation in CMOS integrated circuits and
systems. Suppose a MOSFET has scale current I0 = 100 nA, and is sitting idle in its OFF state with
VG = VS = 0 and VD > 100 mV. Will any current flow in the device? From the weak inversion model,
what should we expect the current to be? Will the current have any dependence on VD ? If the system
contains 106 such devices and operates with a power supply of 2 V, what will be the total static power
consumption?

Solution: Since VD > 100 mV, the device is in the subthreshold saturation mode (this is typical of
switched-OFF MOSFETs in digital circuits). In this mode, the current is given by

κVG − VS
 
Ileak = I0 exp ,
UT

but since VG and VS are both zero, the leakage current is just I0 or 100 nA. As long as VD stays
above 100 mV or so, the leakage current will stay roughly the same. If VD is reduced below this
level, the current will exponentially decrease. If VD → 0 V then the leakage current can be fully
6
suppressed (according to this model). If there are 10 leaking devices then the total static power is
2 V × Ileak × 106 = 200 mW. This may sound small, but it would be enough to drain a high-capacity
cell phone battery, holding a charge of about 2900 mA h, in just over one day, assuming the device
is sitting idle (and in airplane mode) the entire time. Static power is really just the standby power
consumed while the system is idle; active usage will consume dynamic power, which is usually much
greater. Hence it is desirable to save static power so that the energy can be used for actual tasks. As
we saw here, one way of saving static power is to dynamically reduce the supply voltage while the
system is idle, so that the VD for every device is made small. This practice is called dynamic voltage
scaling.
218 ece3410 lecture notes

MOSFET in Strong Inversion (triode)

As the gate voltage is increased, a larger amount of charge is

accumulated in the channel, eventually supporting a voltage gate
drop along the channel. This means an E -field begins to appear + + + + ++

resulting in a drift current between the drain and source. This SiO2
transition occurs when VG ≈ VTh , and the channel is said to be n+ source − − − − −− n+ drain
strongly inverted. In this mode, the potential along the channel
changes gradually from VS to VD . Let φs ( x ) be the surface − − −
potential at some point x along the channel, so that φ(0) = VS
and φ( L) = VD . Now consider a small “slice” of width dx, the p− substrate

total capacitance of the oxide under the gate is Figure 196: MOSFET cross section with strongly
inverted channel.
Cslice = Cox0 Wdx.

(Recall that Cox0 is capacitance per area, so we have to multiply

the total slice area Wdx to get the total capacitance.)
The charge stored in a capacitor is Q = CVC , where VC is
the potential across the capacitor. In the case of a MOSFET, the
gate
gate potential needs to exceed VTh before an appreciable charge +
is stored. Therefore we have to subtract VTh from the potential
across Cslice : Cox Wdx (VG − φs )

Qslice ( x ) = Cox Wdx (VG − φs ( x ) − VTh )

−
channel
The total current in the channel is constant, and is generated by dx
the E -field oriented from the drain toward the source:
Figure 197: Cross-sectional slice of the MOS channel
in strong inversion. The slice has width W (same
ID = µn Qslice E ( x ) , as the MOSFET’s gate width) and length dx. The
dφs ( x ) incremental capacitance in this slice is Cox Wdx,
E (x) = − storing a voltage drop equal to VG − φs ..
dx
Here we can apply a differential trick and say that

ID dx = −µn Qslice dφs ,

and then we can simultaneously integrate the left side over the
length of the channel from x = 0 up to x = L, and on the right
side over the potential from φs (0) = VS up to φs ( L) = VD :
Z L Z VD
ID dx = µn Cox0 W (VG − φs ( x ) − VTh ) dφs
0 VS
 VD
1
⇒ ID L = µn Cox0 W (VG − φs − VTh )2
2 VS
1 W h i
⇒ ID = µn Cox0 (VGS − VTh )2 − (VGD − VTh )2
2 L
 field effect transistors 219

This result describes the triode mode of operation. It can be

rearranged algebraically into the more familiar form:

1 Wh 2 i
ID = µn Cox0 2
VGS − VGD − 2VGS VTh + VTh2 + 2VGD VTh − VTh2
2 L
1 0 W
h   i
= µn Cox 2VG VDS − VD2 − VS2 + 2VTh (VGD − VGS )
2 L
1 W h   i
= µn Cox0 2VG VDS −2VS VDS − 2VTh VDS − VD2 − VS2 +2VS VDS
2 L
1 W h  i
= µn Cox0 2 (VGS − VTh ) VDS − VD2 − 2VD VS + VS2
2 L 
0 W 1 2
= µn Cox (VGS − VTh ) VDS − VDS
L 2
220 ece3410 lecture notes

Channel Pinchoff (saturation)

When the MOSFET is in strong inversion, with vGS > VTh ,

the current depends strongly on vDS . When vDS is increased gate
from zero, the device current also increases until it reaches a + + + + ++

maximum value. The value of the maximum is obtained by SiO2

taking the derivative of i D with respect to vDS . The derivative n+ source − − − − −− n+ drain
should cross zero at the maximum point:
di D W −
= µn Cox0 [(VGS − VTh ) − VDS ] = 0 − −
dvDS L
p− substrate
⇒ vDS = vGS − VTh when i D is maximum.
Figure 198: MOSFET cross section with strongly
The device current at this maximum point is inverted channel. As the drain voltage increases, the
depletion region widens and “pinches” the channel.
1 0 W
i D (sat.)? = µC (vGS − VTh )2 ,
2 ox L
note we have used the star (?) superscript to indicate that this is
an idealized result.
Once vDS exceeds vGS − VTh , the current is no longer strongly
dependent on vDS , so it is said to be saturated. To put it another
way, we consider the channel to be fully formed when vG − ψs ≥
VTh , but if v D is large this will cease to be true in the vicinity of
the drain terminal. When vGD < VTh , the channel is not fully
inverted all the way from the drain to the source, and is said to
be “pinched off” in that it fizzles out part way across. Then by a
simple analysis we can obtain the condition for saturation:

vGD < VTh

⇒ −vGD > −VTh
⇒ v D > vG − VTh
⇒ v D − vS > vG − vS − VTh
⇒ vDS > vGS − VTh .
When the device is in saturation, the current is ideally in-
sensitive to further increases is vDS . The physical story is more
complex. As illustrated in Figure 198, there is a wide depletion
region around the drain terminal. It grows wider when v D is
increased. This effect decreases the device’s channel length L,
hence increasing the current. Because the channel length is al-
tered by the electrical signal at the drain, the effect is commonly
called Channel Length Modulation (CLM). To a first approxi-
mation, the change in current is linear with respect to increasing
v D , and is modeled by a linear adjustment to the saturation
model:
1 W
i D (sat.) = µCox0 (vGS − VTh )2 (1 + λvDS ) ,
2 L
 field effect transistors 221

where λ is an emperically measured parameter with units V−1 .

Typically λ  1, and lower values of λ are generally preferred
so that the device current is more constant under load (in other
words, a device with lower λ has higher output resistance,
making it a better current source).
Since CLM works by shortening the MOSFET channel, it
makes sense that the effect is dependent on the channel’s phys-
ical length L. A little bit of shortening should have little effect
if L is very large. If L is very small, the effect should be much
more pronounced. Suppose we are designing a circuit and have
freedom to alter the length L. Our goal is to maximize the out-
put resistance. Recall the definition of a MOSFET’s differential
output resistance:
   −1
di D  1
ROUT , = .
dvDS DC λID

Noting that CLM contributes a change in the device’s length,

we can say that

 
d 1 W
−1
ROUT = 0
µn Cox (VGS − VTh )2
dvDS 2 L
1 d 1
= µn Cox0 W (VGS − VTh )2
2 dvDS L
 
1 1 dL
= µn Cox0 W (VGS − VTh )2 − 2
2 L dvDS
   
1 W 1 dL
= µn Cox0 (VGS − VTh )2 −
2 L L dvDS
 
? 1 dL
= ID −
L dvDS

Comparing this to our original result, we see that

 
1  dL 
λ =  .
L dvDS 

Assuming that dL/dvDS is approximately constant for different

choices of L, we may conclude that λ is inversely proportional
to L, so the output resistance is proportional to L. So to get a
large output resistance we need a large L.
222 ece3410 lecture notes

MOSFET Energy Bands

E [eV]
When metal, oxide and semiconductor are brought into contact,
the energy bands are altered around the material interfaces.
−qVFB
This so-called “band bending” effect contributes to forming
Φs
the device’s channel. To understand band-bending, we need
to introduce the concept of a material’s work function, which
Ec
is the amount of energy needed to eject an electron from the
Φm
material. This concept was first postulated by Einstein as part of
EF
his work on the photoelectric effect, for which he was awarded
Ev
the Nobel Prize. For metals, the work function energy can be
in the range of visible light, so if a visible photon is absorbed
in metal, it can excite an electron to fly out of the material.
Semiconductors tend to have a much larger work function.
In the MOS structure, shown for the equilibrium case in Fig-
M O S
ure 199, all materials share the same Fermi level, so the vacuum d [nm]

energy level must bend to accommodate differences in the metal Figure 199: MOS band-bending at zero gate bias. The
and semiconductor work functions Φm and Φs , respectively. In bands are bent due to differing metal and semicon-
the bulk (on the far right side of the diagram), the Fermi level ductor work functions, Φm and Φs , respectively.

is close to Ev , representing a typical P-type wafer substrate.

Due to the bending, at the oxide-semiconductor interface the E [eV]
Fermi level is positioned (roughly) midway between the con-
duction and valence bands. Since EF is not close to Ec or Ev , the
semiconductor’s surface acts like an intrinsic material. In other q (vG − VFB )

words, the region near the surface is depleted of any excess Φs

mobile charges; it is a depletion region.

When the gate voltage is different from zero, the metal and
semiconductor Fermi levels are split into quasi-Fermi levels Φm (sem)
EF
separated by qvG . The conduction, valence and vacuum bands qψs
bend to accommodate the shifted Fermi levels. When vG < 0, (met)
EF
the bands tend to straighten and bending is eliminated for a
critical value called the flat-band voltage VFB . When vG > 0,
as illustrated in Figure 200, the bending is intensified. When
vG is sufficiently positive, Ec is bent close to EF near the oxide-
M O S
semiconductor interface. When this happens, the material takes d [nm]
on the characteristics of an N-type material, and therefore the
Figure 200: MOS band-bending in strong inversion.
surface charge population is said to be inverted. The applied voltage separates the Fermi level into
Using energy band analysis, we can precisely define the MOS two quasi-Fermi levels in the semiconductor and
metal regions. The quasi-Fermi levels are separated
threshold voltage. To begin with, we consider the Fermi level
by qvG , but the work functions stay constant. On the
deep in the bulk, where the bands are always flat. We defined semiconductor side, the conduction band edge is
a “bulk potential” φb as the difference between the intrinsic and bent very close to the Fermi level, resulting in a high
concentration of mobile charges.
 field effect transistors 223

doped Fermi levels:

0.6
qφb = Ei − EF
 
NA 0.5
= kT ln
ni
 
NA 0.4

VTh [V]
⇒ φb = UT ln .
ni
To truly invert the channel, the bands at the surface must be 0.3

bent so that the Fermi level is φb above the intrinsic level instead
0.2
of below it. Since the amount of band bending is equal to
ψs − VFB , the threshold voltage is where
0.1
ψs − VFB = 2φb 1014 1015 1016 1017 1018
NA [dopants/cm3 ]
⇒ ψs = VFB + 2φb
Now to complete the solution for VTh , we need to know how the
surface potential ψs is related to vG . We mentioned before that
there is a capacitive divider formed between the gate oxide and
the depletion layer beneath the channel. The analysis is rather
complex, but it basically reduces to the depletion width under
the gate and has a form similar to our previous solutions for
depletion width. The answer can be shown to be
p
4es qNA φb
vG = ψs + ,
Cox0
so the threshold voltage at the gate is equal to
p
4es qNA φb
VTh = VFB + 2φb + .
Cox0
From this result we can see that the threshold voltage is heav-
ily dependent on doping concentration and oxide capacitance,
and secondarily dependent on temperature. Since most MOS-
FETs are made using poly-Si gates over Si substrates, we can
focus our attention on those materials. For a typical poly-Si
gate, the work function is Φm ≈ 4.05 V. Since the work func-
tion is defined as E0 − EF , and in the Si substrate EF depends
on the doping concentration, the Si work function is doping
dependent:

Φs = E0 − Ei + ( Ei − EF )
= E0 − Ei + φb = 4.15 V + φb
⇒ VFB = 4.05 V − 4.15 V − φb
p
4es qNA φb
⇒ VTh = −0.1 V + φb + .
Cox0
This expression is evaluated for different doping concentrations
and temperatures in ??.
224 ece3410 lecture notes

Body Effect (aka Back-Gate Effect)

The foregoing analysis on threshold voltage considered only

the gate potential vG , relative to the bulk of the MOS structure.
But the MOSFET device models conventionally consider vGS , the
gate potential relative to the source terminal. What happens if
the source potential is not the same as the bulk? If vS > v B then
these analyses are out of sync and need some correction (Note:
vS is never allowed to be less than v B since that would forward
bias the terminal’s PN junction and make a mess). The most
common correction is to consider that vS alters the capacitive-
divider between vG and ψs , resulting in a decreased threshold
voltage. The change in threshold is given by
p
4es qNA p 
∆VTh =
p
2φb + v S − 2φb .
Cox0

The leading constant appears often enough that it is given its

own symbol, γ, and is called the body effect parameter. We can
rewrite the threshold voltage as
p
VT0 = VFB + 2φb + γ 2φb
p p 
VTh = VT0 + γ 2φb + VS − 2φb
p
2es qNA
γ= .
Cox0
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