International Journal on Electrical Engineering and Informatics - Volume 6, Number 2, June 2014
 
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)
Mohammad Anisur Rahman, Habibah Binti Mohamed, Mamun Bin Ibne Reaz, Sawal Hamid
Md Ali, and Wan Mimi Diyana Wan Zaki

Department of Electrical, Electronic and Systems Engineering

Faculty of Engineering and Built Environment
Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, MALAYSIA

Abstract: A low power 6-bit CMOS ring based digitally controlled oscillator (DCO)
design is presented. The design is proposed based on binary-to-thermometer (BT)
decoder current mirror digital-to-analog converter (DAC) and ring-based voltage
controlled oscillator (VCO). The DCO is implemented using 0.18 µm CEDEC Mentor
Graphic CMOS process at 2.0 V supply voltage. The simulation results show that the
proposed DCO consumed only 9.5764 mW of power besides the output voltage is
1.8121 V and local oscillator clock frequency is 33 MHz. The phase noise parameter is -
132 dBc/Hz with an offset frequency of 100 kHz has also been reported for the
proposed circuits.

Keyword: Ring Oscillator, Digitally-Controlled Oscillator, Digital-to-Analog

Converter, Phase Noise.

1. Introduction
Radios, mobile phones, televisions, computers, are just a few models that depend on PLLs
for right process that has been used widely in the communications world. A PLL is a control
system that produces an output signal [1] ─ [3]. The phase is linked to the phase of an input
reference signal. There are comprised of a phase detector and a variable frequency oscillator.
From the oscillator’s output, the PLLs measure the input signal’s phase with the phase of the
signal derived and regulate the oscillator’s frequency to hold the phases coordinated. To
control the oscillator in a feedback mesh circuit, the phase detector’s signal has been used. The
other essential purpose of a PLL is to synchronize communications between chips [1]. A
reference clock is directed along with the parallel data is interconnected. Since chip-to-chip
communication most frequently happens at a lower rate than the on-chip clock rate, the
reference clock is separated, but still synchronize with the system clock. However other chip
the reference clock is used to synchronize all the input flip-flop, which can present a significant
clock load in the case of wide data buses [4]. Applying clock buffers to deal with this problem
introduces skew between the data and the sample clock. A PLL aligns, that is de-skews, the
output of the clock buffer with the respect to the data. In addition, the PLL can multiply the
frequency of the incoming reference clock, allowing the core of the second chip to operate at
higher frequency than the input reference clock [5].
There are some types of PLLs that are, analog phase-locked loop (APLL), also known as a
linear phase-locked loop (LPLL), software phase-locked loop (SPLL), all digital phase-locked
loop (ADPLL), and digital phase-locked loop (DPLL) [6] ─ [8]. The upsurge of the operating
range by adding more capacitance loading will effect in a lower maximum frequency and
higher power consumption. The reduction of the power consumption has developed a key
alarm in modern electronic systems since power consumption is of great fear for portable
battery-charger in the computing system.
This paper proposed ring-based DCO, which is the combination of a (DAC) [9] and
differential ring-based VCO [10, 11]. The current-steering converter is the leading formation
for extremely high speed DAC. The current-steering DAC has the benefits of being quite cost
efficient. Generally, a self-calibrated circuit can be designed to solve these problems [12] ─

 Received: November 3rd, 2013.  Accepted: April 18th, 2014

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Mohammad Anisur Rahman, et al.
 
[14] but the circuit will utilize more power and need a large chip area. The segmented current
steering is the current method for designing digital-to-analog converters. It merges the benefits
of binary weighted and thermometer-coded designs. Successively, the circuit area is reduced
with the segmented DAC, as shown in Figure 1.

Figure 1. Single ended DAC construction [9]

Ring oscillators can be developed in any standard CMOS process and might need fewer
chip area. The design is forthright and ring architectures can be used to offer multiple output
phases and wide tuning ranges. With the purpose of reducing the chip area, design of a CMOS
differential ring oscillator has been performed notwithstanding its characteristic decreased the
phase noise. Therefore, Ring-based VCO (RVCO) is normally familiar because of a
moderately small area and toughness over process and temperature changes. The RVCO must
be implemented by using differential as a substitute of single ended circuits as delay circuits.

2. Construction of DCO
Normally oscillators are found in wireless communication devices and used in synthesizers,
mixers and phase lock loops. Apart from a controllable frequency, the specifications for DCO
are frequency range, tuning sensitivity, power consumption, output power, phase noise etc. In
this paper, we present a DCO for fully digital PLL application capable of supplying local
oscillator clocks at 33 MHz to 3 GHz with low phase noise as well as low power consumption.
As mentioned earlier, the proposed DCO is consists of single ended current steering DAC and
ring-based VCO, as shown in figure 2. The DAC circuit contained BT decoders and current
mirror circuits. There are three current mirrors of different weighting in the current mirrors
circuit. Each current mirror regulated a 2-bit BT code decoder.

Digital Current Vout1 

BT Three stages
code mirror and
Decoder Ring-based
input switch VCO
i it Vout2 
R

GN
   
Figure 2. The proposed ring-based DCO

The DAC has gained the advantage of low chip area. It is been obliged low transistor count
of this formation. Hence, this DAC has more probability to use low power. The construction
circuit of one 2-bit BT decoder comprises of one AND gate and one OR gate in the transistors
level. Figure 3 represents the circuit of one 2-bit current mirror circuit of DAC. The transistors
M2, M3 and M4, act as switches. These switches turned on the current route. The BT decoder
stage generated the signals, S0, S1 and S2. When the switches were turned on, operative
resistance looks as if in the middle of the drain of M1 and GND.

 
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Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)
 

(a) (b) 
Figure 3. The
T Current mirror
m DAC circcuits (a) Schem
matic, (b) layouut

The Iunit
u was the curr rent of the unitt output of the 2-bit DAC whhen the inputs of
o the switchess
is 1002. The
T I1 was verrified by the parallel
p resistannce of the swittches (M2, M3 and M4). Thee
current sw
witch of the 6-b
bit single-endeed DAC needs 9 NMOS transsistors acted ass switches. Thee
switches set
s the current will be on or off.
o Iout accumuulated the curreents from the current
c mirrors..
PMOS traansistors M0 an nd M1 were accted as a basic current mirrorr. The widths ofo the switchess
(M2, M3, M4) transisto ors were amennded to achievve an appropriiate current onn M1. Figure 4
describes a 2-bit BT deccoder current mirror
m DAC.

Figure
F 4. A 2-bbit BT decoder current mirrorr DAC

Differrent current weere acquired byy altering the widthw of the PMOS
P M0. Thee DAC neededd
three diffe
ferent current sources that aree Iunit, 4Iunit andd 16Iunit. It is thhe purpose of smaller
s area off

 
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Mohammad Anisur Rahman, et al.
 
the DAC.. The aspect raatio of M0/M1 were w attuned to
t get the unit current Iunit, The aspect ratioo
of M2/M4 and M10/M111 also attuned to t obtain the current
c unit forr each current mirror circuit,,
which is 4I
4 unit and 16Iuniit respectively. As for VCO, there
t are massiive study has been
b performedd
to evaluatte and amend thet phase noisee of ring oscilllator [15] ─ [18]. From thesee studies, it hass
been testiified that the phase
p noise is reduced by thhe improved chhannel thermall noise and thee
decreasedd output voltage swing. Thee Ring-based VCO circuit consists of thhree-stage ringg
oscillator.
The circuit is design ned for every CMOS, eitherr PMOS or NM MOS, is W/L= =0.9/0.18. Thee
method, which
w is using
g multiple-passs loop, adds suupplementary feedf forward looops that workk
in conjunction with the main loop. It is to decrease thhe delay of thee stages. Other configurationss
are possibble to obtain a different frequuency increase or decrease evven though thee illustration off
an oscillaator with an oddd number of stages,
s with the feed forwardd loops passingg over a singlee
stage. Addjusting the strength of the laatch using the Vcontrol , from Vdac that is coonnected to thee
switches N11 and N13 3 regulates thee interval of thhe stage, and the VCO freqquency. Higherr
control voltages
v effectt in a strongger connectionn between N55 and N7. It creates moree
complicatted to switch th he output voltaage, and therefoore reducing thhe frequency.

3. Resultss and Discussiion

As meentioned above, the proposeed ring-based DCO D is a com
mbination of DAC
D and ring--
based VC CO. The propo osed ring-basedd DCO circuit is designed foor low phase noise n and widee
frequencyy tuning range. These circuitts are implemeented using ED DA CEDEC MentorM Graphicc
0.18 µm CMOS
C processs. It is 6-bit rinng-based Digitaally Controlledd Oscillator wiith the value off
supply vooltage is 2.0 V.
V The value off the load resisstor, RL, is 50 Ω, meanwhilee the transistorr
count is 75
7 MOS. For DAC,D the Vdacc is 69.810 mV V, meanwhile thet output volttages for VCO O
are, Vout1 is 1.8121 V. The
T power disssipation is 9.57764 mW. The core c size is esttimated aroundd
6000 µm2 (130.02 µm X 46.21 µm).
From the wave outp put, Figure 5 showss the digiital input by using
u function ‘Pattern’. Thee
input volttage for high in
nput, VIH, is 2 V meanwhile the t input voltagge for low inpuut, VIL, is -2 V.
This DCO O has 6 inputs since
s it is 6-bitt DCO.

Figure 5.
5 The inputs foor 6-bit DCO

Figuree 6 depicts thaat the output voltage

v for 6-bit BT decodeer current mirrror DAC. Thee
output vooltage, Vdac, is 69.810 mV. This
T output volttage will be thhe input voltage or Vcontrol forr
three-stagge ring oscillato
or.

 
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Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)
 

Figure 6. The output vooltage for DAC

C

Vdac will
w be the Vcoontrol to the threee-stage ring oscillator
o for VCO.
V The volttage output forr
DCO is 1.8121
1 V, slig
ghtly lower thaan the supply voltage (2 V), might be theere are currentt
dissipatedd through the circuits.
c It disssipated 9. 395%
%. In figure 7, the phase noiise point out att
offset freqquency 100KH Hz is -132 dBc//Hz.

Figure 7. Phase
P noise at offset
o frequency.

 
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Mohammad Anisur Rahman, et al.
 
Furtheer down, it shoows Figure 8 (a)
( the complette circuit for riing-based DCO O in schematicc
and Figurre 8 (b) shows the layout of DCO. The sizze of DCO corre cell is approoximately 60000
µm2 (1300.02 µm X 46.2 21 µm). The performance Coomparisons with earlier reported circuits inn
terms of power
p consummption, phase noise
n and frequuency range aree presented in Table 1. It hass
been obseerved that the proposed circuuits show conssiderable poweer saving, a suufficient tuningg
range andd better phase noise.
n

(a)

(b)

Figure 8. The ring-based digitally conntrolled oscillattor circuit (a) schematic diagrram, (b) layoutt

Tablle 1. The ring-bbased DCO performance Commparison.

Power Outputt
DCO Phasse noise Technology
consumption frequenccy
s
structure (dB
Bc/Hz) (µm)
(mW) (GHz)
R
Ref. [19] 63.4 0.333–1.4472 –106 @1
@ MHz 0.35
R
Ref. [20] 5.4 0.087–0.2250 – 0.18
R
Ref. [21] 30 4.89–5.36 –114 @1
@ MHz 0.18
R
Ref. [22] 9 8.79–9.17 –105 @1
@ MHz 0.18
Preesent work 9.5764 0.033–33 -132@
@100 KHz 0.18

 
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Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)
 
Conclusion
The structure of low power 6-bit ring-based DCO was proposed using a 0.18 µm CMOS
process have been presented in this paper. This circuit is a combination of BT decoder, current
DAC and three-stage ring-based VCO. Simulation results indicate the new 6-bit DCO is able to
operate at low supply voltage of 2V and low power consumption is 9.5764 mW. The presented
results demonstrate that the proposed design is feasible for various clock control systems for
full digital implementations. The performance, flexibility, and robustness make the 6-bit ring-
based DCO feasible for high performance fully digital PLL application.

References
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Moha ammad Anisu ur Rahman wasw born in Raajshahi, Banglaadesh in 1989.

He reeceived his B.S Sc. degree in Electrical
E and Electronic Enggineering from
m
Rajsh
hahi Universitty of Engineering & Technology, Bangladesh B inn
2011.Currently he is pursuing his Master Degreee by Researchh in the area off
FPGAA based multi--standard baseeband processoor under the Department
D off
Electrrical, Electronnic and Systemms Engineeringg in Universitti Kebangsaann
Malayysia, Malaysiaa. His researcch interest iss in the fieldd of Wirelesss
commmunication, Maathematical moodeling, VLSI design.
d

Habiibah Mohameed was born inn Malaysia, in 13 April 1981. She receivedd
her B.Sc.
B and M.Scc. degree in Eleectronics, both from Universiiti Kebangsaann
Malay ysia (UKM), Malaysia,
M in 2004
2 and 20133, respectivelyy. Her researchh
intereests are in the following fiellds: RF Analoog and Mixed Signal design,,
Wirelless Communiccation, SoC deesign and fabriccation.

Mam mun Bin Ibne Reaz was boorn in Bangladdesh, in Decem mber 1963. Hee
receivved his B.Sc. and M.Sc. deegree in Appliied Physics annd Electronics,,
both from Univerrsity of Rajhhashi, Bangladesh, in 19885 and 1986,,
respeectively. He recceived his D.Enng. degree in 2007
2 from Ibaraaki University,,
Japann. He is currenntly an Associaate Professor in the Universiiti Kebangsaann
Malay ysia, Malaysia involving in teachingg, research and a industriall
consuultation. He iss a regular asssociate of the Abdus Salam m Internationall
Centeer for Theoretical Physics sinnce 2008. He has
h vast researcch experiencess
in Norwaay, Ireland and
d Malaysia. Hee has publishedd extensively in i the area of IC
I Design andd
Biomediccal application IC. He is autthor and co-auuthor of more thant 100 reseaarch articles inn
design auutomation and IC
I design for biomedical
b appplications.

 
304
 
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)
 
Sawaal Hamid Md Ali iss a Senior Lecturer in i Universitii
Kebanngsaan Malayssia. He compleeted his PhD inn 2009. His ressearch interestss
are Analog
A Mixedd Signal Desiggn, VLSI, Beehavioral Moddeling, System m
Optim
mization

Wan Mimi Diyanaa Wan Zaki joined Universitti Kebangsaan Malaysia

M in 022
June 2008. She com mpleted her PhhD from Multiimedia Univerrsity, Malaysia..
Her research
r interests are in the fields medical imaging andd digital imagee
processing. She is currentlyy a Senior Lecturer in i Universitii
Kebanngsaan Malayssia involved in teaching, research and a industriall
consu
ultation.

 
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