GLOBAL INSTITUTE OF ENGINEERING AND TECHNOLOGY

MELVISHARAM- VELLORE-632 509

COURSE MATERIAL
DEPARTMENT: MECHANICAL ENGINEERING
SEMESTER/YEAR: IV /II ACADAMIC YEAR: 2013-2014
COURSE CODE: ME2255 COURSE NAME: ELECTRONICS AND
MICROPROCESSORS

UNIT-I
SEMICONDUCTORS AND RECTIFIERS

Classification of solids based on energy band theory – Intrinsic semiconductors –

Extrinsic semiconductors – P-type and N-type – PN junction – Zener effect –Zener
diode characteristics – Half wave and full wave rectifiers – Voltage regulation.

1. Draw and explain the formation of a PN junction and explain the working of the
diode under forward and reverse biased conditions. (AUC Apr/May 2010)
2. Draw V/I characteristics of PN junction diode and explain the function of a full
wave rectifier with a neat circuit diagram. (AUC Nov/Dec 2011)

FORMATION OF PN JUNCTION:

Prepared by: M.PRABHU AP/ECE

 When the N and P-type semiconductor materials are first joined together a very large
density gradient exists between both sides of the junction.
 The free electrons migrate towards the junction to fill up the holes in P-type.

 It produces negative ions.

 The electrons movement from the N-type silicon to the P-type silicon, leaves positively
charged donor ions on negative side.

 Now the holes from the acceptor impurity migrate across the junction in the opposite
direction into the region where there are large numbers of free electrons.

 As a result, the charge density of the P-type along the junction is filled with negatively
charged acceptor ions (NA).
 The charge density of the N-type along the junction becomes positive.
 This charge transfer of electrons and holes across the junction is known as diffusion.
V-I CHARACTERISTICS:

Prepared by: M.PRABHU AP/ECE

Reverse Bias:

 If the electrons and holes are generated in the vicinity of junction then there is a flow of
current.
 The negative voltage applied to the diode will tend to attract the holes thus generated
and repel the electrons.

 At the same time, the positive voltage will attract the electrons towards the battery and
repel the holes.

 This will cause current to flow in the circuit.

 This current is usually very small (interms of micro amp to nano amp).

 The current is due to minority carriers and these number of minority carriers are fixed.
 At a given temperature, the current is constant known as reverse saturation currentICO.
Forward bias:

 When the diode is forward biased, the majority carriers are pushed towards junction.
 When they collide, recombination takes place.

 Number of majority carriers is fixed in semiconductor.

 As each electron is eliminated at the junction, a new electron must be introduced.

 At the same time, one hole must be created in p-layer.

 Therefore, there is a flow of carriers and thus flow of current.

Prepared by: M.PRABHU AP/ECE

1. What do you mean by zener effect? Explain the characteristics of zener diode. (6)
2. Explain how zener diode is used as a voltage regulator.(10) (AUC May/Jun 2012)
3. Draw zener diode characteristic and explain. (AUC Dec 2011)
4. Is it possible to replace a zener diode with an ordinary rectifier diode? If no, explain
the desired characteristics of zener diode. (AUC Apr/May 2010)
5. Explain the working principle of zener voltage regulator with relevant diagram.
(Nov/Dec 2011)

 The diodes designed to work in breakdown region are called zener diode.
 The carrier collides with crystal ions, gains sufficient energy to disrupt a covalent bond.

 In addition to the original carrier, a new electron-hole pair is generated.

 This action continues and thereby disrupts the covalent bonds. The process is referred to
as impact ionization, avalanche multiplication or avalanche breakdown.
 If the electric field exerts a strong force on a bound electron, the electron can be torn
from the covalent bond thus causing the number of electron-hole pair combinations to
multiply. This mechanism is called high field emission or Zener breakdown.

 The reverse voltage at which the avalanche occurs is called the breakdown or Zener
voltage.

 The maximum reverse current, IZ(max), which the Zener diode can withstand is
dependent on the design and construction of the diode.

 The power handling capacity of these diodes is better.

 The power dissipation of a zener diode equals the product of its voltage and current.
P Z = V Z IZ
 The amount of power which the zener diode can withstand (V Z.IZ(max)) is a limiting factor
in power supply design.

Prepared by: M.PRABHU AP/ECE

1. Explain the function of a full wave rectifier with a neat circuit diagram.
(Nov/Dec 2011)
2. Explain the function of a full wave rectifier with a neat circuit diagram.
(Apr/May 2011)

The output voltage waveform.

 A single – phase full wave rectifier using center tap transformer.
 It supplies current in both half cycles of the input voltage.

 In the first half cycle D1 is forward biased and conducts. But D2 is reverse biased and
does not conduct.

 In the second half cycle D2 is forward biased, and conducts and D1 is reverse biased.

 It is also called 2 – pulse midpoint converter because it supplies current in both the
half cycles.

 The average output voltage is given by

and the average load current is given by

.
 When D1 conducts, then full secondary voltage appears across D2, therefore PIV
rating of the diode should be 2 Vm.

1. Explain the function of a half wave rectifier with a neat circuit diagram.
(Nov/Dec 2011)
2. Explain the function of a half wave rectifier with a neat circuit diagram.
(Apr/May 2011)

Prepared by: M.PRABHU AP/ECE

 The output voltage waveform

 In positive half cycle, D is forward biased and conducts.

 The output voltage is same as the input voltage.
 In the negative half cycle, D is reverse biased, and therefore output voltage is zero.
 The average output voltage of the rectifier is given by

The average output current is given by

 When the diode is reverse biased, entire transformer voltage appears across the diode.
 The maximum voltage across the diode is Vm.

 The diode must be capable to withstand this voltage.

1. Explain the working principle of zener voltage regulator with relevant diagram.
(Nov/Dec 2011)
2. Explain the working principle of zener voltage regulator with relevant diagram.
(Apr/May 2011)

Prepared by: M.PRABHU AP/ECE

 Zener Diodes can be used to produce a stabilised voltage output with low ripple under
varying load current conditions.
 The DC output voltage from the half or full-wave rectifiers contains ripple superimposed
onto the DC voltage.
 By connecting a simple zener stabiliser circuit across the output of the rectifier, a more
stable output voltage can be produced.
 The resistor, RS is connected in series with the zener diode to limit the current flow
through the diode.
 A zener diode is always operated in its reverse biased condition.
 A voltage regulator circuit can be designed using a zener diode to maintain a constant
DC output voltage across the load in spite of variations in the input voltage or changes in
the load current.
 It consists of a current limiting resistor R S connected in series with the input voltage V S
with the zener diode connected in parallel with the load R L in this reverse biased
condition.

1. Discuss about intrinsic and extrinsic semiconductors. (8) (AUC May/Jun 2012)
2. Explain about intrinsic and extrinsic semiconductors. (8) (AUC May/Jun 2013)

INTRINSIC SEMICONDUCTORS:

Prepared by: M.PRABHU AP/ECE

 A perfect semiconductor crystal with no impurities or lattice defects.
 No carriers at 0 K, since the valence band is completely full and the conduction band is
completely empty.
 EHP generation takes place due to breaking of covalent bonds required energy =Eg
 The excited electron becomes free and leaves behind an empty state (hole).
 To maintain a steady-state carrier concentration, the carriers must also recombine at the
same rate at which they are generated.
 Recombination occurs when an electron from the conduction band makes a transition
(direct or indirect) to an empty state in the valence band, thus annihilating the pair

EXTRINSIC SEMICONDUCTORS:

 Introducing impurities into the crystal doping.

 Most common technique for varying the conductivity of semiconductors.
 By doping, the crystal can be made to have predominantly electrons (n-type) or holes (p-
type).
 When a crystal is doped such that the equilibrium concentrations of electrons (n0) and
holes (p0) are different from the intrinsic carrier concentration (ni), the material is said to
be extrinsic.
 Si doped with acceptor impurities can have a significant number of holes in the valence
band.
 Even at a very low temperature, i.e., >> , p-type material, with holes as majority carriers
and electrons as minority carriers.

1. Define PN junction. (2) (AUC Nov/Dec 2011)

 N and P-type materials do very little on their own as they are electrically neutral.

 When we join (or fuse) them together these two materials behave in a very different way
producing a PN Junction.

1. Define Rectification. (2) (AUC May/Jun 2012)

2. What is a rectifier? What are its types? (2) (AUC Nov/Dec 2011)

Prepared by: M.PRABHU AP/ECE

 A rectifier is a circuit which converts the Alternating Current (AC) input power into a
Direct Current (DC) output power.

 Types are i)Half Wave Rectifier ii) Full Wave Rectifier

What is diffusion current? (2) (AUC Apr/May 2011)

 The charge density of the P-type along the junction is filled with negatively charged
acceptor ions (NA), and the charge density of the N-type along the junction becomes
positive. This charge transfer of electrons and holes across the junction is known as
diffusion.

1. Draw the circuit of Bridge rectifier with input and output waveforms. (2) (AUC
Apr/May 2011)

UNIT II
TRANSISTORS AND AMPLIFIERS

Prepared by: M.PRABHU AP/ECE

Bipolar junction transistor – CB, CE, CC configuration and characteristics – Biasing
circuits – Class A, B and C amplifiers – Field effect transistor –Configuration and
characteristic of FET amplifier –SCR, diac, triac, UJT – Characteristics and simple
applications – Switching transistors –Concept of feedback –Negative feedback –
Application in temperature and motor speed control.

Draw and explain the circuit of a Class B Pushpull power amplifier. (10) (AUC May/Jun
2012)

 When a transistor operates in class B, it clips off a half cycle.

 To avoid the resulting distortion, two transistors are used in push pull arrangement.

 This means that one transistor conducts during positive half cycle and other transistor
conducts during negative half cycle.

 The distortion is low, load power is large and efficiency ( h ) is more.

 Biasing resistors are selected so that Q-point is set at cutoff.

 This biases the emitter diode of each transistor between 0.6V and 0.7V i.e. ICQ = 0.

 Because the biasing resistors are equal each emitter diode is biased with the same voltage.

Prepared by: M.PRABHU AP/ECE

 As a result half the supply voltage is dropped across each transistor. VCEQ = VCC / 2.

Draw and explain the characteristic of a FET amplifier and discuss its merits and
applications. (AUC May/Jun 2012)
Draw the circuit of a FET amplifier and explain its operation. (AUC Nov/Dec 2011)

 The field effect transistor is a semiconductor device, which depends for its operation on
the control of current by an electric field.
 There are two of field effect transistors:

1. JFET (Junction Field Effect Transistor)

2. MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

 Ohmic contacts are then added on each side of the channel to bring the external
connection.
 If a voltage is applied across the bar, the current flows through the channel.

 The terminal from where the majority carriers (electrons) enter the channel is called
source designated by S.

Prepared by: M.PRABHU AP/ECE

 The terminal through which majority carriers leaves the channel is called drain and
designated by D.

 For an N-channel device, electrons are the majority carriers, current is the drain current ID.

 If VDS increases, ID increases proportionally.

Sketch the input and output characteristics of common emitter configuration and
explain how these are obtained? (16) (AUC Nov/Dec 2011)
Expalin the input and output characteristics of common emitter configuration and
explain how these are obtained? (16) (AUC Nov/Dec 2012)

 In C.E. configuration the emitter is made common to the input and output.
 It is also referred to as grounded emitter configuration.
 In this, base current and output voltages are taken as independent parameters
 Input voltage and output current are dependent parameters,
VBE = f1 ( IB, VCE ), IC = f2( IB, VCE ).
Input Characteristic:

Prepared by: M.PRABHU AP/ECE

 The curves between IB and VBE for different values of VCE
 With higher values of VCE collector gathers slightly more electrons and therefore base
current reduces.
 Normally this effect is neglected. (Early effect).
 When collector is shorted with emitter then the input characteristic is the characteristic of
a forward biased diode when VBE is zero and IB is also zero.
Output Characteristic:

 The output characteristic is the curve between VCE and IC for various values of IB. For
fixed value of IB and is shown in fig.
 For fixed value of IB, IC is not varying much dependent on VCE but slopes are greater than
CE characteristic.
 The output characteristics can again be divided into three parts.
Active Region:
 In this region collector junction is reverse biased and emitter junction is forward biased.
 If transistor is to be used as an amplifier, it must operate in this region.
Cut Off:
 Cut off in a transistor is given by IB = 0, IC= ICO.
Saturation Region:
 In this region both the diodes are forward biased by at least cut in voltage.
 Hence saturation region is very close to zero voltage axis, where all the current rapidly
reduces to zero.

Why do we prefer negative feedback system? Explain the operation of voltage – shunt
feedback with required diagrams. (16) (AUC Apr/May 2011)
What do you mean by negative feedback? List the characteristics and advantages of a
negative feedback amplifier. (6) (AUC May/Jun 2012)

Prepared by: M.PRABHU AP/ECE

 In the feedback process, a part of output is sampled and fed back to the input of the
amplifier.
 Positive feedback: Input signal and part of output signal are in phase.
 Negative feedback: Input signal and part of output signal are in out of phase.
 Feedback can be either negative (degenerative) or positive (regenerative).
 The Vo is sampled by connecting the feedback network in shunt across the output.
 The Io is sampled by connecting the feedback network in series across the output.
 Reduce the output as a feedback signal to the input mixer network.
 Vf=β Vo; Where β- feedback factor lies between 0 & 1.

Draw and explain the SCR charcteristics and operation . (10) (AUC May/Jun 2012)

Draw and explain the SCR charcteristics and operation . (10) (AUC May/Jun 2011)

Prepared by: M.PRABHU AP/ECE

 The rectifier circuit (anode-cathode) a low forward resistance and a high reverse
resistance.
 Controlled from an off state (high resistance) to the on state (low resistance) by a signal
applied to the third terminal, the gate.
 Once it is turned on it remains on even after removal of the gate signal.
 As long as a minimum current, the holding current, IH, is maintained.
 We ground both the cathode and the gate, and apply a positive voltage to the anode, no
current will flow through this device
 This device acts as a switch that is cheaper than a relay
 It is able to handle the large power dissipation.
SCR Operation / Working:
 The Silicon Control Rectifier SCR start conduction when it is forward biased.
 For this purpose the cathode is kept at negative and anode at positive.
 When positive clock pulse is applied at the gate the SCR turns ON.
 When forward bias voltage is applied to the Silicon Control Rectifier SCR, the junction
J1 and J3 become forward bias while the junction J2 become reverse bias.
 When we apply a clock pulse at the gate terminal, the junction J2 become forward bias
and the Silicon Control Rectifier SCR start conduction.
 The Silicon Control Rectifier SCR turn ON and OFF very quickly.
 At the OFF state the Silicon Control Rectifier SCR provide infinity resistance and in ON
state, it offers very low resistance, which is in the range of 0.01O to 1O.

Draw the transfer characteristics of FET. (2) (AUC May/Jun 2012)

Prepared by: M.PRABHU AP/ECE

 UNIT III
DIGITAL ELECTRONICS
Binary number system – AND, OR, NOT, NAND, NOR circuits – Boolean
algebra –Exclusive OR gate – Flip flops – Half and full adders – Registers – Counters –
A/D and D/A conversion.
BINARY NUMBER SYSTEM:
 The conversion of numbers from one number system to another.
 Radix Divide and Multiply Method is generally used for conversion.
 There is a general procedure for the operation of converting a decimal number to a
number in base r.
BOOLEAN ALGEBRA:
Demorgans:

In general form

Very useful for complementing function expressions; for example

LOGIC GATES:
AND gate
 The AND gate gives a true output (1) only if all its inputs are true.
 A dot (·) is used to show the AND operation
 i.e. A·B. Note that the dot is sometimes omitted i.e. AB

Prepared by: M.PRABHU AP/ECE

OR gate
 The OR gives a true output (1) if one or more of its inputs are true.
 A plus (+) is used to show the OR operation.

NOT gate
 The NOT gate produces an inverted version of the input at its output.
 It is also known as an inverter.
 If the input variable is A, the inverted output is known as NOT A.
 This is also shown as A', or Ā with a bar over the top.

NAND gate
 This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.
 The outputs of all NAND gates are true if any of the inputs are false.
 The symbol is an AND gate with a small circle on the output.
 The small circle represents inversion.

NOR gate:
 This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate.

Prepared by: M.PRABHU AP/ECE

 The outputs of all NOR gates are false if any of the inputs are true.
 The symbol is an OR gate with a small circle on the output.
 The small circle represents inversion.

EXOR gate
 The 'Exclusive-OR' gate is a circuit which will give a true output if either, but not both, of
its two inputs are true.
 An encircled plus sign ( ) is used to show the EOR operation.

EXNOR gate
 The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate.
 It will give a false output if either, but not both, of its two inputs are true.
 The symbol is an EXOR gate with a small circle on the output.
 The small circle represents inversion.

Prepared by: M.PRABHU AP/ECE

Design a half and Full Adder. (16)
HALF ADDER:
 Half adder is a logic circuit that finds the arithmetic sum of two binary digits at a time.

 The outputs of the XOR and AND gates produces the sum and carry respectively.
THE TRUTH TABLE:
Map for SUM Map for CARRY

CARRY = A . B

 The input variables of half adder are augend and addend.

 It is necessary to specify two output variables, because the sum of 1+1=10.
 Let A & B be input variables SUM and CARRY be output variables.
 The Boolean functions of the two outputs are SUM = A B and CARRY = A.B
Design a full adder. (10) (AUC May/Jun 2012)
Design a full adder circuit with the aid of neat diagram and a truth table. (Dec 2011)

Prepared by: M.PRABHU AP/ECE

Implement the full adder circuit from its truth table. (May 2010)
Design a Full adder. (10) [JUNE 12]
Draw the logic diagram of full adder and explain. (8) [DEC 2011]
FULL ADDER:

 A combinational circuit that finds the arithmetic sum of three bits is called a Full adder.
 A Full adder can be constructed using two half adders and an OR gate
Truth table:
Full-adder is a combinational circuit,
performs the arithmetic sum of three input
bits.
 It consists of three inputs and two outputs.
 Two of the input variables denoted by A, B
represents the two significant bits to be added.
 The third input C represents the carry from
the lower significant position.

 The two outputs are denoted by SUM and CARRY.

 The Boolean expressions for SUM and CARRY outputs.

Discuss the operation of RS flip flop and D flip flop. (6) (AUC May/Jun 2012)
Draw the circuit diagram of clocked SR Flip-Flop and explain its truth table. (8)[DEC
11]
FLIP FLOPS:

Prepared by: M.PRABHU AP/ECE

 The storage elements employed in clocked sequential circuits are called flip-flops.
 A flip-flop is a one bit memory device.
 It has two outputs, one for the normal value and one for the complement value of the bit
stored in it.
Type of flip-flops:
1. SR flip-flops. 2. D flip-flops. 3. JK flip-flops. 4. T-flip-flops.

SR FLIP-FLOP:
 In SR flip-flop if S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0.
 It has a clock input, and the Q output can change only after an active clock edge.
Operation summary:
S=R=0 no state change
S = 1, R = 0 set Q to 1 (after active Ck edge)
S = 0, R = 1 reset Q to 0 (after active Ck edge)
S=R=1 not allowed

D FLIP-FLOP:
 A D flip-flop has two inputs, D (data) and Ck (clock).
 The small arrowhead on the flip-flop symbol identifies the clock input.
 If the output can change in response to a 0 to 1 transition on the clock input, we say that
the flip-flop is triggered on the rising edge (or positive edge) of the clock.
 If the output can change in response to a 1 to 0 transition of the clock input, we say that
the flip-flop is triggered on the falling edge (or negative edge) of the clock.

Prepared by: M.PRABHU AP/ECE

Timing for D Flip-Flop (Falling-Edge Trigger) D Flip-Flop
Discuss the operation of JK flip flop and T flip flop. (8)
J-K FLIP-FLOP:
 The J-K flip-flop is an extended version of the S-R flip-flop.
 The J input corresponds to S, and K corresponds to R.
 1 input may be applied simultaneously to J and K, in which case the flip-flop changes
state after the active clock edge.

Prepared by: M.PRABHU AP/ECE

T FLIP-FLOP:
 The T flip-flop, also called the toggle flip-flop, is frequently used in building counters.
 It has a T input and a clock input.
 When T = 1 the flip-flop changes state after the active edge of the clock.
 When T = 0, no state change occurs.

Timing Diagram for T Flip-Flop (Falling-Edge Trigger)

With the help of neat circuit diagram explain the function of a Ripple counter. (AUC
Nov/Dec 2011)

Prepared by: M.PRABHU AP/ECE

Asynchronous Counter (Ripple Counter):
 Flip-flops can be connected to get an binary counter, which counts the number of input
triggers (clock pulses).

 The clock pulse drives A. The output of ‘A’ drives ‘B’ and the output of ‘B’ drives ‘C’.
 All the J&K inputs are tied to +Vcc, which means J=K=1.
 Each flip-flop will toggle with a negative transition at its clock input.
 This kind of a counter in which output of one flipflop drives the other is called a ripple or
asynchronous counter (as trigger moves like a ripple in water).
OPERATION:
 Initially all the flip-flops are reset to produce 0 outputs by making use of the clear inputs.
 The output condition is CBA=000.
 When the first clock pulse strikes, ‘A’ changes its states from 0 to 1. Since it is a positive
change it will not trigger ‘B’. So the output is CBA=001.
 For the second pulse ‘A’ changes from 1 to 0. Since it is a negative change it triggers ‘B’.
So ‘B’ changes from 0 to 1.
 Since it is a positive change, it will not trigger ‘C’. Now output is CBA=010.
 For the third pulse ‘A’ changes from 0 to 1 and it will not trigger ‘B’. So the output is
CBA=011.
 In this manner the counter will count up to 111.
 The waveform at ‘A’ is one half of the clock frequency.
 ‘B’ is one fourth of the clock frequency and ‘C’ is one eighth of the clock frequency.

Prepared by: M.PRABHU AP/ECE

 Truth table: Waveforms:

With the logic diagram, explain the working of Ring

counter. Also draw the timing diagrams. (AUC
Apr/May 2011)
With the logic diagram, explain the working of Ring
Counter. Also draw
the timing diagrams. (16)
Ring Counter:

 Ring counters are implemented using shift registers.

 It is essentially a circulating shift register connected so that the last flip-flop shifts its
value into the first flip-flop.
 A single 1 circulating in the register, as long as clock pulses are applied.
 (Starts 1000->0100->0010->0001 repeat).

Prepared by: M.PRABHU AP/ECE

 Start control signal, which presets the left-most flip-flop to 1 and clears the others to 0.

Design a four bit binary parallel counter. Support your answer with circuit diagram and
truth table. (AUC Apr/May 2010)
Explain the functions of 4 bit binary up counter. (8) [DEC 11]
Synchronous Counter (Parallel Counter):
 The ripple counter is easy to build but there is a limitation of to its highest operating
frequency.
 Here each flip-flop has a delay time and these delays are additive so the propagation
delay of the entire counter is the sum of the individual delays.
 Here each flip-flop is triggered by the clock and this makes simultaneously transition in
all the flip-flops.

Mod-8 Parallel Binary Counter:

Prepared by: M.PRABHU AP/ECE

 All the three flip-flops are negatively edge triggered and both J&K inputs are tied to
+Vcc.
 The flip-flop A changes state with each negative transition at the clock input.
 The output of the AND gate (1) goes high whenever the clock is high and ‘A’ is high.
 Thus flip-flop ‘B’ changes state with every other clock.
 The output of AND gate (2) goes high each time the clock is high and both ‘A’ are ‘B’ are
high.
 Thus flip-flop ‘A’ changes state with every fourth clock.

Truth table: Waveforms:

Explain the successive approximation type of A/D and resistor to ladder D/A converter.
(16) [DEC 10]
Explain why do we need Analog to Digital converter and Digital to Analog converter in
a microprocessor based system. (8) [DEC 11]

Prepared by: M.PRABHU AP/ECE

Draw and explain the operation of A/D and D/A converters. (AUC May/Jun 2012)
SUCCESSIVE-APPROXIMATION ADCS:

 The successive approximation technique uses a very efficient code search strategy to
complete n-bit conversion in n-clock periods.
 The circuit uses a successive approximation register (SAR) to find the required value of
each bit by trial and error.

 With the arrival START command, the SAR sets MSB d1 = 1 with all other bits to zero.
 The trial code is 10000000, output Vd of DAC is compared with input Va.
 If Va >Vd then 10000000is less than the correct digital representation.
 The MSB is left at ‘1’ and next LSB is made ‘1’ and tested.
 If Va < Vd then 10000000 is greater than correct digital representation, so reset MSB to
‘0’and go on to next LSB.
 It is repeated until all bits are tested.

R-2R LADDER DAC:

 An enhancement of the binary-weighted resistor DAC is the R-2R ladder network.
 This type of DAC utilizes Thevenin’s theorem in arriving at the desired output voltages.
 The R-2R network consists of resistors with only two values - R and 2xR.

Prepared by: M.PRABHU AP/ECE

 If each input is supplied either 0 volts or reference voltage, the output voltage will be an
analog equivalent of the binary value of the three bits.
 VS2 corresponds to the most significant bit (MSB) while VS0 corresponds to the
least significant bit (LSB).

Vout = - (VMSB + Vn + VLSB) = - (VRef + VRef/2 + VRef/ 4)

D/A CONVERTER:
 A DAC converts an abstract finite-precision number (usually a fixed-point binary
number) into a concrete physical quantity (e.g., a voltage or a pressure).
 DACs are often used toconvert finite-precision time series data to a continually-varying
physical signal.
 A typical DAC converts the abstract numbers into a concrete sequence of impulses that
are then processed by a reconstruction filter
A TO D CONVERTER:

 Developments in digital technology like the CD, DVD, Blu-ray, flash devices and other
memory devices addressed these problems.
 For these devices to be used, the analog signals are first converted to digital signals using
analog to digital conversion (ADC).
Sampling rate:
 The analog signal is continuous in time and it is necessary to convert this to a flow of
digital values.

Prepared by: M.PRABHU AP/ECE

 It is therefore required to define the rate at which new digital values are sampled from
the analog signal.

Prepared by: M.PRABHU AP/ECE