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CMOS Inverter Modelling On CADENCE

This document summarizes a digital assignment on modeling and designing a nano-scale CMOS inverter. The objectives are to understand the static voltage transfer characteristics of a CMOS inverter, characterize its switching threshold, noise margins, and on-state resistance, and study the effect of power supply voltage. Key findings include the voltage transfer characteristic curve obtained from a CADENCE simulation with VDD=1.8V. Noise margins and on-state resistances are also characterized. A parametric analysis varying the supply voltage from 0-1.8V shows how the voltage transfer characteristic curve changes with different power supply voltages.

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Sanket Koley
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246 views

CMOS Inverter Modelling On CADENCE

This document summarizes a digital assignment on modeling and designing a nano-scale CMOS inverter. The objectives are to understand the static voltage transfer characteristics of a CMOS inverter, characterize its switching threshold, noise margins, and on-state resistance, and study the effect of power supply voltage. Key findings include the voltage transfer characteristic curve obtained from a CADENCE simulation with VDD=1.8V. Noise margins and on-state resistances are also characterized. A parametric analysis varying the supply voltage from 0-1.8V shows how the voltage transfer characteristic curve changes with different power supply voltages.

Uploaded by

Sanket Koley
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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REG. NO.

:19MVD0006
NAME: SANKET KOLEY

DIGITAL ASSIGNMENT-1
MODELLING AND DESIGN OF NANO SCALE CMOS INVERTER
Objectives
a)Understand CMOS inverter static voltage transfer characteristics.
b)Characterize switching threshold, noise margins and on-state resistance.
c)Study effect of power supply voltage on voltage transfer characteristics.

1.CMOS Inverter Static Voltage Transfer Characterictics:

It is a plot between the output dc voltage and input dc voltage of a CMOS inverter. The
following characterictics are obtained from a CMOS schematic designed on CADENCE
Virtuoso with VDD=1.8 V and dc input voltage to the gate is 1.8 V.
2.Characterizing Switching Threshold, Noise Margins and On state resistance:

Switching threshold is that point on the Voltage Transfer Characterictic where Vin=Vout.

The switching threshold voltage is obtained from the VTC by selecting the intersection point of
the input and output voltage curves.

Noise margin allows to determine the allowable noise voltage on the input of a gate so that the
output will not be corrupted.The Low noise margin is given by, NML=VIL-VOL and the High
noise margin is given by, NMH=VOH-VIH.The values of VIL,VOL,VOH,VIH are calculated on
CADENCE Virtuoso on the points on VTC where the slope is -1.
From the graphs, we get VIL=387.931mV, VOH=1.6109V, VOL=216.247mV, VIH=867.815mV

So, NMH= 743 mV and NML= 171.684 mV.

The on state resistance of the CMOS inverter is as follows for PMOS and NMOS respectively.
3. Study of effect of Power Supply on CMOS Inverter:

Since in the region A of VTC the pmos is linear and it drives the supply voltage VDD to the
output, so with change in supply voltage the magnitude of the region A will change. Also the
switching threshold or mid point value is approximately , the structure of the characteristic
curve changes accordingly.

In the following figure a parametric analysis of a CMOS circuit is done on CADENCE Virtuoso
varying the supply voltage from 0V to 1.8V with linear step size of 0.45V.

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