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Design of Very Large Scale Integration Circuits

This document provides an overview and introduction to the 227-0147-00L VLSI II: Design of Very Large Scale Integration Circuits course at ETH Zurich. It outlines the course structure, topics to be covered including architecture and system design, VLSI circuit design, and microelectronic system design. It also describes the textbook, lecture and exercise schedule, goals of the hands-on exercises, and information on how to make the most of the exercises. The exercises provide opportunities for students to apply what they learn in class to practical design work using industry tools.

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235 views

Design of Very Large Scale Integration Circuits

This document provides an overview and introduction to the 227-0147-00L VLSI II: Design of Very Large Scale Integration Circuits course at ETH Zurich. It outlines the course structure, topics to be covered including architecture and system design, VLSI circuit design, and microelectronic system design. It also describes the textbook, lecture and exercise schedule, goals of the hands-on exercises, and information on how to make the most of the exercises. The exercises provide opportunities for students to apply what they learn in class to practical design work using industry tools.

Uploaded by

Student
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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227-0147-00L VLSI II: Design of Very

Large Scale Integration Circuits


http://vlsi2.ethz.ch
[email protected]
Luca Benini, Frank Gürkaynak, Florian Zaruba
[email protected], [email protected], [email protected]
Computing everywhere

The Cloud, IoT, CPS…

VLSI I From Architectures to VLSI circuits and FPGAs 2


CPS/IoT Hierarchical Processing

Apple A11 90mm2 TSMC10nm NVIDIA V100 815mm2 TSMC12nm


3
IIS Digital Circuits and Systems

Ultra-low power Portable ultrasound Mixed signal processing system


RISC-V based processors system design on FPGAs For biomedical applicartions

FPGA based systems and Low-power communication Student projects on IC Design


emulation platforms For IoT systems i.e. graphic processing

VLSI I From Architectures to VLSI circuits and FPGAs 4


Core competences

Architecture and system design

Industry standard design flow


Optimization of algorithms for VLSI implementation

Translation of algorithms into RTL architectures

VLSI circuit design

Microelectronic system & FPGA design


This class

ASIC integration and test

VLSI I From Architectures to VLSI circuits and FPGAs 5


This class - Info

WEB SITE (only within ETHZ): https://vlsi2.ethz.ch

VLSI I From Architectures to VLSI circuits and FPGAs 6


Frank will help with some of the classes

§ Senior Scientist at IIS and Head of


Microelectronics Design Center
§ At IIS since 2000

§ Has many years of experience in:


§ Testing
§ Asynchronous Circuits
§ Chip Finishing

VLSI I From Architectures to VLSI circuits and FPGAs 7


New people, same class

§ First year for the team teaching this particular course


§ The structure will be mostly the same
§ Both of us have plenty of teaching experience in VLSI design
§ Will use same book, similar structure

§ Smaller changes
§ More emphasis on low power design
§ An introduction to CAD algorithms
§ Business aspects of VLSI Design moved to VLSI III

VLSI I From Architectures to VLSI circuits and FPGAs 8


Textbook
Hubert Kaeslin:
Top-Down Digital VLSI Design
Vol2: From Gate-Level Circuits to
CMOS Fabriction

Lecture notes, will be sold during the


break for 20 CHF to cover part of the
printing costs.

VLSI I From Architectures to VLSI circuits and FPGAs 9


Additional reference (VLSI 1 textbook)
Hubert Kaeslin:
Top-Down Digital VLSI Design
Vol1: From Architectures to Gate-Level
Circuits and FPGAs

Available for FREE online:

https://www.sciencedirect.com/science
/book/9780128007303

VLSI I From Architectures to VLSI circuits and FPGAs 10


Program
Date Who Lecture Topic Exercise Topic
20. Feb Luca Introduction and Motivation Synthesis and Simulation flow
27. Feb Frank Packaging and Interfaces Practical Interfaces and I/Os
06. Mar Luca Cell based Digital Circuit Design Introduction to Innovus
13. Mar Luca Clocking Disciplines Padring and Floorplanning
20. Mar Frank Clock Distribution, Clock Gating Design Review (Theoretical exercise)
27. Mar Frank Acquisition of Analog Signals Timing
Easter Break

10. Apr Luca Power Estimation, Low-power design Power Analysis


17. Apr Frank Advanced techniques for Low power design Power Distribution
24. Apr Luca CAD design tools Placement and Routing Flow
01. May 1st of May - No lecture Testing (Theoretical exercise)
08. May Frank Introduction to VLSI Testing Scan Insertion
15. May Frank Signal Integrity: Switching Noise Crosstalk Chip Finishing / Sign Off
22. May Frank Physical Design Physical Verification
29. May Luca Outlook, summary, and evaluation no exercise
VLSI I From Architectures to VLSI circuits and FPGAs 11
WWW page and other resources

Official www site of the course will include slides & exercises

http://vlsi2.ethz.ch

EDA wiki (ETH Internal www site) with tips and tricks

http://eda.ee.ethz.ch

VLSI I From Architectures to VLSI circuits and FPGAs 12


Exam

§ 30 minutes oral exam during the exam period


§ Timeslots managed by the examination office.

§ Attending laboratory exercises will help with your exam


§ Practical implementation of topics discussed in class
§ Exam may include topics discussed in exercises

VLSI I From Architectures to VLSI circuits and FPGAs 13


Exercises

§ A unique feature of this class, do not miss it


§ Not many universities can manage this level of exercises
§ Allows you to apply what you learn in class to practice.
§ Exam questions may come from topics discussed during exercises

§ Changes this year


§ New introductory exercise
§ Revised exercise flow to better match the timeline of accompanying
chip projects
§ Starts on Wednesday in computer labs ETZ D61

§ Florian will give more details


VLSI I From Architectures to VLSI circuits and FPGAs 14
Projects and continuation

§ Following this lecture will enable you to


§ expand your knowledge from FPGA design to ASIC design
§ work on ASIC designs in semester/master theses
§ VLSI III is about the economics and testing of ASICs
§ Can be attended before or after VLSI II
§ Is not mandatory to visit VLSI III for an ASIC design project

VLSI I From Architectures to VLSI circuits and FPGAs 15


Goals of VLSI II Exercises

§ You will learn the basics of implementing digital


integrated circuits with hands-on exercises
using state-of-the-art industry tools.

§ The focus is on turning digital circuit netlists into


a safe, testable and manufacturable mask
layout.

VLSI I From Architectures to VLSI circuits and FPGAs 16


Are the exercises worth my time?

§ The exercises are not mandatory, but described


by alumni from various fields of EE as very
relevant and helpful for their day job.

§ Your coaches during the exercises daily apply


the skills and use the tools you are learning, so
they are able to help you efficiently and
individually.

§ You can choose your pace yourself.


VLSI I From Architectures to VLSI circuits and FPGAs 17
How do I make the most of the exercises?

§ Come to the exercise classes:


Wednesdays, 09:15 to 12:00 in ETZ D 61.1/2
(computer rooms)

§ Be active: exercises are designed in a hands-on


tutorial style that require you to think and work.

VLSI I From Architectures to VLSI circuits and FPGAs 18


Exercise schedule I

No Topic
0 Synthesis and Simulation Flow
1 Practical Interfaces and Chip I/O
2 Introduction to Innovus
Foundation
3 Padring and Floorplanning
4 Design Review (theoretical exercises)
5 Timing
6 Power Analysis
Core
7 Power Distribution

VLSI I From Architectures to VLSI circuits and FPGAs 19


Exercise schedule II

No Topic
8 Placement and Routing Flow Core
9 Testing (theoretical)
10 Scan Insertion Testing /
11 Chip Finishing / Signoff DFM
12 Physical Verification

VLSI I From Architectures to VLSI circuits and FPGAs 20


Further Information

§ Task sheets available on vlsi2.ethz.ch


(only accessible within the ETH network)

§ Contact for further questions:


[email protected]

§ We will answer single questions by e-mail, but we


cannot provide you the guidance you get when
participating in the exercise classes.

VLSI I From Architectures to VLSI circuits and FPGAs 21


So be there!

See you Wednesday at 09:15


in ETZ D 61.1/2!

VLSI I From Architectures to VLSI circuits and FPGAs 22

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