VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING

QUESTION BANK

VI SEMESTER

CS6303-COMPUTER ARCHITECTURE

Regulation – 2013

Academic Year 2018 – 19

Prepared by

Mr. G. Kumaresan, Assistant professor/CSE

Ms. S. Shanthi, Assistant Professor/CSE
Mr. S. Venkatesh, Assistant professor/CSE
Ms. M. Priyadharshini, Assistant professor/CSE
 VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar , Kattankulathur-603203

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

SUBJECT : CS6303 COMPUTER ARCHITECTURE

SEM/YEAR: VI/III
UNIT I -OVERVIEW & INSTRUCTIONS
Eight ideas – Components of a computer system – Technology – Performance – Power wall – Uniprocessors
to multiprocessors; Instructions – operations and operands – representing instructions – Logical operations –
control operations – Addressing and addressing modes
PART-A
Q.No Questions BT Competence
Level
1 Express the equation for the dynamic power required per BTL 2 Understanding
transistor.
2 Identify general characteristics of Relative addressing mode with BTL 4 Analyzing
an example.
3 List the eight great ideas invented by computer architects. BTL 1 Remembering
4 Tabulate are the components of computer system. BTL 1 Remembering
5 Distinguish Pipelining from Parallelism. BTL 2 Understanding
6 Interpret the various instructions based on the operations they BTL 2 Understanding
perform and give one example to each category.
7 Differentiate DRAM and SRAM. BTL 4 Analyzing
8 Give the highest performance expressed in instructions per BTL 2 Understanding
second by considering the following:
processors Clock Rates CPI
P1 3 Ghz 1.5
P2 2.5 Ghz 1.0
P3 4.0Ghz 2.2
9 What is meant by VLSI? BTL 1 Remembering
10 Calculate throughput and response time. BTL 3 Applying
11 Compose the CPU performance equation. BTL 6 Creating
12 Measure the performance of the computers: BTL 5 Evaluating
If computer A runs a program in 10 seconds, and computer B
runs the same program in 15 seconds, how much faster is A over
B?
13 Formulate the equation of CPU execution time for a program. BTL 6 Creating
14 State the need for indirect addressing mode. Give an example. BTL 1 Remembering
15 Show the formula for CPU clock cycles required for a program. BTL 3 Applying
16 Define Stored Program Concept. BTL 1 Remembering
17 Name the different addressing modes. BTL 1 Remembering
18 Compare multi-processor and uniprocessor. BTL 4 Analyzing
19 Illustrate relative addressing mode with example. BTL 3 Applying
20 Consider the following performance measurements for a program BTL 5 Evaluating
Measurement Computer A Computer B
Instruction 10 billion 8 billion
Count
Clock rate 4GHz 4GHz
CPI 1.0 1.1
Which computer has the higher MIPS rating
PART B
1 i).Summarize the eight great ideas of computer Architecture. (7) BTL 5 Evaluating
ii). Explain the technologies for Building Processors. (6)
2 List the various components of computer system and explain (13) BTL 1 Remembering
with neat diagram.
3 i).Define addressing mode. (4) BTL 1 Remembering
ii).Describe the basic addressing modes for MIPS and give one
suitable example instruction to each category. (9)
4. i). Identify the three broad classes of applications of computers. (6) BTL 1 Remembering
ii). Examine the operands and operations of computer hardware. (7)
5 i).Discuss the logical operations and control operations of (7) BTL 2 Understanding
computer.
ii). Express the concept of Powerwall processor. (6)
6 Consider three different processors P1, P2, and P3 executing the BTL 4 Analyzing
same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5.
P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz
clock rate and has a CPI of 2.2.
i).Which processor has the highest performance expressed in (3)
instructions per second?
ii).If the processors each execute a program in 10 seconds, find (5)
the number of cycles and the number of instructions?
iii).We are trying to reduce the execution time by 30% but this (5)
leads to an increase of 20% in the CPI. What clock rate should
we have to get this time reduction?
7 Assume a program requires the execution of 50 × 106 FP BTL 3 Applying
instructions,110 × 106 INT instructions, 80 × 106 L/S
instructions, and 16 × 106 branch instructions The CPI for each
type of instruction is 1, 1, 4, and 2, respectively. Assume that the
processor has a 2 GHz clock rate.
i).By how much must we improve the CPI of FP instructions if (4)
we want the program to run two times faster?
ii).By how much must we improve the CPI of L/S instructions? (4)
iii).By how much is the execution time of the program improved (5)
if the CPI of INT and FP Instructions are reduced by 40% and
the CPI of L/S and Branch is reduced by 30%?
8 Recall the branching operations in detail with suitable example. (13) BTL 2 Understanding
9 i).Formulate the performance of CPU. (9) BTL 6 Creating
ii).Compose the factors that affect performance. (4)
10 i).Illustrate the following sequence of instructions and identify (7) BTL 3 Applying
the addressing modes used and the operation done in every
instruction
(1) Move (R5)+, R0
(2) Add(R5)+, R0
(3) Move R0, (R5)
(4) Move 16(R5),R3
(5) Add #40, R5
ii).Calculate which code sequence will execute faster according (6)
to execution time for the following conditions:
Consider the computer with three instruction classes and CPI
measurements as given below and instruction counts for each
instruction class for the same program from two different
compilers are given. Assume that the computer’s clock rate is
1GHZ.
Code from CPI for the instruction class
A B C
CPI 1 2 3
Code from CPI for the instruction class
A B C
Compiler1 2 1 2
Compiler2 2 1 1
11 Consider two different implementation of the same instruction (13) BTL 1 Remembering
set architecture, The instruction can be divided into four classes
according to their CPI ( class A,B,C and D). P1 with clock rate
2.5 Ghz and CPI s of 1,2,3, and 3 respectively and P2 with clock
rate 3 Ghz and CPI s of 2,2,2and 2 respectively. Given a
program with a dynamic instruction count of 1.0*106 instruction
divided into classes as follows: 10% class A, 20% class B, 50%
class C, and 20% class D, which implementation is faster? What
is the global CPI for each implementation? Find the clock cycles
required in both cases.
12 i).Compare uni-processors and multi- processors. (8) BTL 4 Analyzing
ii).Suppose we develop a new simpler processor that has 85% of (5)
the capacitive load of the more complex older processor. Further
assume that it has adjustable voltage so that it can reduce voltage
15% compressed to processor B, which results in a 15%
compressed to processor B, which results in a 15% shrink in
frequency. Point out the impact on dynamic power?
13 Analyze the various instruction formats and illustrate with an (13) BTL 4 Analyzing
example.
14 (i)With suitable examples, Summarize the compilation of (8) BTL 2 Understanding
assignment statements into MIPS.
(ii)Translate the following C code to MIPS assembly code .Use a (5)
minimum number of instructions. Assume that I and k
correspond to register $s3 and $s5 and the base of the array save
 is in $s6.What is the MIPs assembly code corresponding to this
is C segment
While(save[i]==k)
i+=1;
PART C
1 Evaluate a MIPS assembly instruction in to a machine (15) BTL 5 Evaluating
instruction, for the add $to, $s1,$s2 MIPS instruction.
2 Integrate the eight ideas from computer architecture to the BTL 6 Creating
following ideas from other fields:
i).Assembly lines in automobile manufacturing. (5)
ii). Express elevators in buildings. (5)
iii).Aircraft and marine navigation systems that incorporate wind (5)
information.
3 Assume that the variables f and g are assigned to register $s0 and (15) BTL 6 Creating
$s1 respectively. Assume that base address of the array A is in
register $s2. Assume f is zero initially.
f- -g – A[4]
A[5]=f + 100
Translate the above C statement into MIPS code . how many
MIPS assembly instructions are needed to perform the C
statements and how many different registers are needed to carry
out the C statements ?
4 Explain the steps that transform a program written in a high level (15) BTL 5 Analyzing
language such as C into a representation that is directly executed
by a computer processor.
UNIT II -ARITHMETIC OPERATIONS
ALU – Addition and subtraction – Multiplication – Division – Floating Point operation -Sub word
parallelism.
PART-A
Q.No Questions BT Competence
Level
1 Calculate the following: BTL 3 Applying
Add 510 to 610 in binary and Subtract -610 from 710 in binary.
2 Analyze overflow conditions for addition and subtraction. BTL 4 Analyzing
3 Construct the Multiplication hardware diagram. BTL 3 Applying
4 List the steps of multiplication algorithm. BTL 1 Remembering
5 What is meant by ALU fast multiplication? BTL 1 Remembering
6 Subtract (11011) 2 – (10011) 2 using 1’s complement and 2’s BTL 2 Understanding
complement method.
7 Illustrate scientific notation and normalization with example. BTL 3 Applying
8 Perform X-Y using 2’s complement arithmetic for the given two BTL 4 Analyzing
16-bit numbers X=0000 1011 1110 1111 and Y=1111 0010 1001
1101.
9 Contrast overflow and underflow with examples. BTL 2 Understanding
10 For the following C statement, Develop MIPS assembly code. BTL 6 Creating
f = g + (h − 5).
11 Name the floating point instructions in MIPS. BTL 1 Remembering
12 Formulate the steps of floating point addition. BTL 6 Creating
13 Evaluate the sequence of floating point multiplication. BTL 5 Evaluating
14 Define guard bit. What are the ways to truncate the guard bits? BTL 1 Remembering
15 Express the IEEE 754 floating point format. BTL 2 Understanding
16 State sub-word parallelism and the data path in CPU. BTL 1 Remembering
17 Interpret single precision floating point number representation with BTL 2 Understanding
example and the representation of double precision floating point
number.
18 Divide 1,001,010 by 1000. BTL 4 Analyzing
19 Label the steps of division algorithm. BTL 1 Remembering
20 For the following MIPS assembly instructions above, decide the BTL 5 Evaluating
corresponding C statement? add f, g, h & add f, i, f
PART-B
1 i).Discuss the multiplication algorithm its hardware and its (6) BTL 2 Understanding
sequential version with diagram.
ii).Express the steps to Multiply 2*3. (7)
2 Illustrate the multiplication of signed 2’s complement numbers? BTL 3 Applying
Give Booth’s algorithm and example (13)
3 Describe about basic concepts of ALU design. (13) BTL 1 Remembering
4 Develop algorithm to implement A*B. Assume A and B for a pair (13) BTL 6 Creating
of signed 2’s complement numbers with values: A=010111,
B=101100
5 i) .State the division algorithm with diagram and examples. (6) BTL 1 Remembering
ii).Divide 00000111 by 0010. (7)
6 i).Express in detail about Carry looks ahead Adder. (8) BTL 2 Understanding
ii).Divide(12)10 by (3)10 (7)
7 Point out the division of A and B (13) BTL 4 Analyzing
A=1111 B= 0011
8 i).Examine, how floating point addition is carried out in a (4) BTL 1 Remembering
computer system?
ii).Give an example for a binary floating point addition. (5)
iii)Examine Non Restoring Division with an example. (4)
9 Tabulate the IEEE 754 binary representation of the number- BTL 1 Remembering
0.75 10
i).Single precision. (6)
ii).Double precision. (7)
10 i).Design an arithmetic element to perform the basic floating (7) BTL 2 Understanding
point operations.
ii).Discuss sub word parallelism. (6)
11 i).Explain floating point addition algorithm with diagram. (6) BTL 5 Evaluating
ii). Assess the result of the numbers (0.5)10 and (0.4375)10 using (7)
binary Floating point Addition algorithm.
12 Calculate using single precision IEEE 754 representation. BTL 4 Analyzing
i). 32.75 (6)
ii).18.125 (7)
13 Arrange the given number 0.0625 BTL 4 Analyzing
i). Single precision. (6)
ii). Double precision formats. (7)
14 Solve using Floating point multiplication algorithm BTL 3 Applying
i).A= 1.10 10 X 1010 B= 9.200X10-5 (7)
ii). 0.5 10 X 0.4375 10 (6)
 PART C
1 Create the logic circuit for CLA. What are the disadvantages of BTL 6 Creating
Ripple carry addition and how it is overcome in carry look ahead (15)
adder?
Evaluate the sum of 2.6125 * 101 and 4.150390625 * 101 by (15) BTL 5 Evaluating
hand, assuming A and B are stored in the 16-bit half precision.
2. Assume 1 guard, 1 round bit and 1 sticky bit and round to the
nearest even. Show all the steps.
3 Summarize 4 bit numbers to save space, which implement the (15) BTL 5 Evaluating
multiplication algorithm for 00102 , 00112 with hardware design.
4 Design 4 bit version of the algorithm to save pages, for dividing (15) BTL 6 Creating
000001112 by 00102 with hardware design.
UNIT III-PROCESSOR AND CONTROL UNIT
Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining – Pipelined
datapath and control – Handling Data hazards & Control hazards – Exceptions.
PART-A
Q.No Questions BT Competence
Level
1 Express the control signals required to perform arithmetic BTL 2 Understanding
operations.
2 Define hazard. Give an example for data hazard. BTL 2 Understanding
3 Recall pipeline bubble. BTL 1 Remembering
4 List the state elements needed to store and access an instruction. BTL 1 Remembering
5 Draw the diagram of portion of data path used for fetching BTL 2 Understanding
instruction and state data path in a CPU
6 Distinguish Sign Extend and Vector interrupts. BTL 2 Understanding
7 Name the R-type instructions. BTL 1 Remembering
8 Evaluate branch taken and branch not taken in instruction BTL 5 Evaluating
execution.
9 State the ideal CPI of a pipelined processor. BTL 1 Remembering
10 Design the instruction format for the jump instruction. BTL 6 Creating
11 Classify the different types of hazards with examples. BTL 4 Analyzing
12 Illustrate data forwarding method to avoid data hazards. BTL 3 Applying
13 Assess the methods to reduce the pipeline stall. BTL 5 Evaluating
14 Tabulate the use of branch prediction buffer. BTL 1 Remembering
15 Show the 5 stages pipeline. BTL 3 Applying
16 Point out the concept of exceptions.Give one example of MIPS BTL 4 Analyzing
exception.
17 What is pipelining? BTL 1 Remember
18 Illustrate the two steps that are common to implement any type of BTL 3 Applying
instruction.
19 Classify the types of instruction classes and their formats. BTL 4 Analyzing
20 Generalize Exception. Give one example for MIPS exception. BTL6 Creating
PART-B
1 Discuss the basic MIPS implementation of instruction set. (13) BTL 2 Understanding
2 i) State the MIPS implementation in detail with necessary (7) BTL 1 Remembering
multiplexers and control lines.
ii) Examine and draw a simple MIPS datapath with the control
unit and the execution of ALU instructions. (6)
3 i).List the types of hazards. (3) BTL 1 Remembering
ii).Describe the methods for dealing with the control hazards. (10)
4 Design and develop an instruction pipeline working under various (13) BTL 6 Creating
situations of pipeline stall.
5 i).What is data hazard? How do you overcome it? (8) BTL 1 Remembering
ii).What are its side effects? (5)
6 i).Summarize control implementation scheme. (9) BTL 2 Understanding
ii).Distinguish the data and control path methods in pipelining. (4)
7 i).Differentiate sequential execution and pipelining. (7) BTL 4 Analyzing
ii).Select the model for building a data path. (6)
8 Recommend the techniques for BTL 5 Evaluating
i).Dynamic branch prediction. (7)
ii).Static branch prediction. (6)
9 Examine the approaches would you use to handle exceptions in (13) BTL 3 Applying
MIPS.
10 i).Analyze the hazards caused by unconditional branching (7) BTL 4 Analyzing
statements and pipelining a processor using an example.
ii).Describe operand forwarding in a pipeline processor with a (6)
diagram.
11 Express the simple data path with control unit and modified data (13) BTL 2 Understanding
path to accommodate pipelined executions with a diagram.
12 i).Explain single cycle and pipelined performance with examples. (7) BTL 4 Analyzing
ii).Point out the advantages of pipeline over single cycle and (6)
limitations of pipelining a processor’s datapath. Suggest the
methods to overcome the later part
13 i) Tabulate the ALU control with suitable truth table. (8) BTL 1 Remembering
ii) Differentiate R-type instruction and memory instruction. (5)
14 With a suitable set of sequence of instructions show what happens (13) BTL 3 Applying
when the branch is taken, assuming the pipeline is optimized for
branches that are not taken and that we moved the branch
execution to the ID stage.
PART C
1 Assume the following sequence of instructions are executed on a BTL6 Creating
5 stage pipelined processor
Or r1,r2,r3
Or r2,r1,r4
Or r1,r1,r2
i) Indicate dependences and their type. (5)
ii) Assume there is no forwarding in this pipelined processor. (5)
Indicate hazards and add NOP instructions to eliminate them.
iii) Assume there is a full forwarding .Indicate hazard and add (5)
NOP instructions to eliminate them.

2 Explain and compare the hardwired and microprogrammed (15) BTL 5 Evaluating
control unit designs in terms of their mechanism of generating
control signals with diagram.
3 Consider the following loop: BTL 5 Evaluating
Loop: lw r1,0(r1)
and r1,r1,r2
lw r1,0(r1)
 lw r1,0(r1)
beq r1,r0,loop
Assume that perfect branch prediction is used (no stalls) that there
are no delay slots, and that the pipeline has full forwarding
support. Also assume that many iterations of this loop are
executed before the loop exits.
i).Assess a pipeline execution diagram for the third iteration of (8)
this loop.
ii).Show all instructions that are in the pipeline during these (7)
cycles (for all iterations).
4 Plan the pipelining in MIPS architecture and generate the (15) BTL 6 Creating
exceptions handled in MIPS.
UNIT IV-PARALLELISM
Instruction-level-parallelism – Parallel processing challenges – Flynn’s classification –
Hardware multithreading – Multicore processors
PART-A
Q.No Questions BT Competence
Level
1 Describe the main idea of ILP. BTL 2 Understanding
2 Illustrate how to organize a multiple issue processor? BTL 3 Applying
3 List the three important properties of vector instructions. BTL 1 Remembering
4 Analyze the main characteristics of SMT processor. BTL 4 Analyzing
5 Quote the importance of loop unrolling technique. BTL 1 Remembering
6 Define VLIW processor. BTL 1 Remembering
7 Express anti-dependence. How is it removed? BTL 2 Understanding
8 State the overall speedup if a webserver is to be enhanced with a BTL 1 Remembering
new CPU which is 10 times faster on computation than an old
CPU .The original CPU spent 40% of its time processing and
60% of its time waiting for I/O.
9 Differentiate between strong scaling and weak scaling. BTL 2 Understanding
10 Show the performance of cluster organization. BTL 3 Applying
11 Compare SMT and hardware multithreading. BTL 5 Evaluating
12 Identify the Flynn classification and give an example for each BTL 1 Remembering
class in Flynn’s classification.
13 Integrate the ideas of in-order execution and out-of-order execution. BTL 6 Creating
14 Discriminate UMA and NUMA. BTL 5 Evaluating
15 Describe fine grained multithreading. BTL 1 Remembering
16 Express the need for instruction level parallelism. BTL 2 Understanding
17 Formulate the various approaches to hardware multithreading. BTL 6 Creating
18 Categorize the various multithreading options. BTL 4 Analyzing
19 Compare fine grained multithreading and coarse grained BTL 4 Analyzing
multithreading.
20 Classify shared memory multiprocessor based on the memory BTL 3 Applying
access latency.
PART-B
1 i).Define parallelism and its types. (4) BTL 1 Remembering
ii).List the main characteristics and limitations of Instruction level (9)
parallelism.
2 i).Give the software and hardware techniques to achieve Instruction (4) BTL 2 Understanding
level parallelism.
ii).Summarize the facts or challenges faced by parallel processing in (9)
enhancing computer architecture.
3 Express in detail about hardware multithreading. (13) BTL 2 Understanding
4 Solve: suppose you want to achieve a speed up to 90 times faster (13) BTL 3 Applying
with 100 processors. What percentage of the original computation
can be sequential?
5 Describe data level parallelism in BTL 1 Remembering
i).SIMD. (6)
ii).MISD. (7)
6 i).Point out how will you classify shared memory multi-processor BTL 4 Analyzing
based on memory access latency. (7)
ii).Compare and contrast Fine grained, Coarse grained multithreading
and Simultaneous Multithreading. (8)
7 Evaluate the features of Multicore processors. (13) BTL 5 Evaluating
8 i).Classify the types of multithreading. (9) BTL 4 Analyzing
ii).Analyze the advantages in multithreading. (4)
9 Formulate the classes in Flynn’s Taxonomy of computer (13) BTL 6 Creating
Architecture classification.
10 Elaborate in detail about the following
i).SISD. (8) BTL 1 Remembering
ii).MIMD (5)
11 Explain simultaneous Multithreading with example. (13) BTL 4 Analyzing
12 Describe the four principle approaches to multithreading with (13) BTL 1 Remembering
necessary diagrams.
13 Illustrate the following in detail BTL 3 Applying
i).Data Dependence (5)
ii).Name Dependence (4)
iii).Control dependence (4)
14 Discuss the following in detail BTL 2 Understanding
i). Vector processor. (7)
ii).Superscalar processor. (6)
PART C
1 Explain how would this loop be scheduled on a static two issue (15)
pipeline for MIPS?
Loop: lw $t0,0($s1) #$t0=array element
Addu $t0,$t0,$s2 #add scalar in $s2
Sw $t0, 0($s1) # store result
BTL 6 Creating
Addi; %s1,$s1, -4#decrement pointer
Bne $s1,$zero,loop # branch $s1!=0
Decide and reorder the instruction to avoid as many pipeline stalls
as possible. Assume branches are predicted, so that control
hazards are handled by the hardware.
2 A pipelined processor uses delayed branch technique. (15)
Recommend any one of the following possibility for the design of
the processor. In the first possibility, the processor has a 4-satge BTL 5 Evaluating
pipeline and one delay slot. In the second possibility, it has a 6-
stage pipeline and two delay slots. Compare the performance of
 these two alternatives, taking only the branch penalty into
account. Assume that 20% of the instructions are branch
instructions and that an optimizing compiler has an 80% success
rate in filling in the single delay slot. For the second alternative,
the compiler is able to fill the second slot 25% of the time.
3 Consider the following portions of two different programs BTL 6 Creating
running at the same time on four processors in a symmetric
multicore processor (SMP). Assume that before this code is run,
both x and y are 0?
Core 1: x=2;
Core 2: y=2;
Core 3: w= x + y +1;
Core 4: z= x + y;
i. What if all the possible resulting values of w,x,y,z ? For each (8)
possible outcomes, explain how we might arrive at those values.
ii. Develop the execution more deterministic so that only one set (7)
of values is possible?
4 Suppose we want to perform 2 sums: one is a sum of 10 scalar (15) BTL 6 Creating
variables and one is a matrix sum of a pair of two dimensional
arrays, with dimensions 10 by 10. For now let’s assume only the
matrix sum is parallelizable. What if the speed up do you get with
10 versus 40 processors and next calculate the speed ups
assuming the matrices grow to 20 by 20.
UNIT V-MEMORY AND I/O SYSTEMS
Memory hierarchy – Memory technologies – Cache basics – Measuring and improving cache performance –
Virtual memory, TLBs – Input/output system, programmed I/O, DMA and interrupts, I/O processors.
PART-A
Q.No Questions BT Competence
Level
1 Distinguish the types of locality of references. BTL 2 Understanding
2 Define the structure of memory hierarchy in a typical computer BTL 1 Remembering
system and draw its diagram.
3 Give the idea of address mapping and memory –mapped I/O. BTL 2 Understanding
4 Compare and contrast SRAM and DRAM. BTL 4 Analyzing
5 What is the need to implement memory as a hierarchy? BTL 1 Remembering
6 Describe Rotational Latency. BTL 1 Remembering
7 State is direct-mapped cache. BTL 1 Remembering
8 Evaluate the following instance wherein the cache size is 64 BTL 5 Evaluating
blocks and block size is 16 bytes. What block number does byte
address 1200 map?
9 Formulate, how many total bits are required for a direct-mapped BTL 6 Creating
cache with 16 KB of data and 4-word blocks, assuming a 32-bit
address?
10 Analyze the writing strategies in cache memory. BTL 4 Analyzing
11 Integrate the functional steps required in an instruction cache BTL 6 Creating
miss.
12 State hit rate and miss rate. BTL 1 Remembering
13 Summarize the various block placement schemes in cache BTL 2 Understanding
memory.
14 Identify the purpose of Dirty/Modified bit in Cache memory. BTL 1 Remembering
15 Point out the use of DMA controller? BTL 4 Analyzing
16 Show the role of TLB in virtual memory. BTL 3 Applying
17 Illustrate the advantages of virtual memory. BTL 3 Applying
18 Assess the relationship between physical address and logical BTL 5 Evaluating
address.
19 Differentiate Programmed I/O and Interrupt I/O. BTL 2 Understanding
20 Demonstrate the sequence of events involved in handling an BTL 3 Applying
interrupt request from a single device.
PART-B
1 i).List the various memory technologies and examine its (8) BTL 1 Remembering
relevance in architecture design.
ii). Identify the characteristics of memory system. (5)
2 Elaborate in detail the memory hierarchy with neat diagram. (13) BTL 1 Remembering
3 i).Give the advantages of cache. (4) BTL 2 Understanding
ii).Identify the basic operations of cache in detail with diagram. (9)
4 Express the need for cache memory. Explain the following three BTL 2 Understanding
mapping methods with examples.
i). Direct. (4)
ii).Associative. (4)
iii).Set associative. (5)
5 i). Analyze the given problem: (8)
A byte addressable computer has a small data cache capable of BTL 4 Analyzing
holding eight 32-bit words. Each cache block contains 132-bit
word. When a given program is executed, the processor reads
data from the following sequence of hex addresses – 200, 204,
208, 20C, 2F4, 2F0, 200,204,218, 21C, 24C, 2F4. The pattern is
repeated four times. Assuming that the cache is initially empty,
show the contents of the cache at the end of each pass, and
compute the hit rate for a direct mapped cache.
ii).What are the methods used to measure and improve the (5)
performance of the cache?
6 i).Define virtual memory and its importance. (5) BTL 1 Remembering
ii).Examine TLB with necessary diagram .What is its use? (8)
7 i).Demonstrate the DMA controller. Discuss how it improves the (4) BTL 3 Applying
overall performance of the system.
ii).Illustrate how DMA controller is used for direct data transfer (9)
between memory and peripherals?
8 i).Evaluate the advantages of interrupts. (5) BTL 5 Evaluating
ii).Summarize the concept of interrupts and interrupts handling
with neat diagrams. (8)
9 Design standard input and output interfaces required to connect (13) BTL 6 Creating
the I/O device to the bus.
10 Classify the bus arbitration techniques of DMA in detail. (13) BTL 4 Analyzing
11 Point out the following in detail BTL 4 Analyzing
i). Programmed I/O associated with computers. (7)
ii).Write the sequence of operations carried out by a processor when(6)
interrupted by peripheral device connected to it.
12 Describe in detail about the methods used to reduce cache misses. (13) BTL 1 Remembering
13 Discuss virtual memory address translation in detail with (13) BTL 2 Understanding
necessary diagram.
14 Calculate the performance the processor : (13) BTL 3 Applying
Assume the miss rate of an instruction cache is 2% and the miss
rate of the data cache is 4%. If a processor has a CPI of 2 without
any memory stalls and the miss penalty is 100 cycles for all
misses, estimate how much faster a processor would run with a
perfect cache that never missed. Assume the frequency of all
loads and stores is 36%.
PART C
1 Mean Time Between Failures (MTBF), Mean Time To
Replacement (MTTR) and Mean Time To Failure (MTTF) are
useful metrics for evaluating the reliability and availability of a
storage resource. Explore these concepts by answering the
questions about devices with the following metrics:
BTL 6 Creating
MTTF : 3 years MTTR: 1 day
i). Develop and calculate the MTBF for each of the devices. (3)
ii).Develop and calculate the availability for each of the devices. (4)
iii).What if happens to availability as the MTTR approaches 0? (4)
iv).What if happens to availability as the MTTR gets very high? (4)
2 Design and explain parallel priority interrupt hardware for a (15)
BTL 6 Evaluating
system with eight interrupt sources.
3 For a direct mapped cache design with a 32 bit address, the BTL 5 Evaluating
following bits of the address are used to access the cache.
Tag : 31-10 Index: 9-5 Offset: 4-0
i). Judge what is the cache block size? (5)
ii).Decide how many entries does the cache have? (5)
iii).Assess what is the ratio between total bits required for such a (5)
cache implementation over the data storage bits?
4 Summarize by considering web application .Assuming both client (15) BTL 5 Evaluating
and servers are involved in the process of web browsing
application, where can caches be placed to speed up the process.
Design a memory hierarchy for the system. Show the typical size
and latency at various levels of the hierarchy. What is the
relationship between the cache size and its access latency? What
are the units of data transfers between hierarchies? What id the
relationship between data location, data size and transfer latency?