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HDLSS Numerical Assignments - DOC Format

This document contains two numerical assignments related to HDLSS (Hardware Description Language Synthesis and Simulation). The first assignment asks students to calculate setup and hold slacks for different flip-flop configurations and find the maximum clock frequency. It also asks students to draw waveform diagrams for a circuit output under different input conditions. The second assignment provides component delay specifications for a circuit that implements the function Y=A+B on an FPGA board. It asks students to calculate path delays, identify the critical path, determine the minimum time to get a valid output, and draw a waveform diagram. Students are instructed to submit their answers via a provided link.

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Nikhil Upadhyay
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125 views

HDLSS Numerical Assignments - DOC Format

This document contains two numerical assignments related to HDLSS (Hardware Description Language Synthesis and Simulation). The first assignment asks students to calculate setup and hold slacks for different flip-flop configurations and find the maximum clock frequency. It also asks students to draw waveform diagrams for a circuit output under different input conditions. The second assignment provides component delay specifications for a circuit that implements the function Y=A+B on an FPGA board. It asks students to calculate path delays, identify the critical path, determine the minimum time to get a valid output, and draw a waveform diagram. Students are instructed to submit their answers via a provided link.

Uploaded by

Nikhil Upadhyay
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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HDLSS Numerical Assignment

PG-DVLSI August 2019 Batch

Assignment 1

Q1. Find out Setup Slack and Hold Slack if U1 is the Launch Flip-Flop and U2 is the capture Flip-Flop.
Assume minimum path delays = 0 ns per path, maximum path delays = 1 ns per path, fclk = 1/(15 ns).

Q2. Find out Setup Slack and Hold Slack if U2 is the Launch Flip-Flop and U1 is the capture Flip-Flop.
Assume minimum path delays = 0 ns per path, maximum path delays = 1 ns per path, fclk = 1/(15 ns).

Q3. Find out the maximum possible clock frequency for the circuit.

Q4. Draw the waveform of output signal Y, assuming the following data:

 Neglect all the delays and violations.


 Clock frequency = 1/(50 ns)
 At t=0 ns in bits of both flip-Flop U1 and U2 are 0, and A = 0. CK is transiting from 0 to 1 (i.e.
posedge event).
 At t=200 ns, input A becomes 1.

Q5. Draw the waveform of output signal Y, assuming the following data:

 Consider all the delays and violations.


 Clock frequency = 1/(50 ns)
 At t=0 ns in bits of both flip-Flop U1 and U2 are 0, and A = 0. CK is transiting from 0 to 1 (i.e.
posedge event).
 At t=200 ns, input A becomes 1.

Assignment 2

A function Y = A+B is implemented on a Virtex-4 FPGA board. It required one CLB, the structure given is
as per above. The following information is given:

Physical Pin Delay (including Pin to Pad) 80 ns


I/O Pad Delay 150 ns
A I/O Pad to LUT Path Delay 17 ns
B I/O Pad to LUT Path Delay 43 ns
Pin Delay of LUT pin connected to A path 2 ns
Pin Delay of LUT pin connected to B path 3 ns
LUT functional Delay 12 ns
LUT to Y I/O Pad Delay 93 ns
Other delays (assume) 0 ns

Q1. Find out the following path delays

 A to Y
 B to Y

Q2. Find out the Critical Path of the circuit.


Q3. Find out the minimum time required for obtaining a valid output at Y if A and B are given to the chip
at the same time.

Q4. Draw the waveforms for the following test conditions:

 At t=0: A = 0, B =0, Y = 0.
 At t=10: A becomes 1.
 Consider all the delays and violations.

Link for submitting answers:

https://goo.gl/forms/YgbfFAa4g0XBhC102

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