Theory and Applications

1
(Chapters 1 thru 9)

Selector Guide 2

Data Sheets 3

Surface Mount
Package Information and 4
Tape and Reel Specifications

Outline Dimensions
5
and Leadform Options

Index and
6
Cross Reference
 Thyristor Data
This edition of the Thyristor Data Manual has been revised extensively to reflect our
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Although information in this book has been carefully checked, no responsibility for
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Previous Edition  1993
“All Rights Reserved” Printed in U.S.A.
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“Preferred devices” are listed in bold, italic in the Selector Guide section and are marked
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 Theory and Applications
(Chapters 1 thru 9)

Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Chapter 6: Applications . . . . . . . . . . . . . . . . . . . . . . . . 1.6–1
Chapter 1: Symbols and Terminology . . . . . . . . . . . 1.1–1 Phase Control with Thyristors . . . . . . . . . . . . . . . . . 1.6–1
Chapter 2: Theory of Thyristor Operation . . . . . . . . 1.2–1 Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6–2
Basic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2–1 Phase Control with Trigger Devices . . . . . . . . . . . . 1.6–9
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . 1.2–3 Cycle Control with Optically Isolated
False Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2–5 Triac Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6–12
Theory of SCR Power Control . . . . . . . . . . . . . . . . . 1.2–7 AC Power Control with Solid–State Relays . . . . . 1.6–17
Triac Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2–13 Triacs and Inductive Loads . . . . . . . . . . . . . . . . . . . 1.6–21
Methods of Control . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2–15 Inverse Parallel SCRs for Power Control . . . . . . . 1.6–23
Zero Point Switching Techniques . . . . . . . . . . . . . . 1.2–16 Interfacing Digital Circuits to Thyristor
Chapter 3: Thyristor Drivers and Triggering . . . . . 1.3–1 Controlled AC Loads . . . . . . . . . . . . . . . . . . . . . . . 1.6–25
Pulse Triggering of SCRs . . . . . . . . . . . . . . . . . . . . . 1.3–1 DC Motor Control with Thyristors . . . . . . . . . . . . . . 1.6–33
Effect of Temperature, Voltage and Loads . . . . . . . 1.3–5 Programmable Unijunction Transistor (PUT)
Using Negative Bias and Shunting . . . . . . . . . . . . . 1.3–7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6–37
Snubbing Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3–9 Silicon Bilateral Switch (SBS) Applications . . . . . 1.6–41
Using Sensitive Gate SCRs . . . . . . . . . . . . . . . . . . 1.3–11 Triac Zero–Point Switch Applications . . . . . . . . . . 1.6–44
Drivers: Programmable Unijunction AN982 — Applications of Zero Voltage Crossing
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3–15 Optically Isolated Triac Drivers . . . . . . . . . . . . . . . 1.6–49
Silicon Bilateral Switch . . . . . . . . . . . . . . . . . . . . . . 1.3–18 AN1045 — Series Triacs in AC High Voltage
Chapter 4: The SIDAC A New High Voltage Switching Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6–59
Bilateral Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4-1 AN1048 — RC Snubber Networks for Thyristor
Chapter 5: SCR Characteristics . . . . . . . . . . . . . . . . . 1.5–1 Power Control and Transient Suppression . . . . . 1.6–68
SCR Turn–Off Characteristics . . . . . . . . . . . . . . . . . 1.5–1 Chapter 7: Mounting Techniques for Thyristors . . 1.7–1
SCR Turn–Off Mechanism . . . . . . . . . . . . . . . . . . . . 1.5–1 Mounting Surface Considerations . . . . . . . . . . . . . . 1.7–2
SCR Turn–Off Time tq . . . . . . . . . . . . . . . . . . . . . . . . 1.5–1 Thermal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7–3
Parameters Affecting tq . . . . . . . . . . . . . . . . . . . . . . . 1.5–6 Insulation Considerations . . . . . . . . . . . . . . . . . . . . . 1.7–4
Characterizing SCRs for Crowbar Applications . . 1.5–10 Fastening Techniques . . . . . . . . . . . . . . . . . . . . . . . . 1.7–8
Switches as Line–Type Modulators . . . . . . . . . . . . 1.5–18 Insulated Packages . . . . . . . . . . . . . . . . . . . . . . . . . 1.7–12
Parallel Connected SCRs . . . . . . . . . . . . . . . . . . . . 1.5–23 Surface Mount Devices . . . . . . . . . . . . . . . . . . . . . . 1.7–13
RFI Suppression in Thyristor Circuits . . . . . . . . . . 1.5–27 Thermal System Evaluation . . . . . . . . . . . . . . . . . . 1.7–16
Chapter 8: Reliability and Quality . . . . . . . . . . . . . . . 1.8–1
Using Transient Thermal Resistance Data in
High Power Pulsed Thyristor Applications . . . . . . 1.8–1
Thyristor Construction . . . . . . . . . . . . . . . . . . . . . . . 1.8–15
In–Process Controls and Inspections . . . . . . . . . . 1.8–15
Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8–16
Stress Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8–17
Environmental Testing . . . . . . . . . . . . . . . . . . . . . . . 1.8–18
Chapter 9: Appendices . . . . . . . . . . . . . . . . . . . . . . NO TAG

i
 INTRODUCTION

Thyristors can take many forms, but they have certain thyristor has a very long service life and very fast turn on and
things in common. All of them are solid state switches which turn off times. Because of their fast reaction times,
act as open circuits capable of withstanding the rated voltage regenerative action and low resistance once triggered,
until triggered. When they are triggered, thyristors become thyristors are useful as power controllers and transient
low–impedance current paths and remain in that condition overvoltage protectors, as well as simply turning devices on
until the current either stops or drops below a minimum value and off. Thyristors are used to control motors, incandescent
called the holding level. Once a thyristor has been triggered, lights and many other kinds of equipment.
the trigger current can be removed without turning off the Although thyristors of all sorts are generally rugged, there
device. are several points to keep in mind when designing circuits
Silicon controlled rectifiers (SCRs) and triacs are both using them. One of the most important is to respect the
members of the thyristor family. SCRs are unidirectional devices’ rated limits on rate of change of voltage and current
devices where triacs are bidirectional. An SCR is designed to (dv/dt and di/dt). If these are exceeded, the thyristor may be
switch load current in one direction, while a triac is designed damaged or destroyed. On the other hand, it is important to
to conduct load current in either direction. provide a trigger pulse large enough and fast enough to turn
Structurally, all thyristors consist of several alternating the gate on quickly and completely. Usually the gate trigger
layers of opposite P and N silicon, with the exact structure current should be at least three times the rated gate trigger
varying with the particular kind of device. The load is applied current with a pulse rise time of less than 1 microsecond and
across the multiple junctions and the trigger current is a pulse width greater than 10 microseconds. Thyristors may
injected at one of them. The trigger current allows the load be driven in many different ways, including directly from
current to flow through the device, setting up a regenerative transistors or logic families, power control integrated circuits,
action which keeps the current flowing even after the trigger by optoisolated triac drivers, programmable unijunction
is removed. transistors (PUTs), silicon bilateral switches (SBSs), and
These characteristics make thyristors extremely useful in SIDACs. These and other design considerations are covered
control applications. Compared to a mechanical switch, a in this manual.

ii
 CHAPTER 1
SYMBOLS AND TERMINOLOGY

SYMBOLS
The following are the most commonly used schematic
symbols for thyristors:

name of device symbol

Silicon controlled A K
rectifier (SCR)
G

Triac MT2 MT1

Programmable unijunction
A K
transistor (PUT)
G

G
Silicon bilateral
MT1 MT2
switch (SBS)

Sidac MT1 MT2

Motorola Thyristor Device Data Theory and Applications

1.1–1
THYRISTOR TERMINOLOGY

The following terms are used in SCR and TRIAC specifications:

RATINGS
These ratings are defined as maximum values. Exceeding these values can result in permanent damage or device failure.

Terminology Symbol Definition

di/dt The maximum rate of change of current the device

will withstand.

FORWARD CURRENT RMS IT(RMS) The maximum value of on–state rms current the
device may conduct.

FORWARD PEAK GATE CURRENT IGM, IGFM The maximum gate current which may be applied to
the device to cause conduction.

PEAK FORWARD SURGE CURRENT ITSM The maximum allowable non–repetitive surge cur-
rent the device will withstand at a specified pulse
width.

AVERAGE ON–STATE CURRENT IT(AV) The maximum average on–state current the device
may conduct under stated conditions.

PEAK GATE POWER PGM The maximum instantaneous value of gate power
dissipation between gate and cathode terminal.

FORWARD AVERAGE GATE POWER PG(AV) The maximum allowable value of gate power,
averaged over a full cycle, that may be dissipated
between the gate and cathode terminal.

CIRCUIT FUSING CONSIDERATIONS I2t The maximum forward non–repetitive overcurrent

capability. Usually specified for one–half cycle of 60
Hz operation.

PEAK GATE VOLTAGE VGM The maximum peak value of voltage allowed be-
tween the gate and cathode terminal for any bias
condition.

PEAK GATE VOLTAGE FORWARD VFGM, VGFM The maximum peak value of voltage allowed be-
tween the gate and cathode terminals with these
terminals forward biased.

PEAK GATE VOLTAGE REVERSE VRGM, The maximum peak value of voltage allowed be-
VGRM tween the gate and cathode with these terminals
reverse biased.

PEAK REPETITIVE FORWARD BLOCKING VDRM The maximum allowed value of repetitive forward
VOLTAGE (SCR) voltage which may be applied and not switch the
SCR on.

PEAK REPETITIVE REVERSE BLOCKING VRRM The maximum allowed value of repetitive reverse
VOLTAGE (SCR) voltage which may be applied to the anode terminal.

PEAK REPETITIVE OFF–STATE VOLTAGE VDRM The maximum allowed value of repetitive off–state
(TRIAC) voltage which may be applied and not switch on the
triac.

Theory and Applications Motorola Thyristor Device Data

1.1–2
CHARACTERISTICS

Terminology Symbol Definition

PEAK FORWARD BLOCKING CURRENT (SCR) IDRM The maximum value of current which will flow at
VDRM and specified temperature.

PEAK REVERSE BLOCKING CURRENT (SCR) IRRM The maximum value of current which will flow at
VRRM and specified temperature.

PEAK BLOCKING CURRENT (TRIAC) IDRM The maximum value of current which will flow for
either polarity of VDRM and at specified temperature.

PEAK ON–STATE VOLTAGE VTM The maximum voltage drop across the terminals at
stated conditions.

GATE TRIGGER CURRENT IGT The maximum value of gate current required to
switch the device from the off state to the on state
under specified conditions.

GATE TRIGGER VOLTAGE VGT The gate dc voltage required to produce the gate
trigger current.

HOLDING CURRENT IH The value of forward anode current which allows the
device to remain in conduction. Below this value the
device will return to a forward blocking state at
prescribed gate conditions.

CRITICAL RISE OF OFF–STATE VOLTAGE dv/dt The minimum value of the rate of rise of forward
voltage which will cause switching from the off state
to the on state.

TURN–ON TIME (SCR) tgt The time interval between a specified point at the
beginning of the gate pulse and the instant when the
device voltage (current) has dropped to a specified
low value during the switching of an SCR from the off
state to the on state by a gate pulse.

TURN–OFF TIME (SCR) tq The time interval between the instant when the SCR
current has decreased to zero after external switch-
ing of the SCR voltage circuit and the instant when
the thyristor is capable of supporting a specified
wave form without turning on.

OPERATING JUNCTION TEMPERATURE TJ The junction temperature of the device as a result of

ambient and load conditions.

STORAGE TEMPERATURE Tstg The temperature at which the device may be stored
without harm.

CASE TEMPERATURE TC The temperature of the device case under specified

conditions.

AMBIENT TEMPERATURE TA The air temperature measured below a device in an

environment of substantially uniform temperature,
cooled only by natural air currents and not materially
affected by radiant and reflective surfaces.

Motorola Thyristor Device Data Theory and Applications

1.1–3
CHARACTERISTICS

Terminology Symbol Definition

THERMAL RESISTANCE, CASE–TO–AMBIENT RθCA The thermal resistance (steady–state) from the
device case to the ambient.

THERMAL RESISTANCE, JUNCTION–TO– RθJA The thermal resistance (steady–state) from the
AMBIENT semiconductor junction(s) to the ambient.

THERMAL RESISTANCE, JUNCTION–TO–CASE RθJC The thermal resistance (steady–state) from the
semiconductor junction(s) to a stated location on the
case.

THERMAL RESISTANCE, JUNCTION–TO– RθJM The thermal resistance (steady–state) from the
MOUNTING SURFACE semiconductor junction(s) to a stated location on the
mounting surface.

TRANSIENT THERMAL IMPEDANCE, ZθJA(t) The transient thermal impedance from the semicon-
JUNCTION–TO–AMBIENT ductor junction(s) to the ambient.

TRANSIENT THERMAL IMPEDANCE, ZθJC(t) The transient thermal impedance from the semicon-
JUNCTION–TO–CASE ductor junction(s) to a stated location on the case.

Theory and Applications Motorola Thyristor Device Data

1.1–4
 CHAPTER 2
THEORY OF THYRISTOR OPERATION

To successfully apply thyristors, an understanding of their because a triac may be considered as two parallel SCRs
characteristics, ratings, and limitations is imperative. In this oriented in opposite directions. Figure 2.1(a) shows the
chapter, significant thyristor characteristics, the basis of their schematic symbol for an SCR, and Figure 2.1(b) shows the
ratings, and their relationship to circuit design are discussed. P–N–P–N structure the symbol represents. In the two–tran-
Several different kinds of thyristors are shown in Table 2.1. sistor model for the SCR shown in Figure 2.1(c), the
Silicon Controlled Rectifiers (SCRs) are the most widely used interconnections of the two transistors are such that regen-
as power control elements; triacs are quite popular in lower erative action occurs. Observe that if current is injected into
current (under 40 A) ac power applications. Diacs, SUSs and any leg of the model, the gain of the transistors (if sufficiently
SBSs are most commonly used as gate trigger devices for high) causes this current to be amplified in another leg. In
the power control elements. order for regeneration to occur, it is necessary for the sum of
the common base current gains (α) of the two transistors to
exceed unity. Therefore, because the junction leakage
Table 2.1. Thyristor Types
currents are relatively small and current gain is designed to
*JEDEC Titles Popular Names, Types be low at the leakage current level, the PNPN device remains
Reverse Blocking Diode { Four Layer Diode, Silicon off unless external current is applied. When sufficient trigger
Thyristor { Unilateral Switch (SUS) current is applied (to the gate, for example, in the case of an
SCR) to raise the loop gain to unity, regeneration occurs and
Reverse Blocking Triode { Silicon Controlled Rectifier the on–state principal current is limited primarily by external
Thyristor { (SCR) circuit impedance. If the initiating trigger current is removed,
Reverse Conducting Diode { Reverse Conducting Four the thyristor remains in the on state, providing the current
Thyristor { Layer Diode level is high enough to meet the unity gain criteria. This
critical current is called latching current.
Reverse Conducting Triode { Reverse Conducting SCR
Thyristor In order to turn off a thyristor, some change in current must
occur to reduce the loop gain below unity. From the model, it
Bidirectional Triode Thyristor { Triac appears that shorting the gate to cathode would accomplish
* JEDEC is an acronym for the Joint Electron Device Engineering this. However in an actual SCR structure, the gate area is
Councils, an industry standardization activity co–sponsored by the only a fraction of the cathode area and very little current is
Electronic Industries Association (EIA) and the National Electrical diverted by the short. In practice, the principal current must
Manufacturers Association (NEMA). be reduced below a certain level, called holding current,
{ Not generally available. before gain falls below unity and turn–off may commence.
In fabricating practical SCRs and Triacs, a “shorted
emitter” design is generally used in which, schematically, a
Before considering thyristor characteristics in detail, a brief
resistor is added from gate to cathode or gate to MT1.
review of their operation based upon the common two–tran-
Because current is diverted from the N–base through the
sistor analogy of an SCR is in order.
resistor, the gate trigger current, latching current and holding
BASIC BEHAVIOR current all increase. One of the principal reasons for the
shunt resistance is to improve dynamic performance at high
The bistable action of thyristors is readily explained by temperatures. Without the shunt, leakage current on most
analysis of the structure of an SCR. This analysis is high current thyristors could initiate turn–on at high tempera-
essentially the same for any operating quadrant of triac tures.

Motorola Thyristor Device Data Theory and Applications

1.2–1
 Sensitive gate thyristors employ a high resistance shunt or the ability of a thyristor to support applied voltage is reduced
none at all; consequently, their characteristics can be altered and there is a certain value of gate current at which the
dramatically by use of an external resistance. An external behavior of the thyristor closely resembles that of a rectifier.
resistance has a minor effect on most shorted emitter Because thyristor turn–on, as a result of exceeding the
designs. breakover voltage, can produce high instantaneous power
dissipation non–uniformly distributed over the die area during
the switching transition, extreme temperatures resulting in
ANODE die failure may occur unless the magnitude and rate of rise of
ANODE principal current (di/dt) is restricted to tolerable levels. For
normal operation, therefore, SCRs and triacs are operated at
applied voltages lower than the breakover voltage, and are
GATE made to switch to the on state by gate signals high enough to
CATHODE assure complete turn–on independent of the applied voltage.
(a) P
IB1
ANODE IC1 N N
IC2
IB2 P P –
N
P
N
GATE
GATE P IK
N
(c)
V
CATHODE CATHODE Ig4 Ig3 Ig2 Ig1 = 0
(b)
Figure 2.2. Thyristor Characteristics Illustrating
Figure 2.1. Two–transistor analogy of an SCR: Breakover as a Function of Gate Current
(a) schematic symbol of SCR; (b) P–N–P–N structure
represented by schematic symbol; (c) two–transistor On the other hand, diacs and other thyristor trigger devices
model of SCR. are designed to be triggered by anode breakover. Neverthe-
less they also have di/dt and peak current limits which must
be adhered to.
Junction temperature is the primary variable affecting A triac works the same general way for both positive and
thyristor characteristics. Increased temperatures make the negative voltage. However since a triac can be switched on
thyristor easier to turn on and keep on. Consequently, circuit by either polarity of the gate signal regardless of the voltage
conditions which determine turn–on must be designed to polarity across the main terminals, the situation is somewhat
operate at the lowest anticipated junction temperatures, more complex than for an SCR.
while circuit conditions which are to turn off the thyristor or The various combinations of gate and main terminal
prevent false triggering must be designed to operate at the polarities are shown in Figure 2.3. The relative sensitivity
maximum junction temperature. depends on the physical structure of a particular triac, but as
Thyristor specifications are usually written with case a rule, sensitivity is highest in quadrant I and quadrant IV is
temperatures specified and with electrical conditions such generally considerably less sensitive than the others.
that the power dissipation is low enough that the junction
temperature essentially equals the case temperature. It is
incumbent upon the user to properly account for changes in MT2(+)
characteristics caused by the circuit operating conditions
QUADRANT II QUADRANT I
different from the test conditions.

TRIGGERING CHARACTERISTICS MT2(+), G(–) MT2(+), G(+)

Turn–on of a thyristor requires injection of current to raise
the loop gain to unity. The current can take the form of current
G(–) G(+)
applied to the gate, an anode current resulting from leakage, QUADRANT III QUADRANT IV
or avalanche breakdown of a blocking junction. As a result,
the breakover voltage of a thyristor can be varied or MT2(–), G(–) MT2(–), G(+)
controlled by injection of a current at the gate terminal. Figure
2.2 shows the interaction of gate current and voltage for an
SCR.
When the gate current Ig is zero, the applied voltage must MT2(–)
reach the breakover voltage of the SCR before switching
occurs. As the value of gate current is increased, however, Figure 2.3. Quadrant Definitions for a Triac

Theory and Applications Motorola Thyristor Device Data

1.2–2
 Gate sensitivity of a triac as a function of temperature is could flow in the load; therefore, some means usually must
shown in Figure 2.4. be provided to remove the gate signal during the reverse
blocking phase.
30
OFF–STATE VOLTAGE = 12 Vdc 300
IGT, GATE TRIGGER CURRENT (mA)

20 ALL QUADRANTS

IGTM , PEAK GATE CURRENT (mA)

OFF–STATE VOLTAGE = 12 V
100
70
10 50
30
7 TJ = – 55°C

5 25°C
1 10
QUADRANT 2 7
3 100°C
4 5
3
– 80 – 60 – 40 – 20 0 20 40 60 80 100 120 3
TJ, JUNCTION TEMPERATURE (°C) 0.2 0.5 1 2 5 10 20 50 100 200
PULSE WIDTH (µs)
Figure 2.4. Typical Triac Triggering Sensitivity in the
Four Trigger Quadrants Figure 2.5. Typical Behavior of Gate Trigger Current as
Pulse Width and Temperature Are Varied
Since both the junction leakage currents and the current
gain of the “transistor” elements increase with temperature,
the magnitude of the required gate trigger current decreases LATCH AND HOLD CHARACTERISTICS
as temperature increases. The gate — which can be In order for the thyristor to remain in the on state when the
regarded as a diode — exhibits a decreasing voltage drop as trigger signal is removed, it is necessary to have sufficient
temperature increases. Thus it is important that the gate principal current flowing to raise the loop gain to unity. The
trigger circuit be designed to deliver sufficient current to the principal current level required is the latching current, IL.
gate at the lowest anticipated temperature. Although triacs show some dependency on the gate current
It is also advisable to observe the maximum gate current, in quadrant II, the latching current is primarily affected by the
as well as peak and average power dissipation ratings. Also temperature on shorted emitter structures.
in the negative direction, the maximum gate ratings should In order to allow turn off, the principal current must be
be observed. Both positive and negative gate limits are often reduced below the level of the latching current. The current
given on the data sheets and they may indicate that level where turn off occurs is called the holding current, IH.
protective devices such as voltage clamps and current Like the latching current, the holding current is affected by
limiters may be required in some applications. It is generally temperature and also depends on the gate impedance.
inadvisable to dissipate power in the reverse direction. Reverse voltage on the gate of an SCR markedly
Although the criteria for turn–on have been described in increases the latch and hold levels. Forward bias on thyristor
terms of current, it is more basic to consider the thyristor as gates may significantly lower the values shown in the data
being charge controlled. Accordingly, as the duration of the sheets since those values are normally given with the gate
trigger pulse is reduced, its amplitude must be correspond- open. Failure to take this into account can cause latch or hold
ingly increased. Figure 2.5 shows typical behavior at various problems when thyristors are being driven from transistors
pulse widths and temperatures. whose saturation voltages are a few tenths of a volt.
The gate pulse width required to trigger a thyristor also Thyristors made with shorted emitter gates are obviously
depends upon the time required for the anode current to not as sensitive to the gate circuit conditions as devices
reach the latching value. It may be necessary to maintain a which have no built–in shunt.
gate signal throughout the conduction period in applications
where the load is highly inductive or where the anode current SWITCHING CHARACTERISTICS
may swing below the holding value within the conduction When triacs or SCRs are triggered by a gate signal, the
period. turn–on time consists of two stages: a delay time, td, and a
When triggering an SCR with a dc current, excess leakage rise time, tr, as shown in Figure 2.6. The total gate controlled
in the reverse direction normally occurs if the trigger signal is turn–on time, tgt, is usually defined as the time interval
maintained during the reverse blocking phase of the anode between the 50 percent point of the leading edge of the gate
voltage. This happens because the SCR operates like a trigger voltage and 90 percent point of the principal current.
remote base transistor having a gain which is generally about The rise time tr is the time interval required for the principal
0.5. When high gate drive currents are used, substantial current to rise from 10 to 90 percent of its maximum value. A
dissipation could occur in the SCR or a significant current resistive load is usually specified.

Motorola Thyristor Device Data Theory and Applications

1.2–3
 point where the principal current changes polarity to a
90% POINT
specified point on the reverse current waveform as indicated
PRINCIPAL in Figure 2.7. During this period the anode and cathode
VOLTAGE junctions are being swept free of charge so that they may
10% POINT support reverse voltage. A second recovery period, called
0 the gate recovery time, tgr, must elapse for the charge stored
in the forward–blocking junction to recombine so that
90% POINT
forward–blocking voltage can be reapplied and successfully
PRINCIPAL blocked by the SCR. The gate recovery time of an SCR is
CURRENT usually much longer than the reverse recovery time. The total
10% POINT
0 time from the instant reverse recovery current begins to flow
td tr
to the start of the forward–blocking voltage is referred to as
circuit–commutated turn–off time tq.
ton Turn–off time depends upon a number of circuit conditions
including on–state current prior to turn–off, rate of change of
GATE current during the forward–to–reverse transition, reverse–
CURRENT IGT blocking voltage, rate of change of reapplied forward voltage,
50% POINT
IGT 50% the gate bias, and junction temperature. Increasing junction
0 temperature and on–state current both increase turn–off time
(WAVESHAPES FOR A SENSITIVE LOAD)
and have a more significant effect than any of the other
factors. Negative gate bias will decrease the turn–off time.
Figure 2.6. Waveshapes Illustrating Thyristor Turn–On
Time For A Resistive Load
REAPPLIED
dv/dt
Delay time decreases slightly as the peak off–state voltage
increases. It is primarily related to the magnitude of the
gate–trigger current and shows a relationship which is
PRINCIPAL
roughly inversely proportional. VOLTAGE FORWARD
The rise time is influenced primarily by the off–state
voltage, as high voltage causes an increase in regenerative
gain. Of major importance in the rise time interval is the 0
relationship between principal voltage and current flow
through the thyristor di/dt. During this time the dynamic REVERSE
voltage drop is high and the current density due to the
possible rapid rate of change can produce localized hot
spots in the die. This may permanently degrade the blocking
characteristics. Therefore, it is important that power dissipa- di/dt
tion during turn–on be restricted to safe levels.
Turn–off time is a property associated only with SCRs and FORWARD
other unidirectional devices. (In triacs of bidirectional devices PRINCIPAL
a reverse voltage cannot be used to provide circuit–commu- CURRENT
tated turn–off voltage because a reverse voltage applied to
one half of the structure would be a forward–bias voltage to 0
the other half.) For turn–off times in SCRs, the recovery REVERSE
period consists of two stages, a reverse recovery time and a
gate or forward blocking recovery time, as shown in Figure trr tgr
2.7.
When the forward current of an SCR is reduced to zero at tq
the end of a conduction period, application of reverse voltage
between the anode and cathode terminals causes reverse
current flow in the SCR. The current persists until the time
Figure 2.7. Waveshapes Illustrating Thyristor
that the reverse current decreases to the leakage level.
Turn–Off Time
Reverse recovery time (trr) is usually measured from the

Theory and Applications Motorola Thyristor Device Data

1.2–4
 For applications in which an SCR is used to control ac over–all device capability to support voltage. The result is a
power, during the entire negative half of the sine wave a loss of power control to the load, and the device remains in
reverse voltage is applied. Turn off is easily accomplished for the conducting state in absence of a gate signal. The
most devices at frequencies up to a few kilohertz. For measure of triac turn–off ability is the rate of rise of the
applications in which the SCR is used to control the output of opposite polarity voltage it can handle without remaining on.
a full–wave rectifier bridge, however, there is no reverse It is called commutating dv/dt (dv/dt[c]). Circuit conditions and
voltage available for turn–off, and complete turn–off can be temperature affect dv/dt(c) in a manner similar to the way tq is
accomplished only if the bridge output is reduced close to affected in an SCR.
zero such that the principal current is reduced to a value It is imperative that some means be provided to restrict the
lower than the device holding current for a sufficiently long rate of rise of reapplied voltage to a value which will permit
time. Turn–off problems may occur even at a frequency of 60 triac turn–off under the conditions of inductive load. A
Hz particularly if an inductive load is being controlled. commonly accepted method for keeping the commutating
In triacs, rapid application of a reverse polarity voltage dv/dt within tolerable levels is to use an RC snubber network
does not cause turn–off because the main blocking junctions in parallel with the main terminals of the triac. Because the
are common to both halves of the device. When the first triac rate of rise of applied voltage at the triac terminals is a
structure (SCR–1) is in the conducting state, a quantity of function of the load impedance and the RC snubber network,
charge accumulates in the N–type region as a result of the the circuit can be evaluated under worst–case conditions of
principal current flow. As the principal current crosses the operating case temperature and maximum principal current.
zero reference point, a reverse current is established as a The values of resistance and capacitance in the snubber
result of the charge remaining in the N–type region, which is area then adjusted so that the rate of rise of commutating
common to both halves of the device. Consequently, the dv/dt stress is within the specified minimum limit under any of
reverse recovery current becomes a forward current to the the conditions mentioned above. The value of snubber
second half of the triac. The current resulting from stored resistance should be high enough to limit the snubber
charge causes the second half of the triac to go into the capacitance discharge currents during turn–on and dampen
conducting state in the absence of a gate signal. Once the LC oscillation during commutation. The combination of
current conduction has been established by application of a snubber values having highest resistance and lowest capaci-
gate signal, therefore, complete loss in power control can tance that provides satisfactory operation is generally pre-
occur as a result of interaction within the N–type base region ferred.
of the triac unless sufficient time elapses or the rate of
application of the reverse polarity voltage is slow enough to FALSE TRIGGERING
allow nearly all the charge to recombine in the common Circuit conditions can cause thyristors to turn on in the
N–type region. Therefore, triacs are generally limited to absence of the trigger signal. False triggering may result
low–frequency – 60 Hz applications. Turn–off or commutation from:
of triacs is more severe with inductive loads than with 1) A high rate of rise of anode voltage, (the dv/dt effect).
resistive loads because of the phase lag between voltage 2) Transient voltages causing anode breakover.
and current associated with inductive loads. Figure 2.8 3) Spurious gate signals.
shows the waveforms for an inductive load with lagging
Static dv/dt effect: When a source voltage is suddenly
current power factor. At the time the current reaches zero
applied to a thyristor which is in the off state, it may switch
crossover (Point A), the half of the triac in conduction begins
from the off state to the conducting state. If the thyristor is
to commutate when the principal current falls below the
controlling alternating voltage, false turn–on resulting from a
holding current. At the instant the conducting half of the triac
transient imposed voltage is limited to no more than one–half
turns off, an applied voltage opposite the current polarity is
cycle of the applied voltage because turn–off occurs during
applied across the triac terminals (Point B). Because this
the zero current crossing. However, if the principal voltage is
voltage is a forward bias to the second half of the triac, the
dc voltage, the transient may cause switching to the on state
suddenly reapplied voltage in conjunction with the remaining
and turn–off could then be achieved only by a circuit
stored charge in the high–voltage junction reduces the
interruption.
The switching from the off state caused by a rapid rate of
rise of anode voltage is the result of the internal capacitance
of the thyristor. A voltage wavefront impressed across the
terminals of a thyristor causes a capacitance–charging
IH current to flow through the device which is a function of the
V I A dr rate of rise of applied off–state voltage (i = C dv/dt). If the rate
c
dt of rise of voltage exceeds a critical value, the capacitance
charging current exceeds the gate triggering current and
B causes device turn–on. Operation at elevated junction
temperatures reduces the thyristor ability to support a steep
Figure 2.8. Inductive Load Waveforms rising voltage dv/dt because of increased sensitivity.

Motorola Thyristor Device Data Theory and Applications

1.2–5
 dv/dt ability can be improved quite markedly in sensitive maximum temperature ratings of a particular part number.
gate devices and to some extent in shorted emitter designs The temperature rating may be chosen by the manufacturer
by a resistance from gate to cathode (or MT1) however to insure satisfactory voltage ratings, switching speeds, or
reverse bias voltage is even more effective in an SCR. More dv/dt ability.
commonly, a snubber network is used to keep the dv/dt within
the limits of the thyristor when the gate is open. OPERATING CURRENT RATINGS
TRANSIENT VOLTAGES: — Voltage transients which Current ratings are not independently established as a
occur in electrical systems as a result of disturbance on the rule. The values are chosen such that at a practical case
ac line caused by various sources such as energizing temperature the power dissipation will not cause the junction
transformers, load switching, solenoid closure, contractors temperature rating to be exceeded.
and the like may generate voltages which are above the Various manufacturers may chose different criteria to
ratings of thyristors. Thyristors, in general, switch from the off establish ratings. At Motorola, use is made of the thermal
state to the on state whenever the breakover voltage of the response of the semiconductor and worst case values of
device is exceeded, and energy is then transferred to the on–state voltage and thermal resistance, to guarantee the
load. However, unless a thyristor is specified for use in a junction temperature is at or below its rated value. Values
breakover mode, care should be exercised to ensure that shown on data sheets consequently differ somewhat from
breakover does not occur, as some devices may incur those computed from the standard formula:
surface damage with a resultant degradation of blocking
characteristics. It is good practice when thyristors are
TC(max) = T (rated) – RθJC 
PD(AV)
exposed to a heavy transient environment to provide some where
form of transient suppression. TC (max) = Maximum allowable case temperature
For applications in which low–energy, long–duration tran- T (rated) = Rated junction temperature or maximum
sients may be encountered, it is advisable to use thyristors rated case temperature with zero principal
that have voltage ratings greater than the highest voltage current and rated ac blocking voltage
transient expected in the system. The use of voltage clipping applied.
cells (MOV or Zener) is also an effective method to hold RθJC = Junction to case thermal resistance
transient below thyristor ratings. The use of an RC “snubber” PD(AV) = Average power dissipation
circuit is effective in reducing the effects of the high–energy The above formula is generally suitable for estimating case
short–duration transients more frequently encountered. The temperature in situations not covered by data sheet informa-
snubber is commonly required to prevent the static dv/dt tion. Worst case values should be used for thermal resis-
limits from being exceeded, and often may be satisfactory in tance and power dissipation.
limiting the amplitude of the voltage transients as well.
For all applications, the dv/dt limits may not be exceeded. OVERLOAD CURRENT RATINGS
This is the minimum value of the rate of rise off–state voltage Overload current ratings may be divided into two types:
applied immediately to the MT1–MT2 terminals after the non–repetitive and repetitive.
principal current of the opposing polarity has decreased to Non–repetitive overloads are those which are not a part of
zero. the normal application of the device. Examples of such
SPURIOUS GATE SIGNALS: In noisy electrical environ- overloads are faults in the equipment in which the devices
ments, it is possible for enough energy to cause gate are used and accidental shorting of the load. Non–repetitive
triggering to be coupled into the gate wiring by stray overload ratings permit the device to exceed its maximum
capacitance or electromagnetic induction. It is therefore operating junction temperature for short periods of time
advisable to keep the gate lead short and have the common because this overload rating applies following any rated load
return directly to the cathode or MT1. In extreme cases, condition. In the case of a reverse blocking thyristor or SCR,
shielded wire may be required. Another aid commonly used the device must block rated voltage in the reverse direction
is to connect a capacitance on the order of 0.01 to 0.1 µF during the current overload. However, no type of thyristor is
across the gate and cathode terminals. This has the added required to block off–stage voltage at any time during or
advantage of increasing the thyristor dv/dt capability, since it immediately following the overload. Thus, in the case of a
forms a capacitance divider with the anode to gate capaci- triac, the device need not block in either direction during or
tance. The gate capacitor also reduces the rate of application immediately following the overload. Usually only approxi-
of gate trigger current which may cause di/dt failures if a high mately one hundred such current overloads are permitted
inrush load is present. over the life of the device. These non–repetitive overload
ratings just described may be divided into two types:
THYRISTOR RATINGS multicycle (which include single cycle) and subcycle. For an
To insure long life and proper operation, it is important that SCR, the multicycle overload current rating, or surge current
operating conditions be restrained from exceeding thyristor rating as it is commonly called, is generally presented as a
ratings. The most important and fundamental ratings are curve giving the maximum peak values of half sine wave
temperature and voltage which are interrelated to some on–state current as a function of overload duration measured
extent. The voltage ratings are applicable only up to the in number of cycles for a 60 Hz frequency.

Theory and Applications Motorola Thyristor Device Data

1.2–6
 For a triac, the current waveform used in the rating is a full angle is the time, measured in electrical degrees, during
sine wave. Multicycle surge curves are used to select proper which the SCR is blocking the line voltage. The period during
circuit breakers and series line impedances to prevent which the SCR is on is called the conduction angle.
damage to the thyristor in the event of an equipment fault. It is important to note that the SCR is a voltage controlling
The subcycle overload or subcycle surge rating curve is so device. The load and power source determine the circuit
called because the time duration of the rating is usually from current.
about one to eight milliseconds which is less than the time of Now we arrive at a problem. Different loads respond to
one cycle of a 60 Hz power source. Overload peak current is different characteristics of the ac waveform. Some loads are
often given in curve form as a function of overload duration. sensitive to peak voltage, some to average voltage and
This rating also applies following any rated load condition some to rms voltage. Figures 2.11(b) and 2.12(b) show the
and neither off–state nor reverse blocking capability is various characteristic voltages plotted against the conduction
required on the part of the thyristor immediately following the angle for half wave and full wave circuits. These voltages
overload current. The subcycle surge current rating may be have been normalized to the rms of the applied voltage. To
used to select the proper current–limiting fuse for protection determine the actual peak, average or rms voltage for any
of the thyristor in the event of an equipment fault. Since this conduction angle, we simply multiply the normalized voltage
use of the rating is so common, manufacturers simply publish by the rms value of the applied line voltage. (These
the i2t rating in place of the subcycle current overload curve normalized curves also apply to current in a resistive circuit.)
because fuses are commonly rated in terms of i2t. The i2t Since the greatest majority of circuits are either 115 or 230
rating can be approximated from the single cycle surge rating volt power, the curves have been redrawn for these voltages
(ITSM) by using: in Figures 2.11(a) and 2.12(a).

i2t = I2TSM t/2 A relative power curve has been added to Figure 2.12 for
constant impedance loads such as heaters. (Incandescent
where the time t is the time base of the overload, i.e., 8.33 ms lamps and motors do not follow this curve precisely since
for a 60 Hz frequency. their relative impedance changes with applied voltage.) To
Repetitive overloads are those which are an intended part use the curves, we find the full wave rated power of the load,
of the application such as a motor drive application. Since then multiply by the fraction associated with the phase angle
this type of overload may occur a large number of times in question. For example, a 180° conduction angle in a half
during the life of the thyristor, its rated maximum operating wave circuit provides 0.5 x full wave full–conduction power.
junction temperature must not be exceeded during the An interesting point is illustrated by the power curves. A
overload if long thyristor life is required. Since this type of conduction angle of 30° provides only three per cent of full
overload may have a complex current waveform and power in a full wave circuit, and a conduction angle of 150°
duty–cycle, a current rating analysis involving the use of the provides 97 per cent of full power. Thus, the control circuit
transient thermal impedance characteristics is often the only can provide 94 per cent of full power control with a pulse
practical approach. In this type of analysis, the thyristor phase variation of only 120°. Thus, it becomes pointless in
junction–to–case transient thermal impedance characteristic many cases to try to obtain conduction angles less than 30°
is added to the user’s heat dissipator transient thermal or greater than 150°.
impedance characteristic. Then by the superposition of
power waveforms in conjunction with the composite thermal CONTROL CHARACTERISTICS
impedance curve, the overload current rating can be The simplest and most common control circuit for phase
obtained. The exact calculation procedure is found in the control is a relaxation oscillator. This circuit is shown
power semiconductor literature. diagrammatically as it would be used with an SCR in Figure
2.13. The capacitor is charged through the resistor from a
voltage or current source until the breakover voltage of the
THEORY OF SCR POWER CONTROL
trigger device is reached. At that time, the trigger device
The most common form of SCR power control is phase changes to its on state, and the capacitor is discharged
control. In this mode of operation, the SCR is held in an off through the gate of the SCR. Turn–on of the SCR is thus
condition for a portion of the positive half cycle and then is accomplished with a short, high current pulse. Commonly
triggered into an on condition at a time in the half cycle used trigger devices are programmable unijunction transis-
determined by the control circuitry (in which the circuit current tors, silicon bilateral switches, SIDACs, optically coupled
is limited only by the load — the entire line voltage except for thyristors, and power control integrated circuits. Phase
a nominal one volt drop across the SCR is applied to the control can be obtained by varying the RC time constant of a
load). charging circuit so that trigger device turn–on occurs at
One SCR alone can control only one half cycle of the varying phase angles within the controlled half cycle.
waveform. For full wave ac control, two SCRs are connected If the relaxation oscillator is to be operated from a pure dc
in inverse parallel (the anode of each connected to the source, the capacitor voltage–time characteristic is shown in
cathode of the other, see Figure 2.9a). For full wave dc Figure 2.14. This shows the capacitor voltage as it rises all
control, two methods are possible. Two SCRs may be used the way to the supply voltage through several time constants.
in a bridge rectifier (see Figure 2.9b) or one SCR may be Figure 2.14(b) shows the charge characteristic in the first
placed in series with a diode bridge (see Figure 2.9c). time constant greatly expanded. It is this portion of the
Figure 2.10 shows the voltage waveform along with some capacitor charge characteristic which is most often used in
common terms used in describing SCR operation. Delay SCR and Triac control circuits.

Motorola Thyristor Device Data Theory and Applications

1.2–7
 Generally, a design starting point is selection of a
capacitance value which will reliably trigger the thyristor
when the capacitor is discharged. Gate characteristics and
ratings, trigger device properties, and the load impedance
play a part in the selection. Since not all of the important
parameters for this selection are completely specified, CONTROL
experimental determination is often the best method. CIRCUIT
Low–current loads and strongly inductive circuits some- LINE LOAD
times cause triggering difficulty because the gate current
pulse goes away before the principal thyristor current
achieves the latching value. A series gate resistor can be (a)
used to introduce a RC discharge time constant in the gate ac Control
circuit and lengthen trigger pulse duration allowing more time
for the main terminal current to rise to the latching value.
Small thyristors will require a series gate resistance to avoid
exceeding the gate ratings. The discharge time constant of a
LINE CONTROL
snubber, if used, can also aid latching. The duration of these
CIRCUIT
capacitor discharge duration currents can be estimated by
tw10 = 2.3 RC where tw10 = time for current to decay to 10%
of the peak.
LOAD
For example, when an 8 volt SBS is used to discharge a
0.5 µF capacitor through a 15 ohm resistor into the gate of an (b)
SCR Two SCR dc Control
tw10 = (2.3) (15) (0.5) = 17.3 µs.
Because of internal voltage drops in the SBS and SCR
gates, the peak current will be somewhat less than
Ipk = 8/15 = 0.53 amp. LINE

All trigger devices require some drive current to fire. Highly

sensitive devices appear to be voltage operated when the
current required to fire them is insignificant. The MBS4991
SBS requires that the switching current be taken into
consideration. For a given RC time constant, larger capaci-
tors allow the use of lower value timing resistors and less CONTROL
sensitive trigger components. CIRCUIT
An example will demonstrate the procedure. Assume that LOAD
we wish to trigger a 2N6397 SCR with an 8 volt MBS4991.
We have determined that a 1 µF capacitor will supply the (c)
necessary SCR gate current magnitude and duration while One SCR dc Control
not exceeding the gate ratings. Assume a 16 volt 60 Hz dc
gate power supply, 30° minimum conduction angle and 150° Figure 2.9. SCR Connections For Various Methods
maximum conduction angle with a 60 Hz anode power Of Phase Control
source. The capacitor must charge to 8/16 or 0.5 of the
available charging voltage in the desired time. Referring to
FULL WAVE RECTIFIED OPERATION
Figure 2.14(b), we see that 0.5 of the charging voltage
represents 0.693 time constant. The 30° conduction angle VOLTAGE APPLIED TO LOAD
requires that the firing pulse be delayed 150° or 6.94
milliseconds (8.33 milliseconds is the period of 1/2 cycle at
60 Hz). To obtain this delay,

6.49 ms + 0.693 RC
RC + 10.01 ms.
DELAY ANGLE

+ 1 mF,
If C CONDUCTION ANGLE

R + 10 10 + 10 k ohms.
–3
Figure 2.10. Sine Wave Showing Principles
1 10 – 6 Of Phase Control

Theory and Applications Motorola Thyristor Device Data

1.2–8
 APPLIED
VOLTAGE
230 V 115 V
1.8 360 180
HALF WAVE HALF WAVE
1.6 PEAK VOLTAGE 320 160
POWER AS FRACTION OF FULL CONDUCTION

1.4 280 140 PEAK VOLTAGE

NORMALIZED SINE WAVE rms VOLTAGE

1.2 240 120

1 200 100

VOLTAGE
rms rms
0.8 160 80

0.6 POWER 120 60

0.4 80 40

0.2 AVG 40 20 AVG

0 0 0
0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
CONDUCTION ANGLE CONDUCTION ANGLE
(a) (b)
Figure 2.11. Half–Wave Characteristics Of Thyristor Power Control

APPLIED
VOLTAGE
230 V 115 V
1.8 360 180
FULL WAVE FULL WAVE
1.6 320 160
PEAK VOLTAGE
POWER AS FRACTION OF FULL CONDUCTION

1.4 280 140 PEAK VOLTAGE

NORMALIZED SINE WAVE rms VOLTAGE

1.2 240 120 rms

1 200 100
VOLTAGE

rms

0.8 POWER 160 80

0.6 120 60
AVG
AVG
0.4 80 40

0.2 40 20

0 0 0
0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
CONDUCTION ANGLE CONDUCTION ANGLE
(a) (b)
Figure 2.12. Full–Wave Characteristics Of Thyristor Power Control

Motorola Thyristor Device Data Theory and Applications

1.2–9
 16 V 4 mA 60 Hz 1
8V
Voltage Source
MBS4991
0.9
2N6397
10 k 2k 15
SCR 0.8
+16 1 µF
0

FRACTION OF SUPPLY VOLTAGE

100 0.7

CAPACITOR VOLTAGE AS
0.6

Figure 2.13. SCR Trigger Circuit 0.5

The timing resistor must be capable of supplying at least 0.4

the worst case maximum SBS switching current at the peak
point voltage. The available current is 0.3

16 V–8 V
104 ohms
+ 800 mA. 0.2

0.1
This is more than the 500 µA needed by the MBS4991 at
25°C. If it were not, the design procedure would need to be 0
0 1 2 3 4 5 6
repeated using larger C and smaller R. Alternatively, a more
sensitive MBS4992 could be used. TIME CONSTANTS
To obtain minimum R, 150° conduction angle, the delay is Figure 2.14(a). Capacitor Charging From dc Source
30° or

ń
30 180x8.33 + 1.39 ms 0.7

1.39 ms+ 0.693 RC

+ 0.6
FRACTION OF SUPPLY VOLTAGE
RC 2.01 ms
CAPACITOR VOLTAGE AS

R + 2.01 10 + 2000 ohms.

–3 0.5

1 10 –6 0.4
A 10 k potentiometer with a 2 k series resistor will serve this
purpose. 0.3
In this application, the trigger circuit is reset by line
crossing each half cycle. Consequently, SBS latching after 0.2
firing is permissible. If the device were used as a free running
oscillator, it would be necessary for the peak point current to 0.1
be less than the minimum holding current specification of the
SBS at maximum operating temperature. Timing accuracy 0
requires the 16 V source to be capable of supplying the worst 0 0.2 0.4 0.6 0.8 1 1.2
case required current. In the example, the initial instanta- TIME CONSTANTS
neous capacitor charging current will be 16 V/2 k = 8 mA. The
Figure 2.14(b). Expanded Scale
gate load line must also enclose the peak point voltage. The
SBS clamps the capacitor voltage when it breaks over
causing little or no further change in the voltage across the
characteristic of the capacitor charged from one half cycle of
capacitor. Consequently, all of the available current at that
a sine wave. Voltage is normalized to the rms value of the
time (16 V–8 V)/2 k = 4 mA) diverts through the SBS causing
sine wave for convenience of use. The parameter of the
it to fire.
curves is a new term, the ratio of the RC time constant to the
In many of the recently proposed circuits for low cost
period of one half cycle, and is denoted by the Greek letter τ.
operation, the timing capacitor of the relaxation oscillator is
It may most easily be calculated from the equation
charged through a rectifier and resistor using the ac power
line as a source. Calculations of charging time with this circuit
become exceedingly difficult, although they are still neces- τ = 2RCf. Where: R = resistance in Ohms
sary for circuit design. The curves of Figure 2.15 simplify the C = capacitance in Farads
design immensely. These curves show the voltage–time f = frequency in Hertz.

Theory and Applications Motorola Thyristor Device Data

1.2–10
 1.80
APPLIED VOLTAGE, V
R
1.40 VC τ = 0.1
V C
0.2
NORMALIZED VOLTAGE AS A FRACTION OF

1.20
rms CHARGING SOURCE VOLTAGE

CAPACITOR 0.3
VOLTAGE, VC
1 0.4
0.5
0.80
0.707 0.7
0.60
1

0.40 1.5
2
3
0.20
5

0
0 20 40 60 80 100 120 140 160 180
180 160 140 120 100 80 60 40 30 20 0

DELAY ANGLE IN DEG.

CONDUCTION ANGLE IN DEG.

Figure 2.15(a). Capacitor Voltage When Charged

0.35
τ = 0.1 0.2 0.3 0.5 0.7 1 1.5 2
2.5
0.30
NORMALIZED VOLTAGE AS A FRACTION OF
rms CHARGING SOURCE VOLTAGE

3
0.25

0.20 4

5
0.15
7
0.10 10
15
0.05
20
50
0
0 20 40 60 80 100 120 140 160 180
180 160 140 120 100 80 60 40 20 0

DELAY ANGLE IN DEG.

CONDUCTION ANGLE IN DEG.

Figure 2.15(b). Expansion of Figure 2.15(a).

Motorola Thyristor Device Data Theory and Applications

1.2–11
 0.1

NORMALIZED VOLTAGE AS A FRACTION OF

τ = 0.1 0.2 0.3 0.7 1 1.5 2 2.5 3 4 5 7 8.5
0.09
rms CHARGING SOURCE VOLTAGE
0.5 10
0.08
0.0696
0.07 12.5
0.06 15
0.05
20
0.04
0.03 35
0.02
0.01 50

0
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 DELAY ANGLE IN DEG.
180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 CONDUCTION
rms CHARGING SOURCE VOLTAGE ANGLE IN DEG.

Figure 2.15(c). Expansion of Figure 2.15(b)

To use the curves when starting the capacitor charge from When the conduction angle is less than 90°, triggering
zero each half cycle, a line is drawn horizontally across the takes place along the back of the power line sine wave and
curves at the relative voltage level of the trigger breakdown maximum firing current thru the SBS is at the start of SBS
compared to the rms sine wave voltage. The τ is determined breakover. If this current does not equal or exceed “ls” the
for maximum and minimum conduction angles and the limits SBS will fail to trigger and phase control will be lost. This can
of R may be found from the equation for τ. be prevented by selecting a lower value resistor and larger
An example will again clarify the picture. Consider the capacitor. The available current can be determined from
same problem as the previous example, except that the Figure 2.15(a). The vertical line drawn from the conduction
capacitor charging source is the 115 Vac, 60 Hz power line. angle of 30° intersects the applied voltage curve at 0.707.
The ratio of the trigger diode breakover voltage to the RMS The instantaneous current at breakover is then
charging voltage is then
I = (0.707  115–8)/110 k = 733 µA.
8/115 = 69.6  10–3.
A line drawn at 0.0696 on the ordinate of Figure 2.15(c) When the conduction angle is greater than 90°, triggering
shows that for a conduction angle of 30°, τ = 12, and for a takes place before the peak of the sine wave. If the current
conduction angle of 150°, τ = 0.8. Therefore, since thru the SBS does not exceed the switching current at the
R = τ/(2CF) moment of breakover, triggering may still take place but not at
the predicted time because of the additional delay for the
Rmax + 2(1.0 12
–
10 6)60
100 k ohms, rising line voltage to drive the SBS current up to the switching
level. Usually long conduction angles are associated with low
value timing resistors making this problem less likely. The
Rmin + 2(1 0.8
10–6 )60
6667 ohms.
SBS current at the moment of breakover can be determined
by the same method described for the trailing edge.
It is advisable to use a shunt gate–cathode resistor across
These values would require a potentiometer of 100 k in sensitive gate SCR’s to provide a path for leakage currents
series with a 6.2 k minimum fixed resistance. and to insure that firing of the SCR causes turn–on of the
The timing resistor must be capable of supplying the trigger device and discharge of the gate circuit capacitor.
highest switching current allowed by the SBS specification at
the switching voltage.

Theory and Applications Motorola Thyristor Device Data

1.2–12
 Figure 2.16(a) shows a simple dc full wave control circuit. LINE
RGK is optional on non–sensitive gate parts. Figure 2.16(b) 2N6397
shows an ac control derived from that of Figure 2.16(a). 100
Figure 2.16(c) is a double time constant circuit featuring low MBS4991
RGK
hysteresis. 100 k
G

TRIAC THEORY 15

The triac is a three–terminal ac semiconductor switch

6.2 k 1 µF
which is triggered into conduction when a low–energy signal
is applied to its gate. Unlike the silicon controlled rectifier or LOAD
SCR, the triac will conduct current in either direction when
turned on. The triac also differs from the SCR in that either a
positive or negative gate signal will trigger the triac into Figure 2.16(a). Simple dc Power Control Circuit
conduction. The triac may be thought of as two complemen-
tary SCRs in parallel.
The triac offers the circuit designer an economical and
versatile means of accurately controlling ac power. It has MAC210–4
several advantages over conventional mechanical switches.
Since the triac has a positive “on” and a zero current “off” RGK
characteristic, it does not suffer from the contact bounce or
MBS4991 100
arcing inherent in mechanical switches. The switching action 1 µF
of the triac is very fast compared to conventional relays, LINE 100 k G LOAD
giving more accurate control. A triac can be triggered by dc,
ac, rectified ac or pulses. Because of the low energy required
6.2 k 15
for triggering a triac, the control circuit can use any of many
low–cost solid–state devices such as transistors, bilateral
switches, sensitive–gate SCRs and triacs, optically coupled
drivers and integrated circuits.

CHARACTERISTICS OF THE TRIAC

Figure 2.17(a) shows the triac symbol and its relationship Figure 2.16(b). Simple Full–Wave Power Control
to a typical package. Since the triac is a bilateral device, the
terms “anode” and “cathode” used for unilateral devices have
no meaning. Therefore, the terminals are simply designated
by MT1, MT2, and G, where MT1 and MT2 are the
current–carrying terminals, and G, is the gate terminal used MAC210–4
for triggering the triac. To avoid confusion, it has become
standard practice to specify all currents and voltages using RGK
MT1 as the reference point.
MBS4991 100
The basic structure of a triac is shown in Figure 2.17(b).
This drawing shows why the symbol adopted for the triac LINE 100 k G LOAD
consists of two complementary SCRs with a common gate.
The triac is a five–layer device with the region between MT1
15
and MT2 being P–N–P–N switch (SCR) in parallel with a
27 k 0.1 µF
N–P–N–P switch (complementary SCR). Also, the structure
gives some insight into the triac’s ability to be triggered with 0.22 µF
either a positive or negative gate signal. The region between
MT1 and G consists of two complementary diodes. A positive
or negative gate signal will forward–bias one of these diodes
causing the same transistor action found in the SCR. This
action breaks down the blocking junction regardless of the
polarity of MT1. Current flow between MT2 and MT1 then Figure 2.16(c). Full Range ac Power Control
causes the device to provide gate current internally. It will
remain on until this current flow is interrupted.

Motorola Thyristor Device Data Theory and Applications

1.2–13
 The voltage–current characteristic of the triac is shown in MT2
Figure 2.18 where, as previously stated, MT1 is used as the
reference point. The first quadrant, Q–I, is the region where
MT2 is positive with respect to MT1 and quadrant III is the
opposite case. Several of the terms used in characterizing GATE
the triac are shown on the figure. VDRM is the breakover
voltage of the device and is the highest voltage the triac may MT1
be allowed to block in either direction. If this voltage is
exceeded, even transiently, the triac may go into conduction (a)
without a gate signal. Although the triac is not damaged by
this action if the current is limited, this situation should be MT2
avoided because control of the triac is lost. A triac for a
particular application should have VDRM at least as high as
the peak of the ac waveform to be applied so reliable control
P N
can be maintained. The holding current (IH) is the minimum
value of current necessary to maintain conduction. When the
N
current goes below IH, the triac ceases to conduct and
reverse to the blocking state. IDRM is the leakage current of P
N N
the triac with VDRM applied from MT2 to MT1 and is several
orders of magnitude smaller than the current rating of the
device. The figure shows the characteristic of the triac
without a gate signal applied but it should be noted that the MT1 G
triac can be triggered into the on state at any value of voltage (b)
up to VDRM by the application of a gate signal. This important Figure 2.17. Triac Structure and Symbol
characteristic makes the triac very useful.
Since the triac will conduct in either direction and can be
triggered with either a positive or negative gate signal there
Q1
are four possible triggering modes (Figure 2.3): ON–STATE
MT2+
Quadrant I; MT2(+), G(+), positive voltage and positive BLOCKING
gate current. Quadrant II; MT2(+), G(–), positive voltage STATE
VDRM VDRM
and negative gate current. Quadrant III; MT2(–), G(–), I IH
IDRM
negative voltage and negative gate current. Quadrant IV;
MT2(–), G(+), negative voltage and positive gate current.
V
Present triacs are most sensitive in quadrants I and III,
slightly less so in quadrant II, and much less sensitive in IH IDRM
quadrant IV. Therefore it is not recommended to use BLOCKING STATE
quadrant IV unless special circumstances dictate it. QIII
An important fact to remember is that since a triac can MT2—ON–STATE
conduct current in both directions, it has only a brief interval
during which the sine wave current is passing through zero to Figure 2.18. Triac Voltage–Current Characteristic
recover and revert to its blocking state. For this reason,
reliable operation of present triacs is limited to 60 Hz line
frequency and lower frequencies. lost. In order to achieve control with certain inductive loads,
For inductive loads, the phase–shift between the current the rate of rise in voltage (dv/dt) must be limited by a series
and voltage means that at the time the current falls below IH RC network across the triac. The capacitor will then limit the
and the triac ceases to conduct, there exists a certain voltage dv/dt across the triac. The resistor is necessary to limit the
which must appear across the triac. If this voltage appears surge of current from the capacitor when the triac fires, and to
too rapidly, the triac will resume conduction and control is damp the ringing of the capacitance with the load inductance.

Theory and Applications Motorola Thyristor Device Data

1.2–14
METHODS OF CONTROL In order for zero–point switching to be effective, it must
indeed be zero point switching. If a triac is turned on with as
little as 10 volts across it into a load of a few–hundred watts,
AC SWITCH
sufficient EMI will result to nullify the advantages of adopting
A useful application of triac is as a direct replacement for
zero–point switching in the first place.
an ac mechanical relay. In this application, the triac furnishes
on–off control and the power–regulating ability of the triac is
not utilized. The control circuitry for this application is usually BASIC TRIAC AC SWITCHES
very simple, consisting of a source for the gate signal and Figure 2.21 shows methods of using the triac as an on–off
some type of small current switch, either mechanical or switch. These circuits are useful in applications where
electrical. The gate signal can be obtained from a separate simplicity and reliability are important. As previously stated,
source or directly from the line voltage at terminal MT2 of the there is no arcing with the triac, which can be very important
triac. in some applications. The circuits are for resistive loads as
shown and require the addition of a dv/dt network across the
PHASE CONTROL triac for inductive loads. Figure 2.21(a) shows low–voltage
An effective and widely–used method of controlling the control of the triac. When switch S1 is closed, gate current is
average power to a load through the triac is by phase control. supplied to the triac from the 10 volt battery. In order to
Phase control is a method of utilizing the triac to apply the ac reduce surge current failures during turn on (ton), this current
supply to the load for a controlled fraction of each cycle. In should be 5 to 10 times the maximum gate current (IGT)
this mode of operation, the triac is held in an off or open required to trigger the triac.
condition for a portion of each positive and negative cycle, The triac turns on and remains on until S1 is opened. This
and then is triggered into an on condition at a time in the half circuit switches at zero current except for initial turn on. S1
cycle determined by the control circuitry. In the on condition, can be a very–low–current switch because it carries only the
the circuit current is limited only by the load — i.e., the entire triac gate current.
line voltage (less the forward drop of the triac) is applied to Figure 2.21(b) shows a triac switch with the same
the load. characteristics as the circuit in Figure 2.21(a) except the
Figure 2.19 shows the voltage waveform along with some need for a battery has been eliminated. The gate signal is
common terms used in describing triac operation. Delay obtained from the voltage at MT2 of the triac prior to turn on.
angle is the angle, measured in electrical degrees, during The circuit shown in Figure 2.21(c) is a modification of
which the triac is blocking the line voltage. The period during Figure 2.21(b). When switch S1 is in position one, the triac
which the triac is on is called the conduction angle. receives no gate current and is non–conducting. With S1 in
It is important to note that the triac is either off (blocking position two, circuit operation is the same as that for Figure
voltage) or fully on (conducting). When it is in the on 2.21(b). In position three, the triac receives gate current only
condition, the circuit current is determined only by the load on positive half cycles. Therefore, the triac conducts only on
and the power source. positive half cycles and the power to the load is half wave.
As one might expect, in spite of its usefulness, phase Figure 2.21(d) shows ac control of the triac. The pulse can
control is not without disadvantages. The main disadvantage be transformer coupled to isolate power and control circuits.
of using phase control in triac applications is the generation Peak current should be 10 times IGT(max) and the RC time
of electro–magnetic interference (EMI). Each time the triac is constant should be 5 times ton(max). A high frequency pulse
fired the load current rises from zero to the load–limited (1 to 5 kHz) is often used to obtain zero point switching.
current value in a very short time. The resulting di/dt
generates a wide spectrum of noise which may interfere with
the operation of nearby electronic equipment unless proper VOLTAGE APPLIED TO LOAD
filtering is used.

ZERO POINT SWITCHING

In addition to filtering, EMI can be minimized by zero–point
switching, which is often preferable. Zero–point switching is a
technique whereby the control element (in this case the triac)
is gated on at the instant the sine wave voltage goes through DELAY ANGLE
zero. This reduces, or eliminates, turn–on transients and the CONDUCTION ANGLE
EMI. Power to the load is controlled by providing bursts of
complete sine waves to the load as shown in Figure 2.20.
Modulation can be on a random basis with an on–off control,
Figure 2.19. Sine Wave Showing Principles
or a proportioning basis with the proper type of proportional
of Phase Control
control.

Motorola Thyristor Device Data Theory and Applications

1.2–15
ZERO POINT SWITCHING TECHNIQUES 15 Ω
LOAD
Zero–point switches are highly desirable in many applica-
tions because they do not generate electro–magnetic inter-
ference (EMI). A zero–point switch controls sine–wave power
in such a way that either complete cycles or half cycles of the 115 VAC R1
2N6346
power supply voltage are applied to the load as shown in 60 Hz 47 Ω S1
Figure 2.22. This type of switching is primarily used to control +
power to resistive loads such as heaters. It can also be used 10 V
for controlling the speed of motors if the duty cycle is
modulated by having short bursts of power applied to the
load and the load characteristic is primarily inertial rather than (a): Low Voltage Controlled Triac Switch
frictional. Modulation can be on a random basis with an
on–off control, or on a proportioning basis with the proper
type of proportioning control. 15 Ω
In order for zero–point switching to be effective, it must be LOAD
true zero–point switching. If an SCR is turned on with an
anode voltage as low as 10 volts and a load of just a few R1
hundred watts, sufficient EMI will result to nullify the 100 Ω
advantages of going to zero–point switching in the first place. 115 VAC
The thyristor to be turned on must receive gate drive exactly S1 2N6342
60 Hz
at the zero crossing of the applied voltage.
The most successful method of zero–point thyristor control
is therefore, to have the gate signal applied before the zero
crossing. As soon as the zero crossing occurs, anode
voltage will be supplied and the thyristor will come on. This is (b): Triac ac Static Contactor
effectively accomplished by using a capacitor to derive a 90°
leading gate signal from the power line source. However,
only one thyristor can be controlled from this phase–shifted 15 Ω
signal, and a slaving circuit is necessary to control the other LOAD
SCR to get full–wave power control. These basic ideas are
illustrated in Figure 2.23. The slaving circuit fires only on the
S1
half cycle after the firing of the master SCR. This guarantees
that only complete cycles of power will be applied to the load. 3 1
115 VAC 2
The gate signal to the master SCR receives all the control; a 2N6342
60 Hz
convenient control method is to replace the switch with a
low–power transistor, which can be controlled by bridge– R1
sensing circuits, manually controlled potentiometers, or 100 Ω
various other techniques.
(c): 3 Position Static Switch

LOAD 15 Ω
VOLTAGE LOAD

HALF POWER TO LOAD

LINE
VOLTAGE 2N6346
R1

FULL POWER TO LOAD

(d): AC Controlled Triac Switch

Figure 2.20. Sine Wave Showing Principles of
Zero–Point Switching
Figure 2.21. Triac Switches

Theory and Applications Motorola Thyristor Device Data

1.2–16
 2 µF LOAD
200 V
LOAD VOLTAGE AC LINE 150
1W Q1
(MASTER) Q2
(SLAVE)

LINE VOLTAGE
Figure 2.23. Slave and Master SCRs for
Zero–Point Switching

Figure 2.22. Load Voltage and Line Voltage for

25% Duty Cycle

1.2 k 2 µF
7W 200 V
A basic SCR is very effective and trouble free. However, it MAC210–4
can dissipate considerable power. This must be taken into AC LINE 150
1W
account in designing the circuit and its packaging.
In the case of triacs, a slaving circuit is also usually
required to furnish the gate signal for the negative half cycle. ON–OFF LOAD
CONTROL
However, triacs can use slave circuits requiring less power
than do SCRs as shown in Figure 2.23. Other considerations
being equal, the easier slaving will sometimes make the triac Figure 2.24. Triac Zero–Point Switch
circuit more desirable than the SCR circuit.
Besides slaving circuit power dissipation, there is another
consideration which should be carefully checked when using
high–power zero–point switching. Since this is on–off switch-
ing, it abruptly applies the full load to the power line every
time the circuit turns on. This may cause a temporary drop in S1
voltage which can lead to erratic operation of other electrical LOAD
D1
equipment on the line (light dimming, TV picture shrinkage, 1N4004
AC
etc.). For this reason, loads with high cycling rates should not C1 D4 Q1
LINE R1 0.25 µF 1N5760
be powered from the same supply lines as lights and other 3.8 k 2N4216
voltage–sensitive devices. On the other hand, if the load
R2 D2 D3
cycling rate is slow, say once per half minute, the loading 8.2 k R3
flicker may not be objectionable on lighting circuits. 1W 1N4004 1N4004 1k
A note of caution is in order here. The full–wave zero–point
switching control illustrated in Figure 2.23 should not be used Figure 2.25. Sensitive–Gate Switch
as a half–wave control by removing the slave SCR. When the
slave SCR in Figure 2.23 is removed, the master SCR has
positive gate current flowing over approximately 1/4 of a
cycle while the SCR itself is in the reverse–blocking state.
This occurs during the negative half cycle of the line voltage.
When this condition exists, Q1 will have a high leakage S1 C1
current with full voltage applied and will therefore be D1 0.25 µF LOAD
1N4004 200 V
dissipating high power. This will cause excessive heating of AC
the SCR and may lead to its failure. If it is desirable to use D3 D4
LINE R1 Q1
C2 3.8 k 1N4004 1N5760
such a circuit as a half–wave control, then some means of MCR218–4
10 nF
clamping the gate signal during the negative half cycle must 200 V R2 D2 R3
be devised to inhibit gate current while the SCR is reverse 8.2 k 1N4004 100
1W
blocking. The circuits shown in Figures 2.25 and 2.26 do not
have this disadvantage and may be used as half–wave
controls. Figure 2.26. Zero–Point Switch

Motorola Thyristor Device Data Theory and Applications

1.2–17
OPERATION
The zero–point switches shown in Figure 2.25 and 2.26 This particular slaving circuit has two important advan-
are used to insure that the control SCR turns on at the start of tages over standard RC discharge slaving circuits. It derives
each positive alternation. In Figure 2.25 a pulse is generated these advantages with practically no increase in price by
before the zero crossing and provides a small amount of gate using a low–cost transistor in place of the current–limiting
current when line voltage starts to go positive. This circuit is resistor normally used for slaving. The first advantage is that
primarily for sensitive–gate SCRs. Less–sensitive SCRs, a large pulse of gate current is available at the zero–crossing
with their higher gate currents, normally require smaller point. This means that it is not necessary to select sensitive–
values for R1 and R2 and the result can be high power gate SCRs for controlling power. The second advantage is
dissipation in these resistors. The circuit of Figure 2.26 uses that this current pulse is reduced to zero within one
a capacitor, C2, to provide a low–impedance path around alternation. This has a couple of good effects on the
resistors R1 and R2 and can be used with less–sensitive, operation of the slaving SCR. It prevents gate drive from
higher–current SCRs without increasing the dissipation. This appearing while the SCR is reverse–biased, which would
circuit actually oscillates near the zero crossing point and produce high power dissipation within the device. It also
provides a series of pulses to assure zero–point switching. prevents the slaved SCR from being turned on for additional
The basic circuit is that shown in Figure 2.25. Operation half cycles after the drive is removed from the control SCR.
begins when switch S1 is closed. If the positive alternation is
present, nothing will happen since diode D1 is reverse OPERATION
biased. When the negative alternation begins, capacitor C1 The SCR slaving circuit shown in Figure 2.27 provides a
will charge through resistor R2 toward the limit of voltage set single power pulse to the gate of SCR Q2 each time SCR Q1
by the voltage divider consisting of resistors R1 and R2. As turns on, thus turning Q2 on for the half cycle following the
the negative alternation reaches its peak, C1 will have one during which Q1 was on. Q2 is therefore turned on only
charged to about 40 volts. Line voltage will decrease but C1 when Q1 is turned on, and the load can be controlled by a
cannot discharge because diode D2 will be reverse biased. It signal connected to the gate of Q1 as shown in the
can be seen that C1 and three–layer diode D4 are effectively schematic. The control signal an be either dc or a power
in series with the line. When the line drops to 10 volts, C1 will pulse. If the control signal is synchronized with the power
still be 40 volts positive with respect to the gate of Q1. At this line, this circuit will make an excellent zero–point switch.
time D4 will see about 30 volts and will trigger. This allows C1 During the time that Q1 is on, capacitor C1 is charged
to discharge through D3, D4, the gate of Q1, R2, and R1. through R1, D1 and Q1. While C1 is being charged, D1
This discharge current will continue to flow as the line voltage reverse–biases the base–emitter junction of Q3, thereby
crosses zero and will insure that Q1 turns on at the start of holding it off. The charging time constant, R1, C1, is set long
the positive alternation. Diode D3 prevents reverse gate–cur- enough that C1 charges for practically the entire half cycle.
rent flow and resistor R3 prevents false triggering. The charging rate of C1 follows an “S” shaped curve,
The circuit in Figure 2.26 operates in a similar manner up charging slowly at first, then faster as the supply voltage
to the point where C1 starts to discharge into the gate. The peaks, and finally slowly again as the supply voltage
discharge path will now be from C1 through D3, D4, R3, the decreases. When the supply voltage falls below the voltage
gate of Q1, and capacitor C2. C2 will quickly charge from this across C1, diode D1 becomes reverse biased and the
high pulse of current. This reduces the voltage across D4 base–emitter of Q3 becomes forward biased. For the values
causing it to turn off and again revert to its blocking state. shown, this occurs approximately 6° before the end of the
Now C2 will discharge through R1 and R2 until the voltage on half cycle conduction of Q1. The base current is derived from
D4 again becomes sufficient to cause it to break back. This the energy stored in C1. This turns on Q3, discharging C1
repetitive exchange of charge from C1 to C2 causes a series through Q3 and into the gate of Q2. As the voltage across C1
of gate–current pulses to flow as the line voltage crosses decreases, the base drive of Q3 decreases and somewhat
zero. This means that Q1 will again be turned on at the start limits the collector current. The current pulse must last until
of each positive alternation as desired. Resistor R3 has been the line voltage reaches a magnitude such that latching
added to limit the peak gate current. current will exist in Q2. The values shown will deliver a

AN SCR SLAVING CIRCUIT

An SCR slaving circuit will provide full–wave control of an
ac load when the control signal is available to only one of a 10 k
2W R1
1000 W MAX
pair of SCRs. An SCR slaving circuit is commonly used
where the master SCR is controlled by zero–point switching. 1N4004
Zero–point switching causes the load to receive a full cycle of 120 VAC + 5 µF
60 Hz C1 50 V
line voltage whenever the control signal is applied. The duty Q3
Q1
cycle of the control signal therefore determines the average 2N6397 CONTROL MPS
Q2
amount of power supplied to the load. Zero–point switching is SCR 3638
2N6397
necessary for large loads such as electric heaters because INPUT SIGNAL
conventional phase–shift techniques would generate an *1000 WATT LOAD. SEE TEXT.
excessive amount of electro–magnetic interference (EMI).
Figure 2.27. SCR Slave Circuit

Theory and Applications Motorola Thyristor Device Data

1.2–18
current pulse which peaks at 100 mA and has a magnitude current duration are controlled by the values of R1 and C1.
greater than 50 mA when the anode–cathode voltage of Q2 The values chosen provide sufficient drive for “shorted
reaches plus 10 volts. This circuit completely discharges C1 emitter” SCRs which typically require 10 to 20 mA to fire. The
during the half cycle that Q2 is on. This eliminates the particular SCR used must be capable of handling the
possibility of Q2 being slaved for additional half cycles after maximum current requirements of the load to be driven; the 8
the drive is removed from Q1. The peak current and the ampere, 200 V SCRs shown will handle a 1000 watt load.

Motorola Thyristor Device Data Theory and Applications

1.2–19
Theory and Applications Motorola Thyristor Device Data
1.2–20
 CHAPTER 3
THYRISTOR DRIVERS AND TRIGGERING

Triggering a thyristor requires meeting its gate energy 1.0

specifications and there are many ways of doing this. In W ≥ BASE WIDTH
general, the gate should be driven hard and fast to ensure L ≥ DIFFUSION LENGTH
complete gate turn on and thus minimize di/dt effects. Usually
this means a gate current of at least three times the gate turn 0.8
on current with a pulse rise of less than one microsecond and

a , COMMON BASE CURRENT GAIN + 0.1

a pulse width greater than 10 microseconds. The gate can W
also be driven by a dc source as long as the average gate L

+ 0.5
power limits are met. 0.6
W
+ 1.0
Some of the methods of driving the gate include: L W
1) Direct drive from logic families of transistors
L
2) Opto triac drivers
3) Programmable unijunction transistors (PUTs) 0.4
4) Silicon bilateral switches (SBSs)
5) SIDACs
In this chapter we will discuss all of these, as well as some 0.2
of the important design and application considerations in
triggering thyristors in general. In the chapter on applications,
we will also discuss some additional considerations relating
to drivers and triggers in specific applications. 0
10–3 10–2 10–1 1.0 10 102

PULSE TRIGGERING OF SCRs EMITTER CURRENT DENSITY (mA/mm2)

GATE TURN–ON MECHANISM Figure 3.1. Typical Variation of Transistor α with

Emitter Current Density
The turn–on of PNPN devices has been discussed in many
papers where it has been shown that the condition of
a2 IG ) ICS1 ) ICS2
switching is given by dv = 0 (i.e., α1 + α2 = 1, where α1 and
di I
A
+ 1*a *a
(1)
α2 are the current amplification factors of the two “transis- 1 2
tors.’’ However, in the case of an SCR connected to a reverse Definitions and derivations are given in Appendix I. Note that
gate bias, the device can have α1 + α2 = 1 and still stay in the the anode current, IA, will increase to infinity as α1 + α2 = 1. This
u
blocking state. The condition of turn–on is actually α1 + α2 1. analysis is based upon the assumption that no majority
The current amplification factor, α, increases with emitter carrier current flows out of the gate circuit. When no such
current; some typical curves are shown in Figure 3.1. The assumption is made, the condition for turn–on is given by:

+ 1 *a a1
monotonical increase of α with IE of the device in the blocking
state makes the regeneration of current (i.e., turn–on) IK
(2)
possible. IA 2
Using the two transistor analysis, the anode current, IA,
can be expressed as a function of gate current, IG, as: which corresponds to α1 + α2 u1 (see Appendix I).

Motorola Thyristor Device Data Theory and Applications

1.3–1
 J1 J2 J3 The collector emits holes back to J1 and electrons to J3 until
a steady state continuity of charge is established.
IA IK During the regeneration process, the time it takes for a
P1 N1 P2 N2 minority carrier to travel across a base region is the transit
ANODE CATHODE time, t, which is given approximately as:

+ base width
(A) (K)
where Wi
IG t1 + W2D2ii D i + diffusion length
(3)

GATE (G)
(The subscript “i’’ can be either 1 or 2 to indicate the
Figure 3.2. Schematic Structure of an SCR, Positive appropriate base.) The time taken from the start of the gate
Currents Are Defined as Shown by the Arrows trigger to the turn–on of the device will be equal to some
multiple of the transit time.

Current regeneration starts when charge or current is

introduced through the gate (Figure 3.2). Electrons are CURRENT PULSE TRIGGERING
injected from the cathode across J3; they travel across the Current pulse triggering is defined as supplying current
P2 “base’’ region to be swept out by the collector junction, through the gate to compensate for the carriers lost by
J2, and thrown into the N1 base. The increase of majority recombination in order to provide enough current to sustain
carrier electrons in region N1 decreases the potential in increasing regeneration. If the gate is triggered with a current
region N1, so that holes from P1 are injected across the pulse, shorter pulse widths require higher currents as shown
junction J1, into the N1 “base’’ region to be swept across J2, by Figure 3.3(a). Figure 3.3(a) seems to indicate there is a
and thrown into the P2 “base’’ region. The increase in the constant amount of charge required to trigger on the device
potential of region P2 causes more electrons to be injected when IG is above a threshold level. When the charge
into P2, thereby repeating the cycle. Since α increases with required for turn–on plotted versus pulse current or pulse
the emitter current, an increase of regeneration takes place width, there is an optimum range of current levels or pulse
u
until α1 + α2 1. Meanwhile, more carriers are collected than widths for which the charge is minimum, as shown in region A
emitted from either of the emitters. The continuity of charge of Figure 3.3(b) and (c). Region C shows that for lower
flow is violated and there is an electron build–up on the N1 current levels (i.e., longer minimum pulse widths) more
side of J2, and a hole build–up on the P2 side. When the charge is required to trigger on the device. Region B shows
inert impurity charges are compensated for by injected increasing charge required as the current gets higher and the
majority carriers, the junction J2 becomes forward biased. pulse width smaller.

100 100
VAK = 10 V VAK = 10 V
TA = 25°C TA = 25°C
50
i G , MINIMUM GATE TRIGGER CURRENT (mA)

80
Qin, MINIMUM TRIGGER CHARGE (nc)

I G THRESHOLD

LOW HIGH UNIT

20 UNIT
60
HIGH UNIT C A B
10

40
LOW 5.0
I G THRESHOLD

UNIT C A B

20
2.0
IG THRESHOLD

0 1.0
0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 2.0 5.0 10 20 50 100
t, PULSE WIDTH (ms) iG, GATE CURRENT (mA)

Figure 3.3(a). Typical Variation of Minimum Gate Figure 3.3(b). Variation of Charge versus Gate Current
Current Required to Trigger

Theory and Applications Motorola Thyristor Device Data

1.3–2
 100 3.4(a), it can be deduced that the total current amplification
factor, αT = α1 + α2, has a characteristic curve as shown in
VAK = 10 V
Figure 3.4(b). (The data does not correspond to the data of
T = 25°C
50 Figure 3.3 — they are taken for different types of devices.)
HIGH UNIT The gate current levels in region A of Figure 3.3 corre-
spond to the emitter (or anode) currents for which the slope of
Q in , MINIMUM TRIGGER CHARGE (nc)

(Q = it) the αT curve is steepest (Figure 3.4(b)). In region A the rate

20 that αT builds up with respect to changes of IE (or IA) is high,
little charge is lost by recombination, and therefore, a
B A C minimum charge is required for turn–on.
10 In region C of Figure 3.3, lower gate current corresponds to
small IE (or IA) for which the slope of αT, as well as αT itself, is
LOW
UNIT
small. It takes a large change in IE (or IA) in order to build up
5.0 αT. In this region, a lot of the charge supplied through the gate
is lost by recombination. The charge required for turn–on
increases markedly as the gate current is decreased to the
threshold level. Below this threshold, the device will not turn
2.0 on regardless of how long the pulse width becomes. At this
point, the slope of αT is equal to zero; all of the charge
supplied is lost completely in recombination or drained out
1.0
0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 through gate–cathode shunt resistance. A qualitative analysis
of variation of charge with pulse width at region A and C is
t, MINIMUM PULSE WIDTH (ms)
discussed in Appendix II.
In region B, as the gate current level gets higher and the
Figure 3.3(c). Variation of Charge versus Minimum
pulse width smaller, there are two effects that contribute to an
Pulse Width
increasing charge requirement to trigger–on the device: (1)
the decreasing slope of αT and, (2) the transit time effect. As
The charge characteristic curves can be explained mentioned previously, it takes some multiple of the transit
qualitatively by the variation of current amplification (αT) time for turn–on. As the gate pulse width decreases to N (tN1
with respect to emitter current. A typical variation of α1 and + tP2) or less, (where N is a positive real number, tN1 = transit
α2 for a thyristor is shown in Figure 3.4(a). From Figure time of base N1, and tP2 = transit time of base P2) the amount

1.0 1.4

N–P–N SECTION a2
1.2
0.8
B
a , CURRENT AMPLIFICATION FACTOR
a , CURRENT AMPLIFICATION FACTOR

1.0

A
0.6
0.8

0.6 C
0.4
P–N–P SECTION a1

0.4

0.2
0.2

0 0
0.1 1.0 10 100 300 0.1 1.0 10 100 300
IE, EMITTER CURRENT (mA) IE, EMITTER CURRENT (mA)

Figure 3.4(a). The Variation of α1 and α2 with Emitter Figure 3.4(b). Typical Variation of αT versus Emitter
Current for the Two Sections of Two Typical Current
Silicon Controlled Rectifiers

Motorola Thyristor Device Data Theory and Applications

1.3–3
of current required to turn–on the device should be large Consider the gate current waveform in Figure 3.6; the
enough to flood the gate to cathode junction nearly instanta- triggering pulse width is made large enough such that τ tfl; uu
neously with a charge which corresponds to IE (or IA) high the threshold trigger current is shown as Ithr. All of the charge
enough to give αT 1. u supplied at a transient current level less than Ithr is lost by
recombination, as shown in the shaded regions.
CAPACITANCE CHARGE TRIGGERING The gate spreading resistance (r′G) of the gate junction
varies inversely with peak current; the higher the peak
Using a gate trigger circuit as shown in Figure 3.5, the
current, the smaller the gate spreading resistance. Variation
charge required for turn–on increases with the value of
of gate spreading resistance measured by the method of
capacitance used as shown in Figure 3.7. Two reasons may
Time Domain Reflectometry is plotted in Figure 3.8.
account for the increasing charge characteristics:
From the data of Figure 3.7, it is clear that for larger
1) An effect due to threshold current. values of capacitance a lower voltage level is required for
2) An effect due to variation of gate spreading resistance. turn–on. The peak current of the spike in Figure 3.6 is given
by I pk ∆V
R s r′ G
+ )
; the smaller ∆V, the smaller Ipk. Smaller

TO Ipk in turn yields large r′G, so that r′G is dependent on the

COMMUTATING value of capacitance used in capacitance charge triggering.
CIRCUIT This reasoning is confirmed by measuring the fall time of the
SCR gate trigger voltage and calculating the transient gate

C
spreading resistance, r′G, from: R s r′ G
tf
2.2 C
. Results ) +
RS are plotted in Figure 3.9. As expected, r′G increases with
D V1 increasing values of capacitance used. Referring back to
0 Figure 3.6, for the same amount of charge (C ∆V), the larger
the (Rs + r′G)C time constant of the current spike, the more
charge under the threshold level is lost in recombination.
Increasing the value of C will increase the time constant more
rapidly than if r′G were invariant. Therefore, increasing the
value of C should increase the charge lost as shown in
Figure 3.5. Gate Circuit of Capacitance Charge Figure 3.7. Note that a two order of magnitude increase in
Triggering capacitance increased the charge by less than 3:1.

DV1 e *t
90%
DV1
Ȁ ) RS
r G1 Ȁ ) RS)C1
(r G 1
15

r G1Ȁ ) RS VAK = 10 V HIGH UNIT

DV2 *t
Q in , MINIMUM TRIGGER CHARGE, Q(nc)

e*
10 TA = –15°C
rȀG 2 ) R (rȀG 2 ) R S)C 2
DV2 S 7.0
Ȁ ) RS
r G2
ÉÉÉ
ÇÇÇÇ Ithr

ÉÉÉ
ÇÇÇÇ
5.0
10% II
I
tf1
3.0 LOW UNIT
tf2
PULSE WIDTH, t
2.0
tfi = 2.2 (r′G1 + RS)C1
SHADED AREA I = |(r′G1 + RS)(C1)|(Ithr)
C1 t C2 PULSE WIDTH = 50 ms
DV1C1 + DV2C2
SHADED AREA II = |(r′G2 + RS)(C2)|(Ithr)
1.0
100 200 500 1000 2000 5000 10,000
|(r′G1 + RS)(C1)|(Ithr) < |(r′G2 + RS)(C2) |(Ithr) C, CAPACITANCE (pF)

Figure 3.7. Variation of Trigger Charge versus

Figure 3.6. Gate Current Waveform in Capacitance Capacitance Used
Charge Triggering

Theory and Applications Motorola Thyristor Device Data

1.3–4
 3.0 40

NORMALIZED GATE SPREADING RESISTANCE IA = 1 A VAK = 10 V

2.0
HIGH UNIT TA = 25°C T = 25°C
VAK = 10 V

r ′G , GATE SPREADING RESISTANCE ( W)

30
1.0

0.7 LOW UNIT

0.5
20

0.3 Z0 = 50 W (R S ) rȀG ) 2.2C

tf

0.2
0.1 20 50 100 200 500 1000 10
GATE CURRENT (mA)

Figure 3.8. Variation of Gate Spreading Resistance

versus Gate Peak Current 0
200 300 500 1000 2000
C, CAPACITANCE (pF)

EFFECT OF TEMPERATURE Figure 3.9. Variation of Transient Base Spreading

Resistance versus Capacitance
The higher the temperature, the less charge required to
turn on the device, as shown in Figure 3.10. At the range of
temperatures where the SCR is operated the life time of 20
minority carriers increases with temperature; therefore less VAK = 10 V
charge into the gate is lost in recombination. t = GATE CURRENT PULSE WIDTH
As analyzed in Appendix II, there are three components of (Q = it)
charge involved in gate triggering: (1) Qr, charge lost in
recombination, (2) Qdr, charge drained out through the
Q in , MINIMUM TRIGGER CHARGE (nc)

built–in gate–cathode shunt resistance, (3) Qtr, net charge for

triggering. All of them are temperature dependent. Since the
temperature coefficient of voltage across a p–n junction is
10
t = 1 ms
small, Qdr may be considered invariant of temperature. At the
9.0
temperature range of operation, the temperature is too low to
give rise to significant impurity gettering, lifetime increases 8.0 t = 300 ns
with temperature causing Qr to decrease with increasing
temperature. Also, Qtr decreases with increasing tempera- 7.0
t = 500 ns
ture because at a constant current the αT of the device in the t = 100 ns
blocking state increases with temperature;7 in other words, to 6.0
attain αT = 1 at an elevated temperature, less anode current,
hence gate current [see equation (3) of Appendix I], is 5.0
needed; therefore, Qtr decreases. The input charge, being
equal to the sum of Qtr, Qr, and Qdr, decreases with
4.0
increasing temperature. –15 +25 +65 +105
The minimum current trigger charge decreases roughly
T, TEMPERATURE (°C)
exponentially with temperature. Actual data taken on an
MCR729 deviate somewhat from exponential trend (Fig- Figure 3.10. Variation of Q versus Temperature
ure 3.10). At higher temperatures, the rate of decrease is
less; also for different pulse widths the rates of decrease of
Qin are different; for large pulse widths the recombination
charge becomes more significant than that of small pulse pulse widths. These effects are analyzed in Appendix II
widths. As the result, it is expected and Figure 3.10 shows [equation (7), page 1–9–2]. The theory and experiment
that Qin decreases more rapidly with temperature at high agree reasonably well.

Motorola Thyristor Device Data Theory and Applications

1.3–5
EFFECT OF BLOCKING VOLTAGE by the voltage at which the device is blocking prior to turn–on;
this reflects that the exponent, n, in equation (6) is small.
An SCR is an avalanche mode device; the turn–on of the
device is due to multiplication of carriers in the middle EFFECT OF GATE CIRCUIT
collector junction. The multiplication factor is given by the
empirical equation As mentioned earlier, to turn on the device, the total
· 1 + amplification factor must be greater than unity. This means
*
M (6) that if some current is being drained out of the gate which
1 ( V )n
VB bleeds the regeneration current, turn–on will be affected. The
where higher the gate impedance, the less the gate trigger charge.

M 5 Multiplication factor Since the regenerative current prior to turn–on is small, the
gate impedance only slightly affects the required minimum
V 5 Voltage across the middle “collector’’ junction trigger charge; but in the case of over–driving the gate to
achieve fast switching time, the gate circuit impedance will
(voltage at which the device is blocking prior to
turn–on) have noticeable effect.

VB 5 Breakdown voltage of the middle “collector’’ junction EFFECT OF INDUCTIVE LOAD

n 5 Some positive number The presence of an inductive load tends to slow down the
change of anode current with time, thereby causing the
Note as V is increased, M also increases and in turn α
required charge for triggering to increase with the value of
increases (the current amplification factor α = γδβM where
γ 5
Emitter efficiency, β Base transport factor, and δ 5 5 inductance. For dc or long pulse width current triggering, the
inductive load has little effect, but its effect increases
Factor of recombination).
markedly at short pulse widths, as shown in Figure 3.12. The
The larger the V, the larger is α T. It would be expected for increase in charge occurs because at short pulse widths, the
the minimum gate trigger charge to decrease with increasing trigger signal has decreased to a negligible value before the
V. Experimental results show this effect (see Figure 3.11). For anode current has reached a level sufficient to sustain
the MCR729, the gate trigger charge is only slightly affected turn–on.

10 80
9.0
8.0
7.0
#1
6.0
Q in , MINIMUM TRIGGER CHARGE (nc)

#2 60
Q in , MINIMUM TRIGGER CHARGE (nc)

5.0 L = 100 mH
#3
4.0

40
3.0
L = 10 mH
L = 0 mH
2.0
20
TA = 25°C
PW = 500 ns TA = 25°C
0.05 mF CAP. DISCHARGE VAK = 10 V

1.0 0
10 20 30 50 100 200 500 1000 30 50 70 100 200 300 500 700 1000
VAK, ANODE VOLTAGE (V) t, MINIMUM PULSE WIDTH (ns)

Figure 3.11. Variation of Current Trigger Charge versus Figure 3.12. Effect of Inductance Load on Triggering
Blocking Voltage Prior to Turn–On Charge

Theory and Applications Motorola Thyristor Device Data

1.3–6
USING NEGATIVE BIAS AND SHUNTING current by use of an external shunt resistor ranged typically
between 5 and 75 percent, whereas with negative bias, the
Almost all SCR’s exhibit some degree of turn–off gain. At range of improvement ran typically between 2–1/2 and 7
normal values of anode current, negative gate current will not times the open gate value. Note that the holding current
have sufficient effect upon the internal feedback loop of the curves are normalized and are referred to the open gate value.
device to cause any significant change in anode current.
However, it does have a marked effect at low anode current SPREAD OF 5 DEVICES
levels; it can be put to advantage by using it to modify certain 6.0
device parameters. Specifically, turn–off time may be reduced
and hold current may be increased. Reduction of turn–off time

NORMALIZED HOLDING CURRENT

and increase of hold current are useful in such circuits as
inverters or in full–wave phase control circuits in which
inductance is present. 4.0
Negative gate current may, of course, be produced by use
of an external bias supply. It may also be produced by taking
advantage of the fact that during conduction the gate is
positive with respect to the cathode and providing an external 2.0
conduction path such as a gate–to–cathode resistor. All
Motorola SCR’s, with the exception of sensitive gate devices,
are constructed with a built in gate–to–cathode shunt, which
produces the same effect as negative gate current. Further 0
change in characteristics can be produced by use of an 0 –2.0 –4.0 –6.0 –8.0 –10
external shunt. Shunting does not produce as much of a GATE–TO–CATHODE VOLTAGE (VOLTS)
change in characteristics as does negative bias, since the
negative gate current, even with an external short circuit, is Figure 3.13(b). Normalized Holding Current
limited by the lateral resistance of the base layer. When using versus Gate–to–Cathode Voltage
external negative bias the current must be limited, and care
must be taken to avoid driving the gate into the avalanche
region. AVERAGE 10 DEVICES
The effects of negative gate current are not shown on the 6.0
device specification sheets. The curves in Figure 3.13
represent measurements made on a number of SCRs, and
IF = 10 A
TURN–OFF TIME ( m s)

should therefore not be considered as spec limits. They do,

however, show definite trends. For example, all of the SCRs 4.0
showed an improvement in turn–off time of about one–third
by using negative bias up to the point where no further IF = 5 A
significant improvement was obtained. The increase in hold

2.0

SPREAD OF 5 DEVICES
1.6
0
0 –5.0 –10
NORMALIZED HOLDING CURRENT

GATE–TO–CATHODE VOLTAGE (VOLTS)

1.4
Figure 3.13(c). Turn–Off Time versus Bias

1.2
REDUCING di/dt — EFFECT FAILURES
Figure 3.14 shows a typical SCR structural cross section
(not to scale). Note that the collector of transistor 1 and the
1.0
base of transistor 2 are one and the same layer. This is also
true for the collector of transistor 2 and the base of transistor
1.0 10 100 1000 5000 1. Although for optimum performance as an SCR the base
GATE–TO–CATHODE RESISTANCE (OHMS) thicknesses are great compared to a normal transistor,
nevertheless, base thickness is still small compared to the
Figure 3.13(a). Normalized Holding Current
lateral dimensions. When applying positive bias to the gate,
versus Gate–to–Cathode Resistance
the transverse base resistance, spreading resistance or rb′
will cause a lateral voltage drop which will tend to forward
bias those parts of the transistor 1 emitter–junction closest to
the base contact (gate) more heavily, or sooner than the
portions more remote from the contact area. Regenerative

Motorola Thyristor Device Data Theory and Applications

1.3–7
action, consequently will start in an area near the gate Let us superimpose a current curve (b) on the anode–to–
contact, and the SCR will turn on first in this area. Once on, cathode voltage versus time curve to better understand this.
conduction will propagate across the entire junction. If we allow the current to rise rapidly to a high value we find by
multiplying current and voltage that the instantaneous
T2 T1 CATHODE GATE dissipation curve (c) reaches a peak which may be hundreds
LAYER
of times the steady state dissipation level for the same value
NO. 4 (E) of current.
NO. 3 (C) (B) At the same time it is important to remember that the

ÉÉÉÉÉÉ
dissipation does not take place in the entire junction, but is
NO. 2 (B) (C)

ÉÉ
confined at this time to a small volume. Since temperature is
N
NO. 1 (E) related to energy per unit volume, and since the energy put
P into the device at high current levels may be very large while
N the volume in which it is concentrated is very small, very high
spot temperatures may be achieved. Under such conditions,

ÉÉÉÉÉÉÉÉÉÉ
P
it is not difficult to attain temperatures which are sufficient to

ÉÉÉÉÉÉÉÉÉÉ
ANODE cause localized melting of the device.
Even if the peak energy levels are not high enough to be
Figure 3.14(a). Construction of Typical SCR destructive on a single–shot basis, it must be realized that
since the power dissipation is confined to a small area, the
power handling capabilities of the device are lessened. For
pulse service where a significant percentage of the power
per pulse is dissipated during the fall–time interval, it is not
acceptable to extrapolate the steady state power dissipation
capability on a duty cycle basis to obtain the allowable peak
pulse power.
TYPICAL SCR
CONSTRUCTION
SHOWING THE ANODE TO CATHODE ANODE
DIE IN PROPER VOLTAGE (a) CURRENT (b)
SCALE…
100
PERCENT OF MAXIMUM (%)

INSTANTANEOUS
POWER
DISSIPATION (c)

50
Figure 3.14 (b)
The phenomenon of di/dt failure is related to the turn–on
mechanism. Let us look at some of the external factors
involved and see how they contribute. Curve 3.15(a) shows
the fall of anode–to–cathode voltage with time. This fall 0
follows a delay time after the application of the gate bias. The 0.1 1.0
delay time and fall time together are called turn–on time, and, TIME (ms)
depending upon the device, will take anywhere from tens of
Figure 3.15. Typical Conditions — Fast–Rise, High
nanoseconds up to a few microseconds. The propagation of
Current Pulse
conduction across the entire junction requires a considerably
longer time. The time required for propagation or equalization The final criterion for the limit of operation is junction
of conduction is represented approximately by the time temperature. For reliable operation the instantaneous junc-
required for the anode–to–cathode voltage to fall from the 10 tion temperature must always be kept below the maximum
percent point to its steady state value for the particular value junction temperature as stated on the manufacturer’s data
of anode current under consideration (neglecting the change sheet. Some SCR data sheets at present include information
due to temperature effects). It is during the interval of time on how to determine the thermal response of the junction to
between the start of the fall of anode–to–cathode voltage and current pulses. This information is not useful, however, for
the final equalization of conduction that the SCR is most determining the limitations of the device before the entire
susceptible to damage from excessive current. junction is in conduction, because they are based on
measurements made with the entire junction in conduction.

Theory and Applications Motorola Thyristor Device Data

1.3–8
 At present, there is no known technique for making a 70

INSTANTANEOUS POWER DISSIPATION (kW)

reasonably accurate measurement of junction temperature in
the time domain of interest. Even if one were to devise a 60
method for switching a sufficiently large current in a short PEAK ANODE CURRENT = 500 A
enough time, one would still be faced with the problem of 50
IGT = 2 A
charge storage effects in the device under test masking the
40
thermal effects. Because of these and other problems, it IGT = 17 mA
becomes necessary to determine the device limitations
30
during the turn–on interval by destructive testing. The
resultant information may be published in a form such as a 20
maximum allowable current versus time, or simply as a
maximum allowable rate of rise of anode current (di/dt). 10
Understanding the di/dt failure mechanism is part of the
problem. To the user, however, a possible cure is infinitely 0
more important. There are three approaches that should be 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
considered. t, TIME (ms)
Because of the lateral base resistance the portion of the
gate closest to the gate contact is the first to be turned on Figure 3.16(b). Effect of Gate Drive On
because it is the first to be forward biased. If the minimum Turn–On Dissipation
gate bias to cause turn–on of the device is used, the spot in
which conduction is initiated will be smallest in size. By If the application should require a rate of current rise
increasing the magnitude of the gate trigger pulse to several beyond the rated di/dt limit of the device, then another
times the minimum required, and applying it with a very fast approach may be taken. The device may be turned on to a
rise time, one may considerably increase the size of the spot relatively low current level for a sufficient time for a large part
in which conduction starts. Figure 3.16(a) illustrates the effect of the junction to go into conduction; then the current level
of gate drive on voltage fall time and Figure 3.16(b) shows may be allowed to rise much more rapidly to very high levels.
the improvement in instantaneous dissipation. We may This might be accomplished by using a delay reactor as
conclude from this that overdriving the gate will improve the shown in Figure 3.17. Such a reactor would be wound on a
di/dt capabilities of the device, and we may reduce the stress square loop core so that it would have sharp saturation
on the device by doing so. characteristic and allow a rapid current rise. It is also possible
to make use of a separate saturation winding. Under these
conditions, if the delay is long enough for the entire junction
to go into conduction, the power handling capabilities of the
350 device may be extrapolated on a duty cycle basis.
ANODE TO CATHODE VOLTAGE (VOLTS)

300
PEAK ANODE CURRENT = 500 A
250 + RL

– DELAY
200
IGT = 2 A REACTOR
150 SCR
IGT = 17 mA
100
Figure 3.17. Typical Circuit Use of a Delay Reactor
50

0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 WHY AND HOW TO SNUB THYRISTORS
t, TIME (ms) Inductive loads (motors, solenoids, etc.) present a problem
for the power triac because the current is not in phase with
Figure 3.16(a). Effect of Gate Drive on Fall Time the voltage. An important fact to remember is that since a
triac can conduct current in both directions, it has only a brief
interval during which the sine wave current is passing
through zero to recover and revert to its blocking state. For
A very straightforward approach is to simply slow down the inductive loads, the phase shift between voltage and current
rate of rise of anode current to insure that it stays within the means that at the time the current of the power handling triac
device ratings. This may be done simply by adding some falls below the holding current and the triac ceases to
series inductance to the circuit. conduct, there exists a certain voltage which must appear

Motorola Thyristor Device Data Theory and Applications

1.3–9
across the triac. If this voltage appears too rapidly, the triac IF(ON)
will resume conduction and control is lost. In order to achieve IF(OFF)
control with certain inductive loads, the rate of rise in voltage
(dv/dt) must be limited by a series RC network placed in
AC LINE
parallel with the power triac as shown in Figure 3.18. The
VOLTAGE
capacitor CS will limit the dv/dt across the triac.
The resistor RS is necessary to limit the surge current from
CS when the triac conducts and to damp the ringing of the
capacitance with the load inductance LL. Such an RC AC CURRENT
network is commonly referred to as a “snubber.’’
Figure 3.19 shows current and voltage waveforms for the COMMUTATING
power triac. Commutating dv/dt for a resistive load is typically dv/dt
only 0.13 V/µs for a 240 V, 50 Hz line source and 0.063 V/µs VOLTAGE
for a 120 V, 60 Hz line source. For inductive loads the ACROSS
“turn–off’’ time and commutating dv/dt stress are more difficult t0 POWER TRIAC
to define and are affected by a number of variables such as TIME
back EMF of motors and the ratio of inductance to resistance
(power factor). Although it may appear from the inductive RESISTIVE LOAD
load that the rate or rise is extremely fast, closer circuit
evaluation reveals that the commutating dv/dt generated is IF(ON)
restricted to some finite value which is a function of the load IF(OFF)
reactance LL and the device capacitance C but still may
exceed the triac’s critical commutating dv/dt rating which is
about 50 V/µs. It is generally good practice to use an RC AC LINE
snubber network across the triac to limit the rate of rise (dv/dt) VOLTAGE
to a value below the maximum allowable rating. This snubber
network not only limits the voltage rise during commutation
but also suppresses transient voltages that may occur as a 0
result of ac line disturbances. AC CURRENT
There are no easy methods for selecting the values for RS THROUGH
and CS of a snubber network. The circuit of Figure 3.18 is a POWER TRIAC
COMMUTATING
damped, tuned circuit comprised of RS, CS, RL and LL, and to d dv/dt
a minor extent the junction capacitance of the triac. When the VOLTAGE
triac ceases to conduct (this occurs every half cycle of the ACROSS
line voltage when the current falls below the holding current), t0 POWER TRIAC
the triac receives a step impulse of line voltage which TIME
depends on the power factor of the load. A given load fixes
RL and LL; however, the circuit designer can vary RS and CS. INDUCTIVE LOAD
Commutating dV/dt can be lowered by increasing CS while
RS can be increased to decrease resonant “over ringing’’ of
the tuned circuit.
Figure 3.19. Current and Voltage Waveforms
During Commutation
1 6 R
series network driven by an ac voltage source. The following
differential equation can be obtained by summing the voltage
2 5 RS drops around the circuit;
AC

3
ZERO
CROSSING 4
CS
(R L ) RS) i(t) ) L di(t)
dt
) q c(t)
CS
+ VMsin(wt ) f) (2)
CIRCUIT
LL RL
in which i(t) is the instantaneous current after the switch
LOAD opens, qc(t) is the instantaneous charge on the capacitor, VM is
Figure 3.18. Triac Driving Circuit — with Snubber the peak line voltage, and φ is the phase angle by which the
voltage leads the current prior to opening of the switch. After
differentiation and rearrangement, the equation becomes a
standard second–order differential equation with constant
BASIC CIRCUIT ANALYSIS coefficients.
Figure 3.20 shows an equivalent circuit used for analysis, With the imposition of the boundary conditions that
in which the triac has been replaced by an ideal switch. i(o) = 0 and qc(o) = 0 and with selected values for RL, L, RS
When the triac is in the blocking or non–conducting state, and CS, the equation can be solved, generally by the use
represented by the open switch, the circuit is a standard RLC of a computer. Having determined the magnitude and time

Theory and Applications Motorola Thyristor Device Data

1.3–10
of occurrence of the peak voltage across the thyristor, it is Prior to the advent of the all–diffused SCR, the next step was
then possible to calculate the values and times of the to form the gate–cathode P–N junction by alloying in a
voltages at 10% and 63% of the peak value. This is gold–antimony foil. This produced a silicon P–N junction of the
necessary in order to compute the dv/dt stress as defined by regrown type over most of the junction area. However, a
the following equation: resistive rather than semiconductor junction would form
dv
dt
+ **
V2 V1
t2 t1
where the molten alloy terminated at the surface. This formed
an internal RGK, looking in at the gate–cathode terminals, that
reduced the “sensitivity’’ of the SCR.
where V1 and t1 are the voltage and time at the 10% point Modern practice is to produce the gate–cathode junction by
and V2 and t2 are the voltage and time at the 63% point. masking and diffusing, a much more controllable process. It
Solution of the differential equation for assumed load produces a very clean junction over the entire junction area
conditions will give the circuit designer a starting point for with no unwanted resistive paths. Good dv/dt performance
selecting RS and CS. by larger SCRs, however, requires resistive paths distributed
Because the design of a snubber is contingent on the load, over the junction area. These are diffused in as emitter shorts
it is almost impossible to simulate and test every possible and naturally desensitize the device. Smaller SCRs may rely
combination under actual operating conditions. It is advisable on an external RGK because the lateral resistance in the gate
to measure the peak amplitude and rate of rise of voltage layer is small enough to prevent leakage and dV/dt induced
across the triac by use of an oscilloscope, then make the final currents from forward biasing the cathode and triggering the
selection of RS and CS experimentally. Additional comments SCR.
about circuit values for SCRs and Triacs are made in Chapter 6. Figure 3.22(a) shows the construction of a sensitive gate
SCR and the path taken by leakage current flowing out
through RGK. Large SCRs (Figure 3.22(b)) keep the path
length small by bringing the gate layer up to contact the
L RL
cathode metal. This allows the current to siphon out all–round
RS the cathode area.
LOAD
AC
When the chip dimensions are small there is little penalty in
POWER CS placing the resistor outside the package. This gives the
SOURCE circuit designer considerable freedom in tailoring the electri-
cal properties of the SCR. This is a great advantage when
low trigger or holding current is needed. Still, there are
trade–offs in the maximum allowable junction temperature
Figure 3.20. Equivalent Circuit used for Analysis
and dV/dt immunity that go with larger resistor values.
Verifying that the design is adequate to prevent circuit upset
by heat or noise is important. The rated value for RGK is
usually 1 K Ohm. Lower values improve blocking and turn–off
USING SENSITIVE GATE SCRs capability.
In applications of sensitive gate SCRs such as the
Motorola 2N6237, the gate–cathode resistor, RGK (Figure K DIFFUSED EMITTER
K CATHODE G K SHORTS G
3.21) is an important factor. Its value affects, in varying
degrees, such parameters as IGT, VDRM, dv/dt, IH, leakage G
METAL
current, and noise immunity. N N N N
P–

ÉÉÉÉÉÉÉÉÉÉÉÉÉ
+ DIFFUSED P
ANODE (A) N BASE N

ÉÉÉÉÉÉÉÉÉÉÉÉÉ
P DIFFUSED P
A A A
GATE (G) CASE CASE
(a). SIMPLE (b). SHORTED EMITTER
RGK CONSTRUCTION CONSTRUCTION

CATHODE (K) Figure 3.22. Sensitive Gate SCR Construction

Figure 3.21. Gate–Cathode Resistor, RGK The sensitive gate SCR, therefore, is an all–diffused
design with no emitter shorts. It has a very high impedance
path in parallel with the gate–cathode P–N diode; the better
the process is the higher this impedance, until a very good
SCR CONSTRUCTION device cannot block voltage in the forward direction without
The initial step in making an SCR is the creation, by an external RGK. This is so, because thermally generated
diffusion, of P–type layers is N–type silicon base material. leakage currents flowing from the anode into the gate

Motorola Thyristor Device Data Theory and Applications

1.3–11
 200 does not always follow the 10° rule below 70°C because of
surface effects.
2N6239 To summarize, the leakage current in a sensitive gate SCR
180 is much more temperature sensitive than voltage sensitive.
TJ = 110°C
IAK CONSTANT Operation at lower junction temperatures allows an increase
in the gate–cathode resistor which makes the SCR–resistor
VAK (VOLTS)

160
combination more “sensitive.’’

140
110

120 2N6239
100
VAK = VDRM = 200 V
IAK CONSTANT
100
0 1K 2K 3K 90

TJ ( °C)
RGK (OHMS)
Figure 3.23(a). VAK versus RGK (Typical) for Constant 80
Leakage Current

70
junction are sufficient to turn on the SCR. The value for
RGK is usually one kilohm and its presence and value 60
affects many other parameters. 1K 5K 10 K 50 K 100 K
RGK (OHMS)
FORWARD BLOCKING VOLTAGE AND CURRENT,
VDRM AND IDRM Figure 3.23(b). TJ versus RGK (Typical) for Constant
The 2N6237 family is specified to have an IDRM, or Leakage Current
anode–to–cathode leakage current, of less than 200 µA at
maximum operating junction temperature and rated VDRM. dv/dt
This leakage current increases if RGK is omitted and, in fact,
the device may well be able to regenerate and turn on. Tests
were run on several 2N6239 devices to establish the CAG
dependency of the leakage current on RGK and to determine
i
its relationship with junction temperature, TJ, and forward
voltage VAK (Figure 3.23a).
RGK
Figure 3.23(a) is a plot of VAK, forward voltage, versus RGK
taken at the maximum rated operating junction temperature
of 110°C. With each device the leakage current, IAK, is set for
a VAK of 200 V, then VAK reduced and RGK varied to Figure 3.23(c). dv/dt Firing of an SCR
re–establish the same leakage current. The plot shows that
the leakage current is not strongly voltage dependent or, 1,000V/ms
conversely, RGK may not be increased for derate.
dv/dt, RATE OF RISE OF ANODE VOLTAGE (V/ m s)

MCR706–6
While the leakage current is not voltage dependent, it is
TJ = 110°C
very temperature dependent. The plot in Figure 3.23(b) of TJ, 400 V PEAK
junction temperature, versus RGK taken at VDRM, the
100V/ms
maximum forward blocking voltage shows this dependence. EXPONENTIAL
For each device (2N6329 again) the leakage current, IAK, METHOD
was measured at the maximum operating junction tempera-
ture of 110°C, then the junction temperature was reduced IGT = 27 mA
and RGK varied to re–establish that same leakage current. 10V/ms
The plot shows that the leakage current is strongly depen- IGT = 5.6 mA
dent on junction temperature. Conversely RGK may be
increased for derated temperature.
A conservative rule of thumb is that leakage doubles every 1V/ms
10°C. If all the current flows out through RGK, triggering will 10 100 1,000 10,000 100,000
not occur until the voltage across RGK reaches VGT. This RGK (W)
implies an allowed doubling of the resistor for every 10°
reduction in maximum junction temperature. However, this Figure 3.23(d). Static dv/dt as a function of
rule should be applied with caution. Static dV/dt may require Gate–Cathode Resistance on two devices
a smaller resistor than expected. Also the leakage current with different sensitivity.

Theory and Applications Motorola Thyristor Device Data

1.3–12
RATE–OF–RISE OF ANODE VOLTAGE, dv/dt gate current that will not fire the device. This requirement
An SCR’s junctions exhibit capacitance due to the separa- conflicts with the basic function of a sensitive gate SCR,
tion of charge when the device is in a blocking state. If an which is to fire at zero or very low gate current, IGT(max).
SCR is subjected to forward dv/dt, this capacitance can Production of devices with a measurable IGT(min) is at best
couple sufficient current into the SCR’s gate to turn it on, as difficult and deliveries can be sporadic!
shown in Figure 3.23(c). RGK acts as a diversionary path for One reason for an IGT(min) requirement might be some
the dv/dt current. (In larger SCRs, where the lateral gate measurable off–state gating circuit leakage current, perhaps
resistance of the device limits the influence of RGK, this path the collector leakage of a driving transistor. Such current can
is provided by the resistive emitter shorts mentioned pre- readily be bypassed by a suitably chosen RGK. The VGT of
viously.) The gate–cathode resistor, then, might be expected the SCR at the temperature in question can be estimated
to have some effect on the dv/dt performance of the SCR. from Figure 3.25, an Ohm’s Law calculation made, and the
Figure 3.23(d) confirms this behavior. The static dV/dt for two resistor installed to define this “won’t fire’’ current. This is a
MCR706 devices varies over several powers of ten with repeatable design well in the control of the equipment
changes in the gate–cathode resistance. Selection of the designer.
external resistor allows the designer to trade dynamic
performance with the amount of drive current provided to the GATE TRIGGER VOLTAGE, VGT
resistor–SCR combination. The sensitive–gate device with The gate–cathode junction is a p–n silicon junction. So the
low RGK provides performance approaching that of an gate trigger voltage follows the diode law and has roughly the
equivalent non–sensitive SCR. This strong dependence does same temperature coefficient as a silicon diode, –2mV/C.
not exist with conventional shorted emitter SCRs because of Figure 3.25 is a plot of VGT versus temperature for typical
their internal resistor. The conventional SCR cannot be made sensitive gate SCRs. They are prone to triggering by noise
more sensitive, but the sensitive–gate device attributes can coupled through the gate circuit because of their low trigger
be reliably set with the resistor to any desired point along the voltage. The smallest noise voltage margin occurs at
sensitivity range. Low values of resistance make the dV/dt maximum temperature and with the most sensitive devices.
performance more uniform and predictable. The curves for
0.9
two devices with different sensitivity diverge at high values of
resistance because the device response becomes more V GT , GATE TRIGGER VOLTAGE (VOLTS)
0.8
dependent on its sensitivity. The resistor is the most HIGH UNIT
important factor determining the static dV/dt capability of the 0.7
IGT = 200 mA @ 300°K
product. Reverse biasing the gate also improves dV/dt. A
0.6
2N6241 improved by a factor of 50 with a 1 volt bias.
0.5
GATE CURRENT, IGT LOW UNIT
The total gate current that a gating circuit must supply is 0.4
IGT = 20 NA @ 300°K
the sum of the current that the device itself requires to fire 0.3
and the current flowing to circuit ground through RGK, as
shown in Figure 3.24. IGT, the current required by the device 0.2
so that it may fire, is usually specified by the device
0.1
manufacturer as a maximum at some temperature (for the –30 –10 10 30 50 70 90 110 130
2N6236 series it is 500 µA maximum at –40°C). The current
JUNCTION TEMPERATURE (°C)
flowing through RGK is defined by the resistor value and by
the gate–to–cathode voltage that the SCR needs to fire. This is Figure 3.25. Typical VGT vs TJ
1 V maximum at –40°C for the 2N6237 series, for example.
HOLDING CURRENT, IH
GATE CURRENT, IGT(min) The holding current of an SCR is the minimum anode
SCR manufacturers sometimes get requests for a sensi- current required to maintain the device in the on state. It is
tive–gate SCR specified with an IGT(min), that is, the maximum usually specified as a maximum for a series of devices (for
instance, 5 mA maximum at 25°C for the 2N6237 series). A
particular device will turn off somewhere between this
ITOT IGT maximum and zero anode current and there is perhaps a
20–to–1 spread in each lot of devices.
Figure 3.26 shows the holding current increasing with
VGT RGK IR decreasing RGK as the resistor siphons off more and more of
the regeneratively produced gate current when the device is
in the latched condition.
Note that the gate–cathode resistor determines the holding
current when it is less than 100 Ohms. SCR sensitivity is the
Figure 3.24. SCR and RGK “Gate’’ Currents determining factor when the resistor exceeds 1 meg Ohm.

Motorola Thyristor Device Data Theory and Applications

1.3–13
 10 capacitor also requires the gate drive circuit to supply
TJ = 25°C enough current to fire the SCR without excessive time delay.
This is particularly important in applications with rapidly rising
u
I H , HOLDING CURRENT, mA
(di/dt 50 A/µs) anode current where a fast rise high
1.0
amplitude gate pulse helps to prevent di/dt damage to the
SCR.
IGT = 1.62 mA
Reverse gate voltage can cause unwanted turn–off of the
SCR. Then the SCR works like a gate turn–off thyristor.
Turn–off by the gate signal is more probable with small SCRs
0.1 because of the short distance between the cathode and gate
regions. Whether turn–off occurs or not depends on many
variables. Even if turn–off does not occur, the effect of high
IGT = 20 NA
reverse gate current is to move the conduction away from the
0.01 gate, reducing the effective cathode area and surge capability.
0.1 1.0 10 100 1,000 Suppressing the reverse gate voltage is particularly important
RGK, GATE–CATHODE RESISTANCE, KW when the gate pulse duration is less than 1 microsecond. Then
the part triggers by charge instead of current so halving of the
Figure 3.26. 2N5064 Holding Current
gate pulse width requires double the gate current. Capaci-
tance coupled gate drive circuits differentiate the gate pulse
This allows the designer to set the holding current over a
(Figure 3.27) leading to a reverse gate spike. The reverse
wide range of possible values using the resistor. Values
gate voltage rating should not be exceeded to prevent
typical of those in conventional non–sensitive devices occur
avalanche damage.
when the external resistor is similar to their internal gate–
This discussion has shown that the use of RGK, the
cathode shorting resistance. The holding current uniformity
gate–cathode resistor, has many implications. Clear under-
also improves when the resistor is small.
standing of its need and its influence on the performance of
the sensitive gate SCR will enable the designer to have
NOISE IMMUNITY better control of his circuit designs using this versatile part.
Changes in electromagnetic and electrostatic fields
coupled into wires or printed circuit lines can trigger these
sensitive devices, as can logic circuit glitches. The result is
more serious than with a transistor since an SCR will latch
on. Careful wire harness design (twisted pairs and adequate
separation from high–power wiring) and printed circuit layout
(gate and return runs adjacent to one another) can minimize
potential problems. A gate cathode network consisting of a
resistor and parallel capacitor also helps. The resistor
provides a static short and is helpful with noise signals of any
frequency. For example, with a 1,000 Ohm resistor, between OPTIONAL
100 µA to 1 mA of noise current is necessary to generate REVERSE
GATE
enough voltage to fire the device. Adding a capacitor sized
SUPPRESSOR
between 0.01 and 0.1 µF creates a noise filter and improves
DIODE
dV/dt by shunting dV/dt displacement current out through the
gate terminal. These components must be placed as close
as possible to the gate and cathode terminals to prevent lead
inductance from making them ineffective. The use of the Figure 3.27. Capacitance Coupled Gate Drive

Theory and Applications Motorola Thyristor Device Data

1.3–14
DRIVERS: PROGRAMMABLE UNIJUNCTION In characterizing the PUT, it is convenient to speak of the
TRANSISTORS Thevenin equivalent circuit for the external gate voltage (VS)
and the equivalent gate resistance (RG). The parameters are
The programmable unijunction transistor (PUT) is a four defined in terms of the divider resistors (R1 and R2) and
layer device similar to an SCR. However, gating is with supply voltage as follows:
respect to the anode instead of the cathode. An external VS + ń )
R1 V1 (R1 R2)
resistive voltage divider accurately sets the triggering voltage
and allows its adjustment. The PUT finds limited application
RG + ń )
R1 R2 (R1 R2)

as a phase control element and is most often used in long Most device parameters are sensitive to changes in VS
duration or low battery drain timer circuits where its high and RG. For example, decreasing RG will cause peak and
sensitivity permits the use of large timing resistors and small valley currents to increase. This is easy to see since RG
capacitors. Like an SCR, the PUT is a conductivity modu- actually shunts the device and will cause its sensitivity to
lated device capable of providing high current output pulses. decrease.

OPERATION OF THE PUT CHARACTERISTICS OF THE PUT

The PUT has three terminals, an anode (A), gate (G), and Table 3.1 is a list of typical characteristics of Motorola’s
cathode (K). The symbol and a transistor equivalent circuit 2N6027/2N6028 of programmable unijunction transistors.
are shown in Figure 3.28. As can be seen from the equivalent The test circuits and test conditions shown are essentially the
circuit, the device is actually an anode–gated SCR. This same as for the data sheet characteristics. The data
means that if the gate is made negative with respect to the presented here defines the static curve shown in Figure
anode, the device will switch from a blocking state to its on 3.29(b) for a 10 V gate reference (VS) with various gate
state. resistances (RG). It also indicates the leakage currents of
these devices and describes the output pulse. Values given
are for 25°C unless otherwise noted.
A
ANODE
(A)
G RT R2
GATE
(G)
+
V1
–
OUTPUT VS R1

(K) CT R0
CATHODE K

Figure 3.28(a). Figure 3.28(b). Figure 3.29(a). Typical Oscillator Circuit

PUT Symbol Transistor Equivalent

The PUT is a complementary SCR when its anode is PEAK POINT

VP
connected like an SCR’s cathode and the circuit bias
VS
voltages are reversed. Negative resistance terminology NEGATIVE RESISTANCE REGION
describes the device characteristics because of the tradition-
VAK

al application circuit. An external reference voltage must be VALLEY POINT

maintained at the gate terminal. A typical relaxation type
oscillator circuit is shown in Figure 3.29(a). The voltage
divider shown is a typical way of obtaining the gate reference. VF
In this circuit, the characteristic curve looking into the VV
anode–cathode terminals would appear as shown in Figure
3.29(b). The peak and valley points are stable operating
points at either end of a negative resistance region. The peak IGAO
IP IV IF
point voltage (VP) is essentially the same as the external gate
IA
reference, the only difference being the gate diode drop.
Since the reference is circuit and not device dependent, it
may be varied, and in this way, VP is programmable. Figure 3.29(b). Static Characteristics

Motorola Thyristor Device Data Theory and Applications

1.3–15
 Table 3.1. Typical PUT Characteristics

Symbol Test Circuit Figure Test Conditions 2N6027 2N6028 Unit

IP 3.64 RG = 1 mΩ 1.25 0.08 µA
RG = 10 kΩ 4 0.70 µA
IV 3.64 RG = 1 MΩ 18 18 µA
RG = 10 kΩ 150 150 µA
VAG (See Figure 3.44)
IGAO VS = 40 V (See Figure 3.45)
IGKS VS = 40 V 5 5 nA
VF Curve Tracer Used IF = 50 mA 0.8 0.8 V
VO 3.67 11 11 V
tr 3.68 40 40 ns

PEAK POINT CURRENT, (IP) PEAK POINT VOLTAGE, (VP)

The peak point is indicated graphically by the static curve. The unique feature of the PUT is that the peak point
Reverse anode current flows with anode voltages less than voltage can be determined externally. This programmable
the gate voltage (VS) because of leakage from the bias feature gives this device the ability to function in voltage
network to the charging network. With currents less than IP, controlled oscillators or similar applications. The triggering or
the device is in a blocking state. With currents above IP, the peak point voltage is approximated by
device goes through a negative resistance region to its on )
V P ≈ V T V S,
state.
where VS is the unloaded divider voltage and VT is the offset
The charging current, or the current through a timing
voltage. The actual offset voltage will always be higher than
resistor, must be greater than IP at VP to insure that a
the anode–gate voltage VAG, because IP flows out of the gate
device will switch from a blocking to an on state in an
just prior to triggering. This makes VT = VAG + IP RG. A
oscillator circuit. For this reason, maximum values of IP are
change in RG will affect both VAG and IP RG but in opposite
given on the data sheet. These values are dependent on
ways. First, as RG increases, IP decreases and causes VAG
VS temperature, and RG. Typical curves on the data sheet
to decrease. Second, since IP does not decrease as fast as
indicate this dependence and must be consulted for most
RG increases, the IP RG product will increase and the actual
applications.
VT will increase. These second order effects are difficult to
The test circuit in Figure 3.30 is a sawtooth oscillator
predict and measure. Allowing VT to be 0.5 V as a first order
which uses a 0.01 µF timing capacitor, a 20 V supply, an
approximation gives sufficiently accurate results for most
adjustable charging current, and equal biasing resistors
applications.
(R). The two biasing resistors were chosen to given an
The peak point voltage was tested using the circuit in
equivalent RG of 1 MΩ and 10 kΩ. The peak point current
Figure 3.30 and a scope with 10 MΩ input impedance across
was measured with the device off just prior to oscillation as
the PUT. A Tektronix, Type W plug–in was used to determine
detected by the absence of an output voltage pulse. The
this parameter.
2N5270 held effect transistor circuit is used as a current
source. A variable gate voltage supply was used to control
this current. FORWARD ANODE–GATE VOLTAGE, (VAG)
The forward anode–to–gate voltage drop affects the peak
VALLEY POINT CURRENT, (IV) point voltage as was previously discussed. The drop is
The valley point is indicated graphically in Figure 3.28. essentially the same as a small signal silicon diode and is
With currents slightly less than IV, the device is in an plotted in Figure 3.31. The voltage decreases as current
unstable negative resistance state. A voltage minimum decreases, and the change in voltage with temperature is
occurs at IV and with higher currents, the device is in a greater at low currents. At 10 nA the temperature coefficient
stable on state. is about –2.4 V/°C and it drops to about –1.6 mV/°C at
When the device is used as an oscillator, the charging 10 mA. This information is useful in applications where it is
current or the current through a timing resistor must be less desirable to temperature compensate the effect of this diode.
than IV at the valley point voltage (VV). For this reason,
minimum values for IV are given on the data sheet for RG = GATE–CATHODE LEAKAGE CURRENT, (IGKS)
10 kΩ. With RG = 1 MΩ, a reasonable “low’’ is 2 µA for all The gate–to–cathode leakage current is the current that
devices. flows from the gate to the cathode with the anode shorted to
When the device is used in the latching mode, the anode the cathode. It is actually the sum of the open circuit
current must be greater than IV. Maximum values for IV are gate–anode and gate–cathode leakage currents. The shorted
given with RG = 1 MΩ. All devices have a reasonable “high’’ leakage represents current that is shunted away from the
of 400 µA IV with RG = 10 kΩ. voltage divider.

Theory and Applications Motorola Thyristor Device Data

1.3–16
 IP, IV
NOTES: 1) VARIOUS SENSE RESISTORS (RS) ARE USED TO
KEEP THE SENSE VOLTAGE NEAR 1 Vdc.
RS
G S 2) THE GATE SUPPLY (VG) IS ADJUSTED FROM
– + 2N5270 ABOUT –0.5 V TO +20 V.
VG D
Vp
+ R
20 V 0.01 mF
–

PUT OUTPUT PULSE

UNDER
TEST
R 20
R = 2 RG
VS = 10 V

Figure 3.30. Test Circuit for IP, VP and IV

GATE–ANODE LEAKAGE CURRENT, (IGAO) and dynamic impedance, but is also affected by switching
The gate–to–anode leakage current is the current that speed. This is particularly true when small capacitors (less
flows from the gate to the anode with the cathode open. It than 0.01 µF) are used for timing since they lose part of
is important in long duration timers since it adds to the their charge during the turn on interval. The use of a
charging current flowing into the timing capacitor. The relatively large capacitor (0.2 µF) in the test circuit of
typical leakage currents measured at 40 V are shown in Figure 3.33 tends to minimize this last effect. The output
Figure 3.32. Leakage at 25°C is approximately 1 nA and voltage is measured by placing a scope across the 20 ohm
the current appears to double for about every 10°C rise in resistor which is in series with the cathode lead.
temperature.
RISE TIME, (tr)
FORWARD VOLTAGE, (VF)
Rise time is a useful parameter in pulse circuits that use
The forward voltage (VF) is the voltage drop between the
capacitive coupling. It can be used to predict the amount of
anode and cathode when the device is biased on. It is the
current that will flow between these circuits. Rise time is
sum of an offset voltage and the drop across some internal
specified using a fast scope and measuring between 0.6 V
dynamic impedance which both tend to reduce the output
and 6 V on the leading edge of the output pulse.
pulse. The typical data sheet curve shows this impedance to
be less than 1 ohm for up to 2 A of forward current.
MINIMUM AND MAXIMUM FREQUENCY
PEAK OUTPUT VOLTAGE, (VO) In actual tests with devices whose parameters are known,
The peak output voltage is not only a function of V P, VF it is possible to establish minimum and maximum values of

0.9 70

0.7 60
TEMPERATURE ( °C)
VAG (VOLTS)

0.5 50
25°C

75°C
0.3 40

0.1 30

0 20
0.01 0.1 1.0 10 100 1K 10 K 1.0 10
IAG (mA) IGAO, GATE TO ANODE LEAKAGE CURRENT (nA)

Figure 3.31. Voltage Drop of 2N6027 Series Figure 3.32. Typical Leakage Current of the 2N6027,
2N6028 Reverse Voltage Equals 40 V

Motorola Thyristor Device Data Theory and Applications

1.3–17
 minimum value of timing resistance is obtained using the
following rule of thumb:
510 k
A 16 k R (min)+ * ń
2(V 1 V V) I V
1 mF
where the valley voltage (VV) is often negligible.
+ To obtain minimum frequency, it is desirable to use high
20 V
–
0.2 mF G values of capacitance (10 µF) and to select devices and bias
OUTPUT conditions to obtain low IP. It is important that the capacitor
K leakage be quite low. Glass and mylar dielectrics are often
V0
20 27 k used for these applications. The maximum timing resistor is
as follows:
R (max) + * ń(V I V P) 2I P
In a circuit with a fixed value of timing capacitance, our
Figure 3.33. PUT Test Circuit for Peak Output Voltage
most sensitive PUT, the 2N6028, offers the largest dynamic
(Vo)
frequency range. Allowing for capacitance and bias changes,
the approximate frequency range of a PUT is from 0.003 Hz
timing resistors that will guarantee oscillation. The circuit to 2.5 kHz.
under discussion is a conventional RC relaxation type
oscillator. TEMPERATURE COMPENSATION
To obtain maximum frequency, it is desirable to use low The PUT with its external bias network exhibits a relatively
values of capacitance (1000 pF) and to select devices and small frequency change with temperature. The uncompen-
bias conditions to obtain high IV. It is possible to use stray sated RC oscillator shown in Figure 3.35 was tested at
capacitance but the results are generally unpredictable. The various frequencies by changing the timing resistor RT. At
discrete frequencies of 100, 200, 1000 and 2000 Hz, the
TO TEKTRONICS ambient temperature was increased from 25° to 60°C. At
510 k TYPE 567 OR these low frequencies, the negative temperature coefficient
16 k EQUIVALENT of VAG predominated and caused a consistent 2% increase
A
in frequency. At 10 kHz, the frequency remained within 1%
0.001 mF RG = 10 k over the same temperature range. The storage time phenom-
+
V1 G enon which increases the length of the output pulse as
20 V – temperature increases is responsible for this result. Since
1000 pF 100
K
this parameter has not been characterized, it is obvious that
temperature compensation is more practical with relatively
20 27 k 100 low frequency oscillators.
Various methods of compensation are shown in Figure
3.36. In the low cost diode–resistor combination of 3.36(a),
the diode current is kept small to cause its temperature
coefficient to increase. In 3.36(b), the bias current through
Figure 3.34. tr Test Circuit for PUTs
the two diodes must be large enough so that their total
coefficient compensates for VAG. The transistor approach in
3.36(c) can be the most accurate since its temperature
coefficient can be varied independently of bias current.
RT
A 1k
THE SILICON BILATERAL SWITCH
The silicon bilateral switch (SBS) is bidirectional and
+ switches, breakover triggers, or gate triggers in either
G
12 V polarity. Its characteristics are describable in terms of
– negative resistance switching theory.
0.01 mF
K OUTPUT These devices are not just an improved version of a PNPN
diode. They are actually fabricated as simple integrated
75 2k circuits consisting of transistors, diodes and resistors,
connected as two anti–parallel, regenerative switches. Since
the device is fabricated as an IC, the components are well
matched resulting in an asymmetry, or difference of positive
Figure 3.35. Uncompensated Oscillator VS and negative VS, of less than 0.5 volts.

Theory and Applications Motorola Thyristor Device Data

1.3–18
 A third lead, designated the Gate, has been brought out for the off or blocking state. As the supply voltage is increased, a
increased circuit flexibility. Since these devices are a point will be reached (near VS) where a small increase in
voltage results in a substantial increase in current flow. The
100 k < R < 1 M PNP transistor purposely has high current gain and most of
this increased current flows out of its collector and produces
a voltage drop across RB.
The two transistors are connected in a positive feedback
loop similar to the equivalent circuit for an SCR where the
collector current of one is the base current for the other.
When the voltage across RB is sufficient to turn the NPN
transistor on and the loop gain exceeds unity, both transistors
R are driven into saturation, the voltage across the device
abruptly drops and the current through it is limited mainly by
the external circuitry. The device has now switched to the on
(a) DIODE–RESISTOR or conducting state.
The 6.8 volt zener diode has a positive temperature
voltage coefficient which is opposite to that of VBE of the PNP
transistor. The net result is good temperature stability of VS,
typically + 0.02%/°C.

ANODE 1

RB
15 k
6.8 V
A1

(b) DUAL–DIODE (c) TRANSISTOR GATE

G
Figure 3.36. Temperature Compensation Techniques

regenerative switch, they may also be designed into many 6.8 V

low power latching circuits. RB
A2
The equivalent circuit diagram of an SBS and its symbol 15 k
are shown in Figure 3.37. The device is actually a simple IC Figure 3.37(a).
and consists of two halves of a PNP and an NPN transistor, a SBS Equivalent Circuit ANODE 2
6.8 volt zener diode and a 15 kΩ resistor, RB. Unlike existing and Symbol
4–layer diodes which use a stacked structure, the SBS is Figure 3.37(b)
constructed using annular techniques. The result is a device +1
with better stability and control of its electrical parameters. VF1
Electrical characteristics are shown in Figure 3.38 and the
parameters are defined as follows: VS, the switching voltage,
is the maximum forward voltage the device can sustain
without switching to the conducting state; IS, the switching IH1 VS1
current, is the current through the device when VS is applied; IS1
IS1
VF, the forward voltage, is the voltage drop across the device
–V +V
when it is in the conducting state and passing a specified
current; IH, the holding current, is the current necessary to IS2 IS1
sustain conduction; IB is the leakage current through the VS2 IH2
device with five volts bias.
Operation of the SBS can be best understood by referring
to Figures 3.38 and 3.39. Consider an adjustable source of
voltage with a current limiting resistor in series supplying a VF2
voltage to a device anode 1 that is five volts positive with –1
respect to anode 2. Since this voltage is less than the sum of
VBE of the PNP transistor and VZ of the 6.8 volt zener diode, Figure 3.38. SBS Main Terminal (V–I) Characteristic
only a very small leakage current will flow and the device in

Motorola Thyristor Device Data Theory and Applications

1.3–19
 VF, the forward voltage across the device, remains VS
relatively low even if the current through it is greatly
increased, rising approximately 3 volts/ampere. The device
will remain on until the current through it is reduced below the 0
holding current value. One method of insuring turn–off is to 10 s
apply a reverse voltage less than VR, the maximum reverse (a) TIME (UNSCALED)
voltage. After a few microseconds (turn–off time) have
elapsed, the transistors will have recovered from saturation
TURN–ON–PULSES
and the device will again block a forward voltage up to VS.
A third lead, the gate, can be used to modify the VS
characteristics of the SBS. As an example, connecting a 3.9
volt zener diode from gate to cathode would lower VS to
0
approximately 4.6 volts. Connecting a 20 kΩ resistor from
t > 200 ms
gate to anode and a similar resistor from gate to cathode will
(b) TIME (UNSCALED)
lower VS to approximately 4 volts at the expense of increased
current around the device prior to switching. Also, if a voltage
less than VS is applied to an SBS it can be “gated’’ on by Figure 3.39. Waveforms for dv/dt Test
drawing a small current out of the gate lead.
Like other regenerative switches, the SBS has a tendency and the next ramp is longer than the turn–off time of the
to switch on in the presence of rapidly rising anode voltage. device. The turn–on pulse in (b) is necessary to discharge
The dv/dt rating of the SBS is difficult to define and the internal capacitance which can accumulate a charge and
method of measurement may produce erroneous results. A give false indication of very high dv/dt capability.
test ramp of voltage with adjustable dv/dt as shown in Figure Sweeping an SBS in either direction will yield similar
3.39(a) may be applied to the device if not repeated more results. However, when an SBS has been conducting in one
frequently than every 10 seconds. The device may switch to direction and the anode voltage is rapidly reversed, the dv/dt
the on state when the dv/dt is in the range of 1 to 10 volts/ must be limited to approximately 0.1 volt/microsecond. This
microsecond. The repetitive waveform of (b) may be applied is necessary because if the transistors in the conducting half
much more frequently (convenient for an oscilloscope of the device have not recovered from saturation, they will
display) providing only that the time interval between turn–off provide a path for a current to turn the opposite side on.

Theory and Applications Motorola Thyristor Device Data

1.3–20
 CHAPTER 4
THE SIDAC, A NEW HIGH VOLTAGE BILATERAL TRIGGER

The SIDAC is a high voltage bilateral trigger device that are available. The MKP3V devices feature bigger chips and
extends the trigger capabilities to significantly higher volt- provide much greater surge capability along with somewhat
ages and currents than have been previously obtainable, higher RMS current ratings.
thus permitting new, cost-effective applications. Being a The high-voltage and current ratings of SIDACs make
bilateral device, it will switch from a blocking state to a them ideal for high energy applications where other trigger
conducting state when the applied voltage of either polarity devices are unable to function alone without the aid of
exceeds the breakover voltage. As in other trigger devices, additional power boosting components.
(SBS, Four Layer Diode), the SIDAC switches through a The basic SIDAC circuit and waveforms, operating off of ac
negative resistance region to the low voltage on-state (Figure are shown in Figure 4.2. Note that once the input voltage
4.1) and will remain on until the main terminal current is exceeds V(BO), the device will switch on to the forward
interrupted or drops below the holding current. on-voltage VTM of typically 1.1 V and can conduct as much
SIDAC’s are available in the large MKP3V series and as the specified repetitive peak on-state current ITRM of 20 A
economical, easy to insert, small MKP1V series axial lead (10 µs pulse, 1 kHz repetition frequency).
packages. Breakdown voltages ranging from 104 to 280 V

SLOPE = RS
ITM VTM

IH

IS
IDRM
VS
I(BO)

VDRM V(BO)

* VS)
+
(V(BO)
RS
(IS * I(BO))

Figure 4.1(a). Idealized SIDAC V-I Characteristics

Figure 4.1(b). Actual MKP1V130 V-I Characteristic.
Horizontal: 50 V/Division. Vertical: 20 mA/Division.
(0,0) at Center. RL = 14 k Ohm.

Motorola Thyristor Device Data Theory and Applications

1.4-1
 VIN

V(BO)
VT
V(BO)

RL V(BO)
VIN I

IH
* VS) IH
+
(V(BO) IT
RL t  RS RS
(IS * I(BO))
CONDUCTION
RS = SIDAC SWITCHING θON ANGLE θOFF
RESISTANCE

Figure 4.2. Basic SIDAC Circuit and Waveforms

Operation from an AC line with a resistive load can be If the load resistance is less than the SIDAC switching
analyzed by superimposing a line with slope = – 1/RL on the resistance, the voltage across the device will drop quickly as
device characteristic. When the power source is AC, the load shown in Figure 4.2. A stable operating point (VT, IT) will
line can be visualized as making parallel translations in step result if the load resistor and line voltage provide a current
with the instantaneous line voltage and frequency. This is greater than the latching value. The SIDAC remains in an
illustrated in Figure 4.3 where v1 through v5 are the “on” condition until the generator voltage causes the current
instantaneous open circuit voltages of the AC generator and through the device to drop below the holding value (IH). At
i1 through i5 are the corresponding short circuit currents that that time, the SIDAC switches to the point (Voff, Ioff) and once
would result if the SIDAC was not in the circuit. When the again only a small leakage current flows through the device.
SIDAC is inserted in the circuit, the current that flows is Figure 4.4 illustrates the result of operating a SIDAC with
determined by the intersection of the load line with the SIDAC a resistive load greater than the magnitude of its switching
characteristic. Initially the SIDAC blocks, and only a small resistance. The behavior is similar to that described in
leakage current flows at times 1 through 4. The SIDAC does Figures 4.2 and 4.3 except that the turn-on and turn-off of
not turn-on until the load line supplies the breakover current the SIDAC is neither fast nor complete. Stable operating
(I(BO)) at the breakover voltage (V(BO)). points on the SIDAC characteristics between (V (BO) , I (BO) )

i5
(VT, IT)

SLOPE + RIL v1, ..., v5 = INSTANTANEOUS OPEN

i3 CIRCUIT VOLTAGES
(VOFF, IOFF) AT TIME 1, ..., 5
RL
i
i1, ..., i5 = INSTANTANEOUS
SHORT CIRCUIT
IH CURRENTS AT

RL tȧRSȧ i1
TIME 1, ..., 5

(VBO, IBO)
v
v1 v2 v3 v4 v5
i + RvL

Figure 4.3. Load Line for Figure 4.2. (1/2 Cycle Shown.)

Theory and Applications Motorola Thyristor Device Data

1.4-2
 (VT, IT)
v I RL
i4 IH
i3 (VS, IS)
i2
i1
uȧ ȧ
RL RS
(VOFF, IOFF)
(VBO, IBO)
RS = SIDAC SWITCHING RESISTANCE
v
v1 v2 v3 v4

Figure 4.4. High Resistance Load Line with Incomplete Switching

and (V S , I S ) result as the generator voltage increases from tion. The SIDAC will switch from a blocking to full on-state in
v 2 to v 4 . The voltage across the SIDAC falls only partly as less than a fraction of a microsecond.
the loadline sweeps through this region. Complete turn-on The timing resistor must supply sufficient current to fire the
of the SIDAC to (V T, I T ) does not occur until the load line SIDAC but not enough current to hold the SIDAC in an
passes through the point (V S , I S ). The load line illustrated on-state. These conditions are guaranteed when the timing
in Figure 4.4 also results in incomplete turn-off. When the resistor is selected to be between Rmax and Rmin.
current drops below I H , the operating point switches to For a given time delay, capacitor size and cost is
(Voff , I off ) as shown on the device characteristic. minimized by selecting the largest allowable timing
The switching current and voltage can be 2 to 3 orders of resistor. Rmax should be determined at the lowest tempera-
magnitude greater than the breakover current and on-state ture of operation because I(BO) increases then. The load
voltage. These parameters are not as tightly specified as VBO line corresponding to Rmax passes through the point
and IBO. Consequently operation of the SIDAC in the state (V(BO), I(BO)) allowing the timing resistor to supply the
between fully on and fully off is undesirable because of needed breakover current at the breakover voltage. The
increased power dissipation, poor efficiency, slow switching, load line for a typical circuit design should enclose this
and tolerances in timing. point to prevent sticking in the off state.
Requirements for higher oscillation frequencies and great-
Figure 4.5 illustrates a technique which allows the use of
er stored energy in the capacitor result in lower values for the
the SIDAC with high impedance loads. A resistor can be
timing resistor. Rmin should be determined at the highest
placed around the load to supply the current required to
operating temperature because IH is lower then. The load
latch the SIDAC. Highly inductive loads slow the current
line determined by R and Vin should pass below IH on the
rise and the turn-on of the SIDAC because of their L/R time
device characteristic or the SIDAC will stick in the on-state
constant. The use of shunt resistor around the load will
after firing once. IH is typically more than 2 orders of
improve performance when the SIDAC is used with magnitude greater than IBO. This makes the SIDAC well
inductive loads such as small transformers and motors. suited for operation over a wide temperature span.
The SIDAC can be used in oscillator applications. If the SIDAC turn-off can be aided when the load is an
load line intersects the device characteristic at a point under-damped oscillatory CRL circuit. In such cases, the
where the total resistance (R L + RS) is negative, an SIDAC current is the sum of the currents from the timing
unstable operating condition with oscillation will result. resistor and the ringing decay from the load. SIDAC
The resistive load component determines steady-state turn-off behavior is similar to that of a TRIAC where turn-off
behavior. The reactive components determine transient will not occur if the rate of current zero crossing is high.
behavior. Figure 4.10 shows a SIDAC relaxation oscillator This is a result of the stored charge within the volume of the
application. The wide span between I BO and IH makes the device. Consequently, a SIDAC cannot be force com-
SIDAC easy to use. Long oscillation periods can be muted like an SCR. The SIDAC will pass a ring wave of
achieved with economical capacitor sizes because of the sufficient amplitude and frequency. Turn-off requires the
low device I(BO). device current to approach the holding current gradually.
Z1 is typically a low impedance. Consequently the This is a complex function of junction temperature, holding
SIDAC’s switching resistance is not important in this applica- current magnitude, and the current wave parameters.

Motorola Thyristor Device Data Theory and Applications

1.4-3
 The operating cost of the lamp is also reduced because
RSL
RSL tȧRSȧ of the lower power to the lamp; however, a higher wattage
bulb is required for the same lumen output. The maximum
TYPICAL: possible energy reduction is 50% if the lamp wattage is not
L RL RSL = 2.7 k OHM increased. The minimum conduction angle is 90° because
10 WATT the SIDAC must switch on before the peak of the line
HIGH RS = 3 k OHM
LOW voltage. Line regulation and breakover voltage tolerances
v will require that a conduction angle longer than 90° be
RSL = TURN-ON SPEED
UP RESISTOR used, in order to prevent lamp turn-off under low line
RS = SIDAC SWITCHING voltage conditions. Consequently, practical conduction
RESISTANCE angles will run between 110° and 130° with corresponding
power reductions of 10% to 30%.
Figure 4.5. Inductive Load Phase Control In Figure 4.2 and Figure 4.7, the SIDAC switching angles
are given by:
+ * ń

ǒ@ Ǔ
q ON SIN 1 (V (BO) V pk)
How can the SIDAC be used? One application is to
where Vpk = Maximum Instantaneous Line Voltage
replace the combination of a small-signal trigger and
TRIAC with the SIDAC, as shown in Figure 4.6. In this
q OFF + 180 * SIN*1 )
(I H R L) V T
example, the trigger — an SBS (Silicon Bidirectional V pk
Switch) that conducts at about 8 V — will fire the TRIAC by
dumping the charge from the capacitor into the gate of the where θON, θOFF = Switching Angles in degrees
TRIAC. This circuit is amenable to phase controlling the VT = 1 V = Main Terminal Voltage at IT = IH
TRIAC, if so required, as the RC time constant can be Generally the load current is much greater than the SIDAC
readily varied. holding current. The conduction angle then becomes 180°
The simple SIDAC circuit can also supply switchable minus θ(on).
load current. However, the conduction angle is not readily Rectifiers have also been used in this application to supply
controllable, being a function of the peak applied voltage half wave power to the lamp. SIDAC’s prevent the flicker
and the breakover voltage of the SIDAC. As an example, associated with half-wave operation of the lamp. Also, full
for peak line voltage of about 170 V, at V(BO) of 115 V and wave control prevents the introduction of a DC component
a holding current of 100 mA, the conduction angle would into the power line and improves the color temperature of the
be about 130°. With higher peak input voltages (or lower light because the filament has less time to cool during the off
breakdown voltages) the conduction angle would corre- time.
spondingly increase. For non-critical conduction angle, The fast turn-on time of the SIDAC will result in the
1 A rms switching applications, the SIDAC is a very generation of RFI which may be noticeable on AM radios
cost-effective device. operated in the vicinity of the lamp. This can be prevented by
Figure 4.7 shows an example of a SIDAC used to phase the use of an RFI filter. A possible filter design is shown in
control an incandescent lamp. This is done in order to Figure 4.5. This filter causes a ring wave of current through
lower the RMS voltage to the filament and prolong the life the SIDAC at turn-on time. The filter inductor must be
of the bulb. This is particularly useful when lamps are used selected for resonance at a frequency above the upper
in hard to reach locations such as outdoor lighting in signs frequency limit of human hearing and as low below the start
where replacement costs are high. Bulb life span can be of the AM broadcast band as possible for maximum
extended by 1.5 to 5 times depending on the type of lamp, harmonic attenuation. In addition, it is important that the filter
the amount of power reduction to the filament, and the inductor be non-saturating to prevent dI/dT damage to the
number of times the lamp is switched on from a cold SIDAC. For additional information on filter design see page
filament condition. 1-5-30 and Figure 5.34.

ZL ZL

R
SBS
TRIAC
VIN VIN SIDAC

Figure 4.6. Comparison of a TRIAC and SIDAC Circuits

Theory and Applications Motorola Thyristor Device Data

1.4-4
 100 WATT
240 V

220 VAC 100 µHY PREM SPE304

RDC = 0.04 Ω

0.1 µF (2)MKP1V130

400 V
OPTIONAL
RFI FILTER

Figure 4.7. Long-Life Circuit for Incandescent Lamp

The sizing of the SIDAC must take into account the RMS Another example of OVP is the telephony applications as
current of the lamp, thermal properties of the SIDAC, and the illustrated in Figure 4.9. To protect the Subscriber Loop
cold start surge current of the lamp which is often 10 to 20 Interface Circuit (SLIC) and its associated electronics from
times the steady state load current. When lamps burn out, voltage surges, two SIDACs and two rectifiers are used for
at the end of their operating life, very high surge currents secondary protection (primary protection to 1,000 V is
which could damage the SIDAC are possible because of provided by the gas discharge tube across the lines). As an
arcing within the bulb. The large MKP3V device is recom- example, if a high positive voltage transient appeared on the
mended if the SIDAC is not to be replaced along with the lines, rectifier D1 (with a P.I.V. of 1,000 V) would block it and
bulb.
SIDAC D4 would conduct the surge to ground. Conversely,
Since the MKP3V series of SIDACs have relatively tight
rectifier D2 and SIDAC D3 would protect the SLIC for
V(BO) tolerances (104 V to 115 V for the – 115 device), other
negative transients. The SIDACs will not conduct when
possible applications are over-voltage protection (OVP)
normal signals are present.
and detection circuits. An example of this, as illustrated in
Figure 4.8, is the SIDAC as a transient protector in the Being a negative resistance device, the SIDAC also can
transformer-secondary of the medium voltage power supply, be used in a simple relaxation oscillator where the
replacing the two more expensive back-to-back zeners or frequency is determined primarily by the RC time constant
an MOV. The device can also be used across the output of (Figure 4.10). Once the capacitor voltage reaches the
t
the regulator ( 100 V) as a simple OVP, but for this SIDAC breakover voltage, the device will fire, dumping the
application, the regulator must have current foldback or a charged capacitor. By placing the load in the discharge
circuit breaker (or fuse) to minimize the dissipation of the path, power control can be obtained; a typical load could be a
SIDAC. transformer-coupled xeon flasher, as shown in Figure 4.12.

SIDAC AS A TRANSIENT
PROTECTOR

SIDAC AS AN
OVP VO p 100 V
VIN REG.

Figure 4.8. Typical Application of SIDACs as a Transient Protector and OVP in a Regulated Power Supply

Motorola Thyristor Device Data Theory and Applications

1.4-5
 MOC3030
90 V RMS @ – 48 Vdc
RING GENERATOR
RING ENABLE
RE 0 TO + 5 V

GND
RG1

105 V 135 V

RG2

TIP RPT 1N4007

TIP
DRIVE
RT D1
TIP
SENSE SLIC
RR MC3419-1L
RING
SENSE
RPR 1N4007
RING
DRIVE
RING PRIMARY D2
PROTECTION
SECONDARY
GAS DISCHARGE
PROTECTION
TUBE – 48 V
BATTERY

Figure 4.9. SIDACs Used for OVP in Telephony Applications

V(BO)
R
VC
VIN u V(BO) VC t
iL
C ZL iL

*
ȡȧ ȣȧ
t
p
V IN V (BO)
R MAX
I (BO)

^ RC In
Ȣ* Ȥ
I

R MIN q VIN * VTM t

I
VBO
IH VIN

Figure 4.10. Relaxation Oscillator Using a SIDAC

Theory and Applications Motorola Thyristor Device Data

1.4-6
 SIDAC’s provide an economical means for starting high
intensity high pressure gas discharge lamps. These lamps
are attractive because of their long operating life and high LB
efficiency. They are widely used in outdoor lighting for these R
reasons. C1
Figure 4.13 illustrates how SIDAC’s can be used in sodium vac
vapor lamp starters. In these circuits, the SIDAC is used to
generate a short duration (1 to 20 µs) high-voltage pulse of
C
several KV or more which is timed by means of the RC
network across the line to occur near the peak of the AC input
line voltage. The high voltage pulse strikes the arc which
(a). Conventional HV Transformer
lights the lamp.
In these circuits, an inductive ballast is required to provide
a stable operating point for the lamp. The lamp is a negative
resistance device whose impedance changes with current,
temperature, and time over the first few minutes of operation. LB
Initially, before the lamp begins to conduct, the lamp
impedance is high and the full line voltage appears across it. C
This allows C to charge to the breakover voltage of the vac
SIDAC, which then turns on discharging the capacitor
through a step-up transformer generating the high voltage R
pulse. When the arc strikes, the voltage across the lamp falls
reducing the available charging voltage across RC to the
point where VC no longer exceeds V(BO) and the SIDAC
remains off. The low duty cycle lowers average junction (b). H.V. Auto-Transformer
temperature improving SIDAC reliability. Normal operation
approximates non-repetitive conditions. However, if the lamp
fails or is removed during replacement, operation of the
SIDAC will be at the 60 Hz line frequency. The design of the
LB
circuit should take into account the resulting steady state
power dissipation.

vac

VIN HV R

Figure 4.11. Typical Capacitor Discharge SIDAC Circuit (c). Tapped Ballast Auto Transformer

Figure 4.13. Sodium Vapor Lamp Starter Circuits

220
2W +
1M
20 µF 2W
VIN ≈ 400 V 2 kW Figure 4.14 illustrates a solid state fluorescent lamp starter
300 V XEON TUBE
560 k using the SIDAC. In this circuit the ballast is identical to that
125 V RS-272-1145
2W used with the conventional glow-tube starter shown in Figure
4.15.
1 µF + The glow tube starter consists of a bimetallic switch placed
200 V in series with the tube filaments which closes to energize the
filaments and then opens to interrupt the current flowing
4 kV PULSE TRANSFORMER through the ballast inductor thereby generating the high-volt-
RS-272-1146 age pulse necessary for starting. The mechanical glow-tube
starter is the circuit component most likely to cause unreli-
Figure 4.12. Xeon Flasher Using a SIDAC able starting.

Motorola Thyristor Device Data Theory and Applications

1.4-7
 LB The evolution of this circuit can be understood by first
considering an impractical circuit (Figure 4.16).
If LB and C are adjusted for resonance near 60 Hz, the
D1 application of the AC line voltage will result in a charging
D2 current that heats the filaments and a voltage across the
capacitor and tube that grows with each half-cycle of the AC
line until the tube ionizes. Unfortunately, C is a large
capacitor which can suddenly discharge through the tube

F15T8/CW
SYLVANIA
R causing high current pulses capable of destroying the tube
115 VAC filament. Also C provides a permanent path for filament
current after starting. These factors cause short tube
operating life and poor efficiency because of filament power
PTC losses. The impractical circuit must be modified to:
(1) Switch off the filament current after starting.
(2) Limit capacitor discharge current spikes.
L
In Figure 4.14 a parallel connected rectifier and SIDAC
have been added in series with the capacitor C. The
breakover voltage of the SIDAC is higher than the peak of the
LB UNIVERSAL MFG CORP CAT200-H2 line voltage. Diode D1 is therefore necessary to provide a
14-15-20-22 WATT BALLAST current path for charging C.
325 mHY 28.9 Ω DCR
On the first half-cycle, C resonant charges through diode
D1 1N4005 RECTIFIER D1 to a peak voltage of about 210 V, and remains at that
value because of the blocking action of the rectifier and
D2 (2) MKP1V130 SIDAC SIDAC. During this time, the bleeder resistor R has negligible
effect on the voltage across C because the RC time constant
C 3 VFD 400 V
is long in comparison to the line period. When the line
R 68 k OHMS 112 WATT reverses, the capacitor voltage boosts the voltage across the
SIDAC until breakover results. This results in a sudden step
PTC KEYSTONE CARBON COMPANY of voltage across the inductor L, causing resonant charging
RL3006-50-40-25-PTO
of the capacitor to a higher voltage on the 2nd half-cycle.
50 OHMS/25°C

L MICROTRAN QIL 50-F

50 mHY 11 OHMS

Figure 4.14. Fluorescent Starter Using SIDAC

NEON GAS

The heating of the filaments causes thermonic emission of

electrons from them. These electrons are accelerated along FLUORESCENT STARTER
COATING
the length of the tube causing ionization of the argon gas
within the tube. The heat generated by the starting current (ARGON GAS)
COATED
flow through the tube vaporizes the mercury droplets FILAMENT
within the tube which then become ionized themselves MERCURY DROPLETS
causing the resistance and voltage across the tube to drop
significantly. The drop in voltage across the tube is used to
turn off the starting circuit and prevent filament current
after the lamp is lit.
VAC
The SIDAC can be used to construct a reliable starter BALLAST
circuit providing fast, positive lamp ignition. The starter INDUCTOR
shown in Figure 4.14 generates high voltage by means of a
series CRL charging circuit. The circuit is roughly analogous Figure 4.15. Fluorescent Lamp with Glow Tube Starter
to a TRIAC snubber used with an inductive load, except for a
lower damping factor and higher Q. The size of C determines
the amount of filament heating current by setting the
impedance in the filament circuit before ionization of the tube.

Theory and Applications Motorola Thyristor Device Data

1.4-8
 BALLAST
CHOKE
fo + 2a Ǹ1 LC + 60 Hz
RB LB

C
V
VAC

Q + RTOTAL
X LB – VSTART

V max + Q VAC Ǹ2 VSTART t VMAX

Figure 4.16. Impractical Starter Circuit

(a). 5 ms/DIVISION (b). 100 ms/DIVISION

Figure 4.17. Starting Voltage Across Fluorescent Tube 100 V/DIV

0 V AT CENTER
VLine = 110 V

Several cycles of operation are necessary to approach Figure 4.18 illustrates this concept. The resistor R can be
steady state operating conditions. Figure 4.17 shows the added to aid turn-off of the SIDAC by providing a small idle
starting voltage waveform across the tube. current resulting in a voltage drop across the impedance Z.
The components R, PTC, and L serve the dual role of The impedance Z could be a saturable reactor and or
guarantying SIDAC turn-off and preventing capacitor dis- positive temperature coefficient thermistor. These compo-
charge currents through the tube. nents help to insure stability of the system comprised of the
SIDAC’s can also be used with auto-transformer ballasts. negative resistance SIDAC and negative resistance tube
The high voltage necessary for starting is generated by the during starting, and promote turn off of the SIDAC.
leakage autotransformer. The SIDAC is used to turn-on the The techniques illustrated in Figure 4.13 are also possible
filament transformer initially and turn it off after ionization methods for generation of the necessary high-voltage
causes the voltage across the tube to drop. required in fluorescent starting. The circuits must be modified

Motorola Thyristor Device Data Theory and Applications

1.4-9
 C

Z VBO t VSTART
VBO u VOPERATING

VAC

Figure 4.18. Fluorescent Starter Using SIDAC and Autotransformer Ballast

Table 4.1. Possible Sources for Thermistor Devices underdamped CRL discharge circuit). The question then
becomes; how much “real world” surge current can the
Fenwal Electronics, 63 Fountain Street SIDAC sustain? The data sheet defines an ITSM of 20 A, but
Framingham MA 01701 this is for a 60 Hz, one cycle, peak sine wave whereas the
capacitor discharge current waveform has a fast-rise time
Keystone Carbon Company, Thermistor Division
with an exponential fall time.
St. Marys, PA 15857
To generate the surge current curve of peak current
Thermometrics, 808 U.S. Highway 1 versus exponential discharge pulse width, the test circuit
Edison, N.J. 08817 of Figure 4.19 was implemented. It simulates the topology
of many applications whereby a charged capacitor is
Therm-O-Disc, Inc. Micro Devices Product Group dumped by means of a turned-on SIDAC to produce a
1320 South Main Street, Mansfield, OH 44907 current pulse. Timing for this circuit is derived from the
nonsymmetrical CMOS astable multivibrator (M.V.) gates
Midwest Components Inc., P.O Box 787 G1 and G2. With the component values shown, an
1981 Port City Boulevard, Muskegon, MI 49443 approximate 20 second positive-going output pulse is fed
to the base of the NPN small-signal high voltage transistor
Nichicon (America) Corp., Dept. G Q1, turning it on. The following high voltage PNP transistor
927 E. State Pkwy, Schaumburg, IL 60195 is consequently turned on, allowing capacitor C1 to be
charged through limiting resistor R1 in about 16 seconds.
to allow heating of the fluorescent tube cathodes if starting is The astable M.V. then changes state for about 1.5 seconds
to simulate the conditions existing when a glow tube is used. with the positive going pulse from Gate 1 fed through
Thermistors are useful in delaying the turn-on or insuring integrator R2-C2 to Gate 3 and then Gate 4. The net result
the turn-off of SIDAC devices. Table 4.1 shows possible of about a 100 µs time delay from G4 is to ensure
sources of thermistor devices. non-coincident timing conditions. This positive going output
Other high voltage nominal current trigger applications are: is then differentiated by C3-R3 to produce an approximate 1
ms, leading edge, positive going pulse which turns on NPN
• Gas or oil igniters transistor Q3 and the following PNP transistor Q4. Thus,
• Electric fences an approximate 15 mA, 1 ms pulse is generated for turning
• HV electrostatic air filters on SCR Q5 about 100 µs after capacitor charging
• Capacitor Discharge ignitions transistor Q2 is turned off. The SCR now fires, discharging
Note that all these applications use similar circuits where a C1 through the current limiting resistor R4 and the SIDAC
charged capacitor is dumped to generate a high transformer Device Under Test (D.U.T.). The peak current and its
secondary voltage (Figure 4.11). duration is set by the voltage VC across capacitor C1 and
In many cases, the SIDAC current wave can be approxi- current limiting resistor R4. The circuit has about a 240 V
mated by an exponential or quasi-exponential current wave capability limited by C1, Q1 and Q2 (250 V, 300 V and 300
(such as that resulting from a critically damped or slightly V respectively).

Theory and Applications Motorola Thyristor Device Data

1.4-10
 +15 V +15 V

R2 1 5 4
100 k 3 G4
G3
2 6
C2 0.001 µF
VCC p 240 V
MC14011 10 k
+15 V Q2
+15 V MJ4646
39 k
14 2W R1
12 11 47 k Q1 4k
8 10 G2 5W +15 V
G1 MPS
13 A42 SIDAC
9 7 LED C3
DUT
R4 0.1 µF
22 k 10 k
22 M 22 M 2.2 M C1
3.3 Ω 2N3906 R3
80 µF Q4
2W 10 k
250 V
1N914 Q5 1k
MCR 10 k
6507 1N
0.47 µF 1k 4003
Q3
2N3904
22 k
1N914

Figure 4.19. SIDAC Surge Tester

The SCR is required to fire the SIDAC, rather than the 100
breakover voltage, so that the energy to the D.U.T. can be
I pk, SURGE CURRENT (AMPS)

predictably controlled.
30
By varying VC, C1 and R4, the surge current curve of
Figure 15 was derived. Extensive life testing and adequate Ipk
derating ensure that the SIDAC, when properly used, will 10
reliably operate in the various applications.
10%
tw
3

1
0.3 1 3 10 30 100 300
tw, PULSE WIDTH (ms)

Figure 4.20. Exponential Surge Current Capability of the

MKP3V SIDAC. Pulse Width versus Peak Current

Motorola Thyristor Device Data Theory and Applications

1.4-11
Theory and Applications Motorola Thyristor Device Data
1.4-12
 CHAPTER 5
SCR CHARACTERISTICS

SCR TURN–OFF CHARACTERISTICS ANODE

In addition to their traditional role of power control devices,

ANODE
SCRs are being used in a wide variety of other applications in P
which the SCR’s turn–off characteristics are important. As in J1
example — reliable high frequency inverters and converter
t
N
designs ( 20 kHz) require a known and controlled circuit– GATE J2
commutated turn–off time (tq). Unfortunately, it is usually P
J3
difficult to find the turn–off time of a particular SCR for a given GATE N
set of circuit conditions.
This section discusses tq in general and describes a circuit
CATHODE
capable of measuring tq. Moreover, it provides data and
curves that illustrate the effect on tq when other parameters CATHODE
are varied, to optimize circuit performance.
P–N–P–N STRUC-
TURE
SCR TURN–OFF MECHANISM
The SCR, being a four layer device (P–N–P–N), is ANODE
represented by the two interconnected transistors, as shown ANODE
ITM
in Figure 5.1. This regenerative configuration allows the
device to turn on and remain on when the gate trigger is Q1 IB1 = IC2
removed, as long as the loop gain criteria is satisfied; i.e., P
when the sum of the common base current gains (α) of both
N
the equivalent NPN transistor and PNP transistor, exceed N IC1 = IB2
one. To turn off the SCR, the loop gain must be brought below P
unity, whereby the on–state principal current (anode current P
Q2
iT) limited by the external circuit impedance, is reduced below GATE GATE
N
the holding current (IH). For ac line applications, this occurs
automatically during the negative going portion of the
waveform. However, for dc applications (inverters, as an CATHODE
CATHODE
example), the anode current must be interrupted or diverted;
(diversion of the anode current is the technique used in the tq
test fixture described later in this application note). TWO TRANSISTOR MODEL

Figure 5.1. Two Transistor Analogy of an SCR

SCR TURN–OFF TIME tq
Once the anode current in the SCR ceases, a period of
time must elapse before the SCR can again block a forward regions (base regions) on either side of J2 are heavily
voltage. This period is the SCR’s turn–off time, tq, and is saturated with holes and electrons (stored charge). In order
dependent on temperature, forward current, and other to turn off the SCR in a minimum amount of time, it is
parameters. The turn–off time phenomenon can be under- necessary to apply a negative (reverse) voltage to the device
stood by considering the three junctions that make up the anode, causing the holes and electrons near the two end
SCR. When the SCR is in the conducting state, each of the junctions, J1 and J3, to diffuse to these junctions. This
three junctions is forward biased and the N and P causes a reverse current to flow through the SCR. When the

Motorola Thyristor Device Data Theory and Applications

1.5–1
holes and electrons near junctions J1 and J3 have been tq GENERAL TEST FIXTURE
removed, the reverse current will cease and junctions J1 and The simplified circuit for generating these waveforms is
J3 will assume a blocking state. However, this does not schematically illustrated in Figure 5.3. This circuit is imple-
complete the recovery of the SCR since a high concentration mented with as many as eight transformers including variacs,
of holes and electrons still exist near the center junction, J2. and in addition to being very bulky, has been known to be
This concentration decreases by the recombination process troublesome to operate. However, the configuration is
and is largely independent of the external circuit. When the relevent and, in fact, is the basis for the design, as described
hole and electron concentration near junction J2 has in the following paragraphs.
reached some low value, junction J2 will assume its blocking
condition and a forward voltage can, after this time, be
applied without the SCR switching back to the conduction tq TEST FIXTURE BLOCK DIAGRAMS AND
state. WAVEFORMS
The block diagram of the tq Test Fixture, illustrated in
tq MEASUREMENT Figure 5.4, consists of four basic blocks: A Line Synchro-
When measuring SCR turn–off time, tq, it is first nized Pulse Generator establishes system timing; a Constant
necessary to establish a forward current for a period of Current Generator (variable in amplitude) powers the Device
time long enough to ensure carrier equilibrium. This must Under Test (DUT); a di/dt Circuit controls the rate of change
be specified, since ITM has a strong effect on the turn–off of the SCR turn–off current; and the dv/dt Circuit reapplies a
time of the device. Then, the SCR current is reversed at a controlled forward blocking voltage. Note from the wave-
specified di/dt rate, usually by shunting the SCR anode to forms illustrated that the di/dt circuit, in parallel with the DUT,
some negative voltage through an inductor. The SCR will diverts the constant current from the DUT to produce the
then display a “reverse recovery current,” which is the described anode current ITM.
charge clearing away from the junctions. A further waiting
time must then elapse while charges recombine, before a
forward voltage can be applied. This forward voltage is tq TEST FIXTURE CHARACTERISTICS
ramped up a specified dv/dt rate. The dv/dt delay time is The complete schematic of the tq Test Fixture and the
reduced until a critical point is reached where the SCR can important waveforms are shown in Figures 5.5 and 5.6,
no longer block the forward applied voltage ramp. In effect, respectively.
the SCR turns on and consequently, the ramp voltage A CMOS Gate is used as the Line Synchronized Pulse
collapses. The elapsed time between this critical point and Generator, configured as a wave shaping Schmitt trigger,
the point at which the forward SCR current passes through clocking two cascaded monostable multivibrators for delay
zero and starts to go negative (reverse recovery phase), is and pulse width settings (Gates 1C to 1F). The result is a
the tq of the SCR. This is illustrated by the waveforms pulse generated every half cycle whose width and position
shown in Figure 5.2. (where on the cycle it triggers) are adjustable by means

ITM di/dt

50% ITM
IDX

50% IRM
IRM

trr

tq VDX

dv/dt
VT

Figure 5.2. SCR Current and Voltage Waveforms

During Circuit–Commutated Turn–Off

Theory and Applications Motorola Thyristor Device Data

1.5–2
 S2
S3 L1 R2
IT

D1
D2
S1
dv/dt
di/dt
IT
D3
I1
V2
S4 DUT

C1

V1 R1
V3

Figure 5.3. Simplified tq Test Circuit

of potentiometers R2 and R3, respectively. The output pulse transistor Q16, b) PNP transistor Q1, c) optocoupler U3, and
is normally set to straddle the peak of the ac line, which not d) transistors Q3, Q4 and Q5. The board mounted Current
only makes the power supplies more efficient, but also allows Set potentiometer R5, sets the maximum output current and R4,
a more consistent oscilloscope display. This pulse shown in the Current Control, is a front panel, multiturn potentiometer.
waveform A of Figure 5.6 initiates the tq test, which requires Time delay for the di/dt Circuit is derived from cascaded
approximately 0.5 ms to assure the device a complete turn op–amps U2B and U5 (waveforms F and G of Figure 5.6).
on. A fairly low duty cycle results, (approximately 5%) which The output gate, in turn, drives NPN transistor Q8, followed
is important in minimizing temperature effects. The repetitive
nature of this test permits easy oscilloscope viewing and CONSTANT
allows one to readily “walk in” the dv/dt ramp. This is CURRENT
accomplished by adjusting the appropriate potentiometer GENERATOR
D1
(R7) which, every 8.33 ms (every half cycle) will apply the
dv/dt ramp at a controlled time delay
IT
To generate the appropriate system timing delays, four RC DUT
dv CIRCUIT di CIRCUIT
integrating network/comparators are used, consisting of dt dt
op–amps U2, U5 and U6. LINE SYNC
PULSE IGT
Op–amp U2A, along with transistor Q2, opto–coupler U4
GENERATOR
and the following transistors Q6 and Q7, provide the gate
drive pulse to the DUT (see waveforms B, C and D of Figure
5.6). The resulting gate current pulse is about 50 µs wide and CONSTANT
can be selected, by means of switch S2, for an IGT of from CURRENT
about 1 mA to 90 mA. Opto–coupler U4, as well as U1 in the
Constant Current Circuit, provide electrical isolation between
di/dt
the power circuitry and the low level circuitry.
The Constant Current Circuit consists of an NPN Darling-
ton Q3, connected as a constant current source driving a IT di/dt
PNP tri–Darlington (Darlington Q4, Bipolar Q5). By varying 0
the base voltage of Q3 (with Current Control potentiometer
V1
R4), the collector current of Q3 and thus the base voltage of dv/dt dv/dt
Q4 will also vary. The PNP output transistor Q5 (MJ14003)
(rated at 70 A), is also configured as a constant current
source with four, parallel connected emitter resistors (approx-
imately 0.04 ohms, 200 W), thus providing as much as 60 A
test current. Very briefly, the circuit operates as follows: — Figure 5.4. Block Diagram of the tq Test Fixture
CMOS Gate 1E is clocked high, turning on, in order, a) NPN and Waveforms

Motorola Thyristor Device Data Theory and Applications

1.5–3
 LINE SYNCHRONIZED PULSE GENERATOR

1.5–4
+ 10 V
R2
U1 PULSE
+ 10 V MC14572 DELAY + 10 V
220 k
CONTROL
+ 10 V 1M
1N914 0.01
1k 22 k 2 1 4 16 220 pF µF 150 k 100 k 15 0.1 µF 11
6 9 12
1A 1B 1E 1F
1C 1D
8 3 5 10 14 13
TRIAD 10 k 100 k 7 0.001 4.7 k

Theory and Applications

F93X µF
+ 10 V
1N4001 25 k R3 POWER ON
2 + 10 V + 20 V (UNLOADED) 2 A S.B.
3 LM317T 1k PULSE WIDTH
+ 12 V (LOADED)

SWD
Q1

120 V
+ U7 1.5 k CONTROL 0.1 µF
2000 + 2N
240 50 µF 47 k 200 V SW S1 120 V
µF 25 V 1 20 V 3906 2N3904
Q16 (4) 0.15 Ω, 50 W 60 Hz
–V1 1.8 k 10 k 0.1 µF, 200 V
– 18 V CONSTANT 1.2 k +
TYP CURRENT 2W 50,000 STANCOR
1/2 W 330 CIRCUIT 47 0.1 µF P6337
1k 2N6042 2W µF
20,000 + 1W – 10 V 25 V
–5 V 1N + 10 V Q4
µF 25 V 914 430 MJ
10 V 510 k 10 k 100 14003
100 µF 2W 5 1W
+ 20 V Q5 di
0.1 CIRCUIT
12 k + 10 V 4N35 100 L1 (3) MTM15N06E dt
µF 1/2 W
1N4733 0.1 µF U3 *
5.1 V, 1 W 1N4740 Q3 Q10 Q11 Q12
10 V, 1 W + 2 4 100 k 560 560 560
3 1N4728 3.3 k
Q2 1k 2W 2W 2W
2 U2A .001
CURRENT MPS
820 pF 3.3 V A13 D1 1N 0.001
– CONTROL 5370A µF
R4 1.2 K 1K µF 1K
(1/2) 1k 56 V 2W 2W 2W + 10 V
2N3904 100
MC1458 CURRENT 1W 5W
SET GATE CURRENT o 1N 0.001 1N 0.002 1N
– V2 470
R5 SW S2 5932A µF 5932A µF 5932A
+ 10 V – V1 20 V MJE254
1 5 + 10 V MR856 1.5 W
82 90 mA Q9 56
4N35 2N 120 70 IT 0.001 µF 2W
1k 10 k
L1: 0 µH (TYP) U4 4919 DUT 150 k I1
o
Q7 160 50 R1 1k
*DIODE REQUIRED WITH L1 2 4 V o
100 20 o A + V1 2N4401
330 30 Q8 SYNC
1k 1W 1000
D1: MR506 FOR 3 A, HIGH tq DUTS 1W OUT
1k 820 10 150 MTM2N90 10 k
MR856 FOR 3 A, LOW tq DUTS 1k C1
Q15
(DIODE IF SCALED TO DUT IA) Q6 470 1N
1k 914
8.2 k 1 mA
I1: ≈ 50 mA FOR HIGH tq DUTS 10 k 1N 2W
SW.53 –5V 4747 1N4728
V1 2N3904 OFF
50 V + 10 V BIAS + 10 V
(TYP)
R1 1 k + 10 V 0.1 – V1
0.1 µF µF – 18 V 100
≈ 1 A FOR LOW tq 10 k
3.3 k U6
VREF 7 1N4728 1k MJE
V1
50 V MC1741 3 250
(TYP) + 6 1.8 k
R1 50 150 k, 10 T 1 k 2 U6 2N3904 Q14
R6
4.7 k ON TIME
– 4
3.3 V 10 k Q13
C1: DETERMINED BY SPEC dv/dt 0.1 0.001 µF + 10 V
50 k CONTROL 0.1 µF dv
µF CIRCUIT
– V2: – 12 V (TYP), t – 50 V tq TIME 0.1 µF dt
5 + CONTROL R7 – 10 V 39 k – 10 V
7 5 8 10 µF
0.02 6 U2B + 7 15 V
µF (1/2) 0.002 6 –U5 +
– MC1458 µF 4 (1/2)
MC1458
U5

Figure 5.5. tq Test Fixture

Motorola Thyristor Device Data

by PNP transistor Q9, whose output provides the gate drive indicate tq limitation, it latches up, thus suppressing the dv/dt
for the three parallel connected N–channel power MOSFET ramp voltage; and, for fast SCRs (low tq), I1 should be large
transistors Q10 – Q12 (waveforms H of Figure 5.6). These enough to ensure measurement repeatability. Typical values
three FETs (MTM15N06), are rated at 15 A continuous drain of I1 for standard and fast SCRs may be 50 mA and 500 mA,
current and 40 A pulsed current and thus can readily divert respectively. Obviously, for high forward blocking voltage
the maximum 60 A constant current that the Fixture can + V1 tests, the power requirements must be met.
generate. The results of this diversion from the DUT is
described by waveforms E, H and I of Figure 5.6, with the EFFECTS OF GATE BIAS ON tq
Examples of the effects of I1 on tq are listed in Table 5.III
di/dt of of ITM dictated by the series inductance L1. For all
whereby standard and fast SCRs were tested with about 50
subsequent testing, the inductor was a shorting bar, resulting
mA and 1 A, respectively. Note that the low tq SCR’s required
in very little inductance and consequently, the highest di/dt
fast recovery diodes and high I1 current.
(limited primarily by wiring inductance). When a physical
inductor L1 is used, a clamp diode, scaled to the diverted TEST FIXTURE POWER SUPPLIES
current, should be placed across L1 to limit “inductive kicks.” Most of the power supplies for the system are self
contained, including the + 12 V supply for the Constant
dv/dt CIRCUIT Current Circuit. This simple, unregulated supply furnishes up
The last major portion of the Fixture, the dv/dt Circuit, is to 60 A peak pulsed current, primarily due to the line
variable time delayed by the multi–turn, front panel tq Time synchronized operation of the system. Power supplies + V1
Control potentiometer R7, operating as part of an integrator and – V2, for this exercise, were external supplies, since they
on the input of comparator U6. Its output (waveform J of are variable, but they can be incorporated in the system. The
Figure 5.6) is used to turn–off, in order, a) normally on NPN reverse blocking voltage to the DUT is supplied by – V2 and
transistor Q13, b) PNP transistor Q14 and c) N–channel is typically set for about – 10 V to – 20 V, being limited to
power MOSFET Q15 (waveform L of Figure 5.6). This FET is
placed across ramp generating capacitor C1, and when
unclamped (turned off), the capacitor is allowed to charge
through resistor R1 to the supply voltage + V1. Thus, the Q1 COL.
voltage appearing on the drain will be an exponentially rising A
voltage with a dv/dt dictated by R1, C1, whose position in U2, P1
time can be advanced or delayed. This waveform is then B
applied through a blocking diode to the anode of the DUT for
U4, P4
the forward blocking voltage test. C
Another blocking diode, D1, also plays an important role in
tq measurements and must be properly selected. Its purpose IGT
D
is to prevent the dv/dt ramp from feeding back into the CONSTANT
Current Source and di/dt Circuit and also to momentarily CURRENT
GEN. E
apply a reverse blocking voltage (a function of – V2 of the Q5 COL.
di/dt circuit) to the DUT. Consequently, D1 must have a U2, P7
reverse recovery time trr greater than the DUT, but less than F
the tq time. When measuring standard recovery SCRs, its U5, P7
selection — fast recovery rectifiers or standard recovery — is G
not that critical, however, for fast recovery, low tq SCRs, the Q9 COL.
diode must be tailored to the DUT to produce accurate Q10–Q12
di/dt H
results. Also, the current rating of the diode must be CIRCUIT
compatible with the DUT test current. These effects are IT
illustrated in the waveforms shown in Figure 5.7 where both a DUT I
fast recovery rectifier and standard recovery rectifier were U6, P6 J
used in measuring tq of a standard 2N6058 SCR. Although dv/dt
CIRCUIT
the di/dt’s were the same, the reverse recovery current IRM K
and trr were greater with the standard recovery rectifier, Q15
GATE
resulting in a somewhat shorter tq (59 µs versus 63 µs). In dv/dt
fact, tq is affected by the initial conditions (ITM, di/dt, IRM, Q15
dv/dt, etc.) and these conditions should be specified to DRAIN L
dv/dt
maintain measurement repeatability. This is later described in OUTPUT 0 200 400 600 800
the published curves and tables. t, TIME (µs)
Finally, the resistor R1 and the resultant current I1 in the
dv/dt circuit must meet certain criteria: I1 should be greater
than the SCR holding current so that when the DUT does Figure 5.6. tq Test Fixture System Waveforms

Motorola Thyristor Device Data Theory and Applications

1.5–5
 I = 2 A/Div

0A
V = 10 V/Div

0V

tq = 63 µs t = 50 µs/Div t = 1 µs/Div

D1 = MR856, FAST RECOVERY RECTIFIER

I = 2 A/Div

0A
V = 10 V/Div

0V

tq = 59 µs t = 1 µs/Div
t = 50 µs/Div

D1 = 1N5402, STANDARD RECOVERY RECTIFIER

Figure 5.7. The Effects of Blocking Diode D1 on tq of a

2N6058 SCR

the breakdown voltage of the diverting power MOSFETS current magnitude (ITM), b) forward current duration, c) rate of
(VDSS = 60 V). The + 12 V unregulated supply can be as high change of turn–off current (di/dt), d) reverse–current magni-
as + 20 V when unloaded; therefore, – V2 (MAX), in theory, tude (IRM), e) reverse voltage (VRM), f) rate of reapplied
would be – 40 V but should be limited to less than – 36 V due forward voltage (dv/dt), g) magnitude limit of reapplied
to the 56 V protective Zener across the drain–source of the voltage, h) gate–cathode resistance and i) gate drive
FETs. Also, – V2 must be capable of handling the peak 60 A, magnitude (IGT).
diverting current, if so required. Typical data of this kind, taken for a variety of SCRs,
The reapplied forward blocking voltage power supply + V1, including standard SCRs, high speed SCRs, is condensed
may be as high as the DUT VDRM which conceivably can be and shown in Table 5.1. The data consists of the different
600 V, 1,000 V or greater and, since this supply is on most of conditions which the particular SCR types were subjected to;
the time, must be able to supply the required I1. Due to the ten SCRs of each type were serialized and tested to each
sometimes high power requirements, + V1 test conditions condition and the ten tq’s were averaged to yield a “typical tq.”
may have to be reduced for extremely fast SCRs. The conditions listed in Column A in Table 5.1, are typical
conditions that might be found in circuit operation. Columns B
PARAMETERS AFFECTING tq through J in Table 5.1, are in order of increasing tq; the
To see how the various circuit parameters can affect tq, conditions listed in these columns are only the conditions that
one condition at a time is varied while the others are held were modified from those in Column A and if a parameter is
constant. The parameters to be investigated are a) forward not listed, it is the same as in Column A.

Theory and Applications Motorola Thyristor Device Data

1.5–6
 Table 5.1. Parameters Affecting tq
Device A B C D E F G H I
2N6508 RGK = 1 k
25 A dv/dt = 15 V/µs
600 V ITM = 25 A RGK = 100 RGK = 100
IRM = 14 A dv/dt = 2.4 V/µs dv/dt = 2.4 V/µs RGK = 100

Motorola Thyristor Device Data

di/dt = – 100 A/µs ITM = 1 A ITM = 2 A dv/dt = 2.4 V/µs RGK = 100
ITM duration = 275 µs IRM = 1.8 A IRM = 50 mA IRM = 50 mA RGK = 100 RGK = 1 dv/dt = 2.4 V/µs
IGT = 30 mA di/dt = 32 A/µs di/dt = 0.5 µs di/dt = 0.45 A/µs dv/dt = 2.4 V/µs dv/dt = 2.4 V/µs ITM = 37 A RGK = 100 IGT = 90 mA

typ tq = 68 µs typ tq = 42 µs typ tq = 45 µs typ tq = 49 µs typ tq = 60 µs typ tq = 64 µs typ tq = 64 µs typ tq = 65 µs typ tq = 68 µs

2N6398 RGK = 1 k
12 A dv/dt = 90 V/µs
ITM = 12 A RGK = 100 RGK = 100 RGK = 100
IRM = 11 A dv/dt = 2.5 V/µs dv/dt = 2.5 V/µs RGK = 100 dv/dt = 2.5 V/µs RGK = 1
di/dt = – 100 A/µs ITM = 1 A ITM = 1 A dv/dt = 2.5 V/µs ITM = 18 A dv/dt = 2.5 V/µs
ITM duration = 275 µs IRM = 50 mA IRM = 2.7 A IRM = 50 mA IRM = 50 mA IRM = 50 mA
IGT = 30 mA di/dt = – 0.5 A/µs di/dt = 56 A/µs di/dt = 32 A/µs di/dt = 0.3 A/µs di/dt = 0.35 A/µs RGK = 100 IGT = 90 mA

typ tq = 48 µs typ tq = 30 µs typ tq = 31 µs typ tq = 32 µs typ tq = 33 µs typ tq = 35.5 µs typ tq = 45 µs typ tq = 48 µs

Theory and Applications

1.5–7
 Table 5.1. Continued
Device A B C D E F G H I

1.5–8
C106F IGT = 1 mA
4A RGK = 1 k
dv/dt = 5 V/ms
ITM = 4A
IRM = 4A ITM = 2 A ITM = 6 A ITM = 6 A dv/dt = 1.4 V/ms IGT = 90 mA
di/dt = 50 A/ms IRM = 2.5 A IRM = –1 A/ms IRM = 0.1 A ITM = 2 A –V2 = 35 V IRM = 0.15 A dv/dt = 1.4 V/ms dv/dt = 1.4 V/ms
ITM duration = 275 ms di/dt = –30 A/ms di/dt = –1 A/ms di/dt = –1 A/ms IRM = 0.2 A IRM = 0.2 A –V2 = 4 V IRM = 0.15 A IRM = 2 A
VDX = 50 V VDX = 50 V VDX = 150 V VDX = 50 V di/dt = –1.4 A/ms di/dt = –1.4 A/ms di/dt = –1.4 A/ms di/dt = 1.4 A/ms di/dt = –1.4 A/ms

Theory and Applications

typ tq = 28 ms typ tq = 25 ms typ tq = 26 ms typ tq = 26 ms typ tq = 26 ms typ tq = 27 ms typ tq = 27 ms typ tq = 27 ms typ tq = 27 ms

2N6240 RGK = 1 k
4A dv/dt = 40 V/ms RGK = 100
ITM = 4 A dv/dt = 1.3 V/ms RGK = 100 dv/dt = 1.75 V/ms RGK = 1
IRM = 4 A ITM = 1 A dv/dt = 1.75 V/ms RGK = 100 RGK = 100 dv/dt = 1.75 V/ms
di/dt = 50 A/ms IRM = 50 mA ITM = 1 A dv/dt = 1.75 V/ms ITM = 6 A RGK = 100 ITM = 1 A
ITM duration = 275 ms di/dt = –0.5 A/ms IRM = 50 mA IRM = 50 mA IRM = 50 mA IRM = 50 mA IRM = 50 mA
IGT = 1 mA IGT = 90 mA di/dt = –0.5 A/ms di/dt = –0.5 A/ms di/dt = –0.5 A/ms di/dt = –0.5 A/ms RGK = 100 di/dt = –0.5 A/ms
VDX = 50 V VDX = 150 V IGT = 90 mA IGT = 90 mA IGT = 90 mA IGT = 90 mA IGT = 900 mA IGT = 90 mA IGT = 90 mA

typ tq = 44.8 ms typ tq = 26 ms typ tq = 26.2 ms typ tq = 27.7 ms typ tq = 28.6 ms typ tq = 30 ms typ tq = 32.7 ms typ tq = 37.2 ms typ tq = 41.4 ms

MCR100–6 RGK = 1 k
0.8 A dv/dt = 160 V/ms
ITM = 0.8 A dv/dt = 30 V/ms
IRM = 0.8 A dv/dt = 30 V/ms dv/dt = 30 V/ms ITM = 1.12 A
di/dt = 12 A/ms ITM = 0.25 A dv/dt = 30 V/ms –V2 = 9 V –V2 = 1 V ITM = 1.12 A IRM = 40 mA
VDX = 50 V IRM = 40 mA Ir = 40 mA IRM = 20 mA Ir = 40 mA IRM = 40 mA di/dt = –0.8 A/ms
ITM duration = 275 ms di/dt = –0.6 A/ms di/dt = –0.8 A/ms di/dt = –0.4 A/ms di/dt = –0.8 A/ms di/dt = –0.8 A/ms VDX = 100 V

typ tq = 14.4 ms typ tq = 12.7 ms typ tq = 13.5 ms typ tq = 13.7 ms typ tq = 13.9 ms typ tq = 14.4 ms typ tq = 14.4 ms

2N5063 RGK = 1 k
0.8 A dv/dt = 30 V/ms
ITM = 0.8 A VDX = 100 V
IRM = 0.8 A dv/dt = 5 V/ms dv/dt = 5 V/ms dv/dt = 5 V/ms
di/dt = 12 A/ms ITM = 0.2 A dv/dt = 5 V/ms ITM = 1.12 A IRM = 40 mA IRM = 40 mA ITM = 1.12 A
ITM duration = 275 ms IRM = 50 mA IRM = 50 mA IRM = 50 mA –V2 = 9 V –V2 = 1 V IRM = 50 mA
VDX = 50 V di/dt = –0.6 A/ms di/dt = –0.8 A/ms di/dt = –0.8 A/ms di/dt = –0.45 A/ms di/dt = –0.8 A/ms di/dt = –0.8 A

typ tq = 28.9 ms typ tq = 27/ms typ tq = 30/ms typ tq = 31 ms typ tq = 31.2 ms typ tq = 31.4 ms typ tq = 31.7 ms

2N5061 dv/dt = 10 V/ms

0.8 A ITM = 0.8 A
IRM = 0.8 A dv/dt = 3.5 V/ms
di/dt = 18 A/ms dv/dt = 3.5 V/ms ITM = 1.12 A dv/dt = 3.58/ms
ITM duration = 275 ms ITM = 0.25 A dv/dt = –3.5 V/ms IRM = 40 mA ITM = 1.12 A –V2 = 4 V –V2 = 1 V
RGK = 1 k IRM = 40 mA IRM = 40 mA di/dt = –0.8 A/ms IRM = 40 mA IRM = 20 mA IRM = 40 mA
VDX = 30 V di/dt = –0.7 A/ms di/dt = –0.8 A/ms VDX = 60 V di/dt = –0.7 A/ms di/dt = –0.2 A/ms di/dt = –0.8 A/ms
typ tq = 31.7 ms typ tq = 19.1 ms typ tq = 19/ms typ tq = 19.8 ms typ tq = 20.2 ms typ tq = 30 ms typ tq = 30.2 ms

Motorola Thyristor Device Data

 Table 5.2 is a condensed summary of Table 5.1 and shows 1st 2nd
what happens to the tq of the different devices when a Parameter Changed Device Columns (µs) (µs)
parameter is varied in one direction or the other. IGT Increase 2N6508 AI 68 68
2N6398 AG 48 48
THE EFFECT OF CHANGING PARAMETERS 2N6240 AI 44.8 41.4
ON tq C106D HI 27 27
From Tables 5.1 and 5.2, it is clear that some parameters Decrease RGK 2N6508 AH 68 65
affect tq more than others. The following discussion de- 1 k to 100 ohms 2N6398 AG 48 45
scribes the effect on tq of the various parameters. 2N6240 GI 41.4 32.7
Increase RGK 2N6508 EF 60 64
FORWARD CURRENT MAGNITUDE (ITM)
Of the parameters that were investigated, forward–current 1 k to R 2N6398 DF 32 35.5
2N6240 CH 26.2 37.2
magnitude and the di/dt rate have the strongest effect on tq.
Varying the ITM magnitude over a realistic range of ITM VDX C106D DC 26 26
conditions can change the measured tq by about 30%. The 2N6240 BC 26.2 26
change in tq is attributed to varying current densities (stored MCR100–6 FG 14.4 14.4
charge) present in the SCR’s junctions as the ITM magnitude 2N5063 DG 31 31.7
is changed. Thus, if a large SCR must have a short tq when a 2N5061 DE 20.2 19.8
low ITM is present, a large gate trigger pulse (IGT magnitude) Decrease dv/dt Rate 2N6508 EH 65 60
would be advantageous. This turns on a large portion of the C106D HJ 29 27
SCR to minimize the high current densities that exists if only 2N6240 DF 30 27.7
a small portion of the SCR were turned on (by a weak gate Increase ITM 2N6508 EG 60 64
pulse) and the low ITM did not fully extend the turned on 2N6398 DE 32 33
region. C106D EH 26 27
In general, the SCR will exhibit longer tq times with 2N6240 DC 26.2 27.7
increasing ITM. Increasing temperature also increases the tq DE 27.7 28.6
time. CE 26.2 28.6
MCR100–6 CF 13.5 14.4
di/dt RATE 2N5063 CD 30.7 31
Varying the turn–off rate of change of anode current di/dt 2N5061 BE 19.1 20.7
does have some effect on the tq of SCRs. Although the Table 5.2. The Effects of Changing Parameters on tq
increase in tq versus increasing di/dt was nominal for the
SCRs illustrated, the percentage change for the fast SCRs
was fairly high (about 30 – 40%). rate constant while changing IRM. It was found that IRM has
little or no effect on tq when it is the only variable changed
REVERSE CURRENT MAGNITUDE (IRM) (see Table 5.1 C106D, Columns F and G, for example).
The reverse current is actually due to the stored charge
clearing out of the SCR’s junctions when a negative voltage
is applied to the SCR anode. IRM is very closely related to the REVERSE ANODE VOLTAGE (VRM)
di/dt rate; an increasing di/dt rate causing an increase of IRM Reverse anode voltage has a strong effect on the IRM
and a decreasing di/dt rate causing a lower IRM. magnitude and the di/dt rate, but when VRM alone is varied,
By using different series inductors and changing the with IRM and di/dt held constant, little or no change in tq time
negative anode turn–off voltage, it is possible to keep the was noticed. VRM must always be within the reverse voltage
di/dt of the device.

Gate Bias Conditions + V1 RI dv/dt (v/µs)

0V –5V – V2 = –10 V, IF = 3 A 50 V 1 k/50 2.5/50
Device
Diode dv/dt
tq1 tq2 Remarks
DI (V/µs)
Slow
2N6508 40 µs 30 µs 2.5 Slow diode faster than fast diode, (lower tq)
MR502
2N6240 16 µs 9 µs Slow 2.5 Slow diode faster. 2.5 V/µs faster than 50 V/µs
2N6398 30 µs 25 µs Slow 2.5 Tested slow diode only
C106D 13 µs 8 µs Slow 2.5 Tested slow diode only
Table 5.3 The Effects of Gate Bias on tq

Motorola Thyristor Device Data Theory and Applications

1.5–9
 25 SCR’s tq time unless it is grossly overdriven or underdriven.
STANDARD SCR di/dt
When it is overdriven, there is an unnecessary large amount
20 C106 : 5 A/ µs of charge in SCR’s junction. When underdriven, it is possible
C106D
t q, TURN-OFF TIME (µs)
dv/dt : 45 V/ µs that only a small portion of the chip at the gate region turns
RGK : 100 Ω
15 on. If the anode current is not large enough to spread the
TA : 25°C
small turned on region, there is a high current and charge
10 density in this region that consequently lengthens the tq time.

FORWARD CURRENT DURATION

5
Forward current duration had no measurable effect on tq
time when varied from 100 µs to 300 µs, which were the limits
0
1 2 5 10 20 50 of the Motorola tq Tester. Longer ITM durations heat up the
SCR which causes temperature effects; very short ITM
ITM, ANODE CURRENT (AMPS)
durations affect the tq time due to the lack of time for the
Figure 5.8. Standard SCR Turn–Off Time tq as a charges in the SCR’s junctions to reach equilibrium, but
Function of Anode Current ITM these effects were not seen in the range tested.

REAPPLIED dv/dt RATE REVERSE GATE BIAS VOLTAGE

Varying the reapplied dv/dt rate across the range of dv/dt’s As in transistor operation, reverse biasing the gate of the
commonly encountered can vary the tq of a given SCR by SCR decreases the turn–off time, due to the rapid “sweeping
more than 10%. The effect of the dv/dt rate on tq is due to the out” of the stored charge. The reduction in tq for standard
Anode–Gate capacitance. The dv/dt applied at the SCR SCRs is quite pronounced, approaching perhaps 50% in
anode injects current into the gate through this capacitance some cases; for fast SCRs, only nominal improvement might
(iGT = C dv/dt). As the dv/dt rate increased, the gate current result. Table 5.3 shows this effect on six SCRs where the
also increases and can trigger the SCR on. To complicate gate bias was set for 0 V and – 5 V, respectively (the 1 k gate
matters, this injected current also adds to the current due to resistor of the DUT was either grounded or returned to – 5 V).
leakage or stored charge left in the junctions just after Due to the internal, monolithic resistor of most SCRs, the
turn–off. actual reverse bias voltage between the gate–cathode is less
The stored charge remaining in the center junction is the than the reverse bias supply.
main reason for long tq times and, for the most part, the
charge is removed by the recombination process. If the
CHARACTERIZING SCRs FOR CROWBAR
reapplied dv/dt rate is high, more charge is injected into this
junction and prevents it from returning to the blocking state, APPLICATIONS
as soon as if it were a slow dv/dt rate. The higher the dv/dt
rate, the longer the tq times will be. The use of a crowbar to protect sensitive loads from power
supply overvoltage is quite common and, at the first glance,
MAGNITUDE LIMIT OF REAPPLIED dv/dt (VDX) the design of these crowbars seems like a straightforward,
Changing the magnitude limit of the reapplied dv/dt voltage relatively simple task. The crowbar SCR is selected so as to
has little or no effect on a given SCR’s tq time when the handle the overvoltage condition and a fuse is chosen at 125
maximum applied voltage is well below the voltage break- to 250% of the supply’s rated full–load line current. However,
down of the SCR. The tq times will lengthen if the SCR is upon further investigation, other questions and problems are
being used near its voltage breakdown, since the leakage encountered.
present near breakdown is higher than at lower voltage How much overvoltage and for how long (energy) can the
levels. The leakage will lengthen the time it takes for the load take this overvoltage? Will the crowbar respond too
charge to be swept out of the SCR’s center junction, thus slowly and thus not protect the load or too fast resulting in
lengthening the time it takes for this junction to return to the false, nuisance triggering? How much energy can the
blocking state. crowbar thyristor (SCR) take and will it survive until the fuse
opens or the circuit breaker opens? How fast will the fuse
GATE CATHODE RESISTANCE (RGK)
open, and at what energy level? Can the fuse adequately
In general, the lower the RGK is, the shorter the tq time will
be for a given SCR. This is because low RGK aids in the differentiate between normal current levels — including surge
removal of stored charge in the SCR’s junctions. An currents — and crowbar short circuit conditions?
approximate 15% change in the tq time is seen by changing It is the attempt of this section to answer these questions
RGK from 100 ohms to 1000 ohms for the DUTs. — to characterize the load, crowbar, and fuse and thus to
match their characteristics to each other.
GATE DRIVE MAGNITUDE (IGT) The type of regulator of most concern is the low voltage,
Changing the gate drive magnitude has little effect on a series pass regulator where the filter capacitors to be

Theory and Applications Motorola Thyristor Device Data

1.5–10
crowbarred, due to 60 Hz operation, are relatively large and 20
the charge and energy stored correspondingly large. On the
other hand, switching regulators operating at about 20 kHz TJ ≈ 85°C, DUTY CYCLE = 10%

V , SUPPLY VOLTAGE (VOLTS)

18
require smaller capacitors and thus have lower crowbar VCC
constraints. 5V
These regulators are quite often line–operated using a 16 PULSE WIDTH
high voltage, two–transistor inverter, half bridge or full
bridge, driving an output step–down transformer. If a
transistor were to fail, the regulator–transformed power 14
would be less and the output voltage would drop, not rise,
as is the case for the linear series regulator with a shorted 12

CC
pass transistor. Thus, the need for overvoltage protection
of these types of switching regulators is minimized.
This premise, however, does not consider the case of 10
1 5 10 30 50 100 300 500
the lower power series switching regulator where a
shorted transistor would cause the output voltage to rise. PULSE WIDTH (ms)
Nor does it take into account overvoltage due to transients Figure 5.9. Pulsed Supply Voltage versus Pulse Width
on the output bus or accidental power supply hookup. For
3 to 18 V, is quite immune to most overvoltage conditions.)
these types of operations, the crowbar SCR should be
But, can the TTL sustain 8 V or 10 V or 15 V and, if so, for
considered.
how long and for how many power cycles? Safe Operating
HOW MUCH OVERVOLTAGE CAN THE Area (SOA) of the TTL must be known. Unfortunately, this
information is not readily available and has to be generated.
LOAD TAKE?
Using the test circuit illustrated in Appendix III, a quasi–
Crowbar protection is most often needed when ICs are SOA curve for a typical TTL gate was generated (Figure 5.9).
used, particularly those requiring a critical supply voltage Knowing the overvoltage–time limit, the crowbar and fuse
such as TTL or expensive LSI memories and MPUs. energy ratings can be determined.
If the load is 5 V TTL, the maximum specified continuous The two possible configurations are illustrated in Figure
voltage is 7 V. (CMOS, with its wide power supply range of 5.10, the first case shows the crowbar SCR across the

(a). SCR Across Input of Regulator D1

F

SERIES
Vin REGULATOR

OVERVOLTAGE
SENSE vO
Cin Co

(b). SCR Across Output of Regulator

*
Vin REGULATOR

vO
OVERVOLTAGE
SENSE

*NEEDED IF SUPPLY NOT CURRENT LIMITED

Figure 5.10. Typical Crowbar Configurations

Motorola Thyristor Device Data Theory and Applications

1.5–11
input of the regulator and the second, across the output. For Additionally, the usually much larger input filter capacitor
both configurations, the overvoltage comparator senses the will have to be dumped if the regulator were to short, although
load voltage at the remote load terminals, particularly when that energy to be dissipated will be dependent on the total
the IR drop of the supply leads can be appreciable. As long resistance in the circuit between that capacitor and the SCR
as the output voltage is less than that of the comparator crowbar.
reference, the crowbar SCR will be in an off state and draw The charge to be crowbarred would be
no supply current. When an over–voltage condition occurs,
the comparator will produce a gate trigger to the SCR, firing it, Q + CV + IT,
and thus clamping the regulator input, as in the first case — the energy,
to the SCRs on–state drop of about 1 to 1.5 V, thereby
protecting the load. E + 1ń2 CV2
Placing the crowbar across the input filter capacitors, and the peak surge current
although effectively clamping the output, has several disad-
vantages.
1. There is a stress placed on the input rectifiers during the i pk + VRCT
crowbarring short circuit time before the line fuse opens,
When the SCR crowbars the capacitor, the current
particularly under repeated operation.
waveform will be similar to that of Figure 5.11, with the peak
2. Under low line conditions, the minimum short circuit
surge current, ipk, being a function of the total impedance in
current can be of the same magnitude as the maximum
the circuit (Figure 5.12) and will thus be limited by the
primary line current at high line, high load, making the proper
Equivalent Series Resistance (ESR) and inductance (ESL) of
fuse selection a difficult choice.
the capacitor plus the dynamic impedance of the SCR, any
3. The capacitive energy to be crowbarred (input and
external current limiting resistance, (and inductance) of the
output capacitor through rectifier D1) can be high.
interconnecting wires and circuit board conductors.
When the SCR crowbar and the fuse are placed in the dc
The ESR of computer grade capacitors, depending on the
load circuit, the above problems are minimized. If crowbar-
capacitor size and working voltage, might vary from 10 to
ring occurs due to an external transient on the line and the
1000 milliohms (mΩ). Those used in this study were in the 25
regulator’s current limiting is working properly, the SCR only
to 50 mΩ range.
has to crowbar the generally smaller output filter capacitor
The dynamic impedance of the SCR (the slope of the
and sustain the limited regulator current.
on–state voltage, on–state current curve), at high currents,
If the series pass devices were to fail (short), even with
might be in the 10 to 20 mΩ range. As an example, from the
current limiting or foldback disabled, the crowbarred energy
on–state characteristics of the MCR70, 35 A rms SCR, the
would generally be less than of the previous case. This is due
dynamic impedance is
to the higher impedance of the shorted regulator (due to
(4.5 * 3.4)V
emitter sharing and current sensing resistors) relative to that
of rectifier D1. rd + DDVIFF + (300 * 200)A + 100 A `11 mΩ.
1.1 V

Fuse selection is much easier as a fault will now give a

The interconnecting wire might offer an additional 5 mΩ
greater percentage increase in dc load current than when
measuring transformer primary or secondary rms current. (#20 solid copper wire ` 20 mΩ/ft) so that the total circuit
The disadvantage, however, of placing the fuse in the dc load resistance, without additional current limiting, might be in the
is that there is no protection for the input rectifier, capacitor, 40 to 70 mΩ range. The circuit inductance was considered
low enough to ignore so far as ipk is concerned for this
and transformer, if one of these components were to fail
exercise, being in hundreds of nanohenry range (ESL ` 3
(short). Secondly, the one fuse must protect not only the load
and regulator, but also have adequate clearing time to protect `
nH, L wire 500 nH/ft). However, di/dt will be affected by the
the SCR, a situation which is not always readily accom- inductance.
plished. The input circuitry can be protected with the addition
of a primary fuse or a circuit breaker.
HOW MUCH ENERGY CAN THE CROWBAR SCR
SUSTAIN?
There are several factors which contribute to possible SCR
HOW MUCH ENERGY HAS TO BE failures or degradation — the peak surge current, di/dt, and a
CROWBARRED? measure of the device’s energy capability, I2t.
If the peak current and/or duration of the surge is large,
This is dictated by the power supply filter capacitors, which destruction of the device due to excessive dissipation can
are a function of output current. A survey of several linear occur. Obviously, the ipk can be reduced by inserting
power supply manufacturers showed the output filter capaci- additional impedance in the crowbar path, at an increase in
tor size to be from about 100 to 400 microfarads per ampere dump time. However, this time, which is a measure of how
with about 200 µF/A being typical. A 30 A regulator might long the overvoltage is present, should be within the SOA of
therefore have a 6000 µF output filter capacitor. the load.

Theory and Applications Motorola Thyristor Device Data

1.5–12
 I

ipk

0
t = 0.5 ms/Div
50%

di/dt

10%

2.3 τ 5τ t
tW
10%

tW
0
t = 10 µs/Div
CROWBAR CURRENT TERMS I = 200 A/Div RS = 0
MCR69 VC = 30 V
C = 22,000 µF IGT = 200 mA

Figure 5.11. Typical SCR Crowbar Waveform

The energy stored in the capacitor being a constant for a fast rise time (< 1 µs). The gate current pulse width should be
particular voltage would suggest that the I2t integral for any greater than the propagation time; a figure of 10 µs minimum
limiting resistance is also a constant. In reality, this is not the should satisfy most SCRs with average current ratings under
case as the thermal response of the device must be taken 50 A or so.
into consideration. It has been shown that the dissipation The wiring inductance alone is generally large enough to
capability of a device varies as to the Ǹt for the first tens of
limit the di/dt. Since most SCRs are good for over 100 A/µs,
this effect is not too large a problem. However, if the di/dt is
milliseconds of the thermal response and, in effect, the
found excessive, it can be reduced by placing an inductance
measure of a device’s energy capability would be closer to
i2 Ǹt. This effect is subsequently illustrated in the empirically
RW LW

derived ipk versus time derating curves being a non–linear

function. However, for comparison with fuses, which are
rated in I2t, the linear time base, “ t,” will be used.
ESR RS
The di/dt of the current surge pulse is also a critical
parameter and should not exceed the device’s ratings
(typically about 200 A/µs for 50 A or less SCRs). The
magnitude of di/dt that the SCR can sustain is controlled by ESL LS
the device construction and, to some extent, the gate drive
conditions. When the SCR gate region is driven on,
conduction across the junction starts in a small region and
progressively propagates across the total junction. Anode
current will initially be concentrated in this small conducting
area, causing high current densities which can degrade and
ultimately destroy the device. To minimize this di/dt effect, the RW, LW: INTERCONNECTING WIRE IMPEDANCE
gate should be turned on hard and fast such that the area RS, LS: CURRENT LIMITING IMPEDANCE
turned on is initially maximized. This can be accomplished
with a gate current pulse approaching five times the Figure 5.12. Circuit Elements Affecting SCR
maximum specified continuous gate current, Igt, and with a Surge Current

Motorola Thyristor Device Data Theory and Applications

1.5–13
 100

DUT
V 22,000 µF 50
H.P. 214A
PULSE
GENERATOR
EXTERNAL
TRIGGER

Figure 5.13

in the loop; but, again, this increases the circuit’s response Device VC ipk t
time to an overvoltage and the trade–off should be consid-
ered. MCR68 12 V 250 A 1.5 ms
Since many SCR applications are for 60 Hz line operation, MCR69 30 V 800 A 1.5 ms
the specified peak non–repetitive surge current ITSM and
circuit fusing I2t are based on 1/2 cycle (8.3 ms) conditions.
For some SCRs, a derating curve based on up to 60 or 100 To determine the effect of gate drive on the SCRs, three
cycles of operation is also published. This rating, however, devices from each line were characterized at non–destruct
does not relate to crowbar applications. To fully evaluate a levels using three different capacitors (200, 6,000, and
crowbar system, the SCR must be characterized with the 22,000 µF), three different capacitor voltages (10, 20, and
capacitor dump exponential surge current pulse. 30 V), and three different gate drives (IGT(MAX), 5
A simple test circuit for deriving this pulse is shown in
IGT(MAX), and a ramp IGT(MAX) with a di/dt of about 1
Figure 5.13, whereby a capacitor is charged through a
mA/µs). Due to its energy limitations, the MCR68 was tested
limiting resistor to the supply voltage, V, and then the charge
is dumped by the SCR device under test (DUT). The SCR with only 10 V across the larger capacitors.
gate pulse can be varied in magnitude, pulse width, and rise The slow ramp, IGT, was used to simulate overvoltage
time to produce the various IGT conditions. An estimate of the sense applications where the gate trigger rise time can be
crowbar energy capability of the DUT is determined by first slow such as with a coupling zener diode.
dumping the capacitor charged to low voltage and then No difference in SCR current characteristics were noted
progressively increasing the voltage until the DUT fails. This with the different gate current drive conditions; the peak
is repeated for several devices to establish an average and currents were a function of capacitor voltage and circuit
minimum value of the failure points cluster. impedance, the fall times related to RTC, and the rise times,
This procedure was used to test several different SCRs of tr, and di/dt, were more circuit dependent (wiring inductance)
which the following Table 5.4 describes several of the and less device dependent (SCR turn–on time, ton). Since
pertinent energy specifications and also the measured
the wiring inductance limits, tr, the effect of various IGTs was
crowbar surge current at the point of device failure.
masked, resulting in virtually identical waveforms.
This one–shot destruct test was run with a gate current of
five IGT(MAX) and a 22,000 µF capacitor whose ESR The derated surge current, derived from a single (or low
produced the exponentially decaying current pulse about 1.5 number) pulse test, does not truly reflect what a power supply
ms wide at its 10% point. Based on an appropriate derating, crowbar SCR might have to see over the life of the supply.
ten devices of each line where then successfully tested Life testing over many cycles have to be performed; thus, the
under the following conditions. circuit described in Appendix IV was developed. This life test

Table 5.4. Specified and Measured Current Characteristics of Three SCRs

Measured Crowbar
Maximum Specified Values
Surge Current Ipk
Device Case
IT(rms) IT(AV) ITSM* I2t IGT(Max) Min Max Ave
(A) (A) (A) (A2s) (mA) (A) (A) (A)
MCR68 TO–220 12 8 100 40 30 380 750 480
MCR69 TO–220 25 16 300 375 30 1050 1250 1100
* ITSM = Peak Non–Repetitive Surge Current, 1/2 cycle sine wave, 8.3 ms.

Theory and Applications Motorola Thyristor Device Data

1.5–14
 C = 8400 µF TA = 25°C Ipk
1
ESR ≈ 25 mΩ N = 2000 PULSES
p
VC 60 V f = 3 PULSES/MIN.
N = 2000 PULSES

NORMALIZED PEAK SURGE CURRENT

Ipk , PEAK CURRENT (AMPS)

3000
tW 5 TC 0.8
1000
MCR69
300 0.6
MCR68
100
0.4
30

0.2
0.1 0.5 1 5 10 50 100 0 25 50 75 100 125
tW, BASE PULSE WIDTH (ms) TC, AMBIENT TEMPERATURE (°C)
Figure 5.14(a). Peak Surge Current versus Pulse Width (b). Peak Surge Current versus Ambient Temperature

fixture can simultaneously test ten SCRs under various The logic load has its own overvoltage SOA as a function
crowbar energy and gate drive conditions. of time (Figure 5.9). The crowbar SCR must clamp the
Each of the illustrated SCRs of Figure 5.14(a) were tested overvoltage within a specified time, and still be within its own
with as many as four limiting resistors (0, 50, 100, and 240 energy rating; thus, the series–limiting resistance, RS, in the
mΩ) and run for 1000 cycles at a nominal energy level. If no crowbar path must satisfy both the load and SCR energy
failures occurred, the peak current was progressively in- limitations. The overvoltage response time is set by the total
creased until a failure(s) resulted. Then the current was limitations. The overvoltage response time is set by the total
reduced by 10% and ten new devices were tested for 2000 limiting resistance and dumped capacitor(s) time constant.
cycles (about six hours at 350 cycles/hour). If this test proved Since the SOA of the TTL used in this exercise was derived
successful, the data was further derated by 20% and plotted by a rectangular overvoltage pulse (in effect, over–energy),
as shown on log–log paper with a slope of – 1/4. This
Ǹ
theoretical slope, due to the I2 t one–dimensional heat–flow
the energy equivalent of the real–world exponentially falling
voltage waveform must be made. An approximation can be
relationship (see Appendix VI), closely follows the empirical made by using an equivalent rectangular pulse of 0.7 times
results. Of particular interest is that although the peak current the peak power and 0.7 times the base time.
increases with decreasing time, as expected, the I2t actually Once an overvoltage is detected and the crowbar is
decreases. enabled, in addition to sustaining the peak current, the SCR
Figure 5.14(b) shows the effect of elevated ambient must handle the regulator short–circuit current for the time it
temperature on the peak current capability of the illustrated takes to open the fuse.
SCRs. Thus, all three elements are tied together — the load can
take just so much overvoltage (over–energy) and the
FUSE CHARACTERISTICS crowbar SCR must repeatedly sustain for the life of the
equipment an rms equivalent current pulse that lasts for
SCRs, like rectifiers, are generally rated in terms of
the fuse response time.
average forward current, IT(AV), due to their half–wave
It would seem that the matching of the fuse to the SCR
operation. Additionally, an rms forward current, IT(rms), a peak
would be straightforward — simply ensure that the fuse rms
forward surge current, ITSM, and a circuit–fusing energy limit,
current rating never exceed the SCR rms current rating
I2t, may be shown. However, these specifications, which are
(Figure 5.15), but still be sufficient to handle steady–state
based one–half cycle 60 Hz operation, are not related to the
and normal overload currents. The more exact relationship
crowbar current pulse and some means must be established
would involve the energy dissipated in the system ∫ I2Rdt,
to define their relationship. Also, fuses which must ultimately
which on a comparative basis, can be reduced to I2t. Thus,
match the SCR and the load, are rated in rms currents.
the “let–through” I2t of the fuse should not exceed I2t
The crowbar energy curves are based on an exponentially
capability of the SCR under all operating conditions. These
decaying surge current waveform. This can be converted* to
conditions are many, consisting of “available fault current,”
Irms by the equation.
I rms 0.316 ipk + power factor of the load, supply voltage, supply frequency,
ambient temperature, and various fuse factors affecting the
which now allows relating the SCR to the fuse. I2t.
There has been much detailed information published on
fuse characteristics and, rather than repeat the text which
*See Appendix V would take many pages, the reader is referred to those

Motorola Thyristor Device Data Theory and Applications

1.5–15
sources. Instead, the fuse basics will be defined and an FUSE VOLTAGE PEAK ARC VOLTAGE
example of matching the fuse to the SCR will be shown.
In addition to interrupting high current, the fuse should limit SUPPLY
VOLTAGE
the current, thermal energy, and overvoltage due to the high
current. Figure 5.16 illustrates the condition of the fuse at the
INSTANT OF SHORT
moment the over–current starts. The peak let–through MELTING TIME
ARCING TIME
current can be assumed triangular in shape for a first–order CLEARING TIME
approximation, lasting for the clearing time of the fuse. This PEAK ASYMMETRICAL
time consists of the melting or pre–arcing time and the arcing FAULT CURRENT
time. The melting time is an inverse function of over–current FUSE CURRENT
and, at the time that the fuse element is opened, an arc will PEAK FUSE CURRENT
be formed causing the peak arc voltage. This arc voltage is
IPLT
both fuse and circuit dependent and under certain conditions
can exceed the peak line voltage, a condition the user should
ensure does not overstress the electronics.
The available short–circuit current is the maximum current
the circuit is capable of delivering and is generally limited by Figure 5.16. Typical Fuse Timing Waveforms During
the input transformer copper loss and reactance when the Short Circuit
crowbar SCR is placed at the input to the regulator or the triangular waveform for IPLT, the total clearing time, tc, would
regulator current limiting when placed at the output. For a then approximately be
fuse to safely protect the circuit, it should limit the peak 2
let–through current and clear the fault in a short time, usually tc ≈ 3 I t
I PLT2
less than 10 ms.
Fuse manufacturers publish several curves for character- Once tc of the fuse is known, the comparison with the SCR
izing their products. The current–time plot, which describes can readily be made. As long as the I2t of the fuse is less than
current versus melting time (minimum time being 10 ms), is the I2t of the SCR, the SCR is protected. It should be pointed
used in general industrial applications, but is not adequate for out that these calculations are predicated on a known value
protecting semiconductors where the clearing time must be of available fault current. By inspection of Figure 5.18, it can
in the subcycle range. Where protection is required for be seen that IPLT can vary greatly with available fault current,
normal multicycle overloads, this curve is useful. which could have a marked effect on the degree of
Two other useful curves, the total clearing I2t characteristic protection. Also, the illustrated curves are for particular
and the peak let–through current IPLT characteristic, are operating conditions; the curves will vary somewhat with
illustrated in Figures 5.17 and 5.18 respectively. Some applied voltage and frequency, initial loading, load power
vendors also show total clearing time curves (overlayed on factor, and ambient temperature. Therefore, the reader is
Figure 5.17 as dotted lines) which then allows direct referred to the manufacturer’s data sheet in those cases
comparison with the SCR energy limits. When this clearing where extrapolation will be required for other operating
time information is not shown, then the designer should conditions. The final proof is obtained by testing the fuse in
determine the IPLT and I2t from the respective curves and the actual circuit under worst–case conditions.
then solve for the clearing time from the approximate
equation relating these two parameters. Assuming a CROWBAR EXAMPLE
To illustrate the proper matching of the crowbar SCR to the
load and the fuse, consider the following example. A 50 A
TTL load, powered by a 60 A current limited series regulator,
CURRENT I rms (LOG)

SCR CHARACTERISTICS
has to be protected from transients on the supply bus by
crowbarring the regulator output. The output filter capacitor of
10,000 µF (200 µF/A) contributes most of the energy to be
FUSE crowbarred (the input capacitor is current limited by the
CHARACTERISTIC regulator). The transients can reach 18 V for periods 100 ms.
Referring to Figure 5.9, it is seen that this transient
Irms (max) exceeds the empirically derived SOA. To ensure safe
LIMITED BY FUSE operation, the overvoltage transient must be crowbarred
10 ms 4 HRS within 5 ms. Since the TTL SOA is based on a rectangular
TIME t (LOG) power pulse even though plotted in terms of voltage, the
equivalent crowbarred energy pulse should also be derived.
Figure 5.15. Time–Current Characteristic Curves Thus, the exponentially decaying voltage waveform should
of a Crowbar SCR and a Fuse be multiplied by the exponentially decaying current to result

Theory and Applications Motorola Thyristor Device Data

1.5–16
 4
SF 13X SERIES
130 Vrms, 60 Hz
TA = 25°C
p 15%
20 A
POWER FACTOR
102
15 A

LET-THROUGH I2t (A2S)

4

10 A

10

5 ms 2 ms 1.5 ms TOTAL CLEARING TIME

1
10 4 102 4 103 4 104 4 105
AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS)

Figure 5.17. Maximum Clearing I2t Characteristics

for 10 to 20 A Fuses

in an energy waveform proportional to e–2x. The rectangular faults (shorts), but its selection, which is based on the
equivalent will have to be determined and then compared respective energy limits of those components, is not part of
with the TTL SOA. However, for simplicity, by using the this exercise.
crowbarred exponential waveform, a conservative rating will If a crowbar discharge time of 3 ms were chosen, it would
result. not only be within the rectangular pulsed SOA, but also be
To protect the SCR, a fuse must be chosen that will open well within the derived equivalent rectangular model of the
before the SCR’s I2t is exceeded, the current being the exponential waveform. It would also require about 1.3 time
regulator limiting current which will also be the available fault
constants for the overvoltage to decay from 18 V to 5 V; thus,
current to the fuse.
the RC time constant would be 3 ms/1.3 or 2.3 ms.
The fuse could be eliminated by using a 60 A SCR, but the
cost versus convenience trade–off of not replacing the fuse is The limiting resistance, RS would simply be
not warranted for this example. A second fuse or circuit
breaker will protect the rectifiers and regulator for internal
RS + 10,2.3000msmF + 0.23 W ` 0.2 W
INSTANTANEOUS PEAK LET-THROUGH CURRENT (AMPS)

103 20 A

MAX PEAK AVAILABLE CURRENT

4
(2.35 x SYMMETRICAL rms AMPERES)
15 A
10 A
102

4
SF 13X SERIES
130 Vrms, 60 Hz
POWER FACTOR p 15%
10
10 4 102 4 103 4 104 4 105
AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS)

Figure 5.18. Peak Let–Through Current versus Fault

Current for 10 to 20 A Fuses

Motorola Thyristor Device Data Theory and Applications

1.5–17
Since the capacitor quickly charges up to the over–voltages The circuit designer can then make the cost/performance
VCC1 of 18 V, the peak capacitor discharge current would be trade–offs.
All of these ratings are predicated on the fuse operating
I pk
V CC1
RS
+ 18 V
0.2 W
+90 A + within 6 ms.
With an available fault current of 60 A, Figure 5.17 shows
The rms current equivalent for this exponentially decaying that a 10 A (SF13X series) fuse will have a let–through I2t of
pulse would be about 10 A2s and a total clearing time of about 6 ms,
I rms + 0.316 Ipk + 0.316(90) + 28.4 A rms satisfying the SCR requirements, that is,

Now referring to the SCR peak current energy curves I 2t fuset I2t SCR
(Figure 5.14), it is seen that the MCR68 can sustain 210 A
peak for a base time of 3 ms. This 12 A SCR must also
tcp 6 ms
sustain the 60 A regulator limited current for the time required Figure 5.18 illustrates that for the same conditions,
to open the fuse. The MCR68 has a specified peak forward instantaneous peak let–through current of about 70 A would
surge current rating of 100 A (1/2 cycle, sine wave, 60 Hz, result. For fuse manufacturers that don’t show the clearing
non–repetitive) and a circuit fusing rating of 40 A2s. time information, the approximate time can be calculated
The non–repetitive rating implies that the device can from the triangular model, as follows
sustain 100 occurrences of this 1/2 cycle surge over the life
of the device; the SCR crowbar surge current curves were tc + I3 I2t2 + (70)
3(10)
2
+ 6.1 ms
based on 2000 cycles. PLT
For the 3 ms time frame, the I12t1 for the exponential
waveform is The fuse is now matched to the SCR which is matched to the

+ +
logic load. Other types of loads can be similarly matched, if
2
I1 t1 (28.4 A)2(3 ms) 2.4 A 2s the load energy characteristics are known.
Assuming that the fuse will open within 6 ms, the approxi-
mate energy that the SCR must sustain would be 60 A for an CHARACTERIZING SWITCHES AS LINE–TYPE
additional 3 ms. By superposition, this would amount to MODULATORS
2
I2 t2 + (60 A)2(6 ms) + 21.6 A2s In the past, hydrogen thyratrons have been used exten-
which , when added to the exponential energy, would result in sively as discharge switches for line type modulators. In
24 A2. general, such devices have been highly satisfactory from an
The MCR68 has a 40 A2s rating based on a 1/2 cycle of electrical performance standpoint, but they have some major
8.3 ms. Due to the one–dimensional heat flow in the device, drawbacks including relatively large size and weight, low
the energy capability is not linearly related to time, but varies efficiency (due to filament power requirements), and short life
Ǹ
as to the t. Therefore, with a 6 ms 1/2–cycle sine wave, the expectancy compared with semiconductor devices, now can
40 A2t rating would now decrease to approximately (see be eliminated through the use of silicon controlled rectifiers.

ǒǓ
Appendix VI for derivation). A line type modulator is a modulator whose output–pulse

ń
1 2
characteristics are determined by a lumped–constant trans-
mission line (pulse forming network) and by the proper match
2
I2 t2 + 2
I1 t1
t2
t1
of the line impedance (PFN) to the load impedance.

ǒ Ǔń
A switch for this type modulator should only initiate

+ 40 A2s
1 2 conduction and should have no effect on pulse characteris-
6 ms
8.3 ms tics. This is in contrast to a hard switch modulator where

+ 34 A2s output pulse characteristics are determined by the “hard”

relationship of grid (base) control of conduction through a
vacuum tube (transistor) switch.
Although the 1/2 cycle extrapolated rating is greater than the Referring to the schematic (Figure 5.25), when the power
actual crowbar energy, it is only characterized for 100 cycles supply is first turned on, no charge exists in the PFN, and
of operation. energy is transferred from the power supply to the PFN via
To ensure 2000 cycles of operation, at a somewhat higher the resonant circuit comprising the charging choke and PFN
cost, the 25 A MCR69 could be chosen. Its exponential peak capacitors. At the time that the voltage across the PFN
current capability, at 3 ms, is about 560 A and has a specified capacitors reaches twice the power supply voltage, current
ITSM of 300 A for 8.3 ms. The I2t rating is not specified, but through the charging choke tries to reverse and the power
can be calculated from the equation supply is disconnected due to the back biased impedance of
2 the hold–off diode. If we assume this diode to be perfect, the
I 2t + (ITSM
2
)
t+
(300 A)2
2
(8.3 ms) + 375 A 2s energy remains stored in the PFN until the discharge switch
is triggered to its on state. When this occurs, assuming that
Extrapolating to 6 ms results in about 318 A2s, an I2t rating the pulse transformer has been designed to match the load
much greater than the circuit 24 A2s value. impedance to the PFN impedance, all energy stored in the

Theory and Applications Motorola Thyristor Device Data

1.5–18
PFN reactance will be transferred to the load if we neglect TURN–ON TIME
switch losses. Upon completion of the transfer of energy the In radar circuits the pulse–power handling capability of an
switch must return to its off condition before allowing transfer SCR, rather than the normally specified average–power
of energy once again from the power supply to the PFN capability, is of primary importance.
storage element. For short pulses at high PRFs the major portion of
semiconductor dissipation occurs during the initial turn–on
OPTIMUM SWITCH CHARACTERISTICS during the time that the anode rises from its forward leakage
FORWARD BREAKOVER VOLTAGE value to its maximum value. It is necessary, therefore, that
Device manufacturers normally apply the variable–ampli- turn–on time be as short as possible to prevent excessive
tude output of a half–wave rectifier across the SCR. Thus, power dissipation.
forward voltage is applied to the device for only a half cycle The function of radar is to provide distance information
and the rated voltage is applied only as an ac peak. While measured as a function of time. It is important, therefore, that
this produces a satisfactory rating for ac applications, it does any delay introduced by a component be fixed in relation to
not hold for dc. some variable parameter such as signal strength or tempera-
An estimated 90% of devices tested for minimum break- ture. For radar pulse modulator applications, a minimal delay
over voltage (VBO) in a dc circuit will not meet the data sheet variation versus temperature is required and any such
performance specifications. A switch designed for the pulse variation must be repetitive from SCR to SCR, in production
modulator application should therefore specify a minimum lots, so that adequate circuit compensation may be provided.
continuous forward breakover voltage at rated maximum
leakage current for maximum device temperatures. PULSE GATE CURRENT TO FIRE
The time of delay, the time of rise, and the delay variation
THE OFF SWITCH versus temperature associated with SCR turn–on are func-
The maximum forward leakage current of the SCR must be tions of the gate triggering current available and the trigger
limited to a low value at maximum device temperature. pulse duration. In order to predict pulse circuit operation of
During the period of device nonconduction it is desired that the SCR, the pulse gate current required to turn the device on
the switch offer an off impedance in the range of megohms to when switching the low–impedance modulator should be
hundreds of megohms. This is required for two reasons: (1) specified and the limits of turn–on–time variation for the
to prevent diminishing the efficiency of recharge by an specified pulse trigger current and collector load should be
effective shunt path across the PFN, and (2) to prevent the given at the high and low operating temperature extremes.
bleeding off of PFN charge during the interpulse period. This
second factor is especially important in the design of radar RECOVERY TIME
tansponders wherein the period between interrogations is After the cessation of forward conducting current in the on
variable. Change of the PFN voltage during the interpulse device, a time of SCR circuit isolation must be provided to
period could result in frequency shift, pulse instabilities, and allow the semiconductor to return to its off state. Recovery
loss of power from the transmitter being modulated. time cannot be given as an independent parameter of device
operation, but must include factors as determined by the
THE ON SWITCH external circuit, such as: (1) pulse current and rate of decay;
At present, SCR design is more limited in the achievable (2) availability of an inverse voltage immediately following
maximum forward sustaining voltage than in the current that pulse–current conduction; (3) level of base bias following
the device will conduct. For this reason modulators utilizing pulse current conduction; (4) rate of rise of reapplied positive
SCRs can be operated at lower impedance levels than voltage and its amplitude in relation to SCR breakover
comparable thyratron circuits of yesterday. It is not uncom- voltage; and (5) maximum circuit ambient temperature.
mon for the characteristic impedance of the pulse forming In the reverse direction the controlled rectifier behaves like
network to be in the order of 5 to 10 ohms or less. Operating a conventional silicon diode. Under worst circuit conditions, if
the SCR at higher current to switch the same equivalent an inverse voltage is generated through the existence of a
pulse power as a thyratron requires the SCR on impedance load short circuit, the current available will be limited only by
to be much lower so that the I2R loss is a reasonable value, in the impedance of the pulse forming network and SCR
order to maintain circuit efficiency. Low switch loss, more- inverse characteristics. The reverse current is able to sweep
over, is mandatory because internal power dissipation can be out some of the carriers from the SCR junctions. Intentional
directly translated into junction–temperature–rise and design of the load impedance to something less than the
associated leakage current increase which, if excessive, network impedance allows development of an inverse
could result in thermal runaway. voltage across the SCR immediately after pulse conduction,

Motorola Thyristor Device Data Theory and Applications

1.5–19
enhancing switch turn–off time. Careful use of a fast clamp Tr = time of resonant recharge and is usually equal to
diode in series with a fast zener diode, the two in shunt 1
across the SCR, allows application of a safe value of PRF
circuit–inverse–voltage without preventing the initial useful Lc = value of charging inductance
reverse current. Availability of a negative base–bias following Cn = value of total PFN capacity
pulse current conduction provides a similar enhancement of For a given radar pulse modulator design, the values of
switch turn–off time. power supply voltage, time of resonant recharge, charging
If removal of carriers from the SCR junction enables a choke inductance, and PFN capacitance are established. If
faster switch recovery time, then, conversely, operation of the the time (t) represents the recovery time of the SCR being
SCR at high temperatures with large forward currents and used as the discharge switch, ic then represents the
with slow rate of current decay all increase device recovery minimum value of holding current required by the SCR to
time. prevent power supply lock–on. Conversely, if the modulator
design is about an existing SCR where holding current,
HOLDING CURRENT recovery time, and forward breakover voltage are known, the
One of the anomalies that exist in the design of a pulse charge parameters can be derived by rewriting the above

ȡȧ ȣȧ
SCR is the requirement for a high holding current. This need formula as follows:
can be determined by examining the isolation component *
Ǹ
T r 2(recovery time)
that disconnects the power supply from the discharge circuit
iH +
* Vn(0) cos

ǸLcńCn
V BO 2 Lc Cn

Ȣ Ȥ
during the time that PFN energy is being transferred to the

2ǸL c C n
transmitter and during the recovery time of the discharge Tr
switch. An inductance resonating with the PFN capacitance sin
at twice the time of recharge is normally used for power
supply isolation. Resonant charging restricts the initial flow of The designer may find that for the chosen SCR the desired
current from the power supply, thereby maximizing the time characteristics of modulator pulse width and pulse repetition
at which power supply current flow will exceed the holding frequency are not obtainable.
current of the SCR. If the PFN recharge current from the One means of increasing the effective holding current of an
power supply exceeds the holding current of the SCR before SCR is for the semiconductor to exhibit some turn–off gain
it has recovered, the SCR will again conduct without the characteristic for the residual current flow at the end of the
application of a trigger pulse. As a result continuous modulator pulse. The circuit designer then can provide
conduction occurs from the power supply through the low turn–off base current, making the SCR more effective as a
impedance path of the charging choke and on switch. This pulse circuit element.
lock–on condition can completely disable the equipment
employing the SCR switch. THE SCR AS A UNIDIRECTIONAL SWITCH
The charging current passed by the inductance is given as When triggered to its on state, the SCR, like the hydrogen
(the PFN inductance is considered negligible): thyratron, is capable of conducting current in one direction. A

ȡȧ ȣȧ
load short circuit could result in an inverse voltage across the
* SCR due to the reflection of voltage from the pulse forming

Ǹ
T r 2t
* Vn(0) cos network. The circuit designer may wish to provide an

ic(t) +
ǸLcńCn
E bb 2 Lc Cn intentional load–to–PFN mismatch such that some inverse

Ȣ Ȥ
voltage is generated across the SCR to enhance its turn–off
2ǸL c C n
Tr
sin characteristics. Nevertheless, since the normal circuit ap-
plication is unidirectional, the semiconductor device designer
could take advantage of this fact in restricting the inverse–
Where voltage rating that the SCR must withstand. The circuit
Ebb = power supply voltage designer, in turn, can accommodate this lack of peak–in-
Vn(0) = 0 volts if the PFN employs a clamp diode or is verse–voltage rating by use of a suitable diode clamp across
matched to the load the PFN or across the SCR.

Theory and Applications Motorola Thyristor Device Data

1.5–20
SCRs TESTS FOR PULSE CIRCUIT APPLICATION To measure turn–on time using a Tektronix 545 oscillo-
scope (or equivalent) with a dual trace type CA plug–in,
The suitability for pulse circuit applications of SCRs not
connect probes of Channels A and B to Test Points A and B.
specifically characterized for such purposes can be deter-
Place the Mode selector switch in the Added Algebraically
mined from measurements carried out with relatively simple
position and the Channel B Polarity switch in the Inverted
test circuits under controlled conditions. Applicable test
position. Adjust the HR212A pulse generator to give a
circuits and procedures are outlined in the following section.
positive pulse 1 µs wide (100 pps) as viewed at Test Point A.
Adjust the amplitude of the “added” voltage across the
FORWARD BLOCKING VOLTAGE AND LEAKAGE
100–ohm base resistor for the specified pulse gate current
CURRENT
(200 mA in this example).
Mount the SCRs to a heat sink and connect the units to be
Switch the Mode selector knob to the alternate position.
tested as shown in Figure 5.21. Place the assembly in an
Connect Channel A to Test Point D. Leave the oscilloscope
oven and stabilize at maximum SCR rated temperature. Turn
probe, Channel B, at Test Point B, thereby displaying the
on the power supply and raise the voltage to rated VBO. Allow
input trigger waveform. Measure the time between the 50
units to remain with the voltage applied for minimum of four
percent voltage amplitudes of the two waveforms. This is the
hours. At the end of the temperature soak, determine if any
Turn–On Time (tD + tR).
units exhibit thermal runaway by checking for blown fuses
To measure turn–on time versus temperature, place the
(without removing the power). Reject any units which have
device to be tested on a suitable heat sink and place the
blown circuit fuses. The forward leakage current, ILF, of the
assembly in a temperature chamber. Stabilize the chamber
remaining units may be calculated after measuring the
at minimum rated (cold) temperature. Repeat the above
voltage VL, across resistor R2. Any units with a leakage
measurements. Raise the chamber temperature to maximum
current greater than manufacturer’s rating should be re-
rated (hot) temperature and stabilize. Repeat the measure-
jected.
ments above.
To measure the turn–on impedance for the specified
current load, the on impedance can be measured as an SCR
forward voltage drop. The point in time of measurement shall

+
REGULATED
POWER VL R2
SUPPLY –

1/16 A

ANODE ADDITIONAL UNITS

MAY BE
GATE CATHODE CONNECTED IN
PARALLEL

Figure 5.20. Vertical Set to 4 cm, Horizontal 0.2 µs/cm. R1

Detected RF Magnetron Pulse

TURN–ON TIME, VARIATION AND ON

IMPEDANCE Figure 5.21. Test Setup for SCR Forward Blocking
This circuit assumes that the pulse gate current required to Voltage and Leakage Current Measurements
switch a given modulator load current is specified by the
manufacturer or that the designer is able to specify the
operating conditions. Typical operating values might be: RESISTOR R1 IS USED ONLY IF MANUFACTURER CALLS FOR
BIAS RESISTOR BETWEEN GATE AND CATHODE. RESISTOR
Time of trigger pulse t = 1 µs
R2 CAN HAVE ANY SMALL VALUE WHICH, WHEN MULTIPLIED
Pulse gate current IG = 200 mA
BY MAXIMUM ALLOWABLE LEAKAGE CURRENT, WILL
Forward blocking voltage VBO = 400 V PROVIDE A CONVENIENT READING OF VOLTAGE VL.
Load current ILoad = 30 A

Motorola Thyristor Device Data Theory and Applications

1.5–21
 E = VBO VBO made at the maximum expected temperature of operation.
V BO Resistor R1 should be chosen to allow an initial magnitude of
1
2 2 current flow at the device pulse current rating.
Von
0V To measure holding current, connect the SCRs under test
100
as illustrated in Figure 5.23. Place SCRs in oven and
IC = AS SPECIFIED t = AS SPECIFIED stabilize at maximum expected operating temperature. View
t = AS SPECIFIED k
A B the waveform across R1 by connecting the oscilloscope
D
probe (Tektronix 2465) Channel A to Point A, and Channel B
zO = R C
1:1
100 to Point B. Place the Mode Selector switch in the Added
+ 2 : 1 BO
HP V Algebraically position. Place the Polarity swich of Channel B
212A R
LOAD in the Inverted position. Adjust both Volts/CM switches to the
51
WHERE ILOAD = same scale factor, making sure that each Variable knob is in
AS SPECIFIED its Calibrated position. Adjust pulse generator for a positive
pulse, 1 µs wide, and 1,000 pps pulse repetition frequency.
Adjust power supply voltage to rated VBO. Adjust input pulse
amplitude until unit fully triggers. Measure amplitude of
Figure 5.22. Suggested Test Circuit for SCR “On” voltage drop across R1, V(A – B), and calculate holding
Measurements current in mA from the equation

be half the output pulse width. For a 1 µs output pulse, the

measurement procedure would be:
mA + V(AR1* B) ) 100VBOk W
Connect the oscilloscope probe, Channel B, to Point D Any unit which turns on but does not turn off has a holding
shown in Figure 5.22. Use the oscilloscope controls Time/CM current of less than
and Multiplier to a setting of 0.5 µs per centimeter or faster.
With the Amplitude Control set to view 100 volts per V BO V
centimeter (to prevent amplifier overloading) measure the 100 kW
amplitude of the voltage drop, VF, across the SCR 0.5 µs after
The approximate voltage setting to view the amplitude of
the PFN voltage waveform has dropped to half amplitude. It
the holding current will be 10 or 20 volts per centimeter. The
may be necessary to check ground reference several times
approximate sweep speed will be 2 to 5 µs per centimeter.
during this test to provide the needed accuracy of measure-
These settings will, of course, vary, depending upon the
ment.
holding current of the unit under test.
SCR recovery time is greatly dependent upon the circuit
HOLDING CURRENT in which the device is used. However, any test of SCR
The SCR holding current can be measured with or without recovery time should suffice to compare devices of various
a gate turn–off current, according to the position of switch S2. manufacturers, as long as the test procedure is standard-
The Motorola Trigger Pulse Generator is a transistor circuit ized. Further evaluation of the selected devices could be
capable of generating a 1.5 µs turn–on pulse followed by a made in an actual modulator circuit tester wherein
variable–duration turn–off pulse. Measurements should be techniques conducive to SCR turn–off are used.

HARRISON 2W
800 A B A
P.S. 100k
+ 12 – 12 + TIME AT WHICH TO MEASURE IN
R1 R3
S1A

ANODE
MOTOROLA C1
HP212 S2 TRIGGER S1B
7500 fd.
PULSE GEN. PULSE GATE
GEN REGULATED IH
CATHODE POWER
R2 SUPPLY
VOLTAGE LEVEL FROM
R4 WHICH TO CALCULATE
51 Ω HOLDING CURRENT
–

NOTE: ADDITIONAL UNITS MAY BE TESTED BY SWITCHING THE

ANODE AND GATE CONNECTIONS TO SIMILARLY
MOUNTED SCRs. SHORT LEAD LENGTHS ARE DESIRABLE.

Figure 5.23. Test Setup for Measuring Holding Current

Theory and Applications Motorola Thyristor Device Data

1.5–22
 REGULATED
POWER
SUPPLY

CHARGING
CHOKE

HARRISON B
HOLD OFF
800 A
DIODE
+ 12 – 12
PFN

q RLOAD
A
zO

ANODE C
HP212A MOTOROLA
TRIGGER GATE
PULSE
PULSE
GEN GEN CATHODE RLOAD
R

Figure 5.24. Modulator Circuit for SCR Tests

The above circuit setup shown in Figures 5.24 and 5.25 can SCR should be provided.
be employed for such tests. A slight load to PFN mismatch is
called for to generate an inverse voltage across the SCR at PARALLEL CONNECTED SCRs
the termination of the output pulse. An SCR gate turn–off
pulse is used. The recharge component is a charging choke, When an application requires current capability in excess
providing optimized conditions of reapplied voltage to the of a single economical SCR, it can be worthwhile to consider
PFN (and across the SCR). Adequate heat sinking of the paralleling two or more devices. To help determine if two or

CHARGE
LOAD
IMPEDANCE

POWER ENERGY DISC

SUPPLY STORE SWITCH

BLOCK DIAGRAM;
CHARGING CHOKE
HOLD OFF DIODE
PULSE TRANSFORMER

PFN LOAD
Es

TRIGGER SCR
IN

SIMPLIFIED SCHEMATIC

Figure 5.25. Radar Modulator, Resonant Line Type

Motorola Thyristor Device Data Theory and Applications

1.5–23
more SCRs in parallel are more cost effective than one high The four parameters shown in Table 5.6 were measured
current SCR, some of the advantages and disadvantages with a curve tracer and are:
are listed for parallel devices. IL, latching current; VTM, on–state voltage; IGT and
VGT, minimum gate current and voltage for turn on.
Advantages
1. Less expensive to purchase Of the four parameters, IL and VTM can greatly affect current
2. Less expensive to mount sharing.
3. Less expensive to replace, in case of failure The latching current of each SCR is important at turn–on to
4. Ease of mounting ensure each device turns on and will stay on for the entire
5. Ease of isolation from sink conduction period. On–state voltage determines how well the
SCRs share current when cathode ballasting is not used.
Disadvantages Table 5.5 gives turn–on delay time (td) and turn–on rise
1. Increased SCR count time (tr) of the anode–cathode voltage and the minimum
2. Selected or matched devices forward anode voltage for turn–on. These parameters were
3. Increased component count
measured in the circuits shown in Figures 5.28 and 5.29.
4. Greater R & D effort
One SCR at a time was used in the circuit shown in Figure
There are several factors to keep in mind in paralleling and 5.28.
many are pertinent for single SCR operations as well. Turn–on delay on twenty–five SCRs was measured (only
ten are shown in Table 5.5) and they could be from one or
GATE DRIVE more production lots. The variation in td was slight and
The required gate current (IGT) amplitude can vary greatly ranged from 35 to 44 ns but could vary considerably on other
and can depend upon SCR type and load being switched. As production lots and this possible variation in td would have to
a general rule for parallel SCRs, IGT should be at least two or be considered in a parallel application.
three times the IGT(MAX) specification on the data sheet and Waveforms for minimum forward anode voltage for turn–on
ideally close to, but never exceeding, the maximum specified are shown in Figure 5.26. The trailing edge of the gate
gate power dissipation or peak current. Adequate gate current pulse is phase delayed (R3) so that the SCR is not
current is necessary for rapid turn–on of all the parallel SCRs turned on. The width of the gate current pulse is now
and to ensure simultaneous turn–on without excessive increased (R5) until the SCR turns on and the forward anode
current crowding across any of the individual die. The rise
time of the gate drive pulse should be fast, ideally p 100 ns.
voltage switches to the on–state at about 0.73 V. This is the
minimum voltage at which this SCR will turn on with the circuit
Each gate should be driven from a good current source and conditions shown in Figure 5.28.
through its own resistor, even if transformer drive is used. For dynamic turn–on current sharing, td, tr and VA(MIN) are
Gate pulse width requirements vary but should be of
very important. As an example, with a high wattage incan-
sufficient width to ensure simultaneous turn–on and last well
descent lamp load, it is very important that the inrush current
beyond the turn–on delay of the slowest device, as well as
of the cold filament be equally shared by the parallel SCRs.
beyond the time required for latching of all devices. Ideally,
The minimum anode voltage at which a device turns on is
gate current would flow for the entire conduction period to
also very important. If one of the parallel devices turns on
ensure latching under all operating conditions.
With low voltage switching, which includes conduction
angles near 180° and near zero degrees, the gate drive
requirements can be more critical and special emphasis may Table 5.5. MCR12D Turn–On Delay, Rise Time and
be required of gate pulse amplitude and width. Minimum Forward Anode Voltage For Turn–On
Minimum Anode
PARAMETER MATCHING Turn–On Delay and Rise Time
Voltage For
Off–State Voltage = 8 V Peak
For reliable current sharing with parallel SCRs, there are
certain device parameters that should be matched or held RL = 10 Ohms, IA ^ 6.5 A Peak
Turn–On Off–State
Voltage = 4 V Peak
Device IG = 100 mA (PW = 100 µs)
within close tolerances. The degree of matching required RL = 0.5 Ohm
varies and can be affected by type of load (resistive, IA = 5A
Conduction Angle 90 Degrees
inductive, incandescent lamp or phase controlled loads) IG = 100 mA
being switched. td(ns) tr(µs) (Volts)
The most common device parameters that can effect
current sharing are: 1 35 0.80 0.70
2 38 0.95 0.81
1. ) 3 45 1 0.75
td — turn–on delay time 4 44 1 0.75
2. ) tr — turn–on rise time of anode current 5 44 0.90 0.75
3. ) 6 43 0.85 0.75
VA(MIN) — minimum anode voltage at which device 7 38 1.30 0.75
will turn on 8 38 1.25 0.70
4. ) Static on–state voltage and current 9 38 1 0.75
5. ) IL — Latching current 10 37 0.82 0.70

Theory and Applications Motorola Thyristor Device Data

1.5–24
 rms) was tried. Table 5.5 shows that the minimum anode
OFF–STATE voltage for turn–on is from 7 to 14% lower for device 1 than
on 2, 3 and 4. Also, device 1 turn–on delay is 35 ns versus
ANODE–CATHODE
38, 45 and 44 ns for devices 2, 3 and 4.
VOLTAGE 0.2 V/Div
The tendency for device 1 to turn on, preventing the other
ON–STATE three from turning on, is most probably due to its lower
minimum anode voltage requirement and shorter turn on
IG = 50 delay. The remedy would be closer matching of the minimum
1 mA/Div anode voltage for turn–on and driving the gates hard (but
less than the gate power specifications) and increasing the
0 0 width of the gate current pulse.

FORCED CURRENT SHARING

100 µs/Div
Cathode ballast elements can be used to help ensure
Figure 5.26. Minimum Anode Voltage For Turn–On good static on–state current sharing. Either inductors or
Off–State Voltage = 4 V Peak, RL = 0.5 Ohm, resistors can be used and each has advantages and
IA ≈ 5 A, IG = 75 mA disadvantages. This section discuses resistive ballasting, but
it should be kept in mind that the inductor method is usually
better suited for the higher current levels. Although they are
before the other devices and its on–state voltage is lower more expensive and difficult to design, there is less power
than the required minimum anode voltage for turn–on of the loss with inductor ballasting as well as other benefits.
unfired devices, they therefore cannot turn on. This would The degree of peak current sharing is shown in Figure 5.27
overload the device which turned on, probably causing for four parallel MCR12D SCRs using cathode resistor
failure from over–current and excessive junction tempera- ballasting with an inductive anode load. With devices 1, 3
ture. and 4, on–state voltage is matched within 10 mV at an anode
Turn–off time — tq is important in higher frequency current of 15 A (See Table 5.6) and are within 1A of each
applications which require the SCR to recover from the other in Figure 5.27, with cathode resistance (RK) equal to
forward conduction period and be able to block the next cycle zero. As RK increases, the current sharing becomes even
of forward voltage. Thus, tq matching for high frequency closer. The unmatched device 2, with a VTM of 1.41 V (Table
operation can be as important as td, tr and VA(MIN) matching 5.6), is not carrying its share of current (Figure 5.29) with RK
for equal turn–on current sharing. equal zero. As RK increases, device 2 takes a greater share
Due to the variable in tq measurement, no further attempt of the total current and with RK around 0.25 ohm, the four
will be made here to discuss this parameter and the reader is SCRs are sharing peak current quite well. The value of RK
referred to Application Note AN914. depends on how close the on–state voltage is matched on
The need for on–state matching of current and voltage is the SCRs and the degree of current sharing desired, as well
important, especially in unforced current sharing circuits. as the permissible power dissipation in RK.

UNFORCED CURRENT SHARING

17
When operating parallel SCRs without forced current
IA(pk) , PEAK ANODE CURRENT (AMPS)

sharing, such as without cathode ballasting using resistors or #3 SCR #1

inductors, it is very important that the device parameters be 15
closely matched. This includes td, tr, minimum forward anode
voltage for turn–on and on–state voltage matching. The
degree of matching determines the success of the circuit. 13 #4
In circuits without ballasting, it is especially important that
physical layout, mounting of devices and resistance paths be 11
identical for good current sharing, even with on–state #2 IG = 400 mA
matched devices. PW = 400 µs
Figure 5.27 shows how anode current can vary on devices 9 OFF–STATE VOLTAGE = 26 V
closely matched for on–state voltage (1, 3 and 4) and a (rms)
INDUCTIVE LOAD
mismatched device (2). Without resistance ballasting, the
7 CONDUCTION ANGLE = 120°
matched devices share peak current within one ampere and 0 50 100 150 200 250
device 2 is passing only nine amps, seven amps lower than RK, CATHODE RESISTORS (MILLIOHMS)
device 1. Table 5.6 shows the degree of match or mismatch
of VTM of the four SCRs. Figure 5.27. Effects Of Cathode Resistor On Anode
With unforced current sharing (RK = 0), there was a greater Current Sharing
tendency for one device (1) to turn–on, preventing the others
from turning on when low anode switching voltage ( 10 V p

Motorola Thyristor Device Data Theory and Applications

1.5–25
 Table 5.6. MCR12D Parameters Measured On Curve width monostable multivibrator.
Tracer, TC = 25°C Line synchronization is achieved through the half–wave
section of the secondary winding of the full–wave, center–
Minimum Gate tapped transformer (A). This winding also supplies power to
IL, Latching VTM, On–State Current & Voltage
the circuit through rectifiers D1 and D2.
Current Voltage for Turn–On
Device # The full–wave signal is clipped by diode D5, referenced to
VD = 12 Vdc IA = 15 A VD = 12 Vdc,
IG = 100 mA PW = 300 µs RL = 140 Ω a + 15 volt supply, so that the input limit of the CMOS chip is
IGT VGT not exceeded. The waveform is then shaped by the Schmitt
trigger, which is composed of inverters U1 – a and U1 – b. A fast
1 13 mA 1.25 V 5.6 mA 0.615 V
switching output signal B results.
2 27 1.41 8.8 0.679
The positive–going edge of this pulse is differentiated by
3 28 1.26 12 0.658
4 23 1.26 9.6 0.649 the capacitive–resistive network of C1 and R2 and triggers
5 23 1.28 9.4 0.659 the delay multivibrator that is composed of U1 – c and U1 – d.
6 23 1.26 9.6 0.645 As a result, the normally high output is switched low. The
7 18 1.25 7.1 0.690 trailing edge of this pulse (C) then triggers the following
8 19 1.25 7 0.687 multivibrator, which is composed of NAND gate U1 – e and
9 19 1.25 8.4 0.694 inverter U1 – f. The positive going output pulse (waveform D)
10 16 1.25 6.9 0.679 of this multivibrator, whose width is set by potentiometer R6,
turns on transistors Q1 and Q2, which drives the gates of the
four SCRs. Transistor Q2 supplies about 400 mA drive
current to each gate through 100 ohm resistors and has a
LINE SYNCHRONIZED DRIVE CIRCUIT
Gate drive for phase control of the four parallel SCRs is
rise time of p
100 ns.
accomplished with one complementary MOS hex gate,
MC14572, and two bipolar transistors (Figure 5.28). This PARALLEL SCR CIRCUIT
adjustable line–synchronized driver permits SCR conduction
from near zero to 180 degrees. A Schmitt trigger clocks a The four SCRs are MCR12Ds, housed in the TO–220
delay monostable multivibrator that is followed by a pulse– package, rated at 12 A rms, 50 V and are shown schematically

D1
+ 15 V
100 Ω, 250 1N5352 + 15 V
1 W µF 25 V R3
D2 5 V, 5 W
1 mΩ
D5 R1
1N914 220 kΩ
C1 150
A R4
TRIAD
F90X D3 1N914 1 kΩ 22 kΩ
U1 – a
1
U1 – b
3
0.01
µF
6
t5
U1
kΩ
9
FULL– 2 4 7
B R2 10
WAVE 0 kΩ 0.01
120 V 100
S1 SCHMITT TRIGGER µF U1 – d
60 Hz kΩ
HALF
D4 –
WAVE R5 0.01 t t
0.7 ms τ1 6 rms
1N914 100 kΩ µF DELAY MULTIVIBRATOR
5.30(a)
+ 15 V
U1 ––e
0.01 µF 16
A 15 V
15 13 12 U
1–f
11
t
30 µs τ2 200 µs + 40 V
14 D 8 PULSE–WIDTH
10 k
0 4.7 kΩ MULTIVIBRATOR
15 V
B Q2
0 0.001 10 k R6
MJE253
15 V 25 kΩ TIP122
C τ1
0
15 V 0.005 TO GATES
D RESISTORS
0 1k
τ2 10 k
5.30(b)

Figure 5.28. Line–Synchronized Gate Driver

Theory and Applications Motorola Thyristor Device Data

1.5–26
 LOAD: FOUR STANCOR FILTER CHOKES (#C–2688) IN PARALLEL
EACH RATED AT: 10 mH @ 12.5 Adc AND 0.11 OHMS
ALL ANODES COMMON TO HEAT SINK

26 V rms Q3 Q4 Q5 Q6

100 100 100 100 R7

100
120 V rms SNUBBER
1k 1k 1k 1k
60 Hz

0.25
RK RK RK RK C2

Q3 – Q6, MCR12D

Figure 5.29. Parallel Thyristors

in Figure 5.29. Due to line power limitations, it was decided to EMI can generally be separated into two categories —
use a voltage step down transformer and not try working directly radiated and conducted. Radiated interference travels by
from the 120 V line. Also, line isolation was desirable in an way of electro–magnetic waves just as desirable RF energy
experiment of this type. does. Conducted interference travels on power, communica-
The step down transformer ratings were 120 V rms tions, or control wires. Although this separation and nomen-
primary, 26 V rms secondary, rated at 100 A, and was used clature might seem to indicate two neat little packages,
with a variable transformer for anode voltage adjustment. independently controllable, such is not the case. The two are
The inductive load consisted of four filter chokes in parallel very often interdependent such that in some cases control of
(Stancor #C–2688 with each rated at 10 mH, 12.5 Adc and one form may completely eliminate the other. In any case,
0.11 ohm). both interference forms must be considered when interfer-
For good current sharing with parallel SCRs, symmetry in ence elimination steps are taken.
layout and mounting is of primary importance. The four SCRs Phase control circuits using thyristors (SCRs, triacs, etc.)
were mounted on a natural finish aluminum heat sink and for controlling motor speed or resistive lighting and heating
torqued to specification which is 8 inch pounds. Cathode loads are particularly offensive in creating interference. They
leads and wiring were identical, and when used, the cathode can completely obliterate most stations on any AM radio
resistors RK were matched within 1%. An RC snubber nearby and will play havoc with another control on the same
network (R7 and C2) was connected across the anodes– power line. These controls are generally connected in one of
cathodes to slow down the rate–of–rise of the off–state the two ways shown in the block diagrams of Figure 5.30.
voltage, preventing unwanted turn–on. A common example of the connection of 5.30(a) is the wall
mounted light dimmer controlling a ceiling mounted lamp. A
motorized appliance with a built–in control such as a food
CHARACTERIZING RFI SUPPRESSION IN mixer is an example of the connection shown in 5.30(b).
THYRISTOR CIRCUITS Figure 5.30(a) may be re–drawn as shown in Figure 5.31,
illustrating the complete circuit for RF energy.The switch in
In order to understand the measures for suppression of EMI, the control box represents the thyristor, shown in its blocking
characteristics of the interference must be explored first. To state. In phase control operation, this switch is open at the
have interference at all, we must have a transmitter, or creator of beginning of each half cycle of the power line alternations.
interference, and a receiver, a device affected by the interfer- After a delay determined by the remainder of the control
ence. Neither the transmitter nor the receiver need be related in circuitry, the switch is closed and remains that way until the
any way to those circuits commonly referred to as radio–fre- instantaneous current drops to zero. This switch is the
quency circuits. Common transmitters are opening and closing source from which the RF energy flows down the power lines
of a switch or relay contacts, electric motors with commutators, and through the various capacitors to ground.
all forms of electric arcs, and electronic circuits with rapidly If the load is passive, such as a lamp or a motor which
changing voltages and currents. Receivers are generally elec- does not generate interference, it may be considered as an
tronic circuits, both low and high impedance which are sensitive impedance bypassed with the wire–to–wire capacitance of
to pulse or high frequency energy. Often the very circuits its leads. If it is another RF energy source, however, such as
creating the interference are sensitive to similar interference a motor with a commutator, it must be treated separately to
from other circuits nearby or on the same power line. reduce interference from that source. The power supply may

Motorola Thyristor Device Data Theory and Applications

1.5–27
 and source inductance. This is a form of conducted
CONTROL interference.
A second form of radiated interference is inductive
coupling in which the power line and ground form a one–turn
primary of an air core transformer. In this mode, an
unbalanced transient current flows down the power lines with
LINE LOAD the difference current flowing to ground through the various
capacitive paths available. The secondary is the radio
antenna or the circuit being affected. This type of interference
(a). Separately Mounted Control
is a problem only when the receiver is within about one
wavelength of the transmitter at the offending frequency.
Radiated interference from the control circuit proper is of
little consequence due to several factors. The lead lengths in
CONTROL general are so short compared to the wavelengths in
LOAD question that they make extremely poor antenna. In addition,
LINE
most of these control circuits are mounted in metal enclo-
sures which provide shielding for radiated energy generated
within the control circuitry.
A steel box will absorb radiated energy at 150 kHz such
(b). Control and Load in the Same Enclosure that any signal inside the box is reduced 12.9 dB per mil of
thickness of the box. In other words, a 1/16 inch thick steel
Figure 5.30. Block Diagram of Control Connections box will attenuate radiated interference by over 800 dB! A
similar aluminum box will attenuate 1 dB per mil or 62.5 dB
total. Thus, even in an aluminum box, the control circuitry will
radiate very little energy.
Both forms of radiated interference which are a problem
be considered as dc since the interference pulse is extremely are a result of conducted interference on the power lines
short (10 µs) compared to the period of the power line which is in turn caused by a rapid rise in current. Thus, if this
frequency (16 ms for 60 Hz). The inductance associated with current rise is slowed, all forms of interference will be
the power source comes from two separate phenomena. reduced.
First is the leakage impedance of the supply transformer, and
second is the self–inductance of the wires between the RFI SOLUTIONS
power line transformer and the load.
One of the most difficult parameters to pin down in the Since the switch in Figure 5.31, when it closes, provides a
system is the effect of grounding. Most industrial and very low impedance path, a capacitor in parallel with it will
commercial wiring and many homes use a grounded conduit show little benefit in slowing down the rise of current. The
system which provides excellent shielding of radiated energy capacitor will be charged to a voltage determined by the
emanating from the wiring. However, a large number of
homes are being wired with two to three wire insulated cable
without conduit. In three–wire systems, one wire is grounded
independently of the power system even though one of the
power lines is already grounded. The capacitances to ground
shown in Figure 5.31 will be greatly affected by the type of
grounding used. Of course, in any home appliance, filtering A
must be provided suitable for all three different systems.
Before the switch in the control is closed, the system is in a
steady–state condition with the upper line of the power line at
the system voltage and the bottom line and the load at
ground potential. When the switch is closed, the upper line
potential instantaneously falls due to the line and source
inductance, then it rises back to its original value as the line
inductance is charged. While the upper line is rising, the line
from the control to the load also rises in potential. The effect CONTROL
of both of these lines increasing in potential together causes LOAD
an electro–static field change which radiates energy. In
addition, any other loads connected across the power lines at
point A, for example, would be affected by a temporary loss
of voltage created by the closing of the switch and by the line Figure 5.31. RF Circuit for Figure 5.30(a)

Theory and Applications Motorola Thyristor Device Data

1.5–28
 0.1 µF 100 µH Ferrite core inductors have proved to be the most practical
CONTROL physical configuration. Most ferrites are effective; those with
10 A TRIAC highest permeability and saturation flux density are pre-
ferred. Those specifically designed as high frequency types
8A
are not necessarily desirable.
Laminated iron cores may also be used; however, they
LOAD require a capacitor at point A in Figure 5.33 to be at all
effective. At these switching speeds, the iron requires
considerable current in the windings before any flux change
can take place. We have found currents rising to half their
Figure 5.32. One Possible EMI Reduction Circuit
peak value in less than one µs before the inductance begins
to slow down the rise. The capacitor supplies this current for
the short period without dropping in voltage, thus eliminating
the pulse on the power line.
circuit constants and the phase angle of the line voltage just
Once a core material has been selected, wire size is the
before the switch closes. When the switch closes, the
next decision in the design problems. Due to the small
capacitor will discharge quickly, its current limited only by its
number of turns involved (generally a single layer) smaller
own resistance and the resistance of the switch. However, a
sizes than normally used in transformers may be chosen
series inductor will slow down the current rise in the load and
safely. Generally, 500 to 800 circular mills per ampere is
thus reduce the voltage transient on all lines. A capacitor
acceptable, depending on the enclosure of the filter and the
connected as shown in Figure 5.32 will also help slow down
maximum ambient temperature expected.
the current rise since the inductor will now limit the current out
An idea of the size of the core needed may be determined
of the capacitor. Thus, the capacitor voltage will drop slowly
from the equation:
and correspondingly the load voltage will increase slowly.
Although this circuit will be effective in many cases, the
filter is unbalanced, providing an RF current path through the (1) A cA w + 26 Awire
B MAX
E rms t r

capacitances to ground. It has, therefore, been found

where:
advantageous to divide the inductor into two parts and to put
Ac = the effective cross–sectional area of the core in
half in each line to the control. Figure 5.33 illustrates this
in2
circuit showing the polarity marks of two coils which are
Aw = available core window area in in2
wound on the same core.
Awire = wire cross section in circular mils
A capacitor at point A will help reduce interference further.
BMAX = core saturation flux density in gauss
This circuit is particularly effective when used with the
tr = allowable current rise time in seconds
connection of Figure 5.30(b) where the load is not always on
Erms = line voltage
the grounded side of the power line. In this case, the two
halves of the inductor would be located in the power line (A factor of 3 has been included in this equation to allow for
leads, between the controlled circuit and the power source. winding space factor.) Once a tentative core selection has
Where the control circuit is sensitive to fast rising line been made, the number of turns required may be found from
transients, a capacitor at point B will do much to eliminate this the equation:
problem. The capacitor must charge through the impedance
+ 11 EBrmsMAXtrAc 10
6
of the inductor, thus limiting the rate of voltage change (dv/dt)
(2) N
applied to the thyristor while it is in the blocking state.
where:
N = the total number of turns on the core
DESIGN CRITERIA The next step is to check how well the required number of
turns will fit onto the core. If the fit is satisfactory, the core
Design equations for the split inductor have been devel- design is complete; if not, some trade–offs will have to be
oped based on parameters which should be known before made.
attempting a design. The most difficult to determine is tr, the
240 µH
minimum allowable current rise time which will not cause
objectionable interference. The value of this parameter must CONTROL
120 Vac A B
be determined empirically in each situation if complete 10 A TRIAC
interference reduction is needed. Motorola has conducted
5A 240 µH
extensive tests using an AM radio as a receiver and a 600
Watt thyristor lamp dimmer as a transmitter. A rate of about
0.35 Amp per µs seems to be effective in eliminating LOAD
objectionable interference as well as materially reducing
false triggering of the thyristor due to line transients. The
value of tr may be calculated by dividing the peak current Figure 5.33. Split Inductor Circuit
anticipated by the allowable rate of current rise.

Motorola Thyristor Device Data Theory and Applications

1.5–29
 In most cases, the inductor as designed at this point will As was previously mentioned, a current rise rate of about
have far too much inductance. It will support the entire peak 0.35 ampere per µs has been found to be acceptable for
line voltage for the time selected as tr and will then saturate interference problems with ac–dc radios in most wiring
quickly, giving much too fast a current rise. The required situations. With 5 amperes rms, 7 amperes peak,
inductance should be calculated from the allowable rise time
and load resistance, making the rise time equal to two time tr + 0.35
7 + 20 ms

constants. Thus: Then the equation (1):

(3) 2L + tr or L + R tr
A cA w + 26 2580 120 20 10 *6 + 0.044
R 2 3800 gauss
Paper or other insulating material should be inserted Core part number 1F30 of the same company in a U–1
between the core halves to obtain the required inductance by configuration has an AcAw product of 0.0386, which should
the equation: be close enough.
*8 + 10.93 * +
+ 3.19 N * Imc 120 20 10 6 10 6
2 Ac 10
(4) Ig N 42 turns
L 3800 0.137
Two coils of 21 turns each should be wound on either one or
where:
two legs and be connected as shown in Figure 5.35.
Ig = total length of air gap in inches
The required inductance of the coil is found from
µ = effective ac permeability of the core material at the
equation (3).
power line frequency
Ic = effective magnetic path length of the core in inches
Ac = effective cross sectional area of the core in square L + R2tr + EIrated
rated tr
2
+120
5
20
2
10 *6 + 240 10 *6
L + 240 mH
inches
L = inductance in henries
To obtain this inductance, the air gap should be
DESIGN EXAMPLE
+ 3.19 422402 *8 * 3.33 +0.0321*0.00175
*
Ig 0.137 10
10 6 1900
I g + 0.03035
Consider a 600 watt, 120 Volt lamp dimmer using a
Motorola 2N6148 triac. Line current is 600 = 5 amperes. #16
120
wire will provide about 516 circular mils per ampere. Thus, 15 mils of insulating material in each leg will provide
For core material, type 3C5 of Ferroxcube Corporation of the necessary inductance.
America, Saugerties, New York, has a high Bmax and µ. The If a problem still exists with false triggering of the thyristor
company specifies BMAX = 3800 gauss and µ = 1900 for due to conducted interference, a capacitor at point B in
material. Figure 5.33 will probably remedy the situation.

Theory and Applications Motorola Thyristor Device Data

1.5–30
 CHAPTER 6
APPLICATIONS

Because they are reliable solid state switches, thyristors

have many applications, especially as controls. PORTION OF WAVEFORM
One of the most common uses for thyristors is to control ac APPLIED TO LOAD
loads such as electric motors. This can be done either by
controlling the part of each ac cycle when the circuit conducts α
current (phase control) or by controlling the number of cycles
per time period when current is conducted (cycle control).
α
In addition, thyristors can serve as the basis of relaxation
oscillators for timers and other applications. Most of the
devices covered in this book have control applications.
PHASE CONTROL WITH THYRISTORS
The most common method of electronic ac power control Figure 6.1. Phase Control of AC Waveform
is called phase control. Figure 6.1 illustrates this concept.
During the first portion of each half-cycle of the ac sine wave, LOAD
an electronic switch is opened to prevent the current flow. At
RT
some specific phase angle, α, this switch is closed to allow
the full line voltage to be applied to the load for the remainder
of that half-cycle. Varying α will control the portion of the total AC LINE Q
sine wave that is applied to the load (shaded area), and VOLTAGE
thereby regulate the power flow to the load. D
The simplest circuit for accomplishing phase control is CT
shown in Figure 6.2. The electronic switch in this case is a
triac (Q) which can be turned on by a small current pulse to its
gate. The TRIAC turns off automatically when the current
through it passes through zero. In the circuit shown, Figure 6.2. Simplest Circuit for Phase Control
capacitor CT is charged during each half-cycle by the current
flowing through resistor RT and the load. The fact that the
load is in series with RT during this portion of the cycle is of α = 150°
little consequence since the resistance of RT is many times
greater than that of the load. When the voltage across CT α = 90°
reaches the breakdown voltage of the DIAC bilateral trigger
(D), the energy stored in capacitor CT is released. This
energy produces a current pulse in the DIAC, which flows
α = 90°
through the gate of the TRIAC and turns it on. Since both the
DIAC and the TRIAC are bidirectional devices, the values of
α = 150°
RT and CT will determine the phase angle at which the TRIAC
will be triggered in both the positive and negative half-cycles APPLIED SINE WAVE
of the ac sine wave. Figure 6.3. Waveforms of Capacitor Voltage
at Two Phase Angles

The waveform of the voltage across the capacitor for two

typical control conditions (α = 90° and 150°) is shown in
Figure 6.3. If a silicon controlled rectifier is used in this circuit

Motorola Thyristor Device Data Theory and Applications

1.6–1
in place of the TRIAC, only one half-cycle of the waveform
will be controlled. The other half-cycle will be blocked,
resulting in a pulsing dc output whose average value can VR 3/4 VR
be varied by adjusting RT. TYPICAL FAN
LOAD
CONTROL OF INDUCTION MOTORS
Shaded-pole motors driving low-starting-torque loads VR = FULL RATED VOLTAGE

SPEED
such as fans and blowers may readily be controlled using
1/2 VR
any of the previously described full-wave circuits. One
needs only to substitute the winding of the shaded-pole CONSTANT
motor for the load resistor shown in the circuit diagrams. TORQUE LOAD
Constant-torque loads or high-starting-torque loads are 1/4 VR
difficult, if not impossible, to control using the voltage
controls described here. Figure 6.4 shows the effect of
varying voltage on the speed-torque curve of a typical TORQUE
shaded-pole motor. A typical fan-load curve and a
constant-torque-load curve have been superimposed Figure 6.4. Characteristics of Shaded-Pole Motors
upon this graph. It is not difficult to see that the torque at Several Voltages
developed by the motor is equal to the load torque at two
different points on the constant-torque-load curve, giving
two points of equilibrium and thus an ambiguity to the
speed control. The equilibrium point at the lower speed is
a condition of high motor current because of low counter MOT
EMF and would result in burnout of the motor winding if the
AC LINE
motor were left in this condition for any length of time. By VOLTAGE
contrast, the fan speed-torque curve crosses each of the
motor speed-torque curve crosses each of the motor CONTROL
speed-torque curves at only one point, therefore causing CIRCUIT
no ambiguities. In addition, the low-speed point is one of
low voltage well within the motor winding’s current-carry-
ing capabilities. Figure 6.5. Connection Diagram for
Permanent-split-capacitor motors can also be controlled Permanent-Split-Capacitor Motors
by any of these circuits, but more effective control is
Not all induction motors of either the shaded-pole or the
achieved if the motor is connected as shown in Figure 6.5.
permanent-split-capacitor types can be controlled effec-
Here only the main winding is controlled and the capacitor
tively using these techniques, even with the proper loads.
winding is continuously connected to the entire ac line
Motors designed for the highest efficiencies and, there-
voltage. This connection maintains the phase shift be-
fore, low slip also have a very low starting torque and may,
tween the windings, which is lost if the capacitor phase is
under certain conditions, have a speed-torque character-
also controlled. Figure 6.6(a) shows the effect of voltage
istic that could be crossed twice by a specific fan-load
on the speed-torque characteristics of this motor and a
speed-torque characteristic. Figure 6.6(b) shows motor
superimposed fan-load curve.

TYPICAL FAN HIGH-STARTING-

LOAD TORQUE FAN
LOAD
VR

VR
3/4 VR
SPEED
SPEED

3/4 VR
1/2 VR
1/2 VR

1/4 VR 1/4 VR

VR = FULL RATED VOLTAGE

TORQUE TORQUE
(a). High-Starting-Torque Motor (b). High-Efficiency Motor

Figure 6.6. Speed–Torque Curves for a Permanent–Split–Capacitor Motors at Various Applied Voltages

Theory and Applications Motorola Thyristor Device Data

1.6–2
torque-speed characteristic curves upon which has been
superimposed the curve of a fan with high starting torque. It is VR = FULL RATED VOLTAGE
therefore desirable to use a motor whose squirrel-cage rotor
VR
is designed for medium-to-high impedance levels and,
therefore, has a high starting torque. The slight loss in VR 3/4 VR
efficiency of such a motor at full rated speed and load is a
small price to pay for the advantage of speed control

SPEED

SPEED
3/4 VR 1/2 VR
prevents the TRIAC from turning on due to line transients
and inductive switching transients. 1/2 VR 1/4 VR
A unique circuit for use with capacitor-start motors in
explosive or highly corrosive atmospheres, in which the
arcing or the corrosion of switch contacts is severe and
undesirable, is shown in Figure 6.7. Resistor R1 is
connected in series with the main running winding and is of
such a resistance that the voltage drop under normal TORQUE TORQUE
full-load conditions is approximately 0.2 V peak. Since (A) NON-FEEDBACK CONTROL (B) FEEDBACK CONTROL
starting currents on these motors are quite high, this peak
voltage drop will exceed 1 V during starting conditions, Figure 6.8. Comparison of Feedback Control
triggering the TRIAC, which will cause current to flow in the with Non-Feedback Control
capacitor winding. When full speed is reached, the current
through the main winding will decrease to about 0.2 V, The theory of operation of this control circuit is not at all
which is insufficient to trigger the TRIAC — thus the difficult to understand. Assuming that the motor has been
capacitor winding will no longer be energized. Resistor R2 running, the voltage at point A in the circuit diagram must
and capacitor C2 form a dv/dt suppression network; this be larger than the forward drop of Diode D1, the
prevents the TRIAC from turning on due to line transients gate-to-cathode drop of the SCR, and the EMF generated
and inductive switching transients. by the residual MMF in the motor, to get sufficient current
flow to trigger the SCR.
CONTROL OF UNIVERSAL MOTORS The waveform at point A (VA ) for one positive half-cycle
Any of the half-wave or full-wave controls described is shown in 6.9(b), along with the voltage levels of the SCR
previously can be used to control universal motors. Non- gate (V SCR ), the diode drop (V D ), and the motor-generated
feedback, manual controls, such as those shown in Figure EMF (V M ). The phase angle (α) at which the SCR would
6.2, are simple and inexpensive, but they provide very little trigger is shown by the vertical dotted line. Should the
torque at low speeds. A comparison of typical speed-torque motor for any reason speed up so that the generated motor
curves using a control of this type with those of feedback voltage would increase, the trigger point would move
control is shown in Figure 6.8. upward and to the right along the curve so that the SCR
These motors have some unique characteristics which would trigger later in the half-cycle and thus provide less
allow their speed to be controlled very easily and efficiently power to the motor, causing it to slow down again.
with a feedback circuit such as that shown in Figure 6.9. This Similarly, if the motor speed decreased, the trigger point
circuit provides phase-controlled half-wave power to the would move to the left and down the curve, causing the
motor; that is, on the negative half-cycle, the SCR blocks TRIAC to trigger earlier in the half-cycle providing more
current flow in the negative direction causing the motor to be power to the motor, thereby speeding it up.
driven by a pulsating direct current whose amplitude is Resistors R1, R2, and R3, along with diode D2 and
dependent on the phase control of the SCR. capacitor C1 form the ramp-generator section of the
circuit. Capacitor C1 is changed by the voltage divider R1,
R2, and R3 during the positive half-cycle. Diode D2
prevents negative current flow during the negative half-
cycle, therefore C1 discharges through only R2 and R3
C1 during that half-cycle. Adjustment of R3 controls the
MOT
amount by which C1 discharges during the negative
AC LINE half-cycle. Because the resistance of R1 is very much
VOLTAGE larger than the ac impedance of capacitor C1, the voltage
C2 waveform on C1 approaches that of a perfect cosine wave
with a dc component. As potentiometer R2 is varied, both
R2 the dc and the ac voltages are divided, giving a family of
R1 curves as shown in 6.9(c).

Figure 6.7. Circuit Diagram for Capacitor-Start Motor

Motorola Thyristor Device Data Theory and Applications

1.6–3
 VA
R1
VA

A D1 VD
C1 R2 VSCR
AC LINE C2 VM
VOLTAGE
R3
α
MOT PHASE
ANGLE
D2
(b). Waveform for One Positive Half-Cycle of Circuit

Figure 6.9. (a). Speed-Control Scheme for

Universal Motors
The gain of the system, that is, the ratio of the change of VA
effective SCR output voltage to the change in generator (R2)′
EMF, is considerably greater at low speed settings than it
is at high speed settings. This high gain coupled with a R2 (R2)″
motor with a very low residual EMF will cause a condition VM
sometimes known as cycle skipping. In this mode of
operation, the motor speed is controlled by skipping entire
cycles or groups of cycles, then triggering one or two cycles
early in the period to compensate for the loss in speed. α1 α2 α3 PHASE
Loading the motor would eliminate this condition; however, ANGLE
the undesirable sound and vibration of the motor necessitate (c). Voltage Waveform at Point “A” for Three Settings
that this condition be eliminated. This can be done in two of Potentiometer R2
ways.
The first method is used if the motor design is fixed and
cannot be changed. In this case, the impedance level of the
voltage divider R1, R2 and R3 can be lowered so that C1 will TRIGGER
charge more rapidly, thus increasing the slope of the ramp POINT
and lowering the system gain. The second method, which will
provide an overall benefit in improved circuit performance,
involves a redesign of the motor so that the residual EMF
becomes greater. In general, this means using a lower grade
of magnetic steel for the laminations. As a matter of fact,
UNLOADED
some people have found that ordinary cold-rolled steel used WAVEFORM
as rotor laminations makes a motor ideally suited for this type
of electronic control.
Another common problem encountered with this circuit
is that of thermal runaway. With the speed control set at ACTUAL
low or medium speed, at high ambient temperatures the WAVEFORM
speed may increase uncontrollably to its maximum value.
This phenomenon is caused by an excessive impedance
in the voltage-divider string for the SCR being triggered. If
the voltage-divider current is too low, current will flow into (d). Point “A” Voltage with Excessive Resistance R1
the gate of the SCR without turning it on, causing the
waveform at point A to be as shown in 6.9(d). The flat
portion of the waveform in the early part of the half-cycle is The solutions to this problem are the use of the most
caused by the SCR gate current loading the voltage
sensitive SCR practical and a voltage divider network of
divider before the SCR is triggered. After the SCR is
sufficiently low impedance. As a rough rule of thumb, the
triggered, diode D1 is back-biased and a load is no longer
on the voltage divider so that it jumps up to its unloaded average current through the voltage divider during the
voltage. As the ambient temperature increases, the SCR positive half-cycle should be approximately three times
becomes more sensitive, thereby requiring less gate the current necessary to trigger the lowest-sensitivity
current to trigger, and is triggered earlier in the half- (highest gate current) SCR being used.
cycle.This early triggering causes increased current in the
SCR, thereby heating the junction still further and increas-
ing still further the sensitivity of the SCR until maximum
speed has been reached.

Theory and Applications Motorola Thyristor Device Data

1.6–4
 In addition to the type of steel used in the motor
laminations, consideration should also be given to the design
of motors used in this half-wave speed control. Since the
maximum rms voltage available to the motor under half-wave
conditions is 85 V, the motor should be designed for use at
that voltage to obtain maximum speed. However, U.L.
requirements state that semiconductor devices used in

AC LINE VOLTAGE
appliance control systems must be able to be short-circuited
without causing danger. Many designers have found it
advantageous, therefore, to use 115 V motors with this CONTROL
system and provide a switch to apply full-wave voltage to the CIRCUIT
motor for high-speed operation. Figure 6.10 shows the
proper connection for this switch. If one were to simply
short-circuit the SCR for full-speed operation, a problem
could arise. If the motor were operating at full speed with MOT
the switch closed, and the switch were then opened during
the negative half-cycle, the current flowing in the inductive
field of the motor could then break down the SCR in the
negative direction and destroy the control. With the circuit Figure 6.10. Switching Scheme for
as shown, the energy stored in the field of the motor is Full-Wave Operation
dissipated in the arc of the switch before the SCR is While the TRIAC has its disadvantages, it does offer some
connected into the circuit. advantages. In a SCR speed control either two SCRs must
be used, or the line voltage must be full-wave rectified
CONTROL OF PERMANENT-MAGNET MOTORS using relatively high current rectifiers, or the control must
As a result of recent developments in ceramic perma- be limited to half-wave. The TRIAC eliminates all these
nent-magnet materials that can be easily molded into difficulties. By using a TRIAC the part count, package size,
complex shapes at low cost, the permanent-magnet motor and cost can be reduced. Figure 6.13 shows a TRIAC
has become increasingly attractive as an appliance motor speed control circuit that derives its feedback from
component. Electronic control of this type of motor can be the load current and does not require separate connec-
easily achieved using techniques similar to those just tions to the motor field and armature windings. Therefore,
described for the universal motor. Figure 6.11 is a circuit this circuit can be conveniently built into an appliance or
diagram of a control system that we have developed and used as a separate control.
tested successfully to control permanent-magnet motors The circuit operates as follows: When the TRIAC
presently being used in blenders. Potentiometer R3 and conducts, the normal line voltage, less the drop across the
diode D1 form a dc charging path for capacitor C1; variable TRIAC and resistor R5, is applied to the motor. By delaying
resistor R1 and resistor R2 form an ac charging path which the firing of the TRIAC until a later portion of the cycle, the
creates the ramp voltage on the capacitor. Resistor R4 and rms voltage applied to the motor is reduced and its speed
diode D2 serve to isolate the motor control circuit from the is reduced proportionally. The use of feedback maintains
ramp generator during the positive and negative half- torque at reduced speeds.
cycles, respectively.
A small amount of cycle skipping can be experienced at
low speeds using this control, but not enough to necessi-
tate further development work. Since the voltage gener- D1
ated during off time is very high, the thermal runaway
problem does not appear at all. Typical speed-torque R1 R3
AC LINE VOLTAGE

curves for motors of this type are shown in Figure 6.12.

R2 R4 D2
MOTOR SPEED CONTROL WITH FEEDBACK
While many motor speed control circuits have used
SCRs, the TRIAC has not been very popular in this ap-
plication. At first glance, it would appear that the TRIAC C1
MOT
would be perfect for speed control because of its bilateral
characteristics. There are a couple of reasons why this is
not true. The major difficulty is the TRIAC’s dv/dt charac-
teristic. Another reason is the difficulty of obtaining a feed- Figure 6.11. Circuit Diagram for Controlling
back signal because of the TRIAC’s bilatera nature. Permanent-Magnet Motors

Motorola Thyristor Device Data Theory and Applications

1.6–5
 motor current. The value of R5 is chosen so that C1 cannot
VR VR = FULL RATED VOLTAGE
charge to a high enough voltage to fire Q1 during the
conduction period. However, the amount of charging re-
3/4 VR quired to fire Q1 has been decreased by an amount
proportional to the motor current. Therefore, the firing angle
at which Q1 will fire has been advanced in proportion to the
SPEED

1/2 VR motor current. As the motor is loaded and draws more

current, the firing angle of Q1 is advanced even more,
causing a proportionate increase in the rms voltage applied
1/4 VR
to the motor, and a consequent increase in its available
torque.
Since the firing voltage of Q1 depends on the voltage from
base one to base two, it is necessary to support the base two
TORQUE
voltage during the conduction portion of the cycle to prevent
Figure 6.12. Speed-Torque Characteristic of Permanen the feedback voltage from firing Q1. D6 and C2 perform this
Magnet Motors at Various Applied Voltages function.
Diodes D1 through D4 form a bridge which applies Because the motor is an inductive load, it is necessary to
full-wave rectified voltage to the phase-control circuit. Phase limit the commutation dv/dt for reliable circuit operation. R6
control of the TRIAC is obtained by the charging of capacitor and C3 perform this function.
C1 through resistors R2 and R3 from the voltage level Nominal values for R5 can be obtained from the table or
established by zener diode D5. When C1 charges to the they can be calculated from the equation given. Exact values
firing voltage of PUT Q1, the TRIAC triggers by transform- for R5 depend somewhat on the motor characteristics.
er T1. C1 discharges through the emitter of Q1. While the Therefore, it is suggested that R5 be an adjustable wire-
TRIAC is conducting, the voltage drop between points A wound resistor which can be calibrated in terms of motor
and B falls below the breakdown voltage of D5. Therefore, current, and the speed control can be adapted to many
during the conduction period, the voltage on C1 is deter- different motors. If the value of R5 is too high, feedback will
mined by the voltage drop from A to B and by resistors R1, be excessive and surging or loss of control will result. If the
R2, and R3. Since the voltage between A and B is a function value is too low, a loss of torque will result. The maximum
of motor current due to resistor R5, C1 is charged during the motor current flows through R5, and its wattage must be
determined accordingly.
conduction period to a value which is proportional to the

A
R1

18 k R2 D6
2W 27 k 1N4001

D1 R3 R4 Q2
D2 R6
50 k Q1 16 k MAC9D
115 VAC 2N6027 100 Ω
IN4006(4) D5 C2
60 Hz ZENER 10 µF
9.1 V 10 V C3
D3
D4 0.1 µF
C1 R7
0.1 µF 27 k

T1 R5
DALE SEE TABLE
PT-50 ORIGIN

B
MOTOR NOMINAL R5 VALUES
R5
Motor Rating
(Amperes) OHMS Watts R5 + I2M
2 1 5
3 0.67 10 IM = Max. Rated
Motor Current
6.5 0.32 15
(RMS)

Figure 6.13. Motor Speed Control with Feedback

Theory and Applications Motorola Thyristor Device Data

1.6–6
 + 100
14 R9
100 µF 0.05
C8
8 POSITIVE 9
FEEDBACK
1.0 µF
120 k
R12 FULL-WAVE

+ FULL-WAVE 2
TRIGGER PULSE MAC8D
12 – GENERATOR
SET 6 820 k

+ MONITORING CURRENT
SYNCHRO

13 10 4 – VCC 1 7 820 k
C13 +
R10 C4 SAWTOOTH
RCOMPENSATION SOFT
START GENERATOR VOLTAGE SYNCHRO
PROGRAMMING PIN 2.0 W

MAIN LINE 18 k 1N4005

VOLTAGE COMPENSATION
Figure 6.14. TDA 1185-A Universal Motor Speed Control.
— Internal Block Diagram/Pin Assignment

This circuit has been operated successfully with 2 and 3 advantages to be gained from tachometer feedback are
ampere 1/4-inch drills and has satisfactorily controlled motor the ability to apply feedback control to shaded-pole
speeds down to 1/3 or less of maximum speed with good motors, and better brush life in universal motors used in
torque characteristics. to the motor, and a consequent feedback circuits. This latter advantage results from the
increase in its available torque. use of full-wave rather than half-wave control, reducing the
peak currents for similar power levels.
AN INTEGRATED CIRCUIT FEEDBACK CONTROL THE TACHOMETER
The TDA1185A TRIAC phase angle controller (Figure The heart of this system is, of course, the speed-sensing
6.14) generates controlled triac triggering pulses and applies tachometer itself. Economy being one of the principal goals
positive current feedback to stabilize the speed of universal of the design, it was decided to use a simple magnetic
motors. A ramp voltage synchronized to the ac line half cycle tachometer incorporating the existing motor fan as an
and compared to an external set voltage determines the firing integral part of the magnetic circuit. The generator consists of
angle. Negative gate pulses drive the triac in quadrants two a coil wound on a permanent magnet which is placed so that
and three. the moving fan blades provide a magnetic path of varying
Because the speed of a universal motor decreases as reluctance as they move past the poles of the magnet.
torque increases, the TDA1185A lengthens the triac conduc- Several possible configurations of the magnetic system are
tion angle in proportion to the motor current, sensed through shown in Figure 6.15.
resistor R9. Flux in a magnetic circuit can be found from the “magnetic
The TDA1185A is the best solution for low cost Ohm’s law”:

+ MMF
applications tolerating 5% motor speed variation. Open
loop systems do not have a tachometer or negative φ ,
R
feedback and consequently cannot provide perfect speed
compensation. where φ = the flux,
MMF = the magnetomotive force (strength of the
CONSTANT SPEED MOTOR CONTROL USING magnet), and
TACHOMETER FEEDBACK R = the reluctance of the magnetic path.
Tachometer feedback sensing rotor speed provides
excellent performance with electric motors. The principal

Motorola Thyristor Device Data Theory and Applications

1.6–7
 COIL WIRES

MAGNET
FAN
MOTOR
ARMATURE
MOTOR
ARMATURE
MOTOR FAN
SIDE VIEW

MOTOR FAN
COIL
WIRES FERROUS
MOTOR MOTOR HOUSING
ARMATURE

MAGNET POSSIBLE MAGNET SHAPES

TOP VIEW AND LOCATIONS

Figure 6.15. (a). Locations for Magnetic Sensing (b). Locations for Magnetic Sensing Tachometer
Tachometer Generator Using a Horseshoe Magnet Generator Using an “L” or Bar Magnet
Assuming the MMF of the permanent magnet to be constant, THE ELECTRONICS
it is readily apparent that variations in reluctance will directly In one basic circuit, which is shown in Figure 6.16, the
affect the flux. The steel fan blades provide a low-reluctance generator output is rectified by rectifier D1, then filtered and
path for the flux once it crosses the air gap between them and applied between the positive supply voltage and the base of
the poles of the magnet. If the magnet used has a horseshoe the detector transistor Q1. This provides a negative voltage
or U shape, and is placed so that adjacent fan blades are which reduces the base-voltage on Q1 when the speed
directly opposite each pole in one position of the motor increases.
armature, the magnetic path will be of relatively low reluc- The emitter of the detector transistor is connected to a
tance; then as the motor turns the reluctance will increase voltage divider which is adjusted to the desired tachometer
until one fan blade is precisely centered between the poles of output voltage. In normal operation, if the tachometer voltage
the magnet. As rotation continues, the reluctance will then is less than desired, the detector transistor, Q1, is turned on
alternately increase and decrease as the fan blades pass the by current through R1 into its base. Q1 then turns on Q2
poles of the magnet. If a bar- or L-shaped magnet is used so which causes the timing capacitor for programmable unijunc-
that one pole is close to the shaft or the frame of the motor tion transistor Q3 to charge quickly.
and the other is near the fan blades, the magnetic path As the tachometer output approaches the voltage desired,
reluctance will vary as each blade passes the magnet pole the base-emitter voltage of Q1 is reduced to the point at
near the fan. In either case the varying reluctance causes which Q1 is almost cut off. Thereby, the collector current of
variations in the circuit flux and a voltage is generated in the Q2, which charges the PUT timing capacitor, reduces,
coil wound around the magnet. The voltage is given by the causing it to charge slowly and trigger the thyristor later in the
equation: half cycle. In this manner, the average power to the motor is

+ –N dφdt x 10–8,
reduced until just enough power to maintain the desired
e motor speed is allowed to flow.
Input circuit variations are used when the tachometer
where e = the coil voltage in volts, output voltage is too low to give a usable signal with a silicon
N = the number of turns in the coil, and rectifier. In the variation shown in Figure 6.16(b), the
dφ = the rate of change of flux in lines per tachometer is connected between a voltage divider and the
dt second. base of the amplifier transistor. The voltage divider is set so
In a practical case, a typical small horseshoe magnet wound that with no tachometer output the transistor is just barely in
with 1000 turns of wire generated a voltage of about 0.5 conduction. As the tachometer output increases, QT is cut off
volts/1000 rpm when mounted in a blender. on negative half cycles and conducts on positive half cycles.
Since both generated voltage and frequency are directly Resistors R9 and R10 provide a fixed gain for this amplifier
proportional to the motor speed, either parameter can be stage, providing the hFE of QT is much greater than the ratio
used as the feedback signal. However, circuits using voltage of R9 to R10. Thus the output of the amplifier is a fixed
sensing are less complex and therefore less expensive. Only multiple of the positive values of the tachometer waveform.
that system will be discussed here. The rectifier diode D1 prevents C1 from discharging through
R9 on negative half cycles of the tachometer. The

Theory and Applications Motorola Thyristor Device Data

1.6–8
 + V1 (PURE dc) operation of the remainder of the circuit is the same as the
previously described circuits.
C1 R5 (PULSING dc)
R1 R2 R3 All of the described circuits show a PUT as the trigger
device. An SBS may also be used as shown in Figure 6.18.
+ V2 The rectifier diode which is connected to the pulsing dc
Q2
D1 Q1 voltage, V2, discharges the capacitor at the end of each half
R6 LOAD cycle of the line voltage alternations, providing synchroniza-
TACHOMETER
GENERATOR
tion to the line voltage.
R4 120 V
INPUT CIRCUIT AC PHASE CONTROL WITH TRIGGER DEVICES
C2
DETECTOR AND POWER Phase control using thyristors is one of the most common
CONTROL CIRCUIT means of controlling the flow of power to electric motors,
lamps, and heaters. With an ac voltage applied to the circuit,
Figure 6.16. (a). Basic Tachometer Control Circuit
the gated thyristor (SCR, TRIAC, etc.) remains in its off-state
for the first portion of each half cycle of the power line, then,
at a time (phase angle) determined by the control circuit, the
thyristor switches on for the remainder of the half cycle. By
R9 C1 R1 controlling the phase angle at which the thyristor is switched
R7
on, the relative power in the load may be controlled.
TACH

QT D1 PHASE CONTROL WITH PROGRAMMABLE

UNIJUNCTION TRANSISTORS
R8 R10 PUTs provide a simple, convenient means for obtaining the
thyristor trigger pulse synchronized to the ac line at a
controlled phase angle.
(b). Variation Used when the Tachometer Output is
Too Low for Adequate Control

+ V1 (PURE dc)

R1 + V2 PULSATING dc
R9 C1 R1
R7 TACH
TACH Q1 LOAD

QT 120 VAC
D1
D2 R2 C
R10

(c). Variation Providing Better Temperature Tracking Figure 6.17. Another Basic Tachometer Circuit
and Easier Initial Adjustment

remainder of the filter and control circuitry is the same as + V2 120 VAC
the basic circuit. TO
In the second variation, shown in 6.16(c), R8 has been CHARGING LOAD
replaced by a semiconductor diode, D2. Since the voltage CIRCUIT
and temperature characteristics more closely match those of MBS4991
the transistor base-to-emitter junction, this circuit is easier to
design and needs no initial adjustments as does the circuit in
6.16(b). The remainder of this circuit is identical to that of
Figure 6.15.
In the second basic circuit, which is shown in Figure 6.17,
the rectified and filtered tachometer voltage is added to the NOTE: V1 u VBR OF TRIGGER
output voltage of the voltage divider formed by R1 and R2. If
the sum of the two voltages is less than V1 – VBE Q1 (where Figure 6.18. SBS as an Alternative Triggering
VBE Q1 is the base-emitter voltage of Q1), Q1 will conduct a Device in Figures 6.15 and 6.16
current proportional to V1 – VBE Q1, charging capacitor C. If
the sum of the two voltages is greater than V1 – VBE Q1, Q1
will be cut off and no current will flow into the capacitor. The

Motorola Thyristor Device Data Theory and Applications

1.6–9
 It is often necessary to synchronize the timing of the output
LOAD pulses to the power line voltage zero-crossing points. One
RB1 RT
A simple method of accomplishing synchronization is shown in
G Figure 6.20. Zener diode D1 clips the rectified supply voltage
VS CT resulting in a Vs as shown in 6.20(b). Since VS, and therefore
K the peak point voltage of the PUT drops to zero each time the
RB2
line voltage crosses zero, CT discharges at the end of every
RGK half cycle and begins each half cycle in the discharged state.
Thus, even if the PUT has not triggered during one half cycle,
the capacitor begins the next half cycle discharged. Conse-
(a)
quently, the values of RT and CT directly control the phase
angle at which the pulse occurs on each half cycle. The
zener diode also provides voltage stabilization for the timing
circuit giving the same pulse phase angle regardless of
Von
normal line voltage fluctuations.
CAPACITOR
VOLTAGE
V CT

APPLICATIONS
The most elementary application of the PUT trigger circuit,
shown in Figure 6.21, is a half-wave control circuit. In this
Voff circuit, RD is selected to limit the current through D1 so that
the diode dissipation capability is not exceeded. Dividing the

RD
V
RT R1
OUTPUT VOLTAGE
V RB1

D1
VS
VCG

CT
IBBRB1 R2
0 R3
(b)
LINE
(a)
Figure 6.19. Basic Relaxation Oscillator Circuit (a) RECTIFIED
and Waveforms (b) VS SINE WAVE
These circuits are all based on the simple relaxation
oscillator circuit of Figure 6.19. RT and CT in the figure form
the timing network which determines the time between the
application of voltage to the circuit (represented by the
closing of S1) and the initiation of the pulse. In the case of the
(b)
circuit shown, with Vs pure dc, the oscillator is free running,
RT and CT determine the frequency of oscillation. The peak Figure 6.20. Control Circuit (a) with Zener
of the output pulse voltage is clipped by the forward Clipped,Rectified Voltage (b)
conduction voltage of the gate to cathode diode in the
thyristor. The principal waveforms associated with the circuit LOAD
are shown in Figure 6.19(b).
600 W RD 6.8 k
Operation of the circuit may best be described by referring 2W
to the capacitor voltage waveform. Following power applica-
tion, CT charges at the rate determined by its own capaci- RT R1 5.1 k
AC 100 k
tance and the value of RT until its voltage reaches the peak LINE 2N6027
point voltage of the PUT. Then the PUT switches into D1 MCR8D
conduction, discharging CT through RGK and the gate of the 1N5250A R2 10 k
CT
thyristor. With Vs pure dc, the cycle then repeats immediately; 0.1 µF R3 100 k
however, in many cases Vs is derived from the anode voltage
of the thyristor so that the timing cycle cannot start again until
the thyristor is blocking forward voltage and once again Figure 6.21. Half Wave Control Circuit with Typical
provides Vs. Values for a 600 Watt Resistive Load

Theory and Applications Motorola Thyristor Device Data

1.6–10
 allowable diode dissipation by one-half the zener voltage will resistive; however, if the load is inductive, the load must be
give the allowable positive current in the diode since it is transferred from the SCR to the direct line as shown in Figure
conducting in the voltage regulating mode only during 6.22.
positive half cycles. Once the positive half-cycle current is Full wave control may be realized by the addition of a
found, the resistor value may be calculated by subtracting bridge rectifier, a pulse transformer, and by changing the
0.7 times the zener voltage from the rms line voltage and thyristor from an SCR to a TRIAC, shown in Figure 6.23.
dividing the result by the positive current: Occasionally a circuit is required which will provide

RD
* 0.7 Vz
+ ErmsIpositive
constant output voltage regardless of line voltage changes.
Adding potentiometer P1, as shown in Figure 6.24, to the
circuits of Figures 6.21 and 6.23, will provide an approximate
solution to this problem. The potentiometer is adjusted to
The power rating of RD must be calculated on the basis of full provide reasonably constant output over the desired range of
wave conduction as D1 is conducting on the negative half line voltage. As the line voltage increases, so does the
cycle acting as a shunt rectifier as well as providing Vs on the voltage on the wiper of P1 increasing VS and thus the peak
positive half cycle. point voltage of the PUT. The increased peak point voltage
The thyristor is acting both as a power control device and a results in CT charging to a higher voltage and thus taking
rectifier, providing variable power to the load during the more time to trigger. The additional delay reduces the
positive half cycle and no power to the load during the thyristor conduction angle and maintains the average voltage
negative half cycle. The circuit is designed to be a two at a reasonably constant value.
terminal control which can be inserted in place of a switch. If
full wave power is desired as the upper extreme of this FEEDBACK CIRCUITS
control, a switch can be added which will short circuit the The circuits described so far have been manual control
SCR when RT is turned to its maximum power position. The circuits; i.e., the power output is controlled by a potentiometer
switch may be placed in parallel with the SCR if the load is turned by hand. Simple feedback circuits may be constructed
by replacing RT with heat or light-dependent sensing
resistors; however, these circuits have no means of adjusting
CONTROL the operating levels. The addition of a transistor to the circuits
CIRCUIT of Figures 6.21 and 6.23 allows complete control.
Figure 6.25 shows a feedback control using a sensing
resistor for feedback. The sensing resistor may respond to
any one of many stimuli such as heat, light, moisture,
(a). Resistive Load pressure, or magnetic field. Rs is the sensing resistor and Rc
is the control resistor that establishes the desired operating
point. Transistor Q1 is connected as an emitter follower such
that an increase in the resistance of Rs decreases the
voltage on the base of Q1, causing more current to flow.
CONTROL RD P1
CIRCUIT
6.8 k 500 RG1 5.1 k
RT 100 k
RECTIFIED
LINE 2N6027
D1
(b). Inductive Load (FULL OR 1N5250A
RG2 10 k
HALF WAVE) CT
Figure 6.22. Half Wave Controls with Switching for 0.1 µF 100 RGK TO THYRISTOR
Full Wave Operation GATE-CATHODE

LOAD Figure 6.24. Circuit for Line Voltage Compensation

900 W RD
6.8 k
6.8 k RT
2W 100 k R1 5.1 k
RD RT(MIN)
1N5250A 2N6027 Rs* 5.1 k
10 k MAC12D 10 k
RECTIFIED Q1
LINE D1 R2 LINE 1N5250A MPS6512
(FULL OR D1 2N6027
CT R3 HALF WAVE) 10 k
MDA920A4 0.1 µF 100 k Rc CT
DALE 100 k 0.1 µF 100 TO THYRISTOR
PT50
(OR EQUIVALENT) GATE-CATHODE
*Rs SHOULD BE SELECTED TO BE ABOUT
3 k TO 5 k OHMS AT THE DESIRED OUTPUT LEVEL
Figure 6.23. A Simple Full Wave Trigger Circuit with
Typical Values for a 900 Watt Resistive Load Figure 6.25. Feedback Control Circuit

Motorola Thyristor Device Data Theory and Applications

1.6–11
 Current through Q1 charges CT, triggering the PUT at a If the quantity to be sensed can be fed back to the circuit in
delayed phase angle. As Rs becomes larger, more charging the form of an isolated, varying dc voltage such as the output
current flows, causing the capacitor voltage to increase more of a tachometer, it may be inserted between the voltage
rapidly. This triggers the PUT with less phase delay, boosting divider and the base of Q1 with the proper polarity. In this
power to the load. When Rs decreases, less power is applied case, the voltage divider would be a potentiometer to adjust
to the load. Thus, this circuit is for a sensing resistor which the operating point. Such a circuit is shown in Figure 6.26.
decreases in response to too much power in the load. If the In some cases, average load voltage is the desired
sensing resistor increases with load power, then Rs and Rc feedback variable. In a half wave circuit this type of feedback
should be interchanged. usually requires the addition of a pulse transformer, shown in
Figure 6.27. The RC network, R1, R2, C1, averages load
voltage so that it may be compared with the set point on Rs
6.8 k by Q1. Full wave operation of this type of circuit requires dc in
the load as well as the control circuit. Figure 6.28 is one
10 k RT(MIN) 5.1 k method of obtaining this full wave control.
RECTIFIED
LINE 2N6027 TO Each SCR conducts on alternate half-cycles and supplies
Rc es MPS6512
10 k THYRISTOR pulsating dc to the load. The resistors (Rg) insure sharing of
1N5250A 100 k
GATE-CATHODE the gate current between the simultaneously driven SCRs.
R1
Each SCR is gated while blocking the line voltage every
0.1 µF CT 100
other half cycle. This momentarily increases reverse blocking
leakage and power dissipation. However, the leakage power
Figure 6.26. Voltage Feedback Circuit loss is negligible due to the low line voltage and duty cycle of
the gate pulse.
MCR218-4 There are, of course, many more sophisticated circuits
which can be derived from the basic circuits discussed here.
RD 6.8 k T If, for example, very close temperature control is desired, the
DALE PT50 R1 circuit of Figure 6.25 might not have sufficient gain. To solve
RC (OR EQUIVALENT) 100 k this problem a dc amplifier could be inserted between the
AC
1k Q1 DC voltage divider and the control transistor gate to provide as
LINE 2k MPS6512 LOAD close a control as desired. Other modifications to add
600 W multiple inputs, switched gains, ramp and pedestal control,
1N5250A 2N6028 R2 etc., are all simple additions to add sophistication.
3.9 k

C1
10 µF 30 k
T CT
0.1 µF CLOSED LOOP UNIVERSAL MOTOR SPEED
CONTROL
Figure 6.27. Half Wave, Average Voltage Feedback Figure 6.29 illustrates a typical tachometer stabilized
closed feedback loop control using the TDA1285A integrated
circuit. This circuit operates off the ac line and generates a
T phase angle varied trigger pulse to control the triac. It uses
RG
10 RG inductive or hall effect speed sensors, controls motor starting
10 MPS6512 R1
100 k acceleration and current, and provides a 1 to 2% speed
MCR218-4 variation for temperature and load variations.
2k Q1
(2)
6.8 k
RD 2 W
R2 CYCLE CONTROL WITH OPTICALLY
2N6028
30 k ISOLATED TRIAC DRIVERS
1N4003 D1 In addition to the phase control circuits, TRIAC drivers can
CT DC
(2) 1N5250A 10 also be used for ac power control by on-off or burst control, of
3.9 k

T 0.1 µF C1
µF
LOAD
a number of ac cycles. This form of power control allows logic
1N4721 circuits and microprocessors to easily control ac power with
DALE PT50
(2) (OR EQUIVALENT)
TRIAC drivers of both the zero-crossing and non zero-cross-
AC LINE ing varieties.
Figure 6.28. Full Wave, Average Voltage
Feedback Control

Theory and Applications Motorola Thyristor Device Data

1.6–12
 47 µF
VCC 1N4005 220 V
+ 10 k
C14 R1 Inductive
820 k
47 nF M TACHO
820 k
10 14 9 2 1
330 nF
16 TDA1285A
13
220 k 4 5 8 11 7 6 12 3
220 nF
22 k 0.1 µF
1.5 µF 10 NF C11 0.1 µF

1.0 MΩ C5 C7 2.2 k
R4 C4
100 nF 1.0 µF 220 nF
R3

Figure 6.29. (a). Motor Control Circuit

TDA1285A
NOTES:
Frequency to Voltage converter 6 12
—Max. motor speed 30,000 rpm
—Tachogenerator 4 pairs of poles: max. frequency =30, 000 x 4
60
2 kHz + HALL-
—C11 = 680 pF. R4 adjusted to obtain VPin 4 = 12 V at max. speed: 68 kΩ EFFECT M
47 k SENSOR
—Power Supply
with Vmains = 120 Vac, R1 = 4.7 kΩ. Perfect operation
will occur down to 80 Vac.
(b). Circuit Modifications
to Connect a Hall-Effect Sensor
USING NON-ZERO CROSSING OPTICALLY REMOTE CONTROL OF AC VOLTAGE
ISOLATED TRIAC DRIVERS Local building codes frequently require all 115 V light
USING THE MOC3011 ON 240 VAC LINES switch wiring to be enclosed in conduit. By using a
The rated voltage of a MOC3011 is not sufficiently high for MOC3011, a TRIAC, and a low voltage source, it is possible
it to be used directly on 240 V line; however, the designer to control a large lighting load from a long distance through
may stack two of them in series. When used this way, two low voltage signal wiring which is completely isolated from
resistors are required to equalize the voltage dropped across the ac line. Such wiring usually is not required to be put in
them as shown in Figure 6.30. conduit, so the cost savings in installing a lighting system
in commercial or residential buildings can be considerable.
An example is shown in Figure 6.30. Naturally, the load could
also be a motor, fan, pool pump, etc.

+5V
150 180
LOAD

MOC3011 λ 1M

240 Vac
MOC3011 λ 1M

1k

Figure 6.30. Two MOC3011 TRIAC Drivers in Series to Drive 240 V TRIAC

Motorola Thyristor Device Data Theory and Applications

1.6–13
 NON-CONDUIT #22 WIRE 180

115 V
360
λ 2N6342A

MOC3011

5V

Figure 6.31. Remote Control of AC Loads Through Low Voltage Non-Conduit Cable

SOLID STATE RELAY line voltage as shown in Figure 6.33. This technique extends
Figure 6.31 shows a complete general purpose, solid state the life of incandescent lamps, reduces the surge current
relay snubbed for inductive loads with input protection. When strains on the TRIAC, and reduces EMI generated by load
the designer has more control of the input and output switching. Of course, zero crossing can be generated within
conditions, he can eliminate those components which are not the microcomputer itself, but this requires considerable soft-
needed for his particular application to make the circuit more ware overhead and usually just as much hardware to gener-
cost effective. ate the zero-crossing timing signals

INTERFACING MICROPROCESSORS TO 115 VAC

PERIPHERALS APPLICATIONS USING THE ZERO CROSSING
The output of a typical microcomputer input-output (I/O) TRIAC DRIVER
port is a TTL-compatible terminal capable of driving one or For applications where EMI induced, non-zero crossing-
two TTL loads. This is not quite enough to drive the load switching is a problem, the zero crossing TRIAC driver is
MOC3011, nor can it be connected directly to an SCR or the answer. This TRIAC driver can greatly simplify the
TRIAC, because computer common is not normally refer- suppression of EMI for only a nominal increased cost.
enced to one side of the ac supply. Standard 7400 series Examples of several applications using the MOC3031, 41
gates can provide an input compatible with the output of an follows.
MC6821, MC6846 or similar peripheral interface adaptor and
can directly drive the MOC3011. If the second input of a 2
input gate is tied to a simple timing circuit, it will also provide
energization of the TRIAC only at the zero crossing of the ac

150 180 2.4 k

λ 0.1 µF
2W 2N6071B
1N4002
MOC3011 115 V
2N3904

47 10 k

Figure 6.32. Solid-State Relay

Theory and Applications Motorola Thyristor Device Data

1.6–14
 200 W
+5 V
+5 V 7400 180

300 115 V
ADDRESS MC6820 MOC3011 (RESISTIVE
MC6800 OR 2N6071 LOAD)
OR MC6821
MC6802 OR MOTOR
300 180 2.4 k
MPU MC6846
115 V
DATA I/O MOC3011 0.1 µF
(INDUCTIVE
2N6071B LOAD)

1k OPTO TRIAC
6.3 V 5V DRIVERS
115 V
3k OPTIONAL
2N3904 ZERO-CROSSING
CIRCUITRY
100 k

Figure 6.33. Interfacing an M6800 Microcomputer System to 115 Vac Loads

MATRIX SWITCHING a horizontal line being switched on. Since non-zero crossing
Matrix, or point-to-point switching, represents a method of TRIAC drivers have lower static dv/dt ratings, this ramp
controlling many loads using a minimum number of compo- would be sufficiently large to trigger the device on.
nents. On the 115 V line, the MOC3031 is ideal for this R is determined as before:
application; refer to Figure 6.34. The large static dv/dt rating
+ ITSM
Vin(pk)
of the MOC3031 prevents unwanted loads from being
R (min)
triggered on. This might occur, in the case of non-zero

+ 170 V + 150 ohms

crossing TRIAC drivers, when a TRIAC driver on a vertical
line was subjected to a large voltage ramp due to a TRIAC on 1.2 A

150 Ω
LOAD LOAD LOAD
MOC
3031

150 Ω
LOAD LOAD LOAD
MOC
3031

150 Ω
LOAD LOAD LOAD
MOC
3031
MOC MOC MOC
3031 3031 3031
115 V
150 Ω 150 Ω 150 Ω

CONTROL BUS

Figure 6.34. Matrix Switching

Motorola Thyristor Device Data Theory and Applications

1.6–15
 300 Ω

MOC
CONTROL
3041

POWER 230 VAC

RELAY

LOAD

LOAD

LOAD

LOAD
(230 VAC COIL)

Figure 6.35. Power Relay Control

POWER RELAYS The zero-crossing feature of these devices extends the life
The use of high-power relays to control the application of of incandescent lamps, reduces inrush currents and mini-
ac power to various loads is a very widespread practice. mizes EMI generated by load switching.
Their low contact resistance causes very little power loss and
many options in power control are possible due to their AC MOTORS
multipole-multithrow capability. The MOC3041 is well suited The large static dv/dt rating of the zero-crossing TRIAC
to the use of power relays on the 230 Vac line; refer to Figure drivers make them ideal when controlling ac motors. Figure
6.35. The large static dv/dt of this device makes a snubber 6.37 shows a circuit for reversing a two phase motor using
network unnecessary, thus reducing component count and the MOC3041. The higher voltage MOC3041 is required,
the amount of printed circuit board space required. A even on the 115 Vac line, due to the mutual and self-induc-
non-zero crossing TRAIC driver (MOC3021) could be used in tance of each of the motor windings, which may cause a
this application, but its lower static dv/dt rating would voltage much higher than 115 Vac to appear across the
necessitate a snubber network. winding which is not conducting current.

MICROCOMPUTER INTERFACE DETERMINING LIMITING RESISTOR R FOR A

The output of most microcomputer input/output (I/O) ports HIGH-WATTAGE INCANDESCENT LAMP
is a TTL signal capable of driving several TTL gates. This is Many high-wattage incandescent lamps suffer shortened
insufficient to drive a zero-crossing TRIAC driver. In addition, lifetimes when switched on at ac line voltages other than
it cannot be used to drive an SCR or TRIAC directly, because zero. This is due to a large inrush current destroying the
computer common is not usually referenced to one side of filament. A simple solution to this problem is the use of the
the ac supply. However, standard 7400 NAND gates can be MOC3041 as shown in Figure 6.38. The MOC3041 may be
used as buffers to accept the output of the I/O port and in controlled from a switch or some form of digital logic.
turn, drive the MOC3031 and/or MOC3041; refer to Figure
6.36.

+5 V 200 W
+5 V
7400 300 150 Ω

MOC 115 V
ADDRESS MC6820 3031 2N6071 (RESISTIVE
OR LOAD)
MC68000 MC6821
MOTOR
MPU OR 300 300 Ω
MC6846
DATA I/O MOC 230 V
3041 2N6073 (INDUCTIVE
LOAD)

1 kΩ
+5 V

Figure 6.36. M68000 Microcomputer Interface

Theory and Applications Motorola Thyristor Device Data

1.6–16
 MOTOR
OPTIONAL
CURRENT LIMITING RESISTOR
115 V
R
C
300 300

MOC MOC
3041 3041

Figure 6.37. Reversing Motor Circuit

The minimum value of R is determined by the maximum c. . Optical Isolation Between Input and Output
surge current rating of the MOC3041 (ITSM): d. . Thyristor (SCR or TRIAC) Output
e. . Zero Voltage Switching Output (Will Only Turn On
+
V in(pk)
Close to Zero Volts)
R (min)
I TSM f. . AC Output (50 or 60 Hz)
(10)
Figure 6.39 shows the general format and waveforms of
+
V in(pk)
the SSR. The input on/off signal is conditioned (perhaps only
1.2 A
by a resistor) and fed to the Light-Emitting-Diode (LED) of an
On a 230 Vac Line: optoelectronic-coupler. This is ANDed with a go signal that is
p
+ 340 V + 283 ohms
generated close to the zero-crossing of the line, typically
R (min) (11) 10 Volts. Thus, the output is not gated on via the amplifier
1.2 A
except at the zero-crossing of the line voltage. The SSR
In reality, this would be a 300 ohm resistor. output is then re-gated on at the beginning of every half-cycle
until the input on signal is removed. When this happens, the
thyristor output stays on until the load current reaches zero,
AC POWER CONTROL WITH SOLID-STATE and then turns off.
RELAYS
ADVANTAGES AND DISADVANTAGES OF SSRs
The Solid-State Relay (SSR) as described below, is a relay The SSR has several advantages that make it an attractive
function with: choice over its progenitor, the Electromechanical Relay
a. . Four Terminals (Two Input, Two Output) (EMR) although the SSR generally costs more than its
b. . DC or AC Input electromechanical counterpart. These advantages are:

LAMP

SWITCH OR MOC 300 230 V

DIGITAL LOGIC 3041

Figure 6.38. High-Wattage Lamp Control

Motorola Thyristor Device Data Theory and Applications

1.6–17
 ZERO CROSS
DETECTOR LOAD

GO/NO GO

POWER
INPUT LED AND
SWITCH
ON/OFF
AMPL

LINE
areas such as medical electronics where the reduction of
stray leakage paths is important.
This list of advantages is impressive, but of course, the
designer has to consider the following disadvantages:
LINE 0 1. Voltage Transient Resistance — the ac line is not
the clean sine wave obtainable from a signal genera-
GO tor. Superimposed on the line are voltage spikes from
NO GO motors, solenoids, EMRs (ironical), lightning, etc. The
ON solid-state components in the SSR have a finite volt-
OFF age rating and must be protected from such spikes,
either with RC networks (snubbing), zener diodes,
OUTPUT MOVs or selenium voltage clippers. If not done, the
thyristors will turn on for part of a half cycle, and at
worst, they will be permanently damaged, and fail to
Figure 6.39. SSR Block Diagram block voltage. For critical applications a safety margin
on voltage of 2 to 1 or better should be sought.
The voltage transient has at least two facets — the first
1. No Moving Parts — the SSR is all solid-state. There is the sheer amplitude, already discussed. The second
are no bearing surfaces to wear, springs to fatigue, as- is its frequency, or rate-of-rise of voltage (dv/dt). All thy-
semblies to pick up dust and rust. This leads to several ristors are sensitive to dv/dt to some extent, and the tran-
other advantages. sient must be snubbed, or “soaked up,” to below this level
2. No Contact Bounce — this in turn means no contact with an RC network.(1) Typically this rating (“critical” or
wear, arcing, or Electromagnetic Interference (EMI) “static” dv/dt) is 50 to 100 V/µs at maximum temperature.
associated with contact bounce. Again the failure mode is to let through, to a half-cycle of
3. Fast Operation — usually less than 10 µs. Fast turn- the line, though a high energy transient can cause per-
on time allows the SSR to be easily synchronized with manent damage. Table 6.1 gives some starting points for
line zero-crossing. This also minimizes EMI and can snubbing circuit values. The component values required
greatly increase the lifetime of tungsten lamps, of consid- depend on the characteristics of the transient, which are
erable value in applications such as traffic signals. usually difficult to quantify. Snubbing across the line as
4. Shock and Vibration Resistance — the solid-state well as across the SSR will also help.
contact cannot be “shaken open” as easily as the EMR
contact.
5. Absence of Audible Noise — this devolves from the Table 6.1. Typical Snubbing Values
lack of moving mechanical parts.
6. Output Contact Latching — the thyristor is a latching Load Current Resistance Capacitance
A rms Ω µF
device, and turns off only at the load current zero-cross-
ing, minimizing EMI. 5 47 0.047
7. High Sensitivity — the SSR can readily be designed
10 33 0.1
to interface directly with TTL and CMOS logic, simplifying
circuit design. 25 10 0.22
8. Very Low Coupling Capacitance Between Input and 40 22 0.47
Output. This is a characteristic inherent in the optoelec-
tronic-coupler used in the SSR, and can be useful in
1. For a more thorough discussion of snubbers, see page 1-3.9.

Theory and Applications Motorola Thyristor Device Data

1.6–18
 +
+
INPUT LOAD
R11
R1 C1 R2 R4 R6

SCR1
R13
OC1 Q1 Q2 BR TR11
11
D2
C11
R7
D1 R12
C2 R5

R3
–
–
LINE
INPUT AND CONTROL CIRCUIT TRIAC POWER CIRCUIT

Figure 6.40(a). TRIAC SSR Circuit

VSCR1

CROSSING
LINE ZERO
(b)

“ZERO” VOLTAGE
FIRING LEVEL
E

(c)

FIRING
WINDOW
WITHOUT FIRING
C1 AND C2 WINDOW

(d)

FIRING
WINDOW
WITH
FIRING WINDOW
C1 AND C2

Figure 6.40. Firing Windows

Motorola Thyristor Device Data Theory and Applications

1.6–19
 2. Voltage Drop — The SSR output contact has some the junction of the potential divider R4,R5 to overcome the
offset voltage — approximately 1 V, depending on cur- VBE of Q2. By judicious selection of R4 and R5, Q2 will clamp
rent, causing dissipation. As the thyristor has an oper- SCR1’s gate if more than approximately 5 Volts appear at the
ating temperature limit of +125°C, this heat must be anode of SCR1; i.e., Q2 is the zero-crossing detector.
removed, usually by conduction to air via a heat sink or If OC1 is on, Q1 is clamped off, and SCR1 can be turned
the chassis. on by current flowing down R6, only if Q2 is also off —
3. Leakage Current — When an EMR is open, no cur- which it is only at zero crossing.
rent can flow. When an SSR is open however, it does The capacitors are added to eliminate circuit race
not have as definite an off condition. There is always conditions and spurious firing, time ambiguities in opera-
some current leakage through the output power tion. Figure 6.40(b) shows the full-wave rectified line that
switching thyristor, the control circuitry, and the snub- appears across the control circuit. The zero voltage firing
bing network. The total of this leakage is usually 1 to level is shown in 6.40(b) and 6.40(c), expanded in time and
10 mA rms — three or four orders of magnitude less voltage. A race condition exists on the up-slope of the
than the on-state current rating. second half-cycle in that SCR1 may be triggered via R6
4. Multiple Poles — are costly to obtain in SSRs, and before Q1 has enough base current via R2 to clamp
three phase applications may be difficult to implement. SCR1’s gate. C1 provides current by virtue of the rate of
5. Nuclear Radiation — SSRs will be damaged by nu- change of the supply voltage, and Q1 is turned on firmly as
clear radiation. the supply voltage starts to rise, eliminating any possibility
of unwanted firing of the SSR; thus eliminating the race
TRIAC SSR CIRCUIT condition.
This leaves the possibility of unwanted firing of the SSR
Many SSR circuits use a TRIAC as the output switching on the down-slope of the first half cycle shown. C2
device. Figure 6.40(a) shows a typical TRIAC SSR circuit. provides a phase shift to the zero voltage potential divider,
The control circuit is used in the SCR relay as well, and is and Q2 is held on through the real zero-crossing. The
defined separately. The input circuit is TTL compatible. resultant window is shown in 6.40(d).
Output snubbing for inductive loads will be described later.
A sensitive-gate SCR (SCR1) is used to gate the power CONTROL CIRCUIT COMPONENTS
TRIAC, and a transistor amplifier is used as an interface The parts list for the control circuit at two line voltages is
between the optoelectronic-coupler and SCR1. (A sensitive- shown in Table 6.2.
gate SCR and a diode bridge are used in preference to a R1 limits the current in the input LED of OC1. The input
sensitive gate TRIAC because of the higher sensitivity of the circuit will function over the range of 3 to 33 Vdc.
SCR.) D1 provides reverse voltage protection for the input of
OC1.
CONTROL CIRCUIT OPERATION D2 allows the gate of SCR1 to be reverse biased,
The operation of the control circuit is straightforward. The providing better noise immunity and dv/dt performance.
AND function of Figure 6.39 is performed by the wired-NOR R7 eliminates pickup on SCR1’s gate through the
collector configuration of the small-signal transistors Q1 and zero-crossing interval.
Q2. Q1 clamps the gate of SCR1 if optoelectronic-coupler SCR1 is a sensitive gate SCR; the 2N5064 is a TO-92
OC1 is off. Q2 clamps the gate if there is sufficient voltage at device, the 2N6240 is a Case 77 device.
Alternatives to the simple series resistor (R1) input
Table 6.2. Control Circuit Parts List circuit will be described later.

Line Voltage POWER CIRCUIT COMPONENTS

Part 120 V rms 240 V rms The parts list for the TRIAC power circuit in Figure
6.40(a) is shown in Table 6.3 for several rms current
C1 220 pF,
F, 20%, 200 Vdc 100 pF,
F, 20%, 400 Vdc
C2 0.022 µµF, 20%, 50 Vdc 0.022 µµF, 20%, 50 Vdc
ratings, and two line voltages. The metal TRIACs are in the
D1 1N4001 1N4001 half-inch pressfit package in the isolated stud configura-
D2 1N4001 1N4001 tion; the plastic TRIACs are in the TO-220 Thermowatt
OC1 MOC1005 MOC1005 package. R12 is chosen by calculating the peak control
Q1 MPS5172 MPS5172 circuit off-state leakage current and ensuring that the
Q2 MPS5172 MPS5172 voltage drop across R12 is less than the V GT(MIN) of the
R1 1 kΩ, 10%, 1 W 1 kΩ, 10%, 1 W TRIAC.
R2 47 kΩ,, 5%,, 1/2 W 100 kΩ,, 5%,, 1 W C11 must be an ac rated capacitor, and with R13
R3 1 MΩ, 10%, 1/4 W 1 MΩ, 10%, 1/4 W provides some snubbing for the TRIAC. The values shown
R4 110 kΩ, 5%, 1/2 W 220 kΩ, 5%, 1/2 W
for this network are intended more for inductive load
R5 kΩ 5%
15 kΩ, 5%, 1/4 W kΩ 5%
15 kΩ, 5%, 1/4 W
R6 33 kΩ,
kΩ 10%
10%, 1/2 W 68 kΩ
kΩ, 10%
10%, 1 W
commutating dv/dt snubbing than for voltage transient
R7 kΩ, 10%
10 kΩ 10%, 1/4 W 10 kΩ
kΩ, 10%,
10% 1/4 W suppression. Consult the individual data sheets for the
SCR1 2N5064 2N6240 dissipation, temperature, and surge current limits of the
TRIACs.

Theory and Applications Motorola Thyristor Device Data

1.6–20
 Table 6.3. TRIAC Power Circuit Parts List

Voltage 120 V rms 240 V rms

rms Current Amperes 8 12 25 40 8 12 25 40
BR11 IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4)
C11, µF 0.047 0.047 0.1 0.1 0.047 0.047 0.1 0.1
(10%, line voltage ac rated)
R11 39 39 39 39 39 39 39 39
(10%, 1 W)
R12 18 18 18 18 18 18 18 18
(10%, 1/2 W)
R13 620 620 330 330 620 620 330 330
(10%, 1/2 W)

TR11 Plastic 2N6342 2N6342A — — 2N6343 2N6343A — —

TRIACs AND INDUCTIVE LOADS microsecond. This is normally done by use of a snubber
network R S and C S as shown in Figure 6.42.
The TRIAC is a single device which to some extent is the
SCRs have less trouble as each device has a full
equivalent of two SCRs inverse parallel connected; certainly
half-cycle to turn off and, once off, can resist dv/dt to the
this is so for resistive loads. Inductive loads however, can
critical value of 50 to 100 V/µs.
cause problems for TRIACs, especially at turn-off.
A TRIAC turns off every line half-cycle when the line
current goes through zero. With a resistive load, this CHOOSING THE SNUBBING COMPONENTS(1)
coincides with the line voltage also going through zero. The There are no easy methods for selecting the values of RS
TRIAC must regain blocking-state before there are more than and CS in Figure 6.42 required to limit commutating dv/dt.
1 or 2 Volts of the reverse polarity across it — at 120 V rms, The circuit is a damped tuned circuit comprised by RS, CS, RL
60 Hz line this is approximately 30 µs. The TRIAC has not and LL, and to a minor extent the junction capacitance of the
completely regained its off-state characteristics, but does so TRIAC. At turn-off this circuit receives a step impulse of line
as the line voltage increases at the 60 Hz rate. voltage which depends on the power factor of the load.
Figure 6.41 indicates what happens with an inductive or Assuming the load is fixed, which is normally the case, the
lagging load. The on signal is removed asynchronously designer can vary RS and CS. CS can be increased to
and the TRIAC, a latching device, stays on until the next decrease the commutating dv/dt; RS can be increased to
current zero. As the current is lagging the applied voltage, decrease the resonant over-ring of the tuned circuit — to
the line voltage at that instant appears across the TRIAC. increase damping. This can be done empirically, beginning
It is this rate-of-rise of voltage, the commutating dv/dt, that with the values for C11 and R13 given in Table 6.3, and aiming
must be limited in TRIAC circuits, usually to a few volts per 1. For a more thorough discussion of snubbers, see page 1-3-9.

ON
ON/OFF
SIGNAL OFF

LOAD CURRENT
0
(LAGGING LOAD)
LINE VOLTAGE dv/dt

LINE AND 0
TRIAC VOLTAGE
TRIAC VOLTAGE

Figure 6.41. Commutating dv/dt

Motorola Thyristor Device Data Theory and Applications

1.6–21
 Table 6.4. SCR Power Circuit Parts List

Voltage 120 V rms 240 V rms

rms Current Amperes 5 11 22 49 5 11 22 49
C21 (10%, line voltage ac rated) SEE TEXT
D21-24 1N4003 1N4003 1N4003 1N4003 1N4004 1N4004 1N4004 1N4004
R21 (10%, 1 W) 39 39 39 39 39 39 39 39
R22, 23 (10%, 1/2 W) 18 18 18 18 18 18 18 18
R24 SEE TEXT
SCR21 22
SCR21, Plastic 2N6239 2N6396 2N6402 — 2N6240 2N6397 2N6403 —

SCR SSR CIRCUIT

The inverse parallel connected Silicon Controlled Rectifier
LL LOAD (SCR) pair (shown in Figure 6.43) is less sensitive to
commutating dv/dt. Other advantages are the improved
thermal and surge characteristics of having two devices; the
RL disadvantage is increased cost.
The SCR power circuit can use the same control circuit as
the TRIAC Circuit shown in Figure 6.40(a). In Figure 6.43, for
RS positive load terminal and when the control circuit is gated
on, current flows through the load, D21, R21, SCR1, D22, the
CS gate of SCR21 and back to the line, thus turning on SCR21.
Operation is similar for the other line polarity. R22 and R23
provide a path for the off-state leakage of the control circuit
Figure 6.42. TRIAC with Snubber Network and are chosen so that the voltage dropped across them is
at close to critical damping and the data sheet value for less than the VGT(MIN) of the particular SCR. R24 and C21
commutating dv/dt. Reduced temperatures, voltages, and provide snubbing and line transient suppression, and may be
off-going di/dt (rate-of-change of current at turn-off) will give chosen from Table 6.4 or from the C11, R13 rows of Table
some safety margin. 6.3. The latter values will provide less transient protection but
also less off-state current, with the capacitor being smaller.
Other circuit values are shown in Table 6.46.

LOAD
D21
R23

D24

R21
+ +
CONTROL R24 SCR22
CIRCUIT
INPUT
(SEE FIGURE 6.39(a) SCR21
AND TABLE 6.II) D22 C21
– –

R22

D23
LINE

Figure 6.43. SCR SSR Circuit

Theory and Applications Motorola Thyristor Device Data

1.6–22
 Consult the individual data sheets for packages and +
OC1
dissipation, temperature, and surge current limits.
While the SCRs have much higher dv/dt commutation
ability, with inductive loads, attention should be paid to
maintaining the dv/dt below data sheet levels. R31
330 k
ALTERNATE INPUT CIRCUITS
CMOS COMPATIBLE
The 1 kΩ resistor, R1, shown in Figure 6.40(a) and Table INPUT
6.2, provide an input that is compatible with the current that a
TTL gate output can sink. The resistor R1 must be changed Q32
for CMOS compatibility, aiming at 2 mA in the LED for D31
1N4001
adequate performance to 100°C. At 2 mA do not use the 2N6427
CMOS output for any other function, as a LOGIC 0 or 1 may
not be guaranteed. Assume a forward voltage drop of 1.1 V Q31
for the LED, and then make the Ohm’s Law calculation for the MPS5172
R32
system dc supply voltage, thus defining a new value for R1. TH31 WESTERN THERMISTOR 330
CORP., CURVE 2,
TTL/CMOS COMPATIBLE
650 Ω ± 10% @ 25°C
To be TTL compatible at 5 Volts and CMOS compatible P/N2C6500 OR
over 3 to 15 Volts, a constant current circuit is required, such EQUIVALENT R33
as the one in Figure 6.44. The current is set by the VBE of 180
Q31 and the resistance of the R32, R33, and thermistor
TH31 network, and is between 1 and 2 mA, higher at high TH31
–
temperatures to compensate for the reduced transmission
efficiency of optoelectronic-couplers at higher temperature. Figure 6.44. TTL/CMOS Compatible Input
The circuit of Figure 6.44 gives an equivalent impedance of
approximately 50 kΩ. The circuit performs adequately over 3
to 33 Vdc and – 40 to +100°C. Note that though the SSR is
protected against damage from improperly connected inputs, INVERSE PARALLEL SCRs FOR POWER
the external circuit is not, as D31 acts as a bypass for a CONTROL
wrongly connected input driver.
TRIACs are very useful devices. They end up in solid state
AC LINE COMPATIBLE relays, lamp drivers, motor controls, sensing and detection
To use SSRs as logic switching elements is inefficient, circuits; just about any industrial full-wave application. But in
considering the availability and versatility of logic families high-frequency applications or those requiring high voltage
such as CMOS. When it is convenient to trigger from ac, a or current, their role is limited by their present physical
circuit such as shown in Figure 6.45 may be used. The characteristics, and they become very expensive at current
capacitor C41 is required to provide current to the LED of levels above 40 amperes rms.
OC1 through the zero-crossing time. An in-phase input SCRs can be used in an inverse-parallel connection to
voltage gives the worst case condition. The circuit gives 2 bypass the limitations of a TRIAC. A simple scheme for doing
mA minimum LED current at 75% of nominal line voltage. this is shown in Figure 6.46.The control device can take any

2 kΩ, 10%
R42
1/2 W
R41
C41 2 µF
R41
10%
BR41 50 V 120 V 22 kΩ, 10%, 1 W
OC1 240 V 47 kΩ, 10%, 2 W
INPUT AC

Figure 6.45. AC Compatible Input

Motorola Thyristor Device Data Theory and Applications

1.6–23
 FLOATING
LOAD RL

q ǸIGP
IG1
R
2 V
* (RL ) RC) ILa

IG
SCR1 1 2
WHERE IGP IS b 2V OR
PEAK GATE a A A
CURRENT RC R SCR2
RATING OF SCR
CONTROL DEVICE
(CLOSED RESISTANCE)
GROUNDED IG2 ILb
LOAD RL

Figure 6.46. Use of Inverse Parallel SCRs

of many forms, shown is the reed relay (Figure 6.46). TRIACs Better reliability can be achieved by replacing the reed
and Opto couplers can be inserted at point A-A to replace the relay with a low current TRIAC to drive the SCRs, although
reed relay. some of its limitations come with it. In the preferred circuit of
Compared to a TRIAC, an inverse-parallel configuration Figure 6.47(b), the main requirements of the TRIAC are that it
has distinct advantages. Voltage and current capabilities are be able to block the peak system voltage and that it have a
dependent solely on SCR characteristics with ratings today surge current rating compatible with the gate current require-
of over a thousand volts and several hundred amps. ments of the SCRs. This is normally so small that a TO-92

Ǹ
Because each SCR operates only on a half-wave basis, the cased device is adequate to drive the largest SCRs.
system’s rms current rating is 2 times the SCR’s rms current IfIn circuits like Figure 6.46, the control devices alter-
rating (see Suggested SCR chart). The system has the same nately pass the gate currents I G1 and I G2 during the “a” and
surge current rating as the SCRs do. Operation at 400 Hz is “b” half cycles, respectively. I La and I Lb are the load
also no problem. While turn-off time and dv/dt limits control currents during the corresponding half cycles. Each SCR
TRIAC operating speed, the recovery characteristics of an then gets the other half cycle for recovery time. Heat
SCR need only be better than the appropriate half-wave sinking can also be done more efficiently, since power is
period. being dissipated in two packages, rather than all in one.
With inductive loads you no longer need to worry about The load can either be floated or grounded. the SCRs are
commutating dv/dt, either. SCRs only need to withstand not of the shunted-gate variety, a gate-cathode resistance
static dv/dt, for which they are typically rated an order of should be added to shunt the leakage current at higher
magnitude greater than TRIACs are for commutating dv/dt. temperatures. The diodes act as steering diodes so the
gate-cathode junctions are not avalanched. The blocking
capability of the diodes need only be as high as the VGT of
the SCRs. A snubber can also be used if conditions dictate.

A A A A A A

GATE
CONTROL GATE
GATE CONTROL
CONTROL
(FLOATING)

(a). Reed Relay (b). Low-Current TRIAC (c). Optically Coupled TRIAC Driver

Figure 6.47. Control Devices

Theory and Applications Motorola Thyristor Device Data

1.6–24
 Table 6.6. Driver TRIACs

Gate Negative Or
Line Gate Optically
In Phase With
Voltage Positive Coupled
Line Voltage
120 MAC97A4 MAC97A4 MOC3030*, 3011
220 MAC97A6 MAC97A6 MOC3020, MOC3021

*Includes inhibit circuit for zero crossover firing.

This circuit offers several benefits. One is a considerable USING TRIACs

increase in gain. This permits driving the TRIAC with almost Two important thyristor parameters are gate trigger current
any other semiconductors such as linear ICs, photosensitive (IGT) and gate trigger voltage (VGT).
devices and logic, including MOS. If necessary, it can use an IGT (Gate Trigger Current) is the amount of gate trigger
optically coupled TRIAC driver to isolate (up to 7500 V current required to turn the device on. IGT has a negative
isolation) delicate logic circuits from the power circuit (see temperature coefficient — that is, the trigger current required
Figure 6.47(c)). Table 6.6. lists suggested components. to turn the device on increases with decreasing temperature.
Another benefit is being able to gate the TRIAC with a supply If the TRIAC must operate over a wide temperature range, its
of either polarity. Probably the most important benefit of the IGT requirement could double at the low temperature extreme
TRIAC/SCR combination is its ability to handle variable- from that of its 25°C rating.
phase applications — nearly impossible for non solid-state It is good practice, if possible, to trigger the thyristor with
control devices. three to ten times the IGT rating for the device. This increases
its di/dt capability and ensures adequate gate trigger current
at low temperatures.
INTERFACING DIGITAL CIRCUITS TO VGT (Gate Trigger Voltage) is the voltage the thyristor gate
THYRISTOR CONTROLLED AC LOADS needs to ensure triggering the device on. This voltage is
needed to overcome the input threshold voltage of the
Because they are bidirectional devices, TRIACs are the device. To prevent thyristor triggering, gate voltage should be
most common thyristor for controlling ac loads. A TRIAC can kept to approximately 0.4 V or less.
be triggered by either a positive or negative gate signal on Like IGT, VGT increases with decreasing temperature.
either the positive or negative half-cycle of applied MT2
voltage, producing four quadrants of operation. However, the INDUCTIVE LOAD SWITCHING
TRIAC’s trigger sensitivity varies with the quadrant, with Switching of inductive loads, using TRIACs, may require
quadrants II and III (gate signal negative and MT2 either special consideration in order to avoid false triggering. This
positive or negative) being the most sensitive and quadrant false-trigger mechanism is illustrated in Figure 6.48 which
IV (gate positive, MT2 negative) the least sensitive. shows an inductive circuit together with the accompanying
For driving a TRIAC with IC logic, quadrants II and III are waveforms.
particularly desirable, not only because less gate trigger As shown, the TRIAC is triggered on, at t1, by the positive
current is required, but also because IC power dissipation is gate current (IGT). At that point, TRIAC current flows and the
reduced since the TRIAC can be triggered by an “active low” voltage across the TRIAC is quite low since the TRIAC
output from the IC. resistance, during conduction, is very low.
There are other advantages to operating in quadrants II From point t1 to t2 the applied IGT keeps the TRIAC in a
and III. Since the rate of rise of on-state current of a TRIAC conductive condition, resulting in a continuous sinusoidal
(di/dt) is a function of how hard the TRIAC’s gate is turned current flow that leads the applied voltage by 90° for this pure
on, a given IC output in quadrants II and III will produce a inductive load.
greater di/dt capability than in the less sensitive quadrant At t2, IGT is turned off, but TRIAC current continues to flow
IV. Moreover, harder gate turn-on could reduce di/dt until it reaches a value that is less than the sustaining current
failure. One additional advantage of quadrant II and III (IH), at point A. At that point, TRIAC current is cut off and
operation is that devices specified in all four quadrants are TRIAC voltage is at a maximum. Some of that voltage is fed
generally more expensive than devices specified in back to the gate via the internal capacitance (from MT2 to
quadrants I, II and III, due to the additional testing involved gate) of the TRIAC.
and the resulting lower yields.

Motorola Thyristor Device Data Theory and Applications

1.6–25
TTL-TO-THYRISTOR INTERFACE TTL CIRCUITS WITH TOTEM-POLE OUTPUTS (e.g. 5400
SERIES)
The subject of interfacing requires a knowledge of the
The configuration of a typical totem-pole connected TTL
output characteristics of the driving stages as well as the
output stage is illustrated in Figure 6.49(a). This stage is
input requirements of the load. This section describes the
capable of “sourcing” current to a load, when the load is
driving capabilities of some of the more popular TTL circuits
connected from Vout to ground, and of “sinking” current from
and matches these to the input demands of thyristors under
the load when the latter is connected from Vout to VCC. If the
various practical operating conditions.
load happens to be the input circuit of a TRIAC (gate to MT1),
the TRIAC will be operating in quadrants I and IV (gate goes
positive) when connected from Vout to ground, and of
A
“sinking” II and III (gate goes negative) when connected from
Vout to VCC.
LOAD QUADRANT I-IV OPERATION
60 Hz Considering first the gate-positive condition, Figure
MT2 6.49(b), the operation of the circuit is as follows:
LINE
When Vin to the TTL output stage is low (logical “zero”),
MT1 transistors Q1 and Q3 of that stage are cut off, and Q2 is
GATE conducting. Therefore, Q2 sources current to the thyristor,
VOLTAGE and the thyristor would be triggered on during the Vin = 0
APPLIED B
condition.
TO TERMINALS TRIAC
A AND B CURRENT When Vin goes high (logical “one”), transistors Q1 and Q3
are on and Q2 is off. In this condition depicted by the
equivalent circuit transistor Q3 is turned on and its collector
voltage is, essentially, VCE(sat). As a result, the TRIAC is
clamped off by the low internal resistance of Q3.
A QUADRANT II-III OPERATION
When the TRIAC is to be operated in the more sensitive
quadrants II and III (negative-gate turn-on), the circuit in
t1 t2
Figure 6.50(a) may be employed.
IGT With Q3 in saturation, as shown in the equivalent circuit of
6.50(b), its saturation voltage is quite small, leaving virtually
TRIAC the entire – VEE voltage available for thyristor turn-on. This
VOLTAGE could result in a TRIAC gate current that exceeds the current
WITH SNUBBER CHANGE IN
TRIAC VOLTAGE DURING limit of Q3, requiring a current-limiting series resistor, (R(Iim)).
NETWORK
TURN-OFF (dv) When the Vout level goes high, Q3 is turned off and Q2
becomes conductive. Under those conditions, the TRIAC
gate voltage is below VGT and the TRIAC is turned off.
toff(dt)
TRIAC DIRECT-DRIVE LIMITATIONS
VOLTAGE With sensitive-gate TRIACs, the direct connection of a
WITH SNUBBER TRIAC to a TTL circuit may sometimes be practical.
NETWORK
However, the limitations of such circuits must be recognized.
For example:
For TTL circuits, the “high” logic level is specified as 2.4
UNDESIRED TRIGGERING volts. In the circuit of Figure 6.49(a), transistor Q2 is
DUE TO FEEDBACK capable of supplying a short-circuit output current (ISC) of
20 to 55 mA (depending on the tolerances of R1 and R2,
and on the hFE of Q2). Although this is adequate to turn a
Figure 6.48. Inductive Load TRIAC Circuit and sensitive-gate TRIAC on, the specified 2.4 volt (high) logic
Equivalent Waveforms level can only be maintained if the sourcing current is held
to a maximum of 0.4 mA — far less than the current
required to turn on any thyristor. Thus, the direct connec-
tion is useful only if the driver need not activate other logic
circuits in addition to a TRIAC.

Theory and Applications Motorola Thyristor Device Data

1.6–26
 VCC VCC A similar limiting condition exists in the Logic “0” condition
LOAD of the output, when the thyristor is to be clamped off. In this
SOURCE
CONNECTION condition, Q3 is conducting and Vout equals the saturation
R2 CURRENT
SINK FOR voltage (VCE(sat)) of Q3. TTL specifications indicate that the
100
R1 CURRENT CURRENT low logic level (logic “0”) may not exceed 0.4 volts, and that
1.4 k Q2 SINK the sink current must be limited to 16 mA in order not to
CONDITION exceed this value. A higher value of sink current would cause
Vin
TTL
(VCE(sat)) to rise, and could trigger the thyristor on.
Q1 Vout
GATE LOAD
CONNECTION CIRCUIT DESIGN CONSIDERATIONS
Q3 Where a 5400-type TTL circuit is used solely for controlling
FOR
CURRENT a TRIAC, with positive-gate turn-on (quadrants I-IV), a
1k
SOURCE sensitive gate TRIAC may be directly coupled to the logic
CONDITION output, as in Figure 6.49. If the correct logic levels must be
maintained, however, a couple of resistors must be added to
the circuit, as in Figure 6.51(a). In this diagram, R1 is a
pull-up which allows the circuit to source more current during
Vin a high logical output. Its value must be large enough,
however, to limit the sinking current below the 16 mA
maximum when Vout goes low so that the logical zero level of
Vout 0.4 volts is not exceeded.
Resistor R2, a voltage divider in conjunction with R1,
SOURCE insures VOH (the “high” output voltage) to be 2.4 V or greater.
CURRENT

SINK CURRENT
(a)
VCC R(lim) MT1

LOGIC CIRCUIT
R1 R2
TRIAC 60 Hz
LOAD MT2 LINE

Q2
60 Hz LOAD

Vout
(a)
–5V
GATE
MT1
Isink
(b) R1
Vout MT1

R(lim)
R1 60 Hz
TRIAC Q1
LOAD LINE
VEE(sat) MT2
Q1 Q3
60 Hz 0.4 V MAX
Vout
1k LOAD
Q3

1k
–5V (b)
(c)
Figure 6.50. TTL Circuit for Quadrant II and III TRIAC
Operation Requiring Negative VGT, (b) Schematic
Figure 6.49. Totem-Pole Output Circuit TTL Logic, Illustrates TRIAC Turn-On Condition,
Together with Voltage and Current Waveforms, Vout = Logical “0”
(b) Equivalent Circuit for Triggering TRIAC with a Positive
Voltage — TRIAC-On Condition, (c) TRIAC-Off Condition

Motorola Thyristor Device Data Theory and Applications

1.6–27
 If a logical “1” level must be maintained at the TTL output (2.4
V min.), the entire circuit of Figure 6.51 should be used.
VCC VCC For direct drive (logical “0”) quadrants II and III triggering,
the open collector, negative supplied ( – 5 V) TTL circuit of
Figure 6.53 can be used. Resistor R1 can have a value of
270 Ω, as in Figure 6.50. Resistor R2 ensures that the TRIAC
LOAD R1
gate is referenced to MT1 when the TTL gate goes high (off),
thus preventing unwanted turn-on. An R2 value of about 1 k
MT2 60 Hz should be adequate for sensitive gate TRIACs and still draw
R1 LINE Vout = 2.4 V
minimal current.
Vout R2 VCC
R2
MT1
LOGIC CIRCUIT
G=1V
1.4 k
(a) (b)
Figure 6.51. Practical Direct-Coupled TTL TRIAC Circuit, TTL
GATE Vout
(b) Equivalent Circuit Used for Calculation of Resistor
Values Q1
For a supply voltage of 5 V and a maximum sinking current
of 16 mA 1k
R1 q VCCń16 mA q 5ń0.016 q 312 W
(a)
Thus, 330 Ω, 1/4 W resistor may be used. Assuming R1 to be
330 Ω and a thyristor gate on voltage (VGT) of 1 V, the equiva-
lent circuit of Figure 6.50(b) exists during the logical “1” out- 5V
put level. Since the logical “1” level must be maintaned at 2.4
volts, the voltage drop across R2 must be 1.4 V. Therefore,
+ 1.4ńIR + 1.4ńVR ńR + 1.4ń(2.6ń3.30) ` 175 W
LOAD
R2
1 2
60 Hz
A 180 Ω resistor may be used for R2. If the VGT is less than MT2
LINE
R1
1 volt, R2 may need to be larger.
The MAC97A and 2N6071A TRIACs are compatible Vout G
devices for this circuit arrangement, since they are guaran-
teed to be triggered on by 5 mA, whereas the current through MT1
the circuit of Figure 6.51(b) is approximately 8 mA, (V
R R 1).
1
ń LOGIC CIRCUIT

When the TRIAC is to be turned on by a negative gate

voltage, as in Figure 6.50(b), the purpose of the limiting (b)
resistor R(Iim) is to hold the current through transistor Q3 to
Figure 6.52. Output Section of Open-Collector TTL,
16 mA. With a 5 V supply, a TRIAC VGT of 1 V and a
(b) For Current Sourcing, A Pull-up Resistor, R1,
maximum sink current of 16 mA
Must Be Added
R (lim) + (VCC–VGT)ńIsink + (5–1)(0.016q250 W
In practice, a 270 Ω, 1/4 W resistor may be used. G MT1

OPEN COLLECTOR TTL CIRCUIT

The output section of an open-collector TTL gate is shown R2
in Figure 6.52(a). MT2
60 Hz
A typical logic gate of this kind is the 5401 type Q2-input LINE
NAND gate circuit. This logic gate also has a maximum sink R1
current of 16 mA (VOL = 0.4 V max.) because of the Q1 (sat)
limitations. If this logic gate is to source any current, a LOGIC CIRCUIT LOAD
pull-up-collector resistor, R1 (6.52b) is needed. When this
TTL gate is used to trigger a thyristor, R1 should be chosen to –5V
supply the maximum trigger current available from the TTL
[
circuit ( 16 mA, in this case). The value of R1 is calculated Figure 6.53. Negative-Supplied ( –5 V) TTL Gate
in the same way and for the same reasons as in Figure 6.51. Permits TRIAC Operation in Quadrants II and III

Theory and Applications Motorola Thyristor Device Data

1.6–28
 different supply, if required. The collector-resistor, R4, is
simply
VCC R4 + (VCC * VCE(sat) * VGT(typ))ńIGT
+ (5 * 1 * 0.9)ń100 mA + 40 W
A 39 ohm, 1 W resistor is then chosen, since its actual
LOAD dissipation is about 0.4 W.
If the “logic 1” output level is not important, then the base
R1 R4 limiting resistor R2 is required, and the pull-up resistor R1 is
MT2 60 Hz not. Since the collector resistor of the TTL upper totem-pole
R2 LINE transistor, Q2, is about 100 Ω, this resistor plus R2 should
Q1 limit the base current to 5 mA.
Thus R2 calculates to
+ [(VCC * VBE * VGT)ń5 mA] * 100 W
LOGIC GATE G MT1
R3 R5 R2
+ [(5 * 0.7 * 0.9)ń0.005] 100 W
[ 560 W (specified)
Figure 6.54. Series Switch, High Output (Logic “1”)
Circuits utilizing Schottky TTL are generally designed in When the TTL output is low, the lower transistor of the
the same way as TTL circuits, although the current source/ totem-pole, Q3, is a clamp, through the 560 Ω resistor, across
sink capabilities may be slightly different. the 2N4401; and, since the 560 Ω resistor is relatively low, no
leakage-current shunting resistor, R3, is required.
TRIGGERING THYRISTORS FROM LOGIC GATES In a similar manner, if the TTL output must remain at “logic
USING INTERFACE TRANSISTORS 1” level, the resistor R1 can be calculated as described earlier
For applications requiring thyristors that demand more (R3 may or may not be required).
gate current than a direct-coupled logic circuit can supply, an For low-logic activation (logic “0”), the circuit of Figure 6.55
interface device is needed. This device can be a small-signal can be used. In this example, the PNP-interface transistor
transistor or an opto coupler. 2N4403, when turned on, will supply positive-gate current to
The transistor circuits can take several different configura- the thyristor. To ensure that the high logic level will keep the
tions, depending on whether a series or shunt switch design thyristor off, the logic gate and the transistor emitter must be
is chosen, and whether gate-current sourcing (quadrants I supplied with the same power supply. The base resistors, as
and IV) or sinking (quadrants II and III) is selected. An in the previous example, are dictated by the output character-
example of a series switch, high output (logic 1) activation, is istics of the logic family used. Thus if a TTL gate circuit is
shown in Figure 6.54. Any logic family can be used as long used, it must be able to sink the base current of the PNP
as the output characteristics are known. The NPN interface transistor (IOL(MAX) = 16 mA).
transistor, Q1, is configured in the common-emitter mode — When thyristor operation in quadrants II and III is desired,
the simplest approach — with the emitter connected directly the circuits of Figures 6.56 and 6.57 can be used; Figure 6.56
to the gate of the thyristor. is for high logic output activation and Figure 6.57 is for low.
Depending on the logic family used, resistor R1 (pull-up Both circuits are similar to those on Figures 6.54 and 6.55,
resistor) and R3 (base-emitter leakage resistor) may or may but with the transistor polarity and power supplies reversed.
not be required. If, for example, the logic is a typical TTL Figure 6.56 sinks current from the thyristor gate through a
+5V
totem-pole output gate that must supply 5 mA to the base of
the NPN transistor and still maintain a “high” (2.4 V) logic
output, then R1 and R2 are required. If the “high” logic level is
not required, then the TTL circuit can directly source the base LOAD
current, limited by resistor R2.
R2
To illustrate this circuit, consider the case where the MT2
selected TRIAC requires a positive-gate current of 100 mA. 60 Hz
The interface transistor, a popular 2N4401, has a specified R1 LINE
minimum hFE (at a collector current of 150 mA) of 100. To Q1 R3
ensure that this transistor is driven hard into saturation, under LOGIC GATE G MT1
“worse case” (low temperature) conditions, a forced hFE of 20
R4
is chosen — thus, 5 mA of base current. For this example,
the collector supply is chosen to be the same as the logic
supply (+5 V); but for the circuit configuration, it could be a
Figure 6.55. Low-Logic Activation with
Interface Transistor

Motorola Thyristor Device Data Theory and Applications

1.6–29
 R1 R5 R2 R4
MT1 MT1
R4 G G
R2 R1
Q1

LOGIC GATE 60 Hz
LOGIC GATE 60 Hz
MT2 LINE MT2 LINE
R3
R3
LOAD LOAD

– VEE – VEE

Figure 6.56. High-Logic Output Activation Figure 6.57. Low-Logic Output Activation
switched NPN transistor whose emitter is referenced to a OPTICAL ISOLATORS/COUPLERS
negative supply. The logic circuit must also be referenced to
An Optoelectronic isolator combines a light-emitting device
this negative supply to ensure that transistor Q1 is turned off
and a photo detector in the same opaque package that
when required; thus, for TTL gates, VEE would be –5 V.
provides ambient light protection. Since there is no electrical
In Figure 6.57, the logic-high bus, which is now ground, is
connection between input and output, and the emitter and
the common ground for both the logic, and the thyristor and
detector cannot reverse their roles, a signal can pass through
the load. As in the first example (Figure 6.54), the negative
the coupler in one direction only.
supply for the logic circuit (–VEE) and the collector supply for
Since the opto-coupler provides input circuitry protection
the PNP transistor need not be the same supply. If, for
and isolation from output-circuit conditions, ground-loop
power-supply current limitations, the collector supply is
prevention, dc level shifting, and logic control of high voltage
chosen to be another supply (–VCC), it must be within the
power circuitry are typical areas where opto-couplers are
VCEO ratings of the PNP transistor. Also, the power dissipa-
useful.
tion of collector resistor, R3, is a function of –VCC — the lower
Figure 6.60 shows a photo-TRIAC used as a driver for a
–VCC, the lower the power rating.
higher-power TRIAC. The photo-TRIAC is light sensitive and
The four examples shown use gate-series switching to
is turned on by a certain specified light density (H), which is a
activate the thyristor and load (when the interface transistor is
function of the LED current. With dark conditions (LED
off, the load is off). Shunt-switching can also be used if the
current = 0) the photo-TRIAC is not turned on, so that the
converse is required, as shown in Figures 6.58 and 6.59. In
only output current from the coupler is leakage current, called
Figure 6.58, when the logic output is high, NPN transistor,
peak-blocking current (IDRM). The coupler is bilateral and
Q1, is turned on, thus clamping the gate of the thyristor off. To
designed to switch ac signals.
activate the load, the logic output goes low, turning off Q1 and
The photo-TRIAC output current capability is, typically, 100
allowing positive gate current, as set by resistor R3, to turn on
mA, continuous, or 1 A peak.
the thyristor.
Any Motorola TRIAC can be used in the circuit of Figure
In a similar manner, quadrant’s II and III operation is
6.60 by using Table 6.8. The value of R is based on the
derived from the shunt interface circuit of Figure 6.59.

+5V

MT1
R2 G

R3 LOAD
R1
60 Hz
MT2 LINE
R1 MT2 60 Hz LOGIC GATE
Q1 LINE
R3 LOAD
LOGIC GATE G
R2
MT1
– VEE

Figure 6.59. Shunt-Interface Circuit

Figure 6.58. Shunt-Interface Circuit (High-Logic Output)
(Quadrants I and III Operation)

Theory and Applications Motorola Thyristor Device Data

1.6–30
 R When switching ac loads from microcomputers, it is
I
good practice to optically isolate them from unexpected
H MT2 load or ac line phenomena to protect the computer system
from possible damage. In addition, optical isolation will
LED
PHOTO make UL recognition possible.
TRIAC 60 Hz A typical TTL-compatible microcontroller, such as the
G
MT1 LINE MC3870P offers the following specifications:
+ 300 mA (VOH + 2.4 V)
OPTO COUPLER
I OH
LOAD I OL + 1.8 mA (V OL + 0.4 V)
V CC + 5 V

Since this is not adequate for driving the optocoupler

Figure 6.60. Optically-Coupled TRIAC Driver is Used to directly (10 mA for the MOC3011), an interface transistor
Drive a Higher-Power TRIAC is necessary.
The circuit of Figure 6.61 may be used for thyristor
photo-TRIAC’s current-handling capability. For example, triggering from the 3870 logical “1.”
when the MOC3011 operates with a 120 V line voltage The interface transistor, again, can be the 2N4401. With 10
(approximately 175 V peak), a peak IGT current of 175 V/180 mA of collector current (for the MOC3011) and a base current
ohm (approximately 1 A) flows when the line voltage is at its of 0.75 mA, the VCE(sat) will be approximately 0.1 V.
maximum. If less than 1 A of IGT is needed, R can be R1 can be calculated as in a previous example.
increased. Circuit operation is as follows: Specifically:
1.8 mA (maximum I OL for the 3870)
Table 6.8. Specifications for Typical Optically Coupled
u ń
5 V R 1; R 1 u2.77 k
R 1 can be 3 k, 1ń4 W
TRIAC Drivers

Peak
Device Maximum Required LED With a base current of 0.75 mA, R1 will drop (0.75 mA) (3 k)
Blocking R(Ohms)
Type Trigger Current (mA)
Voltage or 2.25 V. This causes a VOH of 2.75 V, which is within the
logical “1” range.
MOC3009 30 250 180
MOC3011
MOC3011
15
10
250
250
180
180
R2 + [2.75 V–VBE(on)]ńIB + (2.75–0.75)ń0.75 + 2.66 k
R 2 can be a 2.7 k, 1ń4 W resistor.
MOC3020 30 400 260
.
MOC3021 15 400 360
MOC3030 30 250 51 R 3 must limit IC to 10 mA :

+ [5 V–VCE(sat) – VF(diode)ń10 mA]

MOC3031 15 250 51
R3

When an op-amp, logic gate, transistor or any other + (5–0.1–1.2)ń10 mA + 370 W

appropriate device turns on the LED, the emitted light triggers Since R3 is relatively small, no base-emitter leakage
the photo-TRIAC. Since, at this time, the main TRIAC is not resistor is required.
on, MT2-to-gate is an open circuit. The 60 Hz line can now Figure 6.62 shows logical “0” activation. Resistor values
cause a current flow via R, the photo-TRIAC, Gate-MT1 are calculated in a similar way.
junction and load. This Gate-MT1 current triggers the main
TRIAC, which then shorts and turns off the photo-TRIAC. The +5V
process repeats itself every half cycle until the LED is turned
off. R3
Triggering the main TRIAC is thus accomplished by turning
on the LED with the required LED-trigger current indicated in R
Table 6.7.
MT2
R1
MICROPROCESSORS
60 Hz
Microprocessor systems are also capable of controlling ac LINE
power loads when interfaced with thyristors. Commonly, the G MT1
output of the MPU drives a PIA (peripheral interface adaptor)
which then drives the next stage. The PIA Output Port R2
Q1
generally has a TTL compatible output with significantly less LOAD
current source and sink capability than standard TTL. (MPUs MC3870
and PIAs are sometimes constructed together on the same
chip and called microcontrollers.)
Figure 6.61. Logical “1” Activation from MC3870P
Microcomputer

Motorola Thyristor Device Data Theory and Applications

1.6–31
 resistance (rDS(on)), the drain-to-source voltage of the N-
+5V channel device (VDS) is very low (essentially zero) because
of the very low drain current (VDSS) flowing through the
device. Conversely, when the input goes low (zero), the
R1
R2 P-channel device is turned fully on, the N-channel device is
Q1 off and the output voltage will be very near VDD.
MC3870P When interfacing with transistors or thyristors, the CMOS
R3 Gate is current-limited mainly by its relatively high on
resistance, the dc resistance between drain and source,
R when the device is turned on.
The equivalent circuits for sourcing and sinking current into
MT2 an external load is shown in Figures 6.63(b) and 6.63(c).
Normally, when interfacing CMOS to CMOS, the logic
60 Hz outputs will be very near their absolute maximum states (VDD
LINE or 0 V) because of the extremely small load currents. With
G
MT1 other types of loads (e.g. TRIACs), the current, and the
resulting output voltage, is dictated by the simple voltage
LOAD
divider of rDS(on) and the load resistor RL, where rDS(on) is the
total series and/or parallel resistance of the devices compris-
ing the NOR and NAND function.
Interfacing CMOS gates with thyristors requires a knowl-
edge of the on resistance of the gate in the source and sink
Figure 6.62. Logical “0” Activation conditions. The on-resistance of CMOS devices is not
normally specified on data sheets.
THE CMOS INTERFACE It can easily be calculated, however, from the output drive
currents, which are specified. The drive (source/sink) cur-
Another popular logic family, CMOS, can also be used to rents of typical CMOS gates at various supply voltages are
drive thyristors. shown in Table 6.9. From this information, the on resistance
As shown in Figure 6.63(a), the output stage of a typical for worst case design is calculated as follows:
CMOS Gate consists of a P-channel MOS device connected For the source condition
in series with an N-channel device (drain-to-drain), with the
gates tied together and driven from a common input signal. rDS(on)(MAX) + (VDD * VOH)ńIOH(MIN)
When the input signal goes high, logical 1, the P-channel
device is essentially off and conducts only leakage current Similarly, for the sink current condition
(IDSS), on the order of pico-amps. The N-channel unit is
forward-biased and, although it has a relatively high on
rDS(on)(MAX) + VOLńIOL(MIN)
Values of rDS(on) for the various condition shown in Table
6.9 are tabulated in Table 6.10.

VDD VDD VDD

Table 6.9. CMOS Characteristics
S
P-CHANNEL Specified source/sink currents to maintain logical “1” and
RL logical “0” levels for various power-supply (VDD) voltages.
P-CHANNEL rDS(on)
The IOH and IOL values are used to calculate the “on”
D Vout Vout
Vin Vout
resistance of the CMOS output.
D
N-CHANNEL CMOS AL CMOSCL/CP
N-CHANNEL Series Series
RL Output Drive Current mA, dc mA, dc
rDS(on)
S Min Typ Min Typ
(a) (b) (c) I(source) – IOH
VDD = 5 V; VOH = 2.5 V – 0.5 – 1.7 – 0.2 – 1.7
VDD = 10 V; VOH = 9.5 V – 0.5 – 0.9 – 0.2 – 0.9
Figure 6.63. Output Section of a Typical CMOS Gate, VDD = 15 V; VOH = 13.5 V – 3.5 – 3.5
(b) Equivalent Current-Sourcing Circuit is Activated
I(sink) – IOL
when Vin goes Low, Turning the P-Channel Device
VDD = 5 V; VOL= 0.4 V 0.4 7.8 0.2 7.8
Fully On, (c) Equivalent Current Sinking Circuit is
VDD = 10 V; VOL = 0.5 V 0.9 2 0.5 2
Activated when the Input Goes High and Turns the VDD = 15 V; VOL = 1.5 V 7.8 7.8
N-Channel Device On

Theory and Applications Motorola Thyristor Device Data

1.6–32
Table 6.10. Calculated CMOS On Resistance Values For DC MOTOR CONTROL WITH THYRISTORS
Current Sourcing and Sinking at Various VDD Options In order to control the speed of a dc series field motor at
different required torque levels, it is necessary to adjust the
Output Resistance, rDS(on)
Ohms
voltage applied to the motor. For any particular applied
p g Conditions
Operating voltage the motor speed is determined solely by the torque
Typical Maximum requirements and top speed is reached under minimum
Source Condition torque conditions. When a series motor is used as a traction
VDD = 5V 1.7 k 12.5 k drive for vehicles, it is desirable to control the voltage to the
10 V 500 2.5 k motor to fit the various torque requirements of grades, speed
15 V 430 — and load. The common method of varying the speed of the
Sink Condition motor is by inserting resistance in series with the motor to
VDD = 5V 500 2k reduce the supplied voltage. This type of motor speed control
10 V 420 1k is very inefficient due to the I2R loss, especially under high
15 V 190 — current and torque conditions.
A much more efficient method of controlling the voltage
applied to the motor is the pulse width modulation method
It is apparent from this table that the on resistance shown in Figure 6.64. In this method, a variable width pulse
decreases with increasing supply voltage. of voltage is applied to the motor at the same rate to
Although the minimum currents are now shown on the data proportionally vary the average voltage applied to the motor.
sheet for the 15 V case, the maximum on resistance can be A diode is placed in parallel with the inductive motor path to
no greater than the 10 V example and, therefore, can be provide a circuit for the inductive motor current and prevent
assumed for worst case approximation to be 1 and 2.5 abrupt motor current change. Abrupt current changes would
kohms for sink-and-source current cases, respectively. cause high induced voltage across the switching device.
The sourcing on resistance is greater than the sinking The circulating current through the diode decreases only in
case because the difference in carrier mobilities of the two response to motor and diode loss. With reference to Figure
channel types. 6.64, it can be seen that the circulating diode current causes
Since rDS(on) for both source and sink conditions varies more average current to flow through the motor than is taken
with supply voltage (VDD), there are certain drive limitations. from the battery. However, the power taken from the battery is
The relative high rDS(on) of the P-channel transistor could approximately equal to the power delivered to the motor,
possibly limit the direct thyristor drive capability; and, in a like indicating that energy is stored in the motor inductance at the
manner, the N-channel rDS(on) might limit its clamping battery voltage level and is delivered to the motor at the
capability. With a 10 or 15 V supply, the device may be approximate current level when the battery is disconnected.
capable of supplying more than 10 mA, but should be limited To provide smooth and quiet motor operation, the current
to that current, with an external limiting resistor, to avoid variations through the motor should be kept to a minimum
exceeding the reliable limits of the unit metalization. during the switching cycle. There are limitations on the
amount of energy that can be stored in the motor inductance,
which, in turn, limits the power delivered to the motor during
APPLIED the off time; thus the off time must be short. To operate the
BATTERY motor at low speeds, the on time must be approximately 10
+ AVERAGE percent of the off time and therefore, a rapid switching rate is
VM VOLTAGE
– required that is generally beyond the capabilities of mechani-
cal switches. Practical solutions can be found by the use of
BATTERY semiconductor devices for fast, reliable and efficient switch-
LM CURRENT AVERAGE
+ ing operations.
SCR DC MOTOR CONTROL
– BATTERY AVERAGE
DIODE SCRs offer several advantages over power transistors as
RM CURRENT semiconductor switches. They require less driver power, are
less susceptible to damage by overload currents and can
AVERAGE
MOTOR handle more voltage and current. Their disadvantages are
VM = BACK EMF
OF MOTOR CURRENT that they have a higher power dissipation due to higher
LM = MOTOR voltage drops and the difficulty in commutating to the off
INDUCTANCE condition.
RM = MOTOR
RESISTANCE

Figure 6.64. Basic Pulse Width Modulated

Motor Speed Control

Motorola Thyristor Device Data Theory and Applications

1.6–33
 R1

D2
Cc

D1
SCR1 SCR2
TRIGGER
CIRCUIT

Figure 6.65. Speed Control with Resistive Charging

The SCR must be turned off by either interrupting the
current through the anode-cathode circuit or by forcing
current through the SCR in the reverse direction so that the
TRIGGER
net flow of forward current is below the holding current long SCR1 SCR2
CIRCUIT
enough for the SCR to recover blocking ability. Commutation
of the SCR in high current motor control circuits is generally
accomplished by discharging a capacitor through the SCR in
the reverse direction. The value of this capacitor is deter-
mined approximately from the following equation: Figure 6.67. SCR Motor Control with
Transformer Charging

Cc + TVq cIA If the resonant charging commutating circuitry of Figure

6.66 is used, the capacitor is reduced to approximately 55 µF.
Where: In this circuit, SCR3 is gated on at the same time as SCR1
Cc = value of necessary commutating capacitance and allows the resonant charging of Cc through Lc to twice
Tq = turn-off time of the SCR the supply voltage. SCR3 is then turned off by the reversal of
IA = value of anode current before commutation voltage in the resonant circuit before SCR2 is gated on. It is
Vc = voltage of Cc before commutation apparent that there is very little power loss in the charge
circuit depending upon the voltage drop across SCR3 and
This relationship shows that to reduce the size of Cc, the
the resistance in Lc.
capacitor should be charged to as high a voltage as possible
If the commutating capacitor is to be reduced further, it is
and the SCR should be selected with as low a turn-off time as
necessary to use a transformer to charge the capacitor to
possible.
more than twice the supply voltage. This type of circuit is
If a 20 microsecond turn-off time SCR is commutated by a
illustrated by the transformer charge circuit shown in Figure
capacitor charged to 36 volts, it would take over 110 µF to
6.67. In this circuit the capacitor can be charged to several
turn off 200 amperes in the RC commutating circuit of Figure
times the supply voltage by transformer action through diode
6.65. If a 50 cycle switching frequency is desired, the value of
D1 before commutating SCR1. The disadvantage of this
R1 would be approximately 5 ohms to allow charging time
circuit is in the high motor current that flows through the
with an on duty cycle of 10 percent. The value of this resistor
transformer primary winding.
would give approximately 260 watts dissipation in the
charging circuit with 90 percent off duty cycle.
HEAVY DUTY MOTOR CONTROL WITH SCRs
Another advantage of SCRs is their high surge current
capabilities, demonstrated in the motor drive portion of the
golf cart controller shown in Figure 6.68. Germanium power
Lc transistors were used because of the low saturation voltages
and resulting low static power loss. However, since switching
SCR3 speeds are slow and leakage currents are high, additional
circuit techniques are required to ensure reliable operation:
Cc 1. The faster turn-on time of the SCR (Q9) over that of the
germanium transistors shapes the turn-on load line.
SCR1 SCR2 2. The parallelled output transistors (Q3-Q8) require a 6
TRIGGER V reverse bias.
CIRCUIT
3. The driver transistor Q2 obtains reverse bias by
means of diode D4.
Figure 6.66. Speed Control with Inductive Charging To obtain the 6 V bias, the 36 V string of 6 V batteries are

Theory and Applications Motorola Thyristor Device Data

1.6–34
tapped, as shown in the schematic. Thus, the motor is output transistors and the positive going collector output
powered from 30 V and the collector supply for Q2 is 24 V, pulse supplying the SCR gate trigger coupled through
minimizing the dissipation in colllector load resistor R1. transformer T1.
Total switching loss in switchmode applications is the Since the faster turn-on SCR is triggered on first, it will
result of the static (on-state) loss, dynamic (switching) loss carry the high, initial turn-on motor current. Then the slower
and leakage current (off-state) loss. The low saturation turn-on germanium transistors will conduct clamping off the
voltage of germanium transistors produces low static loss. SCR, and carry the full motor current. For the illustrated 2HP
However, switching speeds of the germanium transistors are motor and semiconductors, a peak exponentially rising and
low and leakage currents are high. Loss due to leakage falling SCR current pulse of 120 A lasting for about 60 µs was
current can be reduced with off bias, and load line shaping measured. This current is well within the rating of the SCR.
can minimize switching loss. The turn-off switching loss was Thus, the high turn-on stresses are removed from the
reduced with a standard snubber network (D5, C1, R2) see transistors providing a much more reliable and efficient motor
Figure 6.68. controller while using only a few additional components.
Turn-on loss was uniquely and substantially reduced by
using a parallel connected SCR (across the germanium
transistors) the MCR265-4 (55 A rms, 550 A surge). This DIRECTION AND SPEED CONTROL FOR MOTORS
faster switching device diverts the initial turn-on motor load For a shunt motor, a constant voltage should be applied to
current from the germanium output transistors, reducing both the shunt field to maintain constant field flux so that the
system turn-on loss and transistor SOA stress. armature reaction has negligible effect. When constant voltage
The main point of interest is the power switching portion of is applied to the shunt field, the speed is a direct function of
the PWM motor controller. Most of the readily available PWM the armature voltage and the armature current. If the field is
ICs can be used (MC3420, MC34060, TL494, SG1525A, weak, then the armature reaction may counterbalance the
UA78S40, etc.), as they can source at least a 10 mA, +15 V voltage drop due to the brushes, windings and armature
pulse for driving the following power MOSFET. resistances, with the net result of a rising speed-load
Due to the extremely high input impedance of the power characteristic.
MOSFET, the PWM output can be directly connected to the The speed of a shunt-wound motor can be controlled with
FET gate, requiring no active interface circuitry. The positive a variable resistance in series with the field or the armature.
going output of the PWM is power gained and inverted by the Varying the field current for small motor provides a wide
TMOS FET Q1 to supply the negative going base drive to range of speeds with good speed regulation. However, if the
PNP transistor Q2. Diode D1 provides off-bias to this field becomes extremely weak, a rising speed-load charac-
paraphase amplifier, the negative going pulse from the teristic results. This method cannot provide control below the
emitter furnishing base drive to the six parallel connected

+ 36 V
OFF BIAS
6
25 W 700 µF
Q3 C1 + 30 V
Q8 Q9
MCR 1
1N1183 (6) MATCHED 265-4 R2
27 D4 D5
+ 24 V
+ 15 V Q2 1N914 1N1183
20 1 µF D2
D1
+ 10 µF 50 W 330 470 + 15 V
R1 + 18 V
25 V 0.6 (2)
200 W
0.01 µF D3
1N4744
1N914
FORWARD REVERSE
PWM
1k UTC
10 k H51 dc
MOTOR
Q1 2 HP

MTP12N10E
SENSE 0.001
CURRENT
TO PWM

Figure 6.68. PWM DC Motor Controller Using SCR

Turn-On Feature

Motorola Thyristor Device Data Theory and Applications

1.6–35
design motor speed. Varying the resistance in series with the a no-load condition unless precaution is are taken to limit the
armature results in speeds less than the designed motor maximum speed.
speed; however, this method yields poor speed regulation,
especially at low speed settings. This method of control also SERIES-WOUND MOTORS
increases power dissipation and reduces efficiency and the The circuit shown in Figure 6.69 can be used to control the
torque since the maximum armature current is reduced. speed and direction of rotation of a series-wound dc motor.
Neither type of resistive speed control is very satisfactory. Silicon controlled rectifiers Q1- Q4, which are connected in a
Thyristor drive controls, on the other hand, provide continu- bridge arrangement, are triggered in diagonal pairs. Which
ous control through the range of speed desired, do not have pair is turned on is controlled by switch S1 since it connects
the power losses inherent in resistive circuits, and do not either coupling transformer T1 or coupling transformer T2 to
compromise the torque characteristics of motors. a pulsing circuit. The current in the field can be reversed by
Although a series-wound motor can be used with either dc selecting either SCRs Q2 and Q3 for conduction, or SCRs
or ac excitation, dc operation provides superior performance. Q1 and Q4 for conduction. Since the armature current is
A universal motor is a small series-wound motor designed to always in the same direction, the field current reverses in
operate from either a dc or an ac supply of the same voltage. relation to the armature current, thus reversing the direction
In the small motors used as universal motors, the winding of rotation of the motor.
inductance is not large enough to produce sufficient current A pulse circuit is used to drive the SCRs through either
through transformer action to create excessive commutation transformer T1 or T2. The pulse required to fire the SCR is
problems. Also, high-resistance brushes are used to aid obtained from the energy stored in capacitor C1. This
commutation. The characteristics of a universal motor capacitor charges to the breakdown voltage of zener diode
operated from alternating current closely approximate those D5 through potentiometer R1 and resistor R2. As the
obtained for a dc power source up to full load; however, capacitor voltage exceeds the zener voltage, the zener
above full load the ac and dc characteristics differ. For a conducts, delivering current to the gate of SCR Q5. This
series motor that was not designed as a universal motor, the turns Q5 on, which discharges C1 through either T1 or T2
speed-torque characteristic with ac rather than dc is not as depending on the position of S1. This creates the desired
good as that for the universal motor. At eight loads, the speed triggering pulse. Once Q5 is on, it remains on for the duration
for ac operation may be greater than for dc since the effective of the half cycle. This clamps the voltage across C1 to the
ac field strength is smaller than that obtained on direct forward voltage drop of Q5. When the supply voltage drops to
current. At any rate, a series motor should not be operated in zero, Q5 turns off, permitting C1 to begin charging when the
supply voltage begins to increase.

MCR12D MCR12D
T1 T2
Q1 Q2
(4) 1N4722
D2 OR
D1
AC MDA2503
MCR12D FIELD MCR12D
LINE
D3 D4 Q3 Q4
R1
20 k
5W
T2 T1
R2, 4.7 k
5W 5 µF
75 V
+ ARMATURE

Q5 D5 C1
2N5062 1N5262 S1
T1 (2) T2
R3
1k SPRAGUE
11Z13

Figure 6.69. Direction and Speed Control for Series-Wound or Universal Motor

Theory and Applications Motorola Thyristor Device Data

1.6–36
 D1 D2
ac (4) 1N4722
LINE
D3 D4 Q3 Q1
R1
20 k
5W
FIELD T2 T1
R2, 4.7 k 5 µF ARMATURE
5W 75 V
+

Q5 D5 C1 Q4 Q2

2N5062 1N5262

R3 T1 T2 T1 T2
1k

T1 AND T2 ARE SPRAGUE 11Z13

Q1 THRU Q4 — MCR12D

Figure 6.70. Direction and Speed Control for Shunt-Wound Motor

The speed of the motor can be controlled by potentiome- vided the motor current requirements are within the semi-
ter R1. The larger the resistance in the circuit, the longer conductor ratings. Higher current devices will permit control
required to charge C1 to the breakdown voltage of zener of even larger motors, but the operation of the motor under
D5. This determines the conduction angle of either Q1 and worst case must not cause anode currents to exceed the
Q4, or Q2 and Q3, thus setting the average motor voltage ratings of the semiconductor.
and thereby the speed.

SHUNT-WOUND MOTORS PUT APPLICATIONS

If a shunt-wound motor is to be used, then the circuit in PUTs are negative resistance devices and are often used
Figure 6.70 is required. This circuit operates like the one in relaxation oscillator applications and as triggers for
shown in Figure 6.69. The only differences are that the field is controlling thyristors. Due to their low leakage current, they
placed across the rectified supply and the armature is placed are useful for high-impedance circuits such as long-duration
in the SCR bridge. Thus the field current is unidirectional but timers and comparators.
armature current is reversible; consequently the motor’s TYPICAL CIRCUITS
direction of rotation is reversible. Potentiometer R1 controls
The following circuits show a few of the many ways in
the speed as explained previously.
which the PUT can be used. The circuits are not optimized
even though performance data is shown.
RESULTS
In several of the circuit examples, the versatility of the PUT
Excellent results were obtained when these circuits were
has been hidden in the design. By this it is meant that in
used to control 1/15 hp, 115 V, 5,000 r/min motors. This
designing the circuit, the circuit designer was able to select a
circuit will control larger, fractional-horsepower motors pro-
particular intrinsic standoff ratio or he could select a particular
+3V
RG (gate resistance) that would provide a maximum or
R1 R3 R6 minimum valley and peak current. This makes the PUT very
100 k 1k 51 k C4 versatile and very easy to design with.
Q1 4 µF GE NO. 14
2N6027 + – LOW VOLTAGE LAMP FLASHER
R4 Q2 (SEE TEXT)
The PUT operates very well at low supply voltages
2k C2 2N5060 because of its low on-state voltage drop.
Q3 A circuit using the PUT in a low voltage application is
C1 0.01 µF 2N5060
10 µF 0.01 µF shown in Figure 6.71 where a supply voltage of 3 volts is
used. The circuit is a low voltage lamp flasher composed of a
R2 R5 R7
C3 relaxation oscillator formed by Q1 and an SCR flip flop
910 1k 1k
formed by Q2 and Q3.

Figure 6.71. Low Voltage Lamp Flasher

Motorola Thyristor Device Data Theory and Applications

1.6–37
 With the supply voltage applied to the circuit, the timing
capacitor C1 charges to the firing point of the PUT, 2 volts
R1 R3
10 k 510 k
plus a diode drop. The output of the PUT is coupled through
two 0.01 µF capacitors to the gate of Q2 and Q3. To clarify
Q1 operation, assume that Q3 is on and capacitor C4 is charged
+ MPS6516 plus to minus as shown in the figure. The next pulse from the
PUT oscillator turns Q2 on. This places the voltage on C4
RAMP OUT
40 V – across Q3 which momentarily reverse biases Q3. This
reverse voltage turns Q3 off. After discharging, C4 then
R2 R5 charges with its polarity reversed to that shown. The next
2N6027 100 k
20 k + pulse from Q1 turns Q3 on and Q2 off. Note that C4 is a
C1
R4 5 to 20 V non-polarized capacitor.
100 For the component values shown, the lamp is on for about
1/2 second and off the same amount of time.

Figure 6.72. (a). Voltage Controlled Ramp Generator

(VCRG) VOLTAGE CONTROLLED RAMP GENERATOR
The PUT provides a simple approach to a voltage
20 controlled ramp generator, VCRG, as shown in Figure
6.72(a). The current source formed by Q1 in conjuction with
19
capacitor C1 set the duration time of the ramp. As the positive
18 dc voltage at the gate is changed, the peak point firing
17 voltage of the PUT is changed which changes the duration
C = 0.0047 µF
16 time, i.e., increasing the supply voltage increases the peak
C = 0.01 µF point firing voltage causing the duration time to increase.
15 Figure 6.72(b) shows a plot of voltage-versus-ramp
14 duration time for a 0.0047 µF and a 0.01 µF timing capacitor.
Vin (VOLTS)

13 The figure indicates that it is possible to have a change in

frequency of 3 ms and 5.4 ms for the 0.0047 µF and the 0.01
12
µF capacitor respectively as the control voltage is varied from
11 5 to 20 volts.
10
9
LOW FREQUENCY DIVIDER
8
The circuit shown in Figure 6.73 is a frequency divider with
7 the ratio of capacitors C1 and C2 determining division. With a
6 positive pulse applied to the base of Q1, assume that C1 =
5 C2 and that C1 and C2 are discharged. When Q1 turns off,
1 2 3 4 5 6 7 8 both C1 and C2 charge to 10 volts each through R3. On the
next pulse to the base of Q1, C1 is again discharged but C2
DURATION TIME (ms)

(b). Voltage versus Ramp Duration Time of VCRG

+ 20 Vdc
Table 6.11

R3 R5 8V C1 C2 Division
1k Q2 5.1 k
C1 1N4001 0.01 µF 0.01 µF 2
2N6027
0.01 µF 0.02 µF 3
R1 0.01 µF 0.03 µF 4
3V D2
3.9 k Q1 0.01 µF 0.04 µF 5
MPS6512 D1 0.01 µF 0.05 µF 6
C2 OUT 0.01 µF 0.06 µF 7
1N4001
R2 R4 R6 0.01 µF 0.07 µF 8
2.2 k 100 5.1 k 0.01 µF 0.08 µF 9
0.01 µF 0.09 µF 10
0.01 µF 0.1 µF 11

Figure 6.73. Low Frequency Divider

Theory and Applications Motorola Thyristor Device Data

1.6–38
 + 20 Vdc gate-to-source of the JFET. This turns the JFET off and
increases the charging time of C1. C1 should be a low
Q1
leakage capacitor such as a mylar type.
2N5457
The source resistor of the current source can be computed
R3

+ VP (1 * ǸIOńIDSS )
using the following equation:
R1 2M
22 M V GS

Q2 N R1 + VIGS
O
2N6028
where IO is the current out of the current source.
C1
10 µF MYLAR VP is the pinch off voltage,
OUTPUT VGS is the voltage gate-to-source and,
R2 R4
100 2M IDSS is the current, drain-to-source, with the gate
shorted to the source.
The time needed to charge C1 to the peak point firing
voltage of Q2 can be approximated by the following
Figure 6.74. 20-Minute, Long Duration Timer equation:

+ CDI V ,
remains charged to 10 volts. As Q1 turns off this time, C1 and
C2 again charge. This time C2 charges to the peak point t
firing voltage of the PUT causing it to fire. This discharges
capacitor C2 and allows capacitor C1 to charge to the line where t is time in seconds
voltage. As soon as C2 discharges and C1 charges, the PUT C is capacitance in µF,
turns off. The next cycle begins with another positive pulse ∆V is the change in voltage across capacitor C1,
on the base of Q1 which again discharges C1. and
The input and output frequency can be approximated by I is the constant current used to charge C1.
the equation Maximum time delay of the circuit is limited by the peak

f in
) C2) fout
[ (C1 C1
point firing current, lP, needed to fire Q2. For charging
currents below IP, there is not enough current available from
the current source to fire Q2, causing the circuit to lock up.
For a 10 kHz input frequency with an amplitude of 3 volts, Thus PUTs are attractive for long duration timing circuits
Table 6.11 shows the values for C1 and C2 needed to divide because of their low peak point current. This current
by 2 to 11. becomes very small when RG (the equivalent parallel
This division range can be changed by utilizing the resistance of R3 and R4) is made large. For example, the
programmable aspect of the PUT and changing the voltage 2N6028 has IP guaranteed to be less than 0.15 µA at RG = 1
on the gate by changing the ratio R6/(R6 + R5). Decreasing M Ohm as shown in Figure 6.74.
the ratio with a given C1 and C2 decreases the division range
and increasing the ratio increases the division range. PHASE CONTROL
The circuit works very well and is fairly insensitive to the Figure 6.75 shows a circuit using a PUT for phase control
amplitude, pulse width, rise and fall times of the incoming of an SCR. The relaxation oscillator formed by Q2 provides
pulses. conduction control of Q1 from 1 to 7.8 milliseconds or 21.6°
to 168.5°. This constitutes control of over 97% of the power
PUT LONG DURATION TIMER available to the load.
A long duration timer circuit that can provide a time delay of Only one SCR is needed to provide phase control of
up to 20 minutes is shown in Figure 6.74. The circuit is a both the positive and negative portion of the sine wave
standard relaxation oscillator with a FET current source in byputting the SCR across the bridge composed of diodes D1
which resistor R1 is used to provide reverse bias on the through D4.
R1

D3 15 k
D1 2 WATT R2 R3
250 k 1k
LOAD Q1 D5
100 Ω 2N6402 1N4114
20 V
C1 R4
Q2
D4 1k
115 V rms D2 0.1 µF 2N6027
60 Hz

Figure 6.75. SCR Phase Control

Motorola Thyristor Device Data Theory and Applications

1.6–39
 T1

115 V 14 V
rms rms
SCR
A

R1 R4
10 k 1k
2N6027 R2
+
50 k
12 V
PUT
–
C1
D1
0.1 µF T2 R3
1N5240
10 V 11Z12 47 k
1:1 B

DALE PT50

Figure 6.76. (a). 12-Volt Battery

Charger
BATTERY CHARGER USING A PUT 8
A short circuit proof battery charger is shown in Figure 6.76 SPECIFIC GRAVITY OF ELECTROLYTE versus TIME
which will provide an average charging current of about 8 1250 7
amperes to a 12 volt lead acid storage battery. The charger

CURRENT (AMPS)
circuit has an additional advantage in that it will not function SPECIFIC GRAVITY 6
nor will it be damaged by improperly connecting the battery to
1200 5
the circuit.
With 115 volts at the input, the circuit commences to 4
function when the battery is properly attached. The battery
provides the current to charge the timing capacitor C1 used 1150 CHARGING CURRENT versus TIME 3
in the PUT relaxation oscillator. When C1 charges to the
peak point voltage of the PUT, the PUT fires turning the SCR 2
on, which in turn applies charging current to the battery. As 0 1 2 3 4 5 6 7 8 9
the battery charges, the battery voltage increases slightly TIME (HR)
which increases the peak point voltage of the PUT. This
Figure 6.76 (b) Charging Characteristics
means that C1 has to charge to a slightly higher voltage to
of Battery Charger
fire the PUT. The voltage on C1 increases until the zener
voltage of D1 is reached which clamps the voltage on C1 and
With the input voltage applied, capacitor C1 charges until
thus prevents the PUT oscillator from oscillating and charg-
the firing point of Q3 is reached causing it to fire. This turns
ing ceases. The maximum battery voltage is set by poten-
Q5 on which allows current to flow through the load. As the
tiometer R2 which sets the peak point firing voltage of the
input voltage increases, the voltage across R10 increases
PUT.
which increases the firing point of Q3. This delays the firing of
In the circuit shown, the charging voltage can be set
Q3 because C1 now has to charge to a higher voltage before
from 10 V to 14 V, the lower limit being set by D1 and the
the peak-point voltage is reached. Thus the output voltage is
upper limit by T1. Lower charging voltages can be
held fairly constant by delaying the firing of Q5 as the input
obtained by reducing the reference voltage (reducing the
voltage increases. For a decrease in the input voltage, the
value of zener diode D1) and limiting the charging current
reverse occurs.
(using either a lower voltage transformer, T1, or adding
Another means of providing compensation for increased
resistance in series with the SCR).
input voltage is achieved by Q2 and the resistive divider
Resistor R4 is used to prevent the PUT from being
formed by R6 and R7. As input voltage increases, the voltage
destroyed if R2 were turned all the way up.
at the base of Q2 increases causing Q2 to turn on harder
Figure 6.76(b) shows a plot of the charging characteristics
which decreases the charging rate of C1 and further delays
of the battery charger.
the firing of Q5.
90 V rms VOLTAGE REGULATOR USING A PUT To prevent the circuit from latching up at the beginning of
The circuit of Figure 6.77 is an open loop rms voltage each charging cycle, a delay network consisting of Q1 and its
regulator that will provide 500 watts of power at 90 V rms associated circuitry is used to prevent the current source
with good regulation for an input voltage range of 110 – 130 from turning on until the trigger voltage has reached a
V rms. sufficiently high level. This is achieved in the following way:

Theory and Applications Motorola Thyristor Device Data

1.6–40
 LOAD R1 R6 R9
500 W 10 k 300 k 100 k
90 V ± 2 R2

1k
R3 Q1 Q3
110-130 V D1 2N3906 2N6027
rms 1k
R4 Q5
10 k Q2 MCR16M
2N3903
C1
0.1 µF
D2 100 V
R5
1N4747
6.8 k R7 R8 R10
20 V
4.7 k 10 k 6.8 k

Figure 6.77. (a). rms Voltage Regulator

100 7 These circuits indicate the uses for the SBS. In some

CONDUCTION ANGLE (ms)

applications the device switches on at VS while in others it is
OUTPUT VOLTAGE (V rms)

90 6 turned on by drawing a small current out of the gate lead.

80 5
LAMP DIMMER
70 4 Figure 6.78 is the schematic diagram of a low cost full
range lamp dimmer. Shunting the SBS with two 20 kΩ
CONDUCTION TIME 3 resistors minimizes the “flash-on” or hysteresis effect. VS of
60
OUTPUT VOLTAGE
the SBS is reduced to about 4 volts, and since this is below
50 2 the operating voltage of the internal zener diodes, the
80 90 100 110 120 130 140 150 160 170
temperature sensitivity of the device is increased.
INPUT VOLTAGE (V rms)
An improved full range power controller suitable for lamp
dimming and similar applications is shown in Figure 6.79.
(b). Output Voltage and Conduction Angle It operates from a 120 volt, 60 Hz ac source and can
versus Input Voltage control up to 1000 watts of power to incandescent bulbs. The
power to the bulbs is varied by controlling the conduction
Prior to the conduction of D2, the voltage on the base of Q1 angle of TRIAC Q1. Many circuits can be used for phase
is set by the voltage divider (R4 + R5)/(R1 + R3 + R4 + R5). control, but the single RC circuit used is the simplest by far
This causes the base of Q1 to be more positive than the and was consequently chosen for this particular application.
emitter and thus prevents Q1 from conducting until the For settings such that no power is delivered to the load, the
voltage across R3 is sufficient to forward bias the base-emit- timing capacitor would never discharge through the SBS.
ter junction of Q1. This occurs when the line voltage has The result is an abnormal amount of apparent phase shift
increased to about 15 volts. caused by the capacitor starting to charge toward a source of
The circuit can be operated over a different voltage range voltage with a residual charge of the opposite sign. This is the
by changing resistors R6 and/or R4 which change the cause of the hysteresis effect and is eliminated in this circuit
charging rate of C1. by the addition of the two diodes and 5.1 kΩ resistor
Figure 6.77(b) provides a plot of output voltage and connected to the SBS gate. At the end of each positive half
conduction angle versus input voltage for the regulator. As cycle when the applied voltage drops below that of the
the figure indicates, good regulation can be obtained
LOAD
between the input voltage range of 110 to 130 volts.

SILICON BILATERAL SWITCH (SBS)

20 k 20 k
APPLICATIONS
It is important that thyristor trigger circuitry be capable of
120 VAC 500 k
supplying a fast rising, high current gate pulse to the power
thyristors in order to prevent di/dt failure, especially when
they are subjected to high inrush load currents. Because of
the regenerative switching action and low dynamic on MAC12D
resistance of the SBS, it is ideally suited for this use.
0.22 µF MBS4991

Figure 6.78. Low Cost Lamp Dimmer

Motorola Thyristor Device Data Theory and Applications

1.6–41
 LOAD can be adjusted over the range of 60 to 120 volts dc or 42 to
84 volts ac. The resistor values can be changed to cover a
470 5.1 k 10 k different range of supply voltages. The voltage rating of the
TRIAC must be greater than the highest operating point as
set by R2. I1 is a low power incandescent lamp with a voltage
1N4003
MAC12D rating equal to the supply voltage. It may be used to check
120 VAC 1M
the set point and operation of the unit by opening the test
Q1 switch and adjusting the input or set point to fire the SBS. An
alarm unit such as the Mallory Sonalert may be connected
across the fuse to provide an audible indication of crowbar
0.22 µF MBS4991 1N4003 0.1 µF action. Note that this circuit may not act on short, infrequent
power line transients.

Figure 6.79. 1000 W TRIAC Light Dimmer SBS APPLICATIONS IN POWER CONTROL

The incandescent-lamp dimmer was one of the first

circuits to use thyristors after their invention and has
capacitor, gate current flows out of the SBS and it switches remained one of the most important applications of these
on, discharging the capacitor to near zero volts. devices.
The RC network shown across the TRIAC represents a Figure 6.81 shows the basic control circuit. In the positive
typical snubber circuit that is normally adequate to prevent half-cycle, the 0.1 µF capacitor charges through the dual-
line transients from accidentally firing the TRIAC. section phase-shift circuit until its voltage reaches the
break-over potential of the MBS4991 SBS. The MBS4991
ELECTRONIC CROWBAR potential then drops to about 1 volt, forcing charge from the
Occasionally the need arises for positive protection of 0.1 µF capacitor through the gate of the MAC12D TRIAC.
expensive electrical or electronic equipment against exces- This current turns the TRIAC on. When the TRIAC turns on, it
sive supply voltage. Such overvoltage conditions can occur removes the voltage from the timing circuit. C1 then
due to improper switching, wiring, short circuits or failure of discharges through the latched on TRIAC and the SBS if it
regulators. Where it is economically desirable to shut down also holds. What happens depends on the setting of R1, and
equipment rather than allow it to operate on excessive supply the switching current, switching voltage, latching current and
voltage, an electronic “crowbar” circuit such as the one holding current of the SBS. Analysis of the circuit behavior is
shown in Figure 6.80 can be employed to quickly place a difficult and cannot be treated on a half-cycle basis
short-circuit across the power lines, thereby dropping the because the previous half-cycle must be considered to
voltage across the protected device to near zero and blowing establish the initial conditions, and because large residual
a fuse. Since the TRIAC and SBS are both bilateral devices, voltages remain on C1. Several cycles of the ac line are
the circuit is equally useful on ac or dc supply lines. With the needed to establish steady state conduction angles.
values shown for R1, R2 and R3, the crowbar operating point

PUSH TO TEST I1
R1
10 k

SUPPLY VOLTAGE TO ELECTRICAL OR

AC OR DC ELECTRONIC EQUIPMENT
R2 SET POINT ADJ.
1k TRIAC

MBS4991
R3 0.1 µF
1k

Figure 6.80. Electronic Crowbar

Theory and Applications Motorola Thyristor Device Data

1.6–42
 MT2 MAC12D MT1
G 100

MBS4991

R1
100 k 15 0.1 µF LOAD
LINE

C2
R2 27 k
0.22 µF

C1

Figure 6.81. Low Hysteresis Dual Section

Phase Control Circuit

Hysteresis in the single RC phase controller is a result of charging supply for the 0.1 µF charge-storage capacitor C2.
the initial voltage on the capacitor before triggering. If the The 27 kΩ resistor isolates the trigger circuit from the phase
control is set to completely turn-off the lamp, triggering does shifter so that the voltage on C1 is only minimally affected by
not occur, and the capacitor voltage alternates up and down the triggering action. It is this isolation that reduces the
to some value less than VS. If the control is advanced, the hysteresis, prevalent in single-section phase-shift systems,
SBS fires and latches, causing the capacitor to charge from to an unnoticeable level.
the previous polarity on-state voltage of about 1 V. Conse- Anti-parallel SCRs allow the control of full-wave power at
quently, the control settings for dim illumination depend on higher currents and frequencies than possible with triacs. For
whether the potentiometer is being advanced from an off example, the 55 ampere SCRs in Figure 6.82 provide 75
state or retarded from a state with the lamp on, because the ampere capability compared to 40 amperes with the single
timing capacitor must charge through a different voltage MAC224 triac in Figure 6.81. The current alternates between
gradient in the two cases. the SCRs allowing a half-cycle of recovery time. So, there is
The dual-section phase-shift network prevents hysteresis no commutating dv/dt limitation. This guarantees turn-off
and allows reliable and stable triggering at all conduction even when the load current contains high frequency compo-
angles. The 100 kΩ variable resistor R1 and the 0.22 µF nents.
capacitor C1 perform the basic phase shifting and serve as a Figure 6.82 illustrates a trigger circuit using a low cost

SCR-1 MCR265-6

1N4001
MCR265-6
SCR-2
S
1N4001
T*
P
100 k
MBS4991
LINE LOAD
15 0.1 µF *200 µH
MINIMUM
PRIMARY
27 k INDUCTANCE,
0.22 µF 1:1 TURN RATIO
(SPRAGUE 11Z12)

Figure 6.82. Full-Wave SCR Control Circuit Using Low Cost Single Winding Trigger Transformer

Motorola Thyristor Device Data Theory and Applications

1.6–43
 + LOAD –

LINE MCR265-6 (2)

SCR-1
SCR-2
1N4001

1N4001
100 k
T*
*200 µH MINIMUM PRIMARY
INDUCTANCE, 1:1 TURN RATIO
MBS4991
(DALE PT50)
0.1 µF

15 0.22 µF

27 k
Figure 6.83. Variation of Basic Control Circuit to Provide Controlled DC Output

single winding transformer to fire both SCRs. In the TRIAC ZERO-POINT SWITCH APPLICATIONS
positive half-cycle, SCR-1 is triggered through the primary
of the pulse transformer. In the negative half-cycle, the 0.1
µF triggering capacitor discharges through the shunt G-K BASIC TRIAC ZERO-POINT SWITCH
diode of SCR-1 and the primary of the pulse transformer, Figure 6.84 shows a manually controlled zero-point switch
inducing a pulse in the secondary, which triggers SCR-2. useful in power control for resistive loads. Operation of the
The circuits described above were designed for incan- circuit is as follows. On the initial part of the positive half
descent-lamp dimmers and are ideally suited for this cycle, the voltage is changing rapidly from zero causing a
purpose. However, they may have many other uses, which large current flow into capacitor C2. The current through C2
are perhaps not immediately obvious. For example, flows through R4, D3, and D4 into the gate of the TRIAC Q2
universal and shaded-pole motors are easily and conve- causing it to turn on very close to zero voltage. Once Q2
niently controlled with these circuits. These motors have turns on, capacitor C3 charges to the peak of the line voltage
higher torque at low speeds when open-loop controlled in through D5. When the line voltage passes through the peak,
this manner rather than with rheostats or variable trans- D5 becomes reverse-biased and C3 begins to discharge
formers, owing to the higher voltage pulses applied. In through D4 and the gate of Q2. At this time the voltage on C3
another application, a slight modification of the basic lags the line voltage. When the line voltage goes through
control circuit allows control of the dc output of a fullwave zero there is still some charge on C3 so that when the line
rectifier bridge using pulse-transformer coupling (Figure voltage starts negative C3 is still discharging into the gate of
6.83). Q2. Thus Q2 is also turned on near zero on the negative half
The power rating of these circuits is limited only by the cycle. This operation continues for each cycle until switch S1
thyristors employed. The control circuit will give sufficient is closed, at which time SCR Q1 is turned on. Q1 shunts the
drive for any thyristor that can be triggered with 50 mA or gate current away from Q2 during each positive half cycle
less gate current. For example, with MCR3818-4 con- keeping Q2 from turning on. Q2 cannot turn on during the
trolled rectifiers mounted on a suitable heat sink, these negative cycle because C3 cannot charge unless Q2 is on
circuits will control up to 3 kW power from a 120 V line. during the positive half cycle.

Theory and Applications Motorola Thyristor Device Data

1.6–44
 R3
C2 +
1.2 k
2 µF
7W
200 V
D1 Q2
1N4003 2N6346
R4
150 Ω
D3 D4
1W
1N4003 1N4001
R1
115 VAC 12 k
60 Hz D5
2W D2 1N4003
1N4003
+
R2 Q1 C3
10 k MCR1906-4 1 µF
R5
C1 200 V
+ S1 1k LOAD
10 µF D6 2W
5V 1N4372

Figure 6.84. Zero-Point Switch

If S1 is initially closed during a positive half cycle, SCR Q1 A 3-volt gate signal for SCR Q1 is obtained from D1, R1,
turns on but circuit operation continues for the rest of the C1, and D6.
complete cycle and then turns off. If S1 is closed during a
negative half cycle, Q1 does not turn on because it is reverse AN INTEGRATED CIRCUIT ZERO VOLTAGE SWITCH
biased. Q1 then turns on at the beginning of the positive half A single CA3059/79 integrated circuit operating directly off
cycle and Q2 turns off. the ac line provides the same function as the discrete circuit
Zero-point switching when S1 is opened is ensured by the shown in Figure 6.84. Figure 6.85 shows its block diagram.
characteristic of SCR Q1. If S1 is opened during the positive The circuit operates a power triac in quadrants one and
half cycle, Q1 continues to conduct for the entire half cycle four, providing gate pulses synchronized to the zero voltage
and TRIAC Q2 cannot turn on in the middle of the positive point of the ac cycle. This eliminates the RFI resulting from
half cycle. Q2 does not turn on during the negative half cycle the control of resistive loads like heaters and flashing lamps.
because C3 was unable to charge during the positive half Table 6.12 specifies the value of the input series resistor for
cycle. Q2 starts to conduct at the first complete positive half the operating line voltage. Figure 6.86 shows the pin
cycle. If S1 is opened during the negative half cycle, Q2 connection for a typical application.
again cannot turn on until the beginning of the positive half
cycle because C3 is uncharged.

2
VCC

RS 5
POWER
LIMITER VCC
AC SUPPLY
RL
INPUT CURRENT
ZERO 3
BOOST
CROSSING
12 DETECTOR
MT2
DC MODE or
400 Hz INPUT
14 TRIAC 4 MT1
100 RP PROTECTION
CIRCUIT DRIVE
µF + GATE
AC
INPUT 15 V –
VOLTAGE +
13 ON/OFF
SENSING
9 AMP
–

* VCC
RX 10
11

8 1 6
GND 7 INHIBIT EXTERNAL TRIGGER
*NTC SENSOR

Figure 6.85. Functional Block Diagram

Motorola Thyristor Device Data Theory and Applications

1.6–45
 Table 6.12.
AC Input Voltage Input Series Dissipation Rating
9 10 11 3
RL (50/60 Hz) Resistor (RS) for RS
vac kΩ W
RS 24 20
2.0 05
0.5
10 k 120 10 2.0
20
5 T2800D 208/230 20 40
4.0
120 Vrms CA3059 4 277 25 5.0
60 Hz
7

TEMPERATURE CONTROL WITH ZERO-POINT

8 13 14 2 SWITCHING
R2 ZERO VOLTAGE SWITCH PROPORTIONAL BAND
5k
TEMPERATURE CONTROLLER
Figure 6.87 shows the block diagram for the UAA1016B
R1 integrated circuit temperature controller. Figure 6.88 shows a
ON typical application circuit. This device drives triacs with a zero
5k
OFF voltage full wave technique allowing RFI free power regula-
+ 100 µf
tion of resistive loads and adjustable burst frequency to
15 V comply with standards. It operates directly off the ac line
triggers the triac in Q2 and Q3, is sensor fail-safe, and
provides proportional temperature control over an adjustable
band. Consult the device data sheet (DS9641) for detailed
information.
Figure 6.86. Zero Voltage Switch Using CA3059
Integrated Circuit

220 VAC

TEMP. FAIL-SAFE
SET R1 R2 PULSE
AMPLIFIER
3
+ SAMPLING
6
FULL WAVE
VREF 4 LOGIC MAC224-8
–
COMPARATOR
R4 SAWTOOTH 7
1.0 GENERATOR
UAA1016B
M 1
SYNCHRO- POWER
NIZATION SUPPLY

(NTC)
TEMP. LOAD
SENSOR

2 8 5 +
– VCC
RL CPin 2
R3 RSYNC
180 k

q 5RL
220 VAC
Design Notes: 1. Let R4

2. Select R2 Ratio for a symmetrical reference deviation centered about Pin 1 output swing, R2 will be slightly greater than R3.
R3
DVPin 1
3. Select R2 and R3 values for the desired reference deviation where DV REF +
R4
R2 | | R3
1 )
Figure 6.87. UA1016B Block Diagram and Pin Assignment

Theory and Applications Motorola Thyristor Device Data

1.6–46
 50 k
6.8 k

22 k
3 6 0.1
µF
4
UAA1016B 100
MAC224-8

MOV
R4 Ω
220 VAC
1 7

6.8
RT k RL
2 8 5
+ + HEATER
47 µF 100 k 100 µF
8.0 V 2.0 kW

RT : NTC R @ 25°C = 22 k  10% 18 k

B = 3700 2.0 W 1N4005
MOV: 250 VAC VARISTOR

Figure 6.88. Application Circuit — Electric Radiator with Proportional Band

Thermostat, Proportional Band 1°C at 25°C

TRIAC RELAY-CONTACT PROTECTION There is some delay between the time a relay coil is
A common problem in contact switching high current is energized and the time the contacts close. There is also a
arcing which causes erosion of the contacts. A solution to delay between the time the coil is de-energized and the time
this problem is illustrated in Figure 6.89. This circuit can be the contacts open. For the relay used in this circuit both times
used to prevent relay contact arcing for loads up to 50 are about 15 ms. The TRIAC across the relay contacts will
amperes. turn on as soon as sufficient gate current is present to fire it.
This occurs after switch S1 is closed but before the relay
contacts close. When the contacts close, the load current
R3 passes through them, rather than through the TRIAC, even
though the TRIAC is receiving gate current. If S1 should be
47 C2
closed during the negative half cycle of the ac line, the TRIAC
50 AMP 0.1 µF
will not turn on immediately but will wait until the voltage
LOAD
MAC210A6 begins to go positive, at which time diode D1 conducts
providing gate current through R1. The maximum time that
S1 could elapse before the TRIAC turns on is 8-1/3 ms for the 60
Hz supply. This is adequate to ensure that the TRIAC will be
R1 on before the relay contact closes. During the positive half
115 V RELAY WITH PICK-
115 VAC 1.5 k cycle, capacitor C1 is charged through D1 and R2. This
UP AND DROP-OUT TIMES 10 W
60 Hz stores energy in the capacitor so that it can be used to keep
OF 10-20 ms
the TRIAC on after switch S1 has been opened. The time
R2 constant of R1 plus R2 and C1 is set so that sufficient gate
D1 1N4004
10 current is present at the time of relay drop-out after the
10 W opening of S1, to assure that the TRIAC will still be on. For
+
C1 the relay used, this time is 15 ms. The TRIAC therefore limits
20 µF the maximum voltage, across the relay contacts upon
250 V dropout to the TRIAC’s voltage drop of about 1 volt. The
TRIAC will conduct until its gate current falls below the
threshold level, after which it will turn off when the anode
Figure 6.89. TRIAC Prevents Relay Contact Arcing
current goes to zero. The TRIAC will conduct for several
cycles after the relay contacts open.

Motorola Thyristor Device Data Theory and Applications

1.6–47
 B+

MAC + 220
75 k
228A6FP 250 V

MR506
T
INPUT +
8 10 k 220
92 TO 276 75 k
250 V
VAC 3.0 A
2.54 V
REFERENCE 1.2 k RTN
1

10 k –
7 +
+
+ 2.8 V 6
2 + –
100 k 1.27 V –
+ +
1.6 M 0.6 V
+ 5
3 –
+
+
10 1.27 V
1N +
4742 47
4
10 k
3W

Figure 6.90. Automatic AC Line Voltage Selector

This circuit not only reduces contact bounce and arcing but AN AUTOMATIC AC LINE VOLTAGE SELECTOR USING
also reduces the physical size of the relay. Since the relay is THE MC34161 AND A TRIAC
not required to interrupt the load current, its rating can be Line operated switching regulators run off of 120 or 240
based on two factors: the first is the rms rating of the VAC by configuring the main reservoir input capacitor filter as
current-carrying metal, and the second is the contact area. a full-wave doubler or full-wave bridge. This integrated circuit
This means that many well-designed 5 ampere relays can be provides the control signals and triggering for a TRIAC to
used in a 50 ampere load circuit. Because the size of the automatically provide this function.
relay has been reduced, so will the noise on closing. Another Channel 1 senses the negative half cycles of the AC line
advantage of this circuit is that the life of the relay will be voltage. If the line voltage is less than 150 V, the circuit will
increased since it will not be subjected to contact burning, switch from bridge mode to voltage doubling mode after a
welding, etc. preset time delay. The delay is controlled by the 100 kΩ
The RC circuit shown across the contact and TRIAC (R3 resistor and the 10 µF capacitor. If the line voltage is greater
and C2) is to reduce dv/dt if any other switching element is than 150 V, the circuit will immediately return to fullwave
used in the line. bridge mode.

Theory and Applications Motorola Thyristor Device Data

1.6–48
MOTOROLA
SEMICONDUCTOR APPLICATION NOTE

AN982
Applications of
Zero Voltage Crossing
Optically Isolated Triac Drivers
Prepared by Horst Gempe

INTRODUCTION presence. Brief examples of typical applications are pres-

ented.
The zero–cross family of optically isolated triac drivers in an
inexpensive, simple and effective solution for interface ap- CONSTRUCTION
plications between low current dc control circuits such as logic
gates and microprocessors and ac power loads (120, 240 or The zero–cross family consists of a liquid phase EPI, in-
380 volt, single or 3–phase). frared, light emitting diode which optically triggers a silicon
These devices provide sufficient gate trigger current for high detector chip. A schematic representation of the triac driver
current, high voltage thyristors, while providing a guaranteed is shown in Figure 1. Both chips are housed in a small, 6–pin
7.5 kV dielectric withstand voltage between the line and the dual–in–line (DIP) package which provides mechanical in-
control circuitry. An integrated, zero–crossing switch on the tegrity and protection for the semiconductor chips from exter-
detector chip eliminates current surges and the resulting elec- nal impurities. The chips are insulated by an infrared
tromagnetic interference (EMI) and reliability problems for transmissive medium which reliably isolates the LED input
many applications. The high transient immunity of 5000 V/µs, drive circuits from the environment of the ac power load. This
combined with the features of low coupling capacitance, high insulation system meets the stringent requirements for isola-
isolation resistance and up to 800 volt specified VDRM ratings tion set forth by regulatory agencies such as UL and VDE.
qualify this triac driver family as the ideal link between sensi-
tive control circuitry and the ac power system environment. THE DETECTOR CHIP
Optically isolated triac drivers are not intended for stand The detector chip is a complex monolithic IC which contains
alone service as are such devices as solid state relays. They two infrared sensitive, inverse parallel, high voltage SCRs
will, however, replace costly and space demanding discrete which function as a light sensitive triac. Gates of the individual
drive circuitry having high component count consisting of SCRs are connected to high speed zero crossing detection
standard transistor optoisolators, support components includ- circuits. This insures that with a continuous forward current
ing a full wave rectifier bridge, discrete transistors, trigger through the LED, the detector will not switch to the conducting
SCRs and various resistor and capacitor combinations. state until the applied ac voltage passes through a point near
This paper describes the operation of a basic driving circuit zero. Such a feature not only insures lower generated noise
and the determination of circuit values needed for proper im- (EMI) and inrush (Surge) currents into resistive loads and
plementation of the triac driver. Inductive loads are discussed moderate inductive loads but it also provides high noise immu-
along with the special networks required to use triacs in their nity (several thousand V/µs) for the detection circuit.

MT

IF
ZERO
CROSSING
DETECTOR
ZERO
CROSSING
DETECTOR

MT DETECTOR LED

Figure 6.1. Schematic of Zero Crossing Optically Isolated Triac Driver

REV 1

Motorola Thyristor Device Data Theory and Applications

1.6–49
 ON STATE Q1
A2+ BLOCKING
VDRM STATE
IDRM IH
VDRM I
MT IF
V
ZERO
CROSSING VF V
DETECTOR A2– IH– I
IDRM
BLOCKING STATE
MT Q111
ON STATE

Figure 6.2. Simplified Schematic of Isolator Figure 6.3. Triac Voltage–Current Characteristic

ELECTRICAL CHARACTERISTICS must be used to prevent false “turn on” of the main triac. A de-
tailed discussion of a “snubber” network is given under the
A simplified schematic of the optically isolated triac driver is section “Inductive and Resistive Loads.”
shown in Figure 2. This model is sufficient to describe all im- Figure 4 shows a static dV/dt test circuit which can be used
portant characteristics. A forward current flow through the to test triac drivers and power triacs. The proposed test meth-
LED generates infrared radiation which triggers the detector. od is per EIA/NARM standard RS–443.
This LED trigger current (IFT) is the maximum guaranteed cur- Tests on the MOC3061 family of triac drivers using the test
rent necessary to latch the triac driver and ranges from 5 mA circuit of Figure 4 have resulted in data showing the effects of
for the MOC3063 to 15 mA for the MOC3061. The LED’s for- temperature and voltage transient amplitude on static dV/dt.
ward voltage drop at IF = 30 mA is 1.5 V maximum. Voltage– Figure 5 is a plot of dV/dt versus ambient temperature while
current characteristics of the triac are identified in Figure 3. Figure 6 is a similar plot versus transient amplitude.
Once triggered, the detector stays latched in the “on state”
until the current flow through the detector drops below the BASIC DRIVING CIRCUIT
holding current (IH) which is typically 100 µA. At this time, the
detector reverts to the “off” (non–conducting) state. The detec- Assuming the circuit shown in Figure 7 is in the blocking or
tor may be triggered “on” not only by IFT but also by exceeding “off” state (which means IF is zero), the full ac line voltage ap-
the forward blocking voltage between the two main terminals pears across the main terminals of both the triac and the triac
(MT1 and MT2) which is a minimum of 600 volts for all driver. When sufficient LED current (IFT) is supplied and the ac
MOC3061 family members. Also, voltage ramps (transients, line voltage is below the inhibit voltage (IH in Figure 3), the triac
noise, etc.) which are common in ac power lines may trigger driver latches “on.” This action introduces a gate current in the
the detector accidentally if they exceed the static dV/dt rating. main triac triggering it from the blocking state into full conduc-
Since the fast switching, zero–crossing switch provides a tion. Once triggered, the voltage across the main terminals
minimum dV/dt of 500 V/µs even at an ambient temperature collapses to a very low value which results in the triac driver
of 70°C, accidental triggering of the triac driver is unlikely. Ac- output current decreasing to a value lower than its holding cur-
cidental triggering of the main triac is a more likely occurrence. rent, thus forcing the triac driver into the “off” state, even when
Where high dV/dt transients on the ac line are anticipated, a IFT is still applied.
form of suppression network commonly called a “snubber”

15 V HV SCOPE PROBE 100:1

P8
10 Ω 150 kΩ 10 k
–15 V

100 Ω MERCURY 0.001 µF DUT

SIGNAL IN WETTED
RELAY
470 Ω

HV 0.63HV HV
0 50% DUTY CYCLE 0
VOLTAGE APPLIED TO DUT –
16 ms τRC
TEST PROCEDURE –
Turn the D.U.T. on, while applying sufficient dV/dt to ensure that it remains on, even after the trigger current is re-
moved. Then decrease dV/dt until the D.U.T. turns off. Measure τRC, the time it takes to rise to 0.63 HV, and divide 0.63
HV by τRC to get dV/dt.

Figure 6.4. Static dV/dt Test Circuit

Theory and Applications Motorola Thyristor Device Data

1.6–50
 10000
600
TRANSIENT AMPLITUDE 5000
dV/dt [V/µs]

dV/dt [V/µs]
= 600 V
2000

1000

500
25 50 75 100 100 200 300 400 500 600
TA, AMBIENT TEMPERATURE (°C) TRANSIENT AMPLITUDE (V)

Figure 6.5. Static dV/dt versus Temperature Figure 6.6. Static dV/dt versus Transient Amplitude

The power triac remains in the conducting state until the a typical 220 volt application: Assume the line voltage is 220
load current drops below the power triac’s holding current, a volts RMS. Also assume the maximum peak repetitive driver
situation that occurs every half cycle. The actual duty cycle for current (normally for a 10 micro second maximum time inter-
the triac driver is very short (in the 1 to 3 µs region). When IFT val) is 1 ampere. Then

+ I peak + 2201 Ǹamp

is present, the power triac will be retriggered every half cycle
V
of the ac line voltage until IFT is switched “off” and the power
triac has gone through a zero current point. (See Figure 8).
R
2 volts
+ 311 ohms
peak
Resistor R (shown in Figure 7) is not mandatory when RL is
a resistive load since the current is limited by the gate trigger One should select a standard resistor value >311 ohms !
current (IGT) of the power triac. However, resistor R (in com- 330 ohms.
bination with R–C snubber networks that are described in the The gate resistor RG (also shown in Figure 7) is only neces-
section “Inductive and Resistive Loads”) prevents possible sary when the internal gate impedance of the triac or SCR is
destruction of the triac driver in applications where the load is very high which is the case with sensitive gate thyristors.
highly inductive. These devices display very poor noise immunity and thermal
Unintentional phase control of the main triac may happen if stability without RG. Value of the gate resistor in this case
the current limiting resistor R is too high in value. The function should be between 100 and 500. The circuit designer should
of this resistor is to limit the current through the triac driver in be aware that use of a gate resistor increases the required trig-
case the main triac is forced into the non–conductive state ger current (IGT) since RG drains off part of IGT. Use of a gate
close to the peak of the line voltage and the energy stored in resistor combined with the current limiting resistor R can result
a “snubber” capacitor is discharged into the triac driver. A cal- in an unintended delay or phase shift between the zero–cross
culation for the current limiting resistor R is shown below for point and the time the power triac triggers.

IFT
IFT R
1 6 MT2
AC LINE
VOLTAGE
2 5 AC
TRIAC DRIVER
INPUT
CURRENT
IL I = IGT + II
3 ZERO 4 IGT II
CROSSING
CIRCUIT RG MT1 RL V – ACROSS
MAIN TRIAC
TRIAC DRIVER POWERTRIAC
IL
Figure 6.7. Basic Driving Circuit — Triac
Driver, Triac and Load

Figure 6.8. Waveforms of a Basic Driving

Circuit

Motorola Thyristor Device Data Theory and Applications

1.6–51
 UNINTENDED TRIGGER DELAY TIME
2000
To calculate the unintended time delay, one must remember
that power triacs require a specified trigger current (IGT) and
trigger voltage (VGT) to cause the triac to become conductive.
This necessitates a minimum line voltage VT to be present be-
tween terminals MT1 and MT2 (see Figure 7), even when the
triac driver is already triggered “on.” The value of minimum line

t d (µs)
voltage VT is calculated by adding all the voltage drops in the
trigger circuit:
VT = VR + VTM + VGT.
Current I in the trigger circuit consists not only of IGT but also
the current through RG:
I = IRG + IGT.
Likewise, IRG is calculated by dividing the required gate trig- 200

ger voltage VGT for the power triac by the chosen value of gate 0
300 500 1000 1500 2000
resistor RG:
IRG = VGT/RG R (OHMS)
Thus, I = VGT/RG + IGT.
All voltage drops in the trigger circuit can now be determined Figure 6.9. Time Delay td versus Current Limiting Resistor R
as follows:
VR = I  R = VGT/RG  R + IGT  R = R(VGT/RG
+ IGT)
VTM = From triac driver data sheet
VGT = From power triac data sheet. SWITCHING SPEED
IGT = From power triac data sheet.
With VTM, VGT and IGT taken from data sheets, it can be seen The switching speed of the triac driver is a composition of
that VT is only dependent on R and RG. the LED’s turn on time and the detector’s delay, rise and fall
Knowing the minimum voltage between MT1 and MT2 (line times. The harder the LED is driven the shorter becomes the
voltage) required to trigger the power triac, the unintended LED’s rise time and the detector’s delay time. Very short IFT
phase delay angle θd (between the ideal zero crossing of the duty cycles require higher LED currents to guarantee “turn on”
ac line voltage and the trigger point of the power triac) and the of the triac driver consistent with the speed required by the
trigger delay time td can be determined as follows: short trigger pulses.

+ sin-1 VTńVpeak
Figure 10 shows the dependency of the required LED cur-
qd rent normalized to the dc trigger current required to trigger the

+ sin-1 R(VGTńRG ) IVGT) ) VTM ) VGT

triac driver versus the pulse width of the LED current. LED trig-
ger pulses which are less than 100 µs in width need to be high-
peak er in amplitude than specified on the data sheet in order to
assure reliable triggering of the triac driver detector.
The time delay td is the ratio of θd to θVpeak (which is 90 de- The switching speed test circuit is shown in Figure 11. Note
grees) multiplied by the time it takes the line voltage to go from that the pulse generator must be synchronized with the 60 Hz
zero voltage to peak voltage (simply 1/4f, where f is the line fre- line voltage and the LED trigger pulse must occur near the
quency). Thus zero cross point of the ac line voltage. Peak ac current in the
td = θd/90  1/4f. curve tracer should be limited to 10 mA. This can be done by
setting the internal load resistor to 3 k ohms.
Figure 9 shows the trigger delay of the main triac versus the
value of the current limiting resistor R for assumed values of
IGT. Other assumptions made in plotting the equation for td are
that line voltage is 220 V RMS which leads to Vpeak = 311 volts;
RG = 300 ohms; VGT = 2 volts and f = 60 Hz. Even though the
triac driver triggers close to the zero cross point of the ac volt-
age, the power triac cannot be triggered until the voltage of the
ac line rises high enough to create enough current flow to latch
the power triac in the “on” state. It is apparent that significant
time delays from the zero crossing point can be observed
when R is a large value along with a high value of IGT and/or
a low value of RG. It should be remembered that low values of
the gate resistor improve the dV/dt ratinigs of the power triac
and minimize self latching problems that might otherwise oc-
cur at high junction temperatures.

Theory and Applications Motorola Thyristor Device Data

1.6–52
 Motorola isolated triac drivers are trigger devices and de-
signed to work in conjunction with triacs or reverse parallel 25
SCRs which are able to take rated load current. However, as

IFT, NORMALIZED LED TRIGGER

soon as the power triac is triggered there is no current flow
20 NORMALIZED TO:
through the triac driver. The time to turn the triac driver “off” de-
pends on the switching speed of the triac, which is typically on
q
PW IN 100 µs
the order of 1–2 µs.

CURRENT
15

10

1
0
1 2 5 10 20 50 100
LED TRIGGER PULSE WIDTH (µs)

Figure 6.10. IFT Normalized to IFT dc As Specified on

the Data Sheet

PULSE WIDTH CONTROL

DELAY CONTROL
AMPLITUDE CONTROL DUT

1 6 RL

10 Ω 2 5
PULSE
GENERATOR
3 4
ZERO
CROSSING
CIRCUIT

CURVE
TRACER (AC MODE)

AC LINE IF
SYNC MONITOR
SCOPE

Figure 6.11. Test Circuit for LED Forward Trigger Current versus Pulse Width

INDUCTIVE AND RESISTIVE LOADS only 0.13 V/µs for a 240 V, 50 Hz line source and 0.063 V/µs
for a 120 V, 60 Hz line source. For inductive loads the “turn off”
Inductive loads (motors, solenoids, etc.) present a problem time and commutating dV/dt stress are more difficult to define
for the power triac because the current is not in phase with the and are affected by a number of variables such as back EMF
voltage. An important fact to remember is that since a triac can of motors and the ratio of inductance to resistance (power fac-
conduct current in both directions, it has only a brief interval tor). Although it may appear from the inductive load that the
during which the sine wave current is passing through zero to rate or rise is extremely fast, closer circuit evaluation reveals
recover and revert to its blocking state. For inductive loads, the that the commutating dV/dt generated is restricted to some fi-
phase shift between voltage and current means that at the nite value which is a function of the load reactance LL and the
time the current of the power handling triac falls below the device capacitance C but still may exceed the triac’s critical
holding current and the triac ceases to conduct, there exists commuting dV/dt rating which is about 50 V/µs. It is generally
a certain voltage which must appear across the triac. If this good practice to use an RC snubber network across the triac
voltage appears too rapidly, the triac will resume conduction to limit the rate of rise (dV/dt) to a value below the maximum
and control is lost. In order to achieve control with certain in- allowable rating. This snubber network not only limits the volt-
ductive loads, the rate of rise in voltage (dV/dt) must be limited age rise during commutation but also suppresses transient
by a series RC network placed in parallel with the power triac. voltages that may occur as a result of ac line disturbances.
The capacitor Cs will limit the dV/dt across the triac. There are no easy methods for selecting the values for Rs
The resistor Rs is necessary to limit the surge current from and Cs of a snubber network. The circuit of Figure 13 is a
Cs when the triac conducts and to damp the ringing of the ca- damped, tuned circuit comprised of Rs, Cs, RL and LL, and to
pacitance with the load inductance LL. Such an RC network is a minor extent the junction capacitance of the triac. When the
commonly referred to as a “snubber.” triac ceases to conduct (this occurs every half cycle of the line
Figure 12 shows current and voltage wave forms for the voltage when the current falls below the holding current), the
power triac. Commutating dV/dt for a resistive load is typically

Motorola Thyristor Device Data Theory and Applications

1.6–53
load current receives a step impulse of line voltage which de- ing mode which allows each device to recover and turn “off”
pends on the power factor of the load. A given load fixes RL during a full half cycle. Once in the “off” state, each SCR can
and LL; however, the circuit designer can vary Rs and Cs. resist dV/dt to the critical value of about 100 V/µs. Optically
Commutating dV/dt can be lowered by increasing CS while Rs isolated triac drivers are ideal in this application since both
can be increased to decrease resonant “over ringing” of the gates can be triggered by one triac driver which also provides
tuned circuit. Generally this is done experimentally beginning isolation between the low voltage control circuit and the ac
with values calculated as shown in the next section and, then, power line.
adjusting Rs and Cs values to achieve critical damping and a It should be mentioned that the triac driver detector does not
low critical rate of rise of voltage. see the commutating dV/dt generated by the inductive load
Less sensitive to commutating dV/dt are two SCRs in an in- during its commutation; therefore, the commutating dV/dt ap-
verse parallel mode often referred to as a back–to–back SCR pears as a static dV/dt across the two main terminals of the
pair (see Figure 15). This circuit uses the SCRs in an alternat- triac driver.

IF(ON)
IF(ON) IF(OFF)
IF(OFF)

AC LINE
AC LINE
VOLTAGE
VOLTAGE

AC CURRENT AC CURRENT
THROUGH
COMMUTATING POWER TRIAC
COMMUTATING
dV/dt dV/dt
d
VOLTAGE VOLTAGE
t0 ACROSS t0 ACROSS
TIME POWER TRIAC TIME POWER TRIAC

Resistive Load Inductive Load

Figure 6.12. Current and Voltage Waveforms During Commutation

Theory and Applications Motorola Thyristor Device Data

1.6–54
 SNUBBER DESIGN — THE RESONANT METHOD
V
If R, L and C are chosen to resonate, the voltage waveform
on dV/dt will look like Figure 14. This is the result of a damped
quarter–cycle of oscillation. In order to calculate the compo-
nents for snubbing, the dV/dt must be related to frequency.
Since, for a sine wave,
STEP FUNCTION
V(t) = VP sin wt VOLTAGE ACROSS TRIAC
dV/dt = VP w cost wt
dV/dt(max) = VP w = VP 2pf
Figure 6.14. Voltage Waveform After Step Voltage

f + dV dt ń Rise – Resonant Snubbing

2pV
A(max)
Where dV/dt is the maximum value of off state dV/dt speci-
fied by the manufacturer.
From:

f+ 2p Ǹ1 LC
C+ 1
(2pf) 2L
We can choose the inductor for convenience. Assuming the

Ǹ
resistor is chosen for the usual 30% overshoot:
RG RS
R + L
C CS
AC LINE

Assuming L is 50 µH, then: LL RL

f + 2pV ń
(dV dt)
min Vńµs
+ 250p(294 + 27 kHz
RG
R
V)
A(max)
1 6
+ + 0.69 µF
Ǹ +Ǹ
C 1
(2pf) 2L CONTROL 2 5
R + L
C
50 µH
0.69 µF
+ 8.5 Ω
3 4
ZERO
CROSSING
CIRCUIT

1 6 R
Figure 6.15. A Circuit Using Inverse Parallel SCRs
2 5 RS
AC
CS
3 4
ZERO
CROSSING
CIRCUIT LL RL
LOAD
Figure 6.13. Triac Driving Circuit — with Snubber

Motorola Thyristor Device Data Theory and Applications

1.6–55
 INRUSH (SURGE) CURRENTS driver (MOC3020 family) with special circuitry to provide initial
“turn on” of the power triac at ac peak voltage may be the opti-
The zero crossing feature of the triac driver insures lower mized solution.
generated noise and sudden inrush currents on resistive
loads and moderate inductive loads. However, the user should ZERO CROSS, THREE PHASE CONTROL
be aware that many loads even when started at close to the
ac zero crossing point present a very low impedance. For ex- The growing demand for solid state switching of ac power
ample, incandescent lamp filaments when energized at the heating controls and other industrial applications has resulted
zero crossing may draw ten to twenty times the steady state in the increased use of triac circuits in the control of three
current that is drawn when the filament is hot. A motor when phase power. Isolation of the dc logic circuitry from the ac line,
started pulls a “locked rotor” current of, perhaps, six times its the triac and the load is often desirable even in single phase
running current. This means the power triac switching these power control applications. In control circuits for poly phase
loads must be capable of handling current surges without power systems, this type of isolation is mandatory because
junction overheating and subsequent degradation of its elec- the common point of the dc logic circuitry cannot be referred
trical parameters. to a common line in all phases. The MOC3061 family’s charac-
Almost pure inductive loads with saturable ferromagnetic teristics of high off–state blocking voltage and high isolation
cores may display excessive inrush currents of 30 to 40 times capability make the isolated triac drivers devices for a simpli-
the operating current for several cycles when switched “on” at fied, effective control circuit with low component count as
the zero crossing point. For these loads, a random phase triac shown in Figure 16. Each phase is controlled individually by

A B C
1 6 R

2 5 RS

CS
3 4 A
ZERO
CROSSING
CIRCUIT RG

1 6 R

2 5 RS

CS
3 4 B
ZERO RL
CROSSING
CIRCUIT RG (3 PLACES) RL
(3 PLACES)

1 6 R

2 5 RS

CS
3 4
ZERO C
CROSSING
CIRCUIT RG

LED CURRENT
A B C

3 PHASE LINE VOLTAGE

A AND B SWITCH ON B AND C SWITCH OFF,

A FOLLOWS
C SWITCHES ON

Figure 6.16. 3 Phase Control Circuit

Theory and Applications Motorola Thyristor Device Data

1.6–56
 1 6 R RL

2 5
AC

RIFT 3 4
ZERO
CROSSING
CIRCUIT RG

TEMP. SET +12 V

100 k
10 k
4.7 k 4.7 k 1@4 MC33074A

+ VTEMP 100 k
+ 1@4 MC33074A +
1N4001
–
1N40001 4.7 m – –
Ro
1 µF
TEMP. VD OSC 14@ MC33074A
100 k
SENS.
4.7 k 4.7 k Co

GND

BRIDGE GAIN STAGE COMPARATOR OSCILLATOR

∆ V = 2 mV/°C AV = 1000
Vo = 2 V/°C VOLTAGE CONTROLLED PULSE WIDTH MODULATOR

Figure 6.17. Proportional Zero Voltage Switching Temperature Controller

a power triac with optional snubber network (Rs, Cs) and an PROPORTIONAL ZERO VOLTAGE SWITCHING
isolated triac driver with current limiting resistor R. All LEDs
are connected in series and can be controlled by one logic The built–in zero voltage switching feature of the zero–
gate or controller. An example is shown in Figure 17. cross triac drivers can be extended to applications in which it
At startup, by applying IF, the two triac drivers which see is desirable to have constant control of the load and a mini-
zero voltage differential between phase A and B or A and C or mization of system hysteresis as required in industrial heater
C and B (which occurs every 60 electrical degrees of the ac applications, oven controls, etc. A closed loop heater control
line voltage) will switch “on” first. The third driver (still in the in which the temperature of the heater element or the chamber
“off” state) switches “on” when the voltage difference between is sensed and maintained at a particular value is a good exam-
the phase to which it is connected approaches the same volt- ple of such applications. Proportional zero voltage switching
age as the sum voltage (superimposed voltage) of the phases provides accurate temperature control, minimizes overshoots
already switched “on.” This guarantees zero current “turn on” and reduces the generation of line noise transients.
of all three branches of the load which can be in Y or Delta con- Figure 17 shows a low cost MC33074 quad op amp which
figuration. When the LEDs are switched “off,” all phases provides the task of temperature sensing, amplification, volt-
switch “off” when the current (voltage difference) between any age controlled pulse width modulation and triac driver LED
two of the three phases drops below the holding current of the control. One of the two 1N4001 diodes (which are in a Wheat-
power triacs. Two phases switched “off” create zero current. stone bridge configuration) senses the temperature in the
In the remaining phase, the third triac switches “off” at the oven chamber with an output signal of about 2 mV/°C. This
same time. signal is amplified in an inverting gain stage by a factor of

Motorola Thyristor Device Data Theory and Applications

1.6–57
1000 and compared to a triangle wave generated by an os- VTEMP.
cillator. The comparator and triangle oscillator form a volt-
age controlled pulse width modulator which controls the VOSC
triac driver. When the temperature in the chamber is below
the desired value, the comparator output is low, the triac
driver and the triac are in the conducting state and full power
is applied to the load. When the oven temperature comes Vo COMP.
close to the desired value (determined by the “temp set” po-
tentiometer), a duty cycle of less than 100% is introduced
providing the heater with proportionally less power until ILED
equilibrium is reached. The proportional band can be con-
trolled by the amplification of the gain stage — more gain
provides a narrow band; less gain a wider band. Typical wa- VAC
veforms are shown in Figure 18. (ACROSS RL)
TOO COLD FINE REG. TOO HOT FINE REG.

Figure 6.18. Typical Waveforms of Temperature

Controller

Theory and Applications Motorola Thyristor Device Data

1.6–58
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

AN1045
Series Triacs
In AC High Voltage Switching Circuits
By George Templeton
Thyristor Applications Engineer

INTRODUCTION

This paper describes the series connection of triacs to suggest. It must block the vector sum of the line, auxiliary
create a high voltage switch suitable for operation at winding, and start capacitor voltage. This voltage increases
voltages up to 2000 Volts. They can replace electrome- when triac turn-off occurs at higher rpm.
chanical contactors or extend their current rating and
lifetime. Motor starters and controllers operating at line TRIGGERING
voltages of 240 Volts or more require high-voltage
Figure 1 illustrates a series thyristor switching circuit. In
switches. Transformer action and resonant snubber
this circuit, the top triac triggers in Quadrant 1 when the
charging result in voltages much greater than the peak of
bottom triac triggers in Quadrant 3. When the optocoupler
the line. Triacs can be subjected to both commutating and
turns on, gate current flows until the triacs latch. At that
static dV/dt when multiple switching devices are present in
time, the voltage between the gate terminals drops to
the circuit. Snubber designs to prevent static dV/dt turn-on
about 0.6 Volts stopping the gate current. This process
result in higher voltages at turn-off. Variable load imped-
repeats each half cycle. The power rating of the gate
ances also raise voltage requirements.
resistor can be small because of the short duration of the
The benefits of series operation include: higher blocking
gate current. Optocoupler surge or triac gate ratings
voltage, reduced leakage, better thermal stability, higher
determine the minimum resistance value. For example,
dV/dt capability, reduced snubber costs, possible snub-
when the maximum optocoupler ITSM rating is 1 A:
berless operation, and greater latitude in snubber design.
The advantages of triacs as replacements for relays Rg u+ VpeakńImax (1.0)
R g + 750 Vń1 A + 750 Ohm
include:
• Small size and light weight.
• Safety — freedom from arcing and spark initiated explo- The triacs retrigger every half cycle as soon as the line
sions. voltage rises to the value necessary to force the trigger
• Long lifespan — contact bounce and burning current. The instantaneous line voltage V is
eliminated.
• Fast operation — turn-on in microseconds and turn-off in V + IGT Rg ) 2 VGT ) 2 VTM (1.1)
milliseconds.
where VGT, IGT are data book specifications for the triac
• Quiet operation.
and VTM is the on-voltage specification for the optocoup-

ƪ ƫ
Triacs can be used to replace the centrifugal switch in ler.
capacitor start motors. The blocking voltage required of the The phase delay angle is
triac can be much greater than the line voltage would

qd + SIN*1 Ǹ2 V
V LINE
(1.2)

IG IL
G MEAN
MT1
RG DESIGN
∆I CAPABILITY
MT2
6σ 6σ
3σ 3σ
MT2

MT1 PROCESS WIDTH

G

Figure 6.1. Series Switch Figure 6.2. Designing for Probable Leakage

REV 1

Motorola Thyristor Device Data Theory and Applications

1.6–59
 STATIC VOLTAGE SHARING junction exceeds the rate of removal as temperature in-
creases, this process repeats until the leakage current is
Maximum blocking voltage capability results when the sufficient to trigger the thyristor on.
triacs share voltage equally. The blocking voltage can be DC blocking simplifies analysis. A design providing stable
dc or ac. A combination of both results when the triac dc operation guarantees ac performance. AC operation
switches the start winding in capacitor start motors. In the allows smaller heatsinks.
simple series connection, both triacs operate with an The last term in the stability equation is the applied
identical leakage current which is less than that of either voltage when the load resistance is low and the leakage
part operated alone at the same voltage. The voltages causes negligible voltage drop across it. The second term
across the devices are the same only when their leakage is the thermal resistance from junction to ambient. The first
resistances are identical. Dividing the voltage by the term describes the behavior of leakage at the operating
leakage current gives the leakage resistance. It can range conditions. For example, if leakage doubles every 10°C, a
from 200 kohm to 2000 megohm depending on device triac operating with 2 mA of leakage at 800 Vdc with a
6°C/W thermal resistance is stable because

@ @
characteristics, temperature, and applied voltage.
Drawing a line corresponding to the measured series
leakage on each device’s characteristic curve locates its
2 mA
10°C
6°C
W
800 V + 0.96
operating point. Figure 3a shows the highest and lowest
leakage units from a sample of 100 units. At room Operating two triacs in series improves thermal stability.
temperature, a leakage of 350 nA results at 920 Volts. The When two devices have matched leakages, each device
lowest leakage unit blocks at the maximum specified value sees half the voltage and current or 1/4 of the power in a
of 600 Volts, while the highest blocks 320 Volts. A 50 single triac. The total leakage dissipation will approach
percent boost results. half that of a single device operated at the same voltage.
Figure 3b shows the same two triacs at rated TJmax. The additional voltage margin resulting from the higher
The magnitude of their leakage increased by a factor of total blocking voltage reduces the chance that either
about 1000. Matching between the devices improved, device will operate near its breakdown voltage where the
allowing operation to 1100 Volts without exceeding the 600 leakage current increases rapidly with small increments in
Volt rating of either device. voltage. Higher voltage devices have lower leakage
Identical case temperatures are necessary to achieve currents when operated near breakdown. Consequently,
good matching. Mounting the devices closely together on the highest breakover voltage unit in the pair will carry the
a common heatsink helps. greatest proportion of the burden. If the leakage current is
A stable blocking condition for operation of a single triac large enough to cause significant changes in junction
with no other components on the heatsink results when temperature, (∆TJ = φJC PD), the effect will tend to balance

@ @
the voltage division between the two by lowering the
dIMT
dT J
dT J
dP J
dP J
dI MT
t1 (2.0)
leakage resistance of the hotter unit. If the leakage
mismatch between the two is large, nearly all the voltage
will drop across one device. As a result there will be little
Thermal run-away is a regenerative process which occurs benefit connecting two in series.
whenever the loop gain in the thermal feedback circuit Series blocking voltage depends on leakage matching.
reaches unity. An increase in junction temperature causes Blocking stability depends on predictable changes in leakage
increased leakage current and higher power dissipation. with temperature. Leakage has three components.
Higher power causes higher junction temperature which in
turn leads to greater leakage. If the rate of heat release at the

HIGH

LOW
∆IL

LOW

HIGH

(a) 100 V/ 100 nA/ 25°C (b) 100 V/ 100 µA/ 125°C

Figure 6.3. Leakage Matching versus Temperature

Theory and Applications Motorola Thyristor Device Data

1.6–60
Surface Leakage series operation, devices should be operated at least 100
Passivation technique, junction design, and cleanliness Volts below their rating.
determine the size of this component. It tends to be small Figure 4 shows the leakage histogram for a triac sample
and not very dependent on temperature. operated at two different voltages. The skewedness in the
high-voltage distribution is a consequence of some of the
Diffusion Leakage sample operating near breakdown.
Measurements with 1 volt reverse bias show that this
component is less than 10 percent of the total leakage for HEATSINK SELECTION
allowed junction temperatures. It follows an equation of the Solving equations (2.0) and (2.3) for the thermal
form: resistance required to prevent runaway gives:

and doubles about every 10°C. Its value can be estimated

I T e*(qvńkT) (2.1) θJA
@@
t A 1V i
where θJA is thermal resistance, junction to ambient, in
(3.0)

by extrapolating backward from high temperature data °C/W, A = 0.08 at T J = 125°C, V = rated V DRM , and i = rated
points. IDRM.
θJA must be low enough to remove the heat resulting
Depletion Layer Charge Generation
from conduction losses and insure blocking stability. The
This component is a result of carriers liberated from within
latter can be the limiting factor when circuit voltages are
the blocking junction depletion layer. It grows with the square
high. For example, consider a triac operated at 8 amps
root of the applied voltage. The slope of the leakage versus
(rms) and 8 Watts. The allowed case temperature rise at
applied voltage is the mechanism allowing for series opera-
25° ambient is 85°C giving a required θCA (thermal
tion with less than perfect leakage matching. Predictable
resistance, case to ambient) of 10.6°C/W. Allowing 1°C/W
diffusion processes determine this leakage. At temperatures
for θCHS (thermal resistance, case to heatsink) leaves
between 70 and 150°C it is given by:
9.6°C/W for θSA (thermal resistance, heatsink to ambient).
i T e * kTE (2.2) However, thermal stability at 600 V and 2 mA IDRM requires
θJA = 10.4°C/W. A heatsink with θSA less than 7.4°C/W is
where E = 1.1 eV, k = 8.62E – 5 eV/k, T = degrees Kelvin, needed, given a junction to case thermal resistance of
and k = 8.62 x 10 – 5 eV/k. 2°C/W.
It is useful to calculate the percentage change in leakage The operation of devices in series does not change the
current with temperature: coefficient A. When matching and thermal tracking is
perfect, both devices block half the voltage. The leakage
A + 1 di
i dT J
+ kTE2 + 0.08 + 8%
°C
current and power divide by half and the allowed θJA for
blocking stability increases by 4.
Low duty cycles allow the reduction of the heatsink size.
The coefficient A was evaluated on 3 different die size
The thermal capacitance of the heatsink keeps the
triacs by curve fitting to leakage measurements every 10°
junction temperature within specification. The package
from 70 to 150°C. Actual values measured 0.064 at 125° and
time constant (Cpkg RθJA) is long in comparison with the
0.057 at 150°.
thermal response time of the die, causing the instanta-
Deviations from this behavior will result at voltages and
neous TJ to rise above the case as it would were the
temperatures where leakage magnitude, current gain, and
semiconductor mounted on an infinite heatsink. Heatsink
avalanche multiplication aid unwanted turn-on. Sensitive
design requires estimation of the peak case temperature
gate triacs are not recommended for this reason.
and the use of the thermal derating curves on the data
DERATING AND LEAKAGE MATCHING sheet. The simplest model applies to a very small heatsink
which could be the semicondutor package itself. When θSA
Operation near breakdown increases leakage mismatch is large in comparison with θCHS, it is sufficient to lump both
because of the effects of avalanche multiplication. For the package and heatsink capacitances together and treat
20 them as a single quantity. The models provide good results
18 when the heatsink is small and the thermal paths are short.
650 V
PERCENT (SAMPLE SIZE = 100)

16
Model C, Figure 5 is a useful simplification for low duty
550 V cycle applications. Increasing heatsink mass adds thermal
14 capacitance and reduces peak junction temperature.
TJ = 25°C
12 Heatsink thermal resistance is proportional to surface area
10 and determines the average temperature.
8 q SA + 32.6 A(*0.47) (3.1)
6
where A = total surface area in square inches, θSA =
4
thermal resistance sink to ambient in °C/W.
2 Analysis of heatsink thermal response to a train of periodic
pulses can be treated using the methods in Motorola
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 application note AN569 and Figure 6. For example:

Figure 6.4. Normalized Leakage (Mean = 1.0)

Motorola Thyristor Device Data Theory and Applications

1.6–61
 θCA

Pd CPKG θCA Pd θCA CPKG

ton TC TC

TA TA

(a.) Standard Thermal Analogue For a Thyristor (b.) Equivalent Circuit For (a)
in Free Air
In Circuit (B): In terms of measurable temperatures:
The steady state case temperature is given by DTCpk
(5.0) TCSS + P d q CA )
TA in °C (5.3) r(t on) +
DTCSS
where Pd = Applied average power, watts
θCA = Case to ambient thermal resistance, °C/W In model (b.) this is
TA = ambient temperature, °C
The package rises toward the steady state temperature expo- (5.4) r(t on) + (1 * e*tonńt)
nentially with time constant
Solving 5-4 for the package capacitance gives

(5.1) t + q CA C PKG, seconds (5.5) C PKG + (θCA In*(1ton* r(ton))

where Cpkg = HM, Joules/°C Use simplified model C when
t on tt t
H = Specific heat, calories/(gm S °C)

DTC pk tt DTCSS
M = Mass in grams
and 1 Calorie = 4.184 Joule
1 Joule = 1 Watt S Sec

The case temperature rise above ambient at the end of

power pulse is:

(5.2) DTCpk + DTCSS(1 * e*tonńt) Pd

CPKG
TC
where DTC pk + * TA
TC
pk
DTCSS + TCSS * TA
To account for thermal capacity, a time dependent factor r(t) is TA
applied to the steady state case-to-ambient thermal resis-
tance. The package thermal resistance, at a given on-time,
is called transient thermal resistance and is given by: (c.) Simplified Model
R qCA (ton) + r(ton) qCA
where r(ton) = Unitless transient thermal impedance
(5.6) TC + PCdPKG
ton
) TA
coefficient.

Figure 6.5. Transient Thermal Response For a Single

Power Pulse
Assume the case temperature changes by 40°C for a TC TA * + 175-25 + 30°CńW
single power pulse of 66.67 W and 3 s duration. Then from PD 5
equation (5.6):

+ (66.7 Watts)40°C(3 seconds) + 5 Joules

The application requires a 3 s on-time and 180 s period at
C pkg 66.7 W. Then
°C
The heatsink thermal resistance can be determined by P avg + (66.7 W) (3ń180) + 1.111 W
applying dc power, measuring the final case temperature,
and using equation (5.0).

Theory and Applications Motorola Thyristor Device Data

1.6–62
 Nth N+1 IDRM (T2) I2
PULSE PULSE T2
Pd R2
ton
∆IL
VS
IDRM (T1)
tp I1
PAVG R1 V1
T1
0

DTC (N ) 1) + [P AVG ) (Pd * P AVG) r (ton ) t p) ) P d r (ton)

* Pd r (tp)]qCA V1 + RV1 S)RR1 2 ) DRI1LR)1RR22
Where ∆ TC (N + 1) = maximum rise above ambient
Pd = applied average power within a pulse Let R1 = R (1 + p) and R2 = R (1 – p) where
PAV G = average power within a period R = Nominal resistor value
r(ton + tp) = time dependent factor for sum of ton p = 0.05 for 5% tolerance, etc.
and tp
r(ton) = time dependent factor for ton x 2 VDRM * VS (1 ) p)
DI (1 * p2)
R
r(tp) = time dependent factor for tp L
Worst case becomes:

and IDRM (T1) = 0; IDRM (T2) = Spec. max. value

Figure 6.6. Steady State Peak Case Temperature Rise ∆IL = Spec. Max. Value
Using equation (5.3), the theoretical steady state case
temperature rise is:
T CSS * TA + (66.7 W) (30°CńW) + 2000°C Figure 6.7. Maximum Allowed Resistor for Static
Voltage Sharing
and

R(t on) + R (3 s) + (40°C measured rise)ń2000 + 0.02 step is to statistically characterize the product at maximum
From equation (5.4) and (5.1): temperature. Careful control of the temperature is critical

+ (1 * e*180ń150) + .6988
because leakage depends strongly on it.
R (T p) The process width is the leakage span at plus or minus

R (t on ) Tp) + (1 * 1 *183ń150) + .7047

3 standard deviations (sigma) from the mean. To minimize
the probability of out of spec parts, use a design capability
index (Cp) of 2.0.
+ (design DI)ń(process width)
Then from Figure 6:
delta TC = (1.111 + 46.225 + 1.333 – 46.61) 30 = 61.8°C Cp (4.0)
If the ambient temperature is 25°C, TC = 87°C. Cp + (12 sigma)ń(6 sigma)

COMPENSATING FOR MAXIMUM Figure 2 and Figure 7 describe this. Substituting delta IL
SPECIFIED LEAKAGE at 6 sigma in Figure 7 gives the resistor value. The
required power drops by about 4.
Identical value parallel resistors around each triac will Theoretically there would be no more than 3.4 triacs per
prevent breakdown resulting from mismatched leakages. million exceeding the design tolerance even if the mean
Figure 7 derives the method for selecting the maximum value of the leakage shifted by plus or minus 1.5 sigma.
allowed resistor size. A worst case design assumes that
the series pair will operate at maximum T J and that one of
the triacs leaks at the full specified value while the other
has no leakage at all. A conservative design results when
SELECTING RESISTORS
the tolerances in the shunt resistors place the highest
possible resistor across the low leakage unit and the Small resistors have low voltage ratings which can impose
lowest possible resistor around the high leakage unit. a lower constraint on maximum voltage than the triac. A
This method does not necessarily provide equal voltage common voltage rating for carbon resistors is:
balancing. It prevents triac breakover. Perfect voltage
sharing requires expensive high-wattage resistors to Rated Power (W) Maximum Voltage (V)
provide large bleeder currents. 1/4 Watt 250 Volts
1/2 350
COMPENSATION FOR PROBABLE LEAKAGE 1 500
2 750
Real triacs have a leakage current greater than zero and less
than the specified value. Knowledge of the leakage distribution Series resistors are used for higher voltage.
can be used to reduce resistor power requirements. The first

Motorola Thyristor Device Data Theory and Applications

1.6–63
 I ACTUAL TRIAC
+ E RmaxRmax
ǒ Ǔ
Rmin IDRM MODEL
Let V DRM
) Rmin
E
TRIAC
E + VDRM 1 ) IImax
min

Rmax
R max + VIDRM
min
R min + VIDRM
max
(8.0)
VMT2 – 1

VDRM

(a) Equivalent Circuit (b) Model

Figure 6.8. Maximum Voltage Sharing Without

Shunt Resistor
OPERATION WITHOUT RESISTORS Dynamic matching without a snubber network depends on
Figure 8 derives the method for calculating maximum equality of the thyristor self capacitance. There is little
operating voltage. The voltage boost depends on the values variation in junction capacitance. Device gain variations

ǒ ) Ǔ+
of Imin and Imax. For example : introduce most of the spread in triac performance.
The blocking junction capacitance of a thyristor is a
131 mA declining function of dc bias voltage. Mismatch in static
1 1.19
683 mA blocking voltage will contribute to unequal capacitances.
However, this effect is small at voltages beyond a few volts.
A 19 percent voltage boost is possible with the 6 sigma
The attachment of a heatsink at the high-impedance node
design. Testing to the measured maximum and minimum of
formed by connection of the triac main-terminals can also
the sample allows the boost to approach the values given in
contribute to imbalance by introducing stray capacitance to
Table 1.
ground. This can be made insignificant by adding small
)
(1 0.835 1.228) ń1.68 + capacitors in parallel with the triacs. Snubbers will serve the
same purpose.
Table 1. Normalized leakage and voltage boost factor. 10,000
(Mean = 1.0) 9
8
7
Voltage (V) 550 650 550 550 550 550 550
6
TJ (°C) 25 25 100 125 125 150 150 5
Rshunt — — — — 1.5M 1.5M 510K 4
Sample Size 100 100 16 16 16 16 16 3 1
EXPONENTIAL STATIC dv/dtS (V/ µs)

Maximum 1.315 1.591 1.187 1.228 1.123 1.346 1.186

2 R C
Minimum 0.729 0.681 0.840 0.835 0.920 0.820 0.877
Sigma 0.116 0.172 0.106 0.113 0.055 0.132 0.084 2
Sample Boost 1.55 1.43 1.71 1.68 1.82 1.61 1.74 1000
9 R C
6 Sigma Boost 1.18 1.00 1.22 1.19 1.50 1.12 1.33 8
7
6 1
COMPENSATING FOR SURFACE LEAKAGE 5
4
A small low power shunt resistance will provide nearly R = 270 kΩ
3 C = 1000 pF
perfect low temperature voltage sharing and will improve Vpk = 1000 V
high temperature performance. It defines the minimum
leakage current of the parallel triac-resistor combination. The 2
design method in Figure 8 can be used by adding the resistor
current to the measured maximum and minimum leakage

ǒǓ
currents of the triac sample. This is described in Table 1. 100
0 15 30 45 60 75 90 105 120 135 150
JUNCTION TEMPERATURE (TJ) °C
SERIES dV

ǒǓ
dt s
Figure 6.9. Exponential Static dV/dt, Series
The series connection will provide twice the dV MAC15-4 Triacs
dt s
capability of the lowest device in the pair (Figure 9).

Theory and Applications Motorola Thyristor Device Data

1.6–64
 800 Exponential ǒǓ
dV tests performed at 1000 V and less
dt s
than 2 kV/µs showed that turn-on of the series pair can occur
700
MAXIMUM STEP VOLTAGE (V)

because of breakdown or dV . The former was the limiting

600 dt
factor at junction temperatures below 100°C. Performance
500
improved with temperature because device gain aided
400 voltage sharing. The triac with the highest current gain in the
V pair is most likely to turn-on. However, this device has the
300 largest effective capacitance. Consequently it is exposed to
200
dV
dt
u 10 kV ms ń less voltage and dV . At higher temperatures, rate effects
f = 10 Hz dt
100 pw = 100 µs dominated over voltage magnitudes, and the capability of the
0 series pair fell. dV performance of the series devices was
0 20 40 60 80 100 120 140 160 dt
always better than that of a single triac alone.
TJ (°C)
Figure 6.10. Step Blocking Voltage VS TURNOFF
TJ (Unsnubbed Series Triacs)
Process tolerances cause small variations in triac turn-off
Triacs can tolerate very high rates of voltage rise when the time. Series operation will allow most of the reapplied
peak voltage magnitude is below the threshold needed to blocking voltage to appear across the faster triac when a
trigger the device on. This behavior is a consequence of the dynamic voltage sharing network is not used.
voltage divider action between the device collector and Figure 11 describes the circuit used to investigate this
gate-cathode junction capacitances. If the rise-time is made behavior. It is a capacitor discharge circuit with the load
short in comparison with minority carrier lifetime, voltage and series resonant at 60 Hz. This method of testing is desirable
displaced charge determine whether the device triggers on because of the reduced burn and shock hazard resulting
or not. Series operation will extend the range of voltage and from the limited energy storage in the load capacitor.
load conditions where a static dV snubber is not needed. The triacs were mounted on a temperature controlled
dt hotplate. The single pulse non-repetitive test aids junction
Figure 10 graphs the results of measurements on two
temperature control and allows the use of lower power rated
series connected triacs operated without snubbers. The
components in the snubber and load circuit.
series connection doubled the allowed step voltage. How-
ever, this voltage remained far below the combined 1200 V
breakover voltage of the pair.

PEARSON 301X CL
1 – PROBE
15K CL
13K G2 2W 510 MT1, T2 MT1

TRIAD C30X 50H, 3500 Ω

15K
Rs LL
2W G2 270K
S1 910
MT2 T2 2W S2
S4A MOC3081 G2 Cs Hg
11 2.2 Meg RELAY
+ Ω 910
100 V 2W 1/2W
– MT2
Cs
G1 1N4001 G1 270K
S1 2.2 Meg T1 2W
+ S3
20 µF PUSH TO MT1 Rs
MOC3081

TEST G1 CL VCC
200 V
S4B 1.5 kV
510
MT1, T1
(a) Triac Gate Circuit S1 = GORDES MR988 REED WOUND (c) Load Circuit
WITH 1 LAYER AWG #18
LL = 320 MHY
CL = 24 µFD, NON-POLAR

REVERSE S4 AND VCC TO

CHECK
OPPOSITE POLARITY.
(b) Optocoupler Gate Circuit

Figure 6.11. ǒǓ
dV Test Circuit
dt c
Motorola Thyristor Device Data Theory and Applications
1.6–65
 Snubberless turn-off at 1200 V and 320 milli-henry Designs that satisfy the first two objectives will usually
resulted in 800 V peak and 100 V/µs. Although this test provide capacitor values above the minimum size. Select the
exceeded the ratings of the triacs, they turned off snubber for a satisfactory compromise between voltage and
successfully. dV . Then check the capacitor to insure that it is sufficiently
Snubberless operation is allowable when: dt
1. The total transient voltage across both triacs does not large.
exceed the rating for a single device. This voltage de- Snubber designs for static, commutating, and combined
pends on the load phase angle, self capacitance of the dV stress are shown in Table 2. Circuits switching the line or
load and triac, damping constant, and natural resonance dt

ǒǓ
a charged capacitor across a blocking triac require the
of the circuit.
addition of a series snubber inductor. The snubber must be
2. The total dV across the series combination does designed for maximum dV with the minimum circuit induc-
dt c
dt
not exceed the capability of a single device. tance. This contraint increases the required triac blocking
Maximum turn-off voltage capability and tolerance for voltage.
variable loads requires the use of a snubber network to

ǒǓ ǒǓ
provide equal dynamic voltage sharing. Figure 12 and Figure Table 2. Snubber Designs
13 derives the minimum size snubber capacitor allowed. It is
dV dV
determined by the recovery charge of the triac. Measure- Type dt c dt s Both
ments in fast current crossing applications suggest that the
reverse recovery charge is less than 2 micro-coulombs. L (mh) 320 0.4 320
Recovery currents cannot be much greater than IH or IGT, or RL Ohm 8 0 8
the triac would never turn-off. Recovery can be forward, Rs Ohm 1820 48 48
reverse, or near zero current depending on conditions.
Cs (µf) 0.5 0.5 0.5
Snubber design for the series switch has the following
objectives: Damping Ratio 1.14 0.85 .035
• Controlling the voltage peak. Resonant charging will mag- Vstep (V) 1200 1200 750
nify the turn-off voltage. Vpk (V) 1332 1400 1423
• Controlling the voltage rate. Peak voltage trades with volt-
tpk (µs) 768 29.8 1230
age rate.
• Equalizing the voltage across the series devices by pro- dV (V/µs) 4.6 103 1.3
viding for imbalance in turn-off charge. dt
dV
Note: Divide Rs and by 2, multiply Cs by 2 for each triac.
dt
VMT2-1
AND dl CAPABILITY

ǒǓ
IMT2
C2
dt
V2 dI
T2 Q + ∆Q Q2
dt c The hazard of thyristor damage by dl overstress is greater
dt
VS φ
when circuit operating voltages are high because dl is
t
∆Q dt
VDRM ∆Q
T1 C1 Q IRRM (dv/dt)c proportional to voltage. Damage by short duration transients
Q 1
VMT2-1 is possible even though the pulse is undetectable when
observed with non-storage oscilloscopes. This type of
damage can be consequence of snubber design, transients,
or parasitic capacitances.

ǒǓ
Worst case:
C2 + C(1 ) p); C1 + C(1 * p); Q1 + 0; Q2 + DQ A thyristor can be triggered on by gate current, exceeding

where C = Nominal value of capacitor its breakdown voltage, or by exceeding its dV capability.
dt s
and p = 0.1 for 10% tolerance, etc.
In the latter case, a trigger current is generated by charging of
∆Q = Reverse recovery charge
the internal depletion layer capacitance in the device. This
Note that T1 has no charge while T2 carries full effect aids turn-on current spreading, although damage can
recovery charge.
still occur if the rate of follow on dl is high. Repetitive
dt
For the model shown above, operation off the ac line at voltages above breakdown is a

+ QC11 ) QC22 + C(1Q*1 p) ) QC(11 *)Dp)Q

worst case condition. Quadrant 3 has a slightly slower gated
VS turn-on time, increasing the chance of damage in this

C y 2 VDRM *DQVS(1 ) p)

Figure 6.12. Minimum Capacitor Size for Dynamic

Voltage Sharing

Theory and Applications Motorola Thyristor Device Data

1.6–66
direction. Higher operating voltages raise power density and Test results showed that operation of the triac switch was
local heating, increasing the possibility of die damage due to safe as long as the rate of current rise was below 200 A/µs.
hot-spots and thermal run-away. This was true even when the devices turned on because of
breakover. However, a 0.002 µf capacitor with no series
Ideally, turn-on speed mismatch should not be allowed to
limiting impedance was sufficient to cause damage in the Q3
force the slower thyristor into breakdown. An RC snubber
firing polarity.
across each thyristor prevents this. In the worst case, one
Circuit malfunctions because of breakover will be tempo-
device turns on instantly while the other switches at the
rary if the triac is not damaged. Test results suggest that there
slowest possible turn-on time. The rate of voltage rise at the
will be no damage when the series inductance is sufficient to
slower device is roughly dV
dt 2L
+
V IR s
, where VI is the hold dl/dt to acceptable values. Highly energetic transients
such as those resulting from lightning strikes can cause
maximum voltage across L. This rate should not allow the damage to the thyristor by I2t surge overstress. Device
voltage to exceed VDRM in less than Tgt to prevent breakover. survival requires the use of voltage limiting devices in the
But what if the thyristors are operated without a snubber, or if
avalanche occurs because of a transient overvoltage condi- circuit and dV limiting snubbers to prevent unwanted turn-on.
dt
tion? Alternatively, a large triac capable of surviving the surge can
The circuit in Figure 13 was constructed to investigate be used.
this behavior. The capacitor, resistor, and inductor create
a pulse forming network to shape the current wave. The
initial voltage on the capacitor was set by a series string of T2 lpk
sidac bidirectional breakover devices. IH1
∆Q
∆Q
IH2

T1 ωt = 0 t1 t2
T106-6
RE1 R
L *S1 MT1
NON-INDUCTIVE G DQ

ŕ
5K for turn-off at I H
200W 1K t2
2W
DQ + + pk
w (cos wt1 * cos wt2)
I
I pk SINwt dt
0–6 kV CARBON MT2
1/2A
60 Hz t1
QTY = 6 TO 16 MKP1V130 MT2
I H1+ Ipk Sinwt1
thus t 1 + 1 Sin*1
C
I H1
G MT1
PEARSON
w I pk

Worst case : I H2 + 0; f 2 + wt 2 + p
411 I
PROBE

Ǹ ǒ Ǔ ȣȧȤ
DQ + w ) cos[SIN*1 IIH1
I pk
Vci C L R dl/dt Rejects (1 ])

ȡȧ )
V µFD µHY Ω A/µs Tested pk
1000 4.06 3.4 5.7 100 0/100
2
DQ + w
Ȣ *
1900* 1.05 7.9 5.7 179 0/195 I pk IH1
1 I
1500 0.002 0.3 10 3000 3/10 Ipk

* Open S1 to test breakover dl/dt

Figure 6.13. dl/dt Test Circuit Figure 6.14. Forward Recovery Charge for Turn-Off at lH

Motorola Thyristor Device Data Theory and Applications

1.6–67
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

AN1048
RC Snubber Networks For Thyristor
Power Control and Transient Suppression
By George Templeton
Thyristor Applications Engineer

INTRODUCTION
A
RC networks are used to control voltage transients that A
could falsely turn-on a thyristor. These networks are called
IB IA
snubbers. P
V
PE

The simple snubber consists of a series resistor and CJ

PNP
I1 P IJ IC NB
capacitor placed around the thyristor. These components CJ
N
P
CJ C
along with the load inductance form a series CRL circuit. IC
N
I2 dv
IJ G PB
Snubber theory follows from the solution of the circuit’s NPN G
dt
t
differential equation. IB
N NE
IK
Many RC combinations are capable of providing accept- CJ
dV

able performance. However, improperly used snubbers can K IA +1* )

dt
(aN ap)
cause unreliable circuit operation and damage to the K
+ 1*(aN)ap)
TWO TRANSISTOR MODEL CJ
OF CEFF
semiconductor device. INTEGRATED
SCR STRUCTURE
Both turn-on and turn-off protection may be necessary

ǒǓ
for reliability. Sometimes the thyristor must function with a
range of load values. The type of thyristors used, circuit
configuration, and load characteristics are influential. dV
Figure 6.1. Model

ǒǓ
Snubber design involves compromises. They include cost, dt s
voltage rate, peak voltage, and turn-on stress. Practical
solutions depend on device and circuit physics. CONDITIONS INFLUENCING dV
dt s

STATIC dV Transients occurring at line crossing or when there is no

dt initial voltage across the thyristor are worst case. The
collector junction capacitance is greatest then because the
WHAT IS STATIC dV ? depletion layer widens at higher voltage.
dt Small transients are incapable of charging the
Static dV is a measure of the ability of a thyristor to retain a self-capacitance of the gate layer to its forward biased
dt threshold voltage (Figure 2). Capacitance voltage divider
blocking state under the influence of a voltage transient.

ǒǓ
180

160
dV DEVICE PHYSICS
dt s MAC 228-10 TRIAC
140
TJ = 110°C
STATIC dV (V/ µs)

Static dV turn-on is a consequence of the Miller effect and 120

dt
regeneration (Figure 1). A change in voltage across the 100

ǒǓ
dt

junction capacitance induces a current through it. This

80
current is proportional to the rate of voltage change dV . It
dt 60
triggers the device on when it becomes large enough to raise
40
the sum of the NPN and PNP transistor alphas to unity.
20
0 100 200 300 400 500 600 700 800

ǒǓ
PEAK MAIN TERMINAL VOLTAGE (VOLTS)

dV
Figure 6.2. Exponential versus Peak Voltage
dt s

REV 1

Theory and Applications Motorola Thyristor Device Data

1.6–68
action between the collector and gate-cathode junctions and
built-in resistors that shunt current away from the cathode IMPROVING ǒdVǓ
dt s
emitter are responsible for this effect.
Static dV does not depend strongly on voltage for Static dV can be improved by adding an external resistor
dt dt
operation below the maximum voltage and temperature from the gate to MT1 (Figure 4). The resistor provides a path
rating. Avalanche multiplication will increase leakage current for leakage and dV induced currents that originate in the
dt
and reduce dV capability if a transient is within roughly 50 drive circuit or the thyristor itself.
dt
volts of the actual device breakover voltage.
140
A higher rated voltage device guarantees increased dV at
dt 120
lower voltage. This is a consequence of the exponential
MAC 228-10
rating method where a 400 V device rated at 50 V/µs has a 100 800 V 110°C
higher dV to 200 V than a 200 V device with an identical

STATIC dV (V/ µs)

dt 80
rating. However, the same diffusion recipe usually applies for

dt
all voltages. So actual capabilities of the product are not 60
much different.
40 RINTERNAL = 600 Ω
Heat increases current gain and leakage, lowering ǒdVǓ ,
dt s
the gate trigger voltage and noise immunity (Figure 3). 20

0
170 10 100 1000 10,000
150 GATE-MT1 RESISTANCE (OHMS)

130
MAC 228-10 ǒdVǓ
Figure 6.4. Exponential dt s versus
VPK = 800 V
STATIC dV (V/ µs)

110 Gate to MT1 Resistance

Non-sensitive devices (Figure 5) have internal shorting
90
dt

resistors dispersed throughout the chip’s cathode area. This

70 design feature improves noise immunity and high tempera-
ture blocking stability at the expense of increased trigger and
50
holding current. External resistors are optional for non-sensi-
30 tive SCRs and TRIACs. They should be comparable in size
to the internal shorting resistance of the device (20 to 100
10
25 40 55 70 85 100 115 130 145
ohms) to provide maximum improvement. The internal
resistance of the thyristor should be measured with an
TJ, JUNCTION TEMPERATURE (°C)
ohmmeter that does not forward bias a diode junction.
dVǓ
Figure 6.3. Exponential ǒ versus Temperature
dt s 2200

2000
ǒdVǓ FAILURE MODE 1800
MAC 16-8
dt s VPK = 600 V
STATIC dV (V/ µs)

1600
Occasional unwanted turn-on by a transient may be
acceptable in a heater circuit but isn’t in a fire prevention
dt

1400
sprinkler system or for the control of a large motor. Turn-on is
destructive when the follow-on current amplitude or rate is 1200
excessive. If the thyristor shorts the power line or a charged 1000
capacitor, it will be damaged.
800
Static dV turn-on is non-destructive when series imped-
dt 600
ance limits the surge. The thyristor turns off after a half-cycle 50 60 70 80 90 100 110 120 130
of conduction. High dV aids current spreading in the thyristor, TJ, JUNCTION TEMPERATURE (°C)
dt
ǒdVǓ
improving its ability to withstand dI. Breakdown turn-on does Figure 6.5. Exponential dt s versus
dt Junction Temperature
not have this benefit and should be prevented.

Motorola Thyristor Device Data Theory and Applications

1.6–69
 Sensitive gate TRIACs run 100 to 1000 ohms. With an capacitor without excessive delay, but it does not need to
supply continuous current as it would for a resistor that
external resistor, their dV capability remains inferior to
dt
non-sensitive devices because lateral resistance within the increases dV the same amount. However, the capacitor

ǒǓ
dt
gate layer reduces its benefit. does not enhance static thermal stability.
Sensitive gate SCRs (IGT 200 µA) have no built-in t The maximum dV improvement occurs with a short.
resistor. They should be used with an external resistor. The

ǒǓ
dt s
recommended value of the resistor is 1000 ohms. Higher Actual improvement stops before this because of spread-
ing resistance in the thyristor. An external capacitor of
values reduce maximum operating temperature and dV
dt s about 0.1 µF allows the maximum enhancement at a
(Figure 6). The capability of these parts varies by more than higher value of RGK.
100 to 1 depending on gate-cathode termination.

10
MEG MCR22-2
ǒǓ One should keep the thyristor cool for the highest
dV . Also devices should be tested in the application
dt s
circuit at the highest possible temperature using thyristors
TA = 65°C
GATE-CATHODE RESISTANCE (OHMS)

with the lowest measured trigger current.

A
10
1
V G TRIAC COMMUTATING dV
MEG
K dt

WHAT IS COMMUTATING dV ?
dt
100
K The commutating dV rating applies when a TRIAC has
dt
been conducting and attempts to turn-off with an inductive
load. The current and voltage are out of phase (Figure 8).
10K The TRIAC attempts to turn-off as the current drops below
0.001 0.01 0.1 1 10 10 the holding value. Now the line voltage is high and in the
dV ń opposite polarity to the direction of conduction. Successful

ǒǓ
STATIC (V ms) 0
dt turn-off requires the voltage across the TRIAC to rise to the
instantaneous line voltage at a rate slow enough to prevent
Figure 6.6. Exponential dV versus retriggering of the device.
dt s
Gate-Cathode Resistance

130
VOLTAGE/CURRENT

120 R L
MAC 228-10 i 2
110 800 V 110°C VLINE G VMT2-1
STATIC dV (V/ µs)

ǒǓ
1
100
VMT2-1

dI
dt

90 PHASE dt c
ANGLE
80 Φ

ǒǓ
TIME
TIME
70
dV
i VLINE dt c

ǒǓ
60
0.001 0.01 0.1 1

ǒǓ
GATE TO MT1 CAPACITANCE (µF) dV
Figure 6.8. TRIAC Inductive Load Turn-Off
dt c

ǒǓ
dV
Figure 6.7. Exponential dt versus Gate
s
to MT1 Capacitance dV DEVICE PHYSICS
dt c

A gate-cathode capacitor (Figure 7) provides a shunt path A TRIAC functions like two SCRs connected in inverse-
for transient currents in the same manner as the resistor. It parallel. So, a transient of either polarity turns it on.
also filters noise currents from the drive circuit and enhances There is charge within the crystal’s volume because of
the built-in gate-cathode capacitance voltage divider effect. prior conduction (Figure 9). The charge at the boundaries of
The gate drive circuit needs to be able to charge the

Theory and Applications Motorola Thyristor Device Data

1.6–70
 the volume of the device (Figure 10). If the reverse recovery
G MT1 current resulting from both these components is high, the
TOP lateral IR drop within the TRIAC base layer will forward bias
the emitter and turn the TRIAC on. Commutating dV
dt
N N N N
P capability is lower when turning off from the positive direction
of current conduction because of device geometry. The gate
Previously
Conducting Side is on the top of the die and obstructs current flow.
N Recombination takes place throughout the conduction
period and along the back side of the current wave as it

ǒǓ
+ – declines to zero. Turn-off capability depends on its shape. If
N N N dI is
the current amplitude is small and its zero crossing
dt c
REVERSE RECOVERY
CURRENT PATH
MT2

LATERAL VOLTAGE
DROP
STORED CHARGE
FROM POSITIVE
CONDUCTION
low, there is little volume charge storage and turn-off

becomes limited by dV . At moderate current amplitudes,

dt s
ǒǓ
the volume charge begins to influence turn-off, requiring a
Figure 6.9. TRIAC Structure and Current Flow
at Commutation

ǒǓ crossing, dV
dt c
ǒǓ
larger snubber. When the current is large or has rapid zero

has little influence. Commutating dI and

dt

ǒǓ ǒǓ
the collector junction depletion layer responsible for dV is delay time to voltage reapplication determine whether turn-off
dt s
will be successful or not (Figures 11, 12).
also present. TRIACs have lower dV than dV
dt c dt s
because of this additional charge.
The volume charge storage within the TRIAC depends on E

ǒǓ
V
the peak current before turn-off and its rate of zero crossing
MAIN TERMINAL VOLTAGE (V)

ǒǓ
dI . In the classic circuit, the load impedance and line
dt c

frequency determine dI . The rate of crossing for sinusoi-

dt c
dal currents is given by the slope of the secant line between E

ǒǓ+
the 50% and 0% levels as:

dI
dt c
6 fI TM
1000
A ms ń
VT
where f = line frequency and ITM = maximum on-state current
0 td TIME
in the TRIAC.
Turn-off depends on both the Miller effect displacement
Figure 6.11. Snubber Delay Time
current generated by dV across the collector capacitance
dt
and the currents resulting from internal charge storage within
0.5
NORMALIZED DELAY TIME

0.2
0.1

ǒǓ
0.2
VOLTAGE/CURRENT

(t d* = W0 td)

di 0.05

ǒǓ
0.1
dt c
dV 0.05 0.02
dt c RL = 0
0.03 M=1 0.01
TIME 0.02 IRRM = 0
0 VT
0.005
E
0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1
VMT2-1 CHARGE DUE TO
dV/dt DAMPING FACTOR
VOLUME IRRM Figure 6.12. Delay Time To Normalized Voltage
STORAGE
CHARGE

Figure 6.10. TRIAC Current and Voltage at

Commutation
Motorola Thyristor Device Data Theory and Applications
1.6–71
CONDITIONS INFLUENCING dV ǒǓ IMPROVING dV ǒǓ
ǒǓ ǒǓ
dt c dt c

Commutating dV depends on charge storage and The same steps that improve dV aid dV except
dt dt s dt c
recovery dynamics in addition to the variables influencing
when stored charge dominates turn-off. Steps that reduce
static dV. High temperatures increase minority carrier the stored charge or soften the commutation are necessary
dt
life-time and the size of recovery currents, making turn-off then.
more difficult. Loads that slow the rate of current zero- Larger TRIACs have better turn-off capability than smaller
crossing aid turn-off. Those with harmonic content hinder ones with a given load. The current density is lower in the
turn-off. larger device allowing recombination to claim a greater
proportion of the internal charge. Also junction temperatures
RS C are lower.
TRIACs with high gate trigger currents have greater
i turn-off ability because of lower spreading resistance in the

ǒǓ
gate layer, reduced Miller effect, or shorter lifetime.
LS
The rate of current crossing can be adjusted by adding a
dI commutation softening inductor in series with the load. Small
dt c DC MOTOR high permeability “square loop” inductors saturate causing

ǒu Ǔ
i – +
60 Hz R L no significant disturbance to the load current. The inductor
t resets as the current crosses zero introducing a large
L 8.3 ms
R inductance into the snubber circuit at that time. This slows
the current crossing and delays the reapplication of blocking
voltage aiding turn-off.
The commutation inductor is a circuit element that
Figure 6.13. Phase Controlling a Motor in a Bridge introduces time delay, as opposed to inductance, into the

Circuit Examples circuit. It will have little influence on observed dV at the

dt
Figure 13 shows a TRIAC controlling an inductive load in a device. The following example illustrates the improvement
bridge. The inductive load has a time constant longer than resulting from the addition of an inductor constructed by
the line period. This causes the load current to remain winding 33 turns of number 18 wire on a tape wound core
constant and the TRIAC current to switch rapidly as the line (52000-1A). This core is very small having an outside

ǒǓ
voltage reverses. This application is notorious for causing diameter of 3/4 inch and a thickness of 1/8 inch. The delay
time can be calculated from:

+ (N A BE10*8) where:
TRIAC turn-off difficulty because of high dI .
dt c
High currents lead to high junction temperatures and rates ts
of current crossing. Motors can have 5 to 6 times the normal
ts = time delay to saturation in seconds.
current amplitude at start-up. This increases both junction
B = saturating flux density in Gauss
temperature and the rate of current crossing, leading to
A = effective core cross sectional area in cm2
turn-off problems.
N = number of turns.
The line frequency causes high rates of current crossing in
400 Hz applications. Resonant transformer circuits are For the described inductor:
doubly periodic and have current harmonics at both the
primary and secondary resonance. Non-sinusoidal currents ts + (33 turns) (0.076 cm2 ) (28000 Gauss) (1 10 *8 )
can lead to turn-off difficulty even if the current amplitude is ń (175 V) + 4.0 ms.

ǒǓ
low before zero-crossing.
The saturation current of the inductor does not need to be
dV FAILURE MODE much larger than the TRIAC trigger current. Turn-off failure

ǒǓ
dt c will result before recovery currents become greater than this
value. This criterion allows sizing the inductor with the
dV failure causes a loss of phase control. Temporary following equation:
dt c
turn-on or total turn-off failure is possible. This can be
destructive if the TRIAC conducts asymmetrically causing a
Is + 0.4
H s ML
p N
where :
dc current component and magnetic saturation. The winding Hs = MMF to saturate = 0.5 Oersted
resistance limits the current. Failure results because of ML = mean magnetic path length = 4.99 cm.
+ +
excessive surge current and junction temperature. (.5) (4.99)
Is 60 mA.
.4 p 33

Theory and Applications Motorola Thyristor Device Data

1.6–72
 SNUBBER PHYSICS
100 µH 0.05
UNDAMPED NATURAL RESONANCE
340 V
w0 + ń
VOLTAGE

Ǹ I Radians second 0.1

0 10 µs µF V SENSITIVE
LC CIRCUIT

Resonance determines dV and boosts the peak capacitor + 700

dt
voltage when the snubber resistor is small. C and L are

V (VOLTS)
related to one another by ω02. dV scales linearly with ω0 0
dt
when the damping factor is held constant. A ten to one
reduction in dV requires a 100 to 1 increase in either – 700
dt
component. 0 10 20
TIME (µs)

Ǹ
DAMPING FACTOR

+ R2
Figure 6.14. Undamped LC Filter Magnifies and
ρ C
L Lengthens a Transient
dI
The damping factor is proportional to the ratio of the circuit dt
loss and its surge impedance. It determines the trade off
Non-Inductive Resistor
between dV and peak voltage. Damping factors between
dt The snubber resistor limits the capacitor discharge current
0.01 and 1.0 are recommended.
and reduces dI stress. High dI destroys the thyristor even
dt dt
The Snubber Resistor though the pulse duration is very short.
Damping and dV The rate of current rise is directly proportional to circuit
dt
When ρ t 0.5, the snubber resistor is small, and dV
dt
voltage and inversely proportional to series inductance. The
snubber is often the major offender because of its low
depends mostly on resonance. There is little improvement in inductance and close proximity to the thyristor.
dV for damping factors less than 0.3, but peak voltage and With no transient suppressor, breakdown of the thyristor
dt sets the maximum voltage on the capacitor. It is possible to
snubber discharge current increase. The voltage wave has a exceed the highest rated voltage in the device series
1-COS (θ) shape with overshoot and ringing. Maximum dV because high voltage devices are often used to supply low
dt voltage specifications.
occurs at a time later than t = 0. There is a time delay before The minimum value of the snubber resistor depends on the
the voltage rise, and the peak voltage almost doubles.
When ρ u 0.5, the voltage wave is nearly exponential in
type of thyristor, triggering quadrants, gate current amplitude,
voltage, repetitive or non-repetitive operation, and required
shape. The maximum instantaneous dV occurs at t = 0. life expectancy. There is no simple way to predict the rate of
dt current rise because it depends on turn-on speed of the
There is little time delay and moderate voltage overshoot.
thyristor, circuit layout, type and size of snubber capacitor,
When ρ u 1.0, the snubber resistor is large and dV
dt
and inductance in the snubber resistor. The equations in
Appendix D describe the circuit. However, the values
depends mostly on its value. There is some overshoot even
required for the model are not easily obtained except by
through the circuit is overdamped.
testing. Therefore, reliability should be verified in the actual
High load inductance requires large snubber resistors and
application circuit.
small snubber capacitors. Low inductances imply small
Table 1 shows suggested minimum resistor values esti-
resistors and large capacitors.
mated (Appendix A) by testing a 20 piece sample from the
Damping and Transient Voltages four different TRIAC die sizes.
Figure 14 shows a series inductor and filter capacitor
connected across the ac main line. The peak to peak voltage Table 1. Minimum Non-inductive Snubber Resistor
of a transient disturbance increases by nearly four times. for Four Quadrant Triggering.
Also the duration of the disturbance spreads because of dI
ringing, increasing the chance of malfunction or damage to Peak VC Rs dt
the voltage sensitive circuit. Closing a switch causes this TRIAC Type Volts Ohms A/µs
behavior. The problem can be reduced by adding a damping Non-Sensitive Gate 200 3.3 170
resistor in series with the capacitor. (IGT u
10 mA) 300 6.8 250
8 to 40 A(RMS) 400 11 308
600 39 400
800 51 400

Motorola Thyristor Device Data Theory and Applications

1.6–73
Reducing dI L
dt
I
TRIAC dI can be improved by avoiding quadrant 4 R
dt
triggering. Most optocoupler circuits operate the TRIAC in OPTIONAL
VPK
quadrants 1 and 3. Integrated circuit drivers use quadrants 2
C FAST
and 3. Zero crossing trigger devices are helpful because they
prohibit triggering when the voltage is high. SLOW

Ǹ
Driving the gate with a high amplitude fast rise pulse
increases dI capability. The gate ratings section defines the
dt
maximum allowed current.
dV
dt
+ CI VPK +I L
C
Inductance in series with the snubber capacitor reduces
(b.) Unprotected Circuit
dI. It should not be more than five percent of the load (a.) Protected Circuit
dt
inductance to prevent degradation of the snubber’s dV Figure 6.15. Interrupting Inductive Load Current
dt
suppression capability. Wirewound snubber resistors
sometimes serve this purpose. Alternatively, a separate Capacitor Discharge

ǒ Ǔ
inductor can be added in series with the snubber capacitor. The energy stored in the snubber capacitor
+
It can be small because it does not need to carry the load
Ec 1 C V 2 transfers to the snubber resistor and thyristor
current. For example, 18 turns of AWG No. 20 wire on a 2
T50-3 (1/2 inch) powdered iron core creates a non-saturat- every time it turns on. The power loss is proportional to
ing 6.0 µH inductor. frequency (PAV = 120 Ec @ 60 Hz).
A 10 ohm, 0.33 µF snubber charged to 650 volts resulted
in a 1000 A/µs dI. Replacement of the non-inductive CURRENT DIVERSION
dt
snubber resistor with a 20 watt wirewound unit lowered the The current flowing in the load inductor cannot change
rate of rise to a non-destructive 170 A/µs at 800 V. The instantly. This current diverts through the snubber resistor
inductor gave an 80 A/µs rise at 800 V with the non- causing a spike of theoretically infinite dV with magnitude
inductive resistor. dt
equal to (IRRM R) or (IH R).
The Snubber Capacitor
LOAD PHASE ANGLE

ǒǓ
A damping factor of 0.3 minimizes the size of the snubber
Highly inductive loads cause increased voltage and
capacitor for a given value of dV. This reduces the cost and
dt dV
physical dimensions of the capacitor. However, it raises at turn-off. However, they help to protect the
dt c
voltage causing a counter balancing cost increase. 1.4 2.2
Snubber operation relies on the charging of the snubber E
dV 2.1
capacitor. Turn-off snubbers need a minimum conduction dt
angle long enough to discharge the capacitor. It should be at 1.2 2
VPK
least several time constants (RS CS). 1.9

STORED ENERGY 1 1.8

NORMALIZED PEAK VOLTAGE

M=1 M = 0.75
Inductive Switching Transients 1.7
NORMALIZED dV
dt

+ 12
0.8 1.6
(dVdt)/ (E W0 )

E L I0 2 Watt-seconds or Joules
M = 0.5
1.5 VPK /E
I0 = current in Amperes flowing in the inductor at 0.6 1.4
t = 0.
M = 0.25 1.3
Resonant charging cannot boost the supply voltage at
turn-off by more than 2. If there is an initial current flowing in 0.4 1.2
the load inductance at turn-off, much higher voltages are M=0 1.1
possible. Energy storage is negligible when a TRIAC turns off
0.2 1
because of its low holding or recovery current.
The presence of an additional switch such as a relay, M = RS / (RL + RS) 0.9

ǒ Ǔ
thermostat or breaker allows the interruption of load current 0
and the generation of high spike voltages at switch opening. 0 0.2 0.4 0.6 0.8 1
The energy in the inductance transfers into the circuit DAMPING FACTOR
capacitance and determines the peak voltage (Figure 15). M + RESISTIVE DIVISION RATIO + RL R)S RS
IRRM + 0

Figure 6.16. 0 To 63% dV

dt

Theory and Applications Motorola Thyristor Device Data

1.6–74
thyristor from transients and dV . The load serves as
dt s
ǒǓ A variety of wave parameters (Figure 18) describe dV
dt
Some are easy to solve for and assist understanding. These
the snubber inductor and limits the rate of inrush current if
include the initial dV, the maximum instantaneous dV, and
the device does turn on. Resistance in the load lowers dV dt dt
dt

ǒǓ ǒǓ
and VPK (Figure 16). the average dV to the peak reapplied voltage. The 0 to 63%
dt
dV and 10 to 63% dV definitions on device data
dt s dt c
CHARACTERISTIC VOLTAGE WAVES sheets are easy to measure but difficult to compute.

Damping factor and reverse recovery current determine NON-IDEAL BEHAVIORS

the shape of the voltage wave. It is not exponential when
the snubber damping factor is less than 0.5 (Figure 17) or CORE LOSSES
when significant recovery currents are present. The magnetic core materials in typical 60 Hz loads
introduce losses at the snubber natural frequency. They
appear as a resistance in series with the load inductance and
winding dc resistance (Figure 19). This causes actual dV to
dt
ρ=0 ρ = 0.1 be less than the theoretical value.
500
V MT (VOLTS)

400
300 0.1 L R
0.3
2-1

200 1 ρ = 0.3 ρ=1

100 0
0
0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7

ƪ ǒǓ ƫ
TIME (µs) C

L DEPENDS ON CURRENT AMPLITUDE, CORE

0 63% dV
dt s
* + 100 Vńms, E + 250 V, SATURATION

RL + 0, IRRM + 0 R INCLUDES CORE LOSS, WINDING R. INCREASES

WITH FREQUENCY
Figure 6.17. Voltage Waves For Different
C WINDING CAPACITANCE. DEPENDS ON
Damping Factors
INSULATION, WIRE SIZE, GEOMETRY

2.8
Figure 6.19. Inductor Model
2.6

ǒǓ
E 0–63%
2.4 dV COMPLEX LOADS
dV
dt

2.2 dV MAX dt Many real-world inductances are non-linear. Their core

NORMALIZED PEAK VOLTAGE AND

2 dt
materials are not gapped causing inductance to vary with
1.8 current amplitude. Small signal measurements poorly
10–63%
1.6 characterize them. For modeling purposes, it is best to
1.4 measure them in the actual application.
10–63% VPK
1.2 Complex load circuits should be checked for transient
dV
1 dt voltages and currents at turn-on and off. With a capacitive
0.8 load, turn-on at peak input voltage causes the maximum

ǒǓ
0.6 surge current. Motor starting current runs 4 to 6 times the
0.4 dV steady state value. Generator action can boost voltages
0.2 dt o above the line value. Incandescent lamps have cold start
0 currents 10 to 20 times the steady state value. Transform-
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
ers generate voltage spikes when they are energized.
DAMPING FACTOR (ρ)
(RL + +
0, M 1, I RRM + 0)
Power factor correction circuits and switching devices

NORMALIZED dV + dVńdt NORMALIZED VPK + VEPK

create complex loads. In most cases, the simple CRL
model allows an approximate snubber design. However,
dt E w0
there is no substitute for testing and measuring the worst
Figure 6.18. Trade-Off Between VPK and dV case load conditions.
dt

Motorola Thyristor Device Data Theory and Applications

1.6–75
SURGE CURRENTS IN INDUCTIVE CIRCUITS DISTRIBUTED WINDING CAPACITANCE
Inductive loads with long L/R time constants cause There are small capacitances between the turns and
asymmetric multi-cycle surges at start up (Figure 20). layers of a coil. Lumped together, they model as a single
Triggering at zero voltage crossing is the worst case shunt capacitance. The load inductor behaves like a capaci-
condition. The surge can be eliminated by triggering at the tor at frequencies above its self-resonance. It becomes
zero current crossing angle.
ineffective in controlling dV and VPK when a fast transient
dt
such as that resulting from the closing of a switch occurs.
20 MHY
This problem can be solved by adding a small snubber
240 i 0.1 across the line.
VAC Ω
SELF-CAPACITANCE

A thyristor has self-capacitance which limits dV when the

dt
90 load inductance is large. Large load inductances, high power
i (AMPERES)

factors, and low voltages may allow snubberless operation.

0
ZERO VOLTAGE TRIGGERING, IRMS = 30 A SNUBBER EXAMPLES

40 80 120 160 200 WITHOUT INDUCTANCE

TIME (MILLISECONDS) Power TRIAC Example
Figure 6.20. Start-Up Surge For Inductive Circuit Figure 21 shows a transient voltage applied to a TRIAC
controlling a resistive load. Theoretically there will be an
Core remanence and saturation cause surge currents. instantaneous step of voltage across the TRIAC. The only
They depend on trigger angle, line impedance, core charac- elements slowing this rate are the inductance of the wiring
teristics, and direction of the residual magnetization. For and the self-capacitance of the thyristor. There is an
example, a 2.8 kVA 120 V 1:1 transformer with a 1.0 ampere exponential capacitor charging component added along with
load produced 160 ampere currents at start-up. Soft starting a decaying component because of the IR drop in the snubber
the circuit at a small conduction angle reduces this current. resistor. The non-inductive snubber circuit is useful when the
Transformer cores are usually not gapped and saturate load resistance is much larger than the snubber resistor.
easily. A small asymmetry in the conduction angle causes
magnetic saturation and multi-cycle current surges.
Steps to achieve reliable operation include:
1. Supply sufficient trigger current amplitude. TRIACs have RL
different trigger currents depending on their quadrant of RS
operation. Marginal gate current or optocoupler LED E e
current causes halfwave operation. CS
2. Supply sufficient gate current duration to achieve
latching. Inductive loads slow down the main terminal
τ = (RL + RS) CS
current rise. The gate current must remain above the e
specified IGT until the main terminal current exceeds the E
latching value. Both a resistive bleeder around the load

ǒǓ + E R R)S R

ƪǒ Ǔ ƫ
and the snubber discharge current help latching. V step
S L
3. Use a snubber to prevent TRIAC dV failure. TIME
dt c t=0

) RL e*tń ) (1 * e*tń )
4. Minimize designed-in trigger asymmetry. Triggering must
+ o)) + E
RS
e(t t t
be correct every half-cycle including the first. Use a RS
storage scope to investigate circuit behavior during the
first few cycles of turn-on. Alternatively, get the gate RESISTOR CAPACITOR
circuit up and running before energizing the load. COMPONENT COMPONENT
5. Derive the trigger synchronization from the line instead
of the TRIAC main terminal voltage. This avoids
regenerative interaction between the core hysteresis and
Figure 6.21. Non-Inductive Snubber Circuit
the triggering angle preventing trigger runaway, halfwave
operation, and core saturation.
6. Avoid high surge currents at start-up. Use a current
probe to determine surge amplitude. Use a soft start
circuit to reduce inrush current.

Theory and Applications Motorola Thyristor Device Data

1.6–76
Opto-TRIAC Examples Optocouplers with SCRs
Single Snubber, Time Constant Design Anti-parallel SCR circuits result in the same dV across the
dt
Figure 22 illustrates the use of the RC time constant optocoupler and SCR (Figure 23). Phase controllable opto-
design method. The optocoupler sees only the voltage
across the snubber capacitor. The resistor R1 supplies the couplers require the SCRs to be snubbed to their lower dV
dt
trigger current of the power TRIAC. A worst case design rating. Anti-parallel SCR circuits are free from the charge
procedure assumes that the voltage across the power storage behaviors that reduce the turn-off capability of
TRIAC changes instantly. The capacitor voltage rises to TRIACs. Each SCR conducts for a half-cycle and has the

ǒǓ
63% of the maximum in one time constant. Then: next half cycle of the ac line in which to recover. The

ǒǓ
turn-off dV of the conducting SCR becomes a static for-
R1 CS + + 0.63
t
E where dV is the rated static dV dt

ǒǓ
dV dt s dt
dt s ward blocking dV for the other device. Use the SCR data
dt
for the optocoupler. sheet dV rating in the snubber design.
dt s
1 A, 60 Hz A SCR used inside a rectifier bridge to control an ac load
will not have a half cycle in which to recover. The available
L = 318 MHY time decreases with increasing line voltage. This makes
10 V/µs
Rin 1 6 180 2.4 k 170 V the circuit less attractive. Inductive transients can be
VCC MOC T2322D suppressed by a snubber at the input to the bridge or
2
3020/ 0.1 µF C1 1 V/µs across the SCR. However, the time limitation still applies.

ǒǓ
3021 4

φ CNTL
OPTO dV
dt c
0.63 (170) DESIGN dV
dt
+ (0.63) (170)
(2400) (0.1 mF)
+ 0.45 Vńms
Zero-crossing optocouplers can be used to switch induc-
tive loads at currents less than 100 mA (Figure 24).
TIME
240 µs However a power TRIAC along with the optocoupler
should be used for higher load currents.
dV
dt
ń
(V ms)
80
Power TRIAC Optocoupler
0.99 0.35 70
LOAD CURRENT (mA RMS)

60
CS = 0.01
Figure 6.22. Single Snubber For Sensitive Gate TRIAC 50
and Phase Controllable Optocoupler
40
(ρ = 0.67)
The optocoupler conducts current only long enough to 30 CS = 0.001
trigger the power device. When it turns on, the voltage 20
between MT2 and the gate drops below the forward

ǒǓ
NO SNUBBER
threshold voltage of the opto-TRIAC causing turn-off. The 10

optocoupler sees dV when the power TRIAC turns off 0

dt s 20 30 40 50 60 70 80 90 100
later in the conduction cycle at zero current crossing.

ǒǓ
TA, AMBIENT TEMPERATURE (°C)
Therefore, it is not necessary to design for the lower
(RS = 100 Ω, VRMS = 220 V, POWER FACTOR = 0.5)
optocoupler dV rating. In this example, a single snubber
dt c Figure 6.24. MOC3062 Inductive Load Current versus TA
designed for the optocoupler protects both devices.
A phase controllable optocoupler is recommended with
a power device. When the load current is small, a MAC97
TRIAC is suitable.

ǒǓ
1 MHY
Unusual circuit conditions sometimes lead to unwanted
100
VCC operation of an optocoupler in dV mode. Very large
430 120 V dt c
1 4 1N4001 MCR265–4
MOC3031

400 Hz currents in the power device cause increased voltages

2 5 between MT2 and the gate that hold the optocoupler on.
3 6 51 MCR265–4 0.022 Use of a larger TRIAC or other measures that limit inrush
µF current solve this problem.
100 1N4001
Very short conduction times leave residual charge in the
optocoupler. A minimum conduction angle allows recovery
(50 V/µs SNUBBER, ρ = 1.0)
before voltage reapplication.

Figure 6.23. Anti-Parallel SCR Driver

Motorola Thyristor Device Data Theory and Applications

1.6–77
THE SNUBBER WITH INDUCTANCE
Consider an overdamped snubber using a large capaci-
tor whose voltage changes insignificantly during the time
TRIAC DESIGN PROCEDURE dV
dt c
ǒǓ
under consideration. The circuit reduces to an equivalent 1. Refer to Figure 18 and select a particular damping
factor (ρ) giving a suitable trade-off between VPK and dV.

ǒ * *Ǔ
L/R series charging circuit.
The current through the snubber resistor is: dt
Determine the normalized dV corresponding to the cho-
+ RV t dt
i 1 e t , sen damping factor.

ǒǓ
t
The voltage E depends on the load phase angle:
and the voltage across the TRIAC is:
e + i R S. E + Ǹ2 VRMS Sin (f) where f + tan*1
XL
where
RL
The voltage wave across the TRIAC has an exponential
rise with maximum rate at t = 0. Taking its derivative gives φ = measured phase angle between line V and load I

ǒ Ǔ+
its value as: RL = measured dc resistance of the load.

Ǹ Ǹ
V RS Then
dV .
dt 0 L
Highly overdamped snubber circuits are not practical de- Z + VIRMS
RMS
RL
2
) XL2 XL + Z2 * RL2 and
signs. The example illustrates several properties:
1. The initial voltage appears completely across the
circuit inductance. Thus, it determines the rate of
L + 2 pXfLLine .
change of current through the snubber resistor and the
If only the load current is known, assume a pure inductance.
initial dV. This result does not change when there is This gives a conservative design. Then:
dt

where E + Ǹ2
resistance in the load and holds true for all damping
factors.
2. The snubber works because the inductor controls the
L + 2 p fVLine
RMS
I RMS
V RMS.

rate of current change through the resistor and the rate For example:

+ Ǹ2
of capacitor charging. Snubber design cannot ignore
the inductance. This approach suggests that the
snubber capacitance is not important but that is only
E 120 + 170 V; L + (8 A) 120
(377 rps)
+ 39.8 mH.
true for this hypothetical condition. The snubber Read from the graph at ρ = 0.6, V PK = (1.25) 170 = 213 V.

+ +
resistor shunts the thyristor causing unacceptable
Use 400 V TRIAC. Read dV 1.0.
leakage when the capacitor is not present. If the power dt (ρ 0.6)

ǒ Ǔńǒ Ǔ
loss is tolerable, dV can be controlled without the 2. Apply the resonance criterion:
dt
capacitor. An example is the soft-start circuit used to limit
w0 + spec dV
dt
dV E .
dt (P)
inrush current in switching power supplies (Figure 25).

Snubber With No C
w0 +
5 10 6 V S ń + 29.4 10 3 r p s.
(1) (170 V)
RS

+ w 12 L + 0.029 m F
E
RECTIFIER C
AC LINE SNUBBER C1

Ǹ
0

ǒǓ+
BRIDGE G
L

Ǹ+
3. Apply the damping criterion:
ER S
* + 1400 ohms.
dV
dt
RS
f L
RS + 2ρ L
C
2 (0.6) 39.8
0.029
10 3
10 6*
E
RECTIFIER
AC LINE SNUBBER C1
L BRIDGE
G

Figure 6.25. Surge Current Limiting For

a Switching Power Supply

Theory and Applications Motorola Thyristor Device Data

1.6–78
 ǒǓ
dV SAFE AREA CURVE
dt c 10 0.33 µF

Figure 26 shows a MAC16 TRIAC turn-off safe operating 100 µH t 50 V/µs

ǒǓ
20 A
area curve. Turn-off occurs without problem under the curve.
LS1
The region is bounded by static dV at low values of dI
dt dt c
and delay time at high currents. Reduction of the peak 340
12 Ω
current permits operation at higher line frequency. This V
HEATER
TRIAC operated at f = 400 Hz, TJ = 125°C, and ITM = 6.0
amperes using a 30 ohm and 0.068 µF snubber. Low
damping factors extend operation to higher dI , but
dt c
ǒǓ
capacitor sizes increase. The addition of a small, saturable
commutation inductor extends the allowed current rate by Figure 6.27. Snubbing For a Resistive Load
introducing recovery delay time.

inductance must be known or defined by adding a series

inductor to insure reliable operation (Figure 27).
One hundred µH is a suggested value for starting the
– ITM = 15 A design. Plug the assumed inductance into the equation for C.
Larger values of inductance result in higher snubber resis-

ǒǓ+ tance and reduced dI. For example:

100
dI 6 f ITM 10 *3 A ms ń dt

Ǹ + 340 V.
dt c
Given E = 240 2
( dVdt )c (V/ µs)

10
Pick ρ = 0.3.

WITH COMMUTATION L Then from Figure 18, VPK = 1.42 (340) = 483 V.
1
Thus, it will be necessary to use a 600 V device. Using the
previously stated formulas for ω 0 , C and R we find:

10 VńS
w0 + 50 + 201450
6
rps

ǒǓ
0.1 (0.73) (340 V)
10 14 18 22 26 30 34 38 42 46 50
ń
dI AMPERES MILLISECOND
+ (201450)2 (100
1
*6) + 0.2464 m F
ǒ Ǔ Ǹ
C
dt c 10
+ń
10 *6 + 12 ohms
MAC 16-8, COMMUTATIONAL L 33 TURNS # 18,
52000-1A TAPE WOUND CORE 3 4 INCH OD
R + 2 (0.3) 100
10 *6

ǒ Ǔ ǒǓ
0.2464

dV dI VARIABLE LOADS
Figure 6.26. versus T = 125°C
dt c dt c J
The snubber should be designed for the smallest load
dV
STATIC DESIGN
dt inductance because dV will then be highest because of its
dt
dependence on ω0. This requires a higher voltage device for
There is usually some inductance in the ac main and operation with the largest inductance because of the
power wiring. The inductance may be more than 100 µH if corresponding low damping factor.
there is a transformer in the circuit or nearly zero when a
shunt power factor correction capacitor is present. Usually
the line inductance is roughly several µH. The minimum

Motorola Thyristor Device Data Theory and Applications

1.6–79
 10K
Figure 28 describes dV for an 8.0 ampere load at various
dt
power factors. The minimum inductance is a component
0.6 A RMS 2.5 A
added to prevent static dV firing with a resistive load.
dt
5A

1000 10 A
8 A LOAD
20 A

R S (OHMS)
R L
MAC 218-6
68 Ω 120 V 40 A
60 Hz
0.033 µF 80 A

ǒ Ǔ+ ǒ Ǔ+
100

dV
dt s
100 V ms ń dV
dt c
ń
5 V ms

R L Vstep VPK dv
ρ dt
Ω MHY V V V/µs 10

ǒ Ǔ
0.75 15 0.1 170 191 86 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.03 0 39.8 170 325 4.0 DAMPING FACTOR
0.04 10.6 28.1 120 225 3.3
0.06 13.5 17.3 74 136 2.6 PURE INDUCTIVE LOAD, V + 120 VRMS,
+
ǒǓ
I RRM 0

Figure 6.29. Snubber Resistor For dV = 5.0 V/µs

Figure 6.28. Snubber For a Variable Load dt c

ǒǓ
EXAMPLES OF SNUBBER DESIGNS
1
Table 2 describes snubber RC values for dV . Figures
dt s

ǒǓ
31 and 32 show possible R and C values for a 5.0 V/µs
dV assuming a pure inductive load.
dt c
40 A
80 A RMS

dV
Table 2. Static Designs
dt 0.1
(E = 340 V, Vpeak = 500 V, ρ = 0.3) 20 A
C S ( µ F)

5.0 V/µs 50 V/µs 100 V/µs 10 A

L C R C R C R
µH µF Ohm µF Ohm µF Ohm 5A
47 0.15 10
0.01 2.5 A
100 0.33 10 0.1 20
220 0.15 22 0.033 47
500 0.068 51 0.015 110
1000 3.0 11 0.033 100
0.6 A

0.001
TRANSIENT AND NOISE SUPPRESSION 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

ǒ Ǔ
Transients arise internally from normal circuit operation or DAMPING FACTOR
externally from the environment. The latter is particularly
frustrating because the transient characteristics are unde-
PURE INDUCTIVE LOAD, V + 120 VRMS,
fined. A statistical description applies. Greater or smaller
stresses are possible. Long duration high voltage transients
I RRM 0 +

ǒǓ
are much less probable than those of lower amplitude and
higher frequency. Environments with infrequent lightning
and load switching see transient voltages below 3.0 kV.
Figure 6.30. Snubber Capacitor For dV = 5.0 V/µs
dt c

Theory and Applications Motorola Thyristor Device Data

1.6–80
 The natural frequencies and impedances of indoor ac wiring
The noise induced into a circuit is proportional to dV when
result in damped oscillatory surges with typical frequencies dt
ranging from 30 kHz to 1.5 MHz. Surge amplitude depends on coupling is by stray capacitance, and dI when the coupling is
both the wiring and the source of surge energy. Disturbances dt
by mutual inductance. Best suppression requires the use of a
tend to die out at locations far away from the source. Spark-over
voltage limiting device along with a rate limiting CRL snubber.
(6.0 kV in indoor ac wiring) sets the maximum voltage when
The thyristor is best protected by preventing turn-on from
transient suppressors are not present. Transients closer to the
dV or breakover. The circuit should be designed for what can
service entrance or in heavy wiring have higher amplitudes,
dt
longer durations, and more damping because of the lower happen instead of what normally occurs.
inductance at those locations. In Figure 30, a MOV connected across the line protects
The simple CRL snubber is a low pass filter attenuating many parallel circuit branches and their loads. The MOV
frequencies above its natural resonance. A steady state
sinusoidal input voltage results in a sine wave output at the defines the maximum input voltage and dI through the load.
dt
same frequency. With no snubber resistor, the rate of roll off
With the snubber, it sets the maximum dV and peak voltage
approaches 12 dB per octave. The corner frequency is at the dt
snubber’s natural resonance. If the damping factor is low, the across the thyristor. The MOV must be large because there is
response peaks at this frequency. The snubber resistor little surge limiting impedance to prevent its burn-out.
degrades filter characteristics introducing an up-turn at ω = 1
/ (RC). The roll-off approaches 6.0 dB/octave at frequencies
above this. Inductance in the snubber resistor further
reduces the roll-off rate.
Figure 32 describes the frequency response of the
circuit in Figure 27. Figure 31 gives the theoretical
response to a 3.0 kV 100 kHz ring-wave. The snubber VMAX
reduces the peak voltage across the thyristor. However,
the fast rise input causes a high dV step when series
dt
inductance is added to the snubber resistor. Limiting the
input voltage with a transient suppressor reduces the step.
400
WITHOUT 5 µHY
WITH 5 µHY AND Figure 6.33. Limiting Line Voltage
VMT (VOLTS)

450 V MOV In Figure 32, there is a separate suppressor across each

AT AC INPUT
0 thyristor. The load impedance limits the surge energy
2-1

delivered from the line. This allows the use of a smaller

device but omits load protection. This arrangement protects
WITH 5 µHY
each thyristor when its load is a possible transient
– 400 source.
0 1 2 3 4 5 6
TIME (µs)

Figure 6.31. Theoretical Response of Figure 33 Circuit

to3.0 kV IEEE 587 Ring Wave (RSC = 27.5 Ω)
+ 10

0
VOLTAGE GAIN (dB)

– 10
100 µH
WITH 5 µHY
– 20 5 µH Figure 6.34. Limiting Thyristor Voltage
Vin 10 Vout
– 30 0.33 µF It is desirable to place the suppression device directly across
12 WITHOUT 5µHY the source of transient energy to prevent the induction of energy
– 40 into other circuits. However, there is no protection for energy
10K 100K 1M injected between the load and its controlling thyristor. Placing
FREQUENCY (Hz) the suppressor directly across each thyristor positively limits
V
Figure 6.32. Snubber Frequency Response ǒ VoutǓ maximum voltage and snubber discharge dI .
dt
in

Motorola Thyristor Device Data Theory and Applications

1.6–81
 SNUBBER

φ1 2 1
22 Ω
100 µH 2W
G
300 WIREWOUND
4 MOC 6 91
3081 0.15
FWD µF

SNUBBER

2 1
SNUBBER
ALL MOV’S ARE 275
G
300 VRMS
91 ALL TRIACS ARE
4 MOC 6
MAC218-10
3081
1/3 HP
REV
208 V
SNUBBER 91
3 PHASE

SNUBBER
φ2 2 1 G
1
100 µH 6
G
300 MOC
2
91 3081
4 MOC 6
3081 4
FWD
SNUBBER 43

2 1

G
300
6 MOC 4 91
3081
φ3 REV

Figure 6.35. 3 Phase Reversing Motor

EXAMPLES OF SNUBBER APPLICATIONS Figure 36 shows a split phase capacitor-run motor with
reversing accomplished by switching the capacitor in
series with one or the other winding. The forward and
In Figure 35, TRIACs switch a 3 phase motor on and off reverse TRIACs function as a SPDT switch. Reversing the
and reverse its rotation. Each TRIAC pair functions as a motor applies the voltage on the capacitor abruptly across
SPDT switch. The turn-on of one TRIAC applies the the blocking thyristor. Again, the inductor L is added to
differential voltage between line phases across the prevent ǒdVǓ firing of the blocking TRIAC. If turn-on
blocking device without the benefit of the motor impedance dt s
to constrain the rate of voltage rise. The inductors are occurs, the forward and reverse TRIACs short the
capacitors (Cs ) resulting in damage to them. It is wise to
added to prevent static dV firing and a line-to-line short.
dt add the resistor R S to limit the discharge current.

Theory and Applications Motorola Thyristor Device Data

1.6–82
 THYRISTOR TYPES
REV Sensitive gate thyristors are easy to turn-on because of
0.1
their low trigger current requirements. However, they have
91 3.75
less dV capability than similar non-sensitive devices. A
46 V/µs LS 330 V
MAX dt
FWD 500 µH 5.6 non-sensitive thyristor should be used for high dV .
91 0.1 dt
MOTOR
1/70 HP TRIAC commutating dV ratings are 5 to 20 times less than
RS CS dt
0.26 A
115 static dV ratings.
dt
T2323D
Phase controllable optocouplers have lower dV ratings
dt
than zero crossing optocouplers and power TRIACs.
These should be used when a dc voltage component is
present, or to prevent turn-on delay.
Zero crossing optocouplers have more dV capability
dt
Figure 6.36. Split Phase Reversing Motor than power thyristors; and they should be used in place of
phase controllable devices in static switching
Figure 37 shows a “ tap changer.” This circuit allows the applications.
operation of switching power supplies from a 120 or 240 vac
line. When the TRIAC is on, the circuit functions as a APPENDIX A
conventional voltage doubler with diodes D1 and D2
conducting on alternate half-cycles. In this mode of opera-
TESTING SNUBBER DISCHARGE dI
tion, inrush current and dI are hazards to TRIAC reliability. dt
dt
Series impedance is necessary to prevent damage to the The equations in Appendix D do not consider the
TRIAC. thyristor’s turn-on time or on-state resistance, thus, they
The TRIAC is off when the circuit is not doubling. In this
predict high values of dI.
state, the TRIAC sees the difference between the line voltage dt
and the voltage at the intersection of C1 and C2. Transients Figure 38 shows the circuit used to test snubber discharge
dI. A MBS4991 supplies the trigger pulse while the quad-
on the line cause ǒdVǓ firing of the TRIAC. High inrush dt
dt s
rants of operation are switch selectable. The snubber was
dI
current, , and overvoltage damage to the filter capacitor mounted as close to the TRIAC under test as possible to
dt
are possibilities. Prevention requires the addition of a RC reduce inductance, and the current transformer remained in
snubber across the TRIAC and an inductor in series with the circuit to allow results to be compared with the measured
the line. dI value.
dt
What should the peak capacitor voltage be? A conserva-
tive approach is to test at maximum rated VDRM, or the clamp
SNUBBER INDUCTOR voltage of the MOV.
What is the largest capacitor that can be used without
D1 limiting resistance? Figure 39 is a photo showing the current
D2
+ pulse resulting from a 0.001 µF capacitor charged to 800 V.
C1
120 VAC
D3
– The 1200 A/µs dI destroyed the TRIAC.
OR D4 dt
240 VAC Is it possible for MOV self-capacitance to damage the
RL TRIAC? A large 40 Joule, 2200 A peak current rated MOV
240 V was tested. The MOV measured 440 pF and had an 878
0 G volt breakover voltage. Its peak discharge current (12 A)
+
C2
120 V – was half that of a 470 pF capacitor. This condition was
safe.
RS CS

Figure 6.37. Tap Changer For Dual Voltage

Switching Power Supply

Motorola Thyristor Device Data Theory and Applications

1.6–83
 2000
OPTIONAL PEARSON
500 W 411 CURRENT

OPTIONAL MOV
TRANSFORMER

RS 50 Ω
5000
2.5 kV 200 W MT2
120 VAC 60 Hz
X100
VTC V PROBE G
5–50
56
SWEEP FOR MT1
DESIRED VCi CS

TRIAC
UNDER TEST 91

3000
VMT2-1

2 1 12 V MBS4991
Q1,3 Q2,4 1
VG
µF
3 4
QUADRANT
SWITCH
QUADRANT
MAP

Figure 6.38. Snubber Discharge dl/dt Test

APPENDIX B
MEASURING ǒdVǓ
dt s

Figure 40 shows a test circuit for measuring the static dV

dt
of power thyristors. A 1000 volt FET switch insures that the
voltage across the device under test (D.U.T.) rises rapidly
from zero. A differential preamp allows the use of a
N-channel device while keeping the storage scope
chassis at ground for safety purposes. The rate of voltage
rise is adjusted by a variable RC time constant. The
charging resistance is low to avoid waveform distortion
because of the thyristor’s self-capacitance but is large
enough to prevent damage to the D.U.T. from turn-on dI.
dt
Mounting the miniature range switches, capacitors, and
G-K network close to the device under test reduces stray
inductance and allows testing at more than 10 kV/µs.
HORIZONTAL SCALE — 50 ms/DIV.
VERTICAL SCALE — 10 A/DIV.
CS = 0.001 µF, VCi = 800 V, RS = 0, L = 250 mH, RTRAIC = 10 OHMS

Figure 6.39. Discharge Current From 0.001 µF

Capacitor

Theory and Applications Motorola Thyristor Device Data

1.6–84
 27
VDRM/VRRM SELECT 2W 1000
10 WATT
WIREWOUND
X100 PROBE 2

DIFFERENTIAL DUT 20 k 2W 0.33 1000 V 0.047

PREAMP
X100 PROBE G 1000 V
1

RGK 470 pF
dV
MOUNT DUT ON dt 0.001
100
TEMPERATURE CONTROLLED VERNIER 2W
Cµ PLATE
0.005
1 MEG 2 W EACH
1.2 MEG
82 0.01
2W 2W
POWER
TEST
0.047

1N914 0.1

MTP1N100
20 V 0.47 0–1000 V
10 mA
56
1000 1N967A
f = 10 Hz 2W
1/4 W 18 V
PW = 100 µs
50 Ω PULSE
GENERATOR

ALL COMPONENTS ARE NON-INDUCTIVE UNLESS OTHERWISE SHOWN

Figure 6.40. Circuit For Static dV Measurement of Power Thyristors

dt

APPENDIX C Commercial chokes simplify the construction of the neces-

sary inductors. Their inductance should be adjusted by
MEASURING ǒdVǓ increasing the air gap in the core. Removal of the magnetic
dt c
pole piece reduces inductance by 4 to 6 but extends the
A test fixture to measure commutating dV is shown in current without saturation.
dt The load capacitor consists of a parallel bank of 1500 Vdc
Figure 41. It is a capacitor discharge circuit with the load non-polar units, with individual bleeders mounted at each
series resonant. The single pulse test aids temperature capacitor for safety purposes.
control and allows the use of lower power components. An optional adjustable voltage clamp prevents TRIAC
The limited energy in the load capacitor reduces burn and breakdown.
shock hazards. The conventional load and snubber circuit
provides recovery and damping behaviors like those in the To measure ǒdVǓ , synchronize the storage scope on the
dt c
application.
The voltage across the load capacitor triggers the D.U.T. current waveform and verify the proper current amplitude and
It terminates the gate current when the load capacitor period. Increase the initial voltage on the capacitor to
voltage crosses zero and the TRIAC current is at its peak. compensate for losses within the coil if necessary. Adjust the
Each V DRM , I TM combination requires different compo- snubber until the device fails to turn off after the first
nents. Calculate their values using the equations given in half-cycle. Inspect the rate of voltage rise at the fastest
Figure 41. passing condition.

Motorola Thyristor Device Data Theory and Applications

1.6–85
 HG = W AT LOW LD10-1000-1000
NON-INDUCTIVE + CLAMP – CLAMP LL RL
RESISTOR DECADE
0–10 k, 1 Ω STEP TRIAD C30X

2.2 M, 2W

2.2 M, 2W
51 k 50 H, 3500 Ω
2W 910 k

2W Q3 Q1
MR760

2.2 M

2.2 M

C L (NON-POLAR)
51 k 2W

MR760
CAPACITOR DECADE 1–10 µF, 0.01–1 µ F, 100 pF– 0.01 µ F

2.2 M
910 k
RS 2W
2N3904 2N3906 + 1.5 kV
62 µF

0-1 kV 20 mA
6.2 MEG 2W
1 kV
+ – 70 mA
0.01

0.01

2.2 M

MR760
120 1/2 W
1/2 W 120 – 150 k 6.2 MEG 2W
2N3906 2N3904

Q3 Q1
2N3906 2N3904 –5 +5
0.1 0.1 PEARSON
301 X 360 1/2 W 360 1/2 W
2N3904 2N3906
1k 1k
CASE
2 2N3904
CONTROLLED
HEATSINK
1 – +
51 2W 2N3906
CS +5 G
51 2W –5 56
2 WATT Q3 Q1
TRIAC 0.22 0.22
dV UNDER 270 k 1N5343
dt 2.2 k
7.5 V

ǒ Ǔ
TEST 270 k
SYNC 1/2

CL + W0IPKVCi + 2 pp VCi
I T
LL + W0 CiIPK + 4 pT22C
V

L
W0 + ǸLI
L
ǒǓ+dI
dt c
6f I PK 10 6
A ms
*
ń

Figure 6.41. ǒǓ
dV
dt c
Test Circuit For Power TRIACs

Theory and Applications Motorola Thyristor Device Data

1.6–86
 t ρ t 1)
w + Ǹw + w0 Ǹ1 * ρ2
APPENDIX D 2.2 Underdamped (0

0 *
dV DERIVATIONS 2 a2

Ǹ
dt
2.3 Critical Damped (ρ + 1)
DEFINITIONS
+ RL ) RS + Total Resistance a + w0, w + 0, R + 2 L , C + 2
1.0 RT C a RT
Overdamped (ρ u 1)
w + Ǹa2 * w0 2 + w0 Ǹρ2 * 1
2.4
1.1 M + RT + Snubber Divider Ratio
RS

Laplace transforms for the current and voltage in Figure 42

1.2 w0 +
Ǹ 1
L CS
+ Undamped Natural Frequency are:

ń) S V0L c *
w + Damped Natural Frequency 3.0 i(S) + E L SI
; e E + *
) ) ) )
RT S RT
S2 S 1 S2 S 1
L LC L LC
1.3 a + 2 L + Wave Decrement Factor
RT

1ń2 LI 2
χ2 + + Initial Energy In Inductor RL L
1ń2 CV
1.4

+ Ǹ +
2 Final Energy In Capacitor
t=0
I RS
1.5 χ I L Initial Current Factor e

+ Ǹ +
E C
CS

1.6 ρ
RT C+ Damping Factor
a
w0
2 L
+
INITIAL CONDITIONS

V 0 + E * R S I + Initial Voltage drop at t + 0

I I RRM
1.7
L
VC
S
+ 0
across the load
Figure 6.42. Equivalent Circuit for Load and Snubber

c + CIS * L E RL

ǒǓ
1.8 The inverse laplace transform for each of the conditions
gives:
dV + Initial instantaneous dV at t + 0, ignoring

+ E * V0L ƪCos (wt) * wa sin (wt)ƫe * at )

dt 0 dt UNDERDAMPED (Typical Snubber Design)
any initial instantaneous voltage step at
+ 4.0 e

ǒ Ǔ+
t 0 because of IRRM

ƪ ƫ
c
w sin (wt) e
*at
1.9 dV V OL
RT
) c. For all damping conditions
(w 2 * a2)

ǒǓ sin (wt) e *at)

dt 0 L
de + V
4.1 0 2a Cos (wt) ) w
+ 0, dV + E RS dt L

ƪ * wa sin (wt) ƫ e*at

ǒǓ
2.0 When I
dt 0 L

ȱȧ ȳȧ
c Cos (wt)
dV
dt max
+ Maximum instantaneous dV
dt

ǒ * Ǔ* ȴ
tmax + Time of maximum instantaneous dV
+ *1 * )
2a V0 L c

Ȳ+
1
tpeak + Time of maximum instantaneous peak
dt 4.2 tPK w tan
w2 a2 ca
voltage across thyristor
V0
L w w

+ VPKń tPK + Slope of the secant line + 0, RS 0, I 0 : w tPK + +

Ǹ )
Average dV When M p
from t + 0 through V PK
dt

V PK + E ) a * a tPK w0 V0 L ) c2
2
2 2ac V0 L
+ Maximum instantaneous voltage across the 4.3
w0
When I + 0, R L + 0, M + 1:
V PK
thyristor.

CONSTANTS (depending on the damping factor): 4.4

V PK
+ (1 ) e * a tPK)
+ 0) E

Average dV +
2.1 No Damping (ρ
+ w0
V PK
w
RT + a + ρ + 0
dt tPK

Motorola Thyristor Device Data Theory and Applications

1.6–87
4.5 tmax + w1 ATN ƪ w (2ac * V0 L (w2 * 3a2))
V0 L(a 3 * 3aw2) ) c(a2 * w2) ƫ 6.5 tmax + a3a2VV0L )) 2acc
0L
When I + 0, t max + 0

ǒ Ǔ +Ǹ
dV 2
)
w0 2 2ac V0 L ) c2 e–a tmax
RS
y3ń4,
ǒǓ
4.6 V0 L For
dt max RT

NO DAMPING then dV
dt max
+ dV dt 0

5.0 e + E (1 * Cos (w0t)) ) C Iw0 sin (w0t)

6.6 ǒǓ dV

+ ƪa V0L (2–a tmax) ) c (1–a tmax) ƫe–a tmax

dt max
5.1 de + E w0 sin (w0t) ) CI Cos (w0t)

ǒ Ǔ+
dt

5.2 dV
dt 0
I
C
+ 0 when I + 0

+
p * tan*1 CEIw0ǒ Ǔ APPENDIX E

Ǹ
5.3 tPK
w0 SNUBBER DISCHARGE dI DERIVATIONS
dt
5.4 V PK +E) E2 ) w I22C2 OVERDAMPED

ǒǓ
0
+ wVCLSS a–at sinh (wt)

Ǹ
1.0 i
5.5 dV + VtPK
PK

ƪ ǒ Ǔƫ
dt AVG

5.6 tmax + 1 tan *1 w0 EC + w1 p when I +0 1.1 iPK + VC S CS

LS
e –a t PK
w0 2

ǒǓ
I 0

5.7 dV + CI Ǹ E 2w0 2 C 2 I2) + w0E when I + 0 1.2 tPK + w1 tanh –1 ƪwaƫ

dt max
CRITICAL DAMPED
CRITICAL DAMPING

6.0 e + E * V0L(1 * at)e*at ) cte*at 2.0 i + VLCSS te–at

6.1 de
dt
+ ƪ a VOL (2 * at) ) c(1 * at) ƫe*at 2.1 iPK + 0.736 VRCSS
) 2 Vc0L
+ a1
2
tPK +
2.2 tPK
6.2
a)
c
V0 L UNDERDAMPED

+ E – ƪ V0L (1–a tPK)–c tPK ƫ e–a tPK + wVCLSS e–at sin (wt)

Ǹ
6.3 V PK 3.0 i

Average dV + VtPK
PK
+ VC S
6.4 CS
e –a t PK
dt
When I + 0, R S + 0, M + 0
3.1 iPK
LS

e(t) rises asymptotically to E. tPK and average dV

dt 3.2 tPK + w1 tan –1 ǒwaǓ
do not exist.

Theory and Applications Motorola Thyristor Device Data

1.6–88
 NO DAMPING

+ wVCLSS sin (wt)

Ǹ
4.0 i

RS LS

t=0
4.1 iPK + VC S CS
LS

VCS CS i
4.2 tPK + 2pw

+ 0, VCS + INITIAL VOLTAGE

INITIAL CONDITIONS :
i

Figure 6.43. Equivalent Circuit for Snubber Discharge

BIBLIOGRAPHY

Bird, B. M. and K. G. King. An Introduction To Power Kervin, Doug. “ The MOC3011 and MOC3021,” EB-101,
Electronics. John Wiley & Sons, 1983, pp. 250–281. Motorola Inc., 1982.
Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976. McMurray, William. “Optimum Snubbers For Power Semicon-
Gempe, Horst. “Applications of Zero Voltage Crossing ductors,” IEEE Transactions On Industry Applications, Vol.
Optically Isolated TRIAC Drivers,” AN982, Motorola Inc., IA-8, September/October 1972.
1987. Rice, L. R. “ Why R-C Networks And Which One For Your
“Guide for Surge Withstand Capability (SWC) Tests,” ANSI Converter,” Westinghouse Tech Tips 5-2.
337.90A-1974, IEEE Std 472–1974. “Saturable Reactor For Increasing Turn-On Switching Capa-
“IEEE Guide for Surge Voltages in Low-Voltage AC Power bility,” SCR Manual Sixth Edition, General Electric, 1979.
Circuits,” ANSI/IEEE C62.41-1980, IEEE Std 587–1980. Zell, H. P. “Design Chart For Capacitor-Discharge Pulse
Circuits,” EDN Magazine, June 10, 1968.
Ikeda, Shigeru and Tsuneo Araki. “ The dI Capability of
dt
Thyristors,” Proceedings of the IEEE, Vol. 53, No. 8, August
1967.

Motorola Thyristor Device Data Theory and Applications

1.6–89
REV 1

Theory and Applications Motorola Thyristor Device Data

1.6–90
 CHAPTER 7
MOUNTING TECHNIQUES FOR THYRISTORS

INTRODUCTION Figure 7.1 shows an example of doing nearly everything

wrong. A tab mount TO-220 package is shown being used as
Current and power ratings of semiconductors are insepa- a replacement for a TO-213AA (TO-66) part which was
rably linked to their thermal environment. Except for lead- socket mounted. To use the socket, the leads are bent — an
mounted parts used at low currents, a heat exchanger is operation which, if not properly done, can crack the package,
required to prevent the junction temperature from exceeding break the internal bonding wires, or crack the die. The
its rated limit, thereby running the risk of a high failure rate. package is fastened with a sheet-metal screw through a 1/4″
Furthermore, the semiconductor industry’s field history indi- hole containing a fiber-insulating sleeve. The force used to
cated that the failure rate of most silicon semiconductors tighten the screw tends to pull the package into the hole,
decreases approximately by one half for a decrease in causing enough distortion to crack the die. In addition the
junction temperature from 160°C to 135°C.(1) Guidelines for contact area is small because of the area consumed by the
designers of military power supplies impose a 110°C limit large hole and the bowing of the package; the result is a
upon junction temperature.(2) Proper mounting minimizes the much higher junction temperature than expected. If a rough
temperature gradient between the semiconductor case and heatsink surface and/or burrs around the hole were dis-
the heat exchanger. played in the illustration, most but not all poor mounting
Most early life field failures of power semiconductors can practices would be covered.
be traced to faulty mounting procedures. With metal pack-
aged devices, faulty mounting generally causes unnecessar-
ily high junction temperature, resulting in reduced component
lifetime, although mechanical damage has occurred on
occasion from improperly mounting to a warped surface.
With the widespread use of various plastic-packaged semi- PLASTIC BODY
conductors, the prospect of mechanical damage is very LEADS
significant. Mechanical damage can impair the case moisture PACKAGE HEATSINK
resistance or crack the semiconductor die. MICA WASHER

(1) MIL-HANDBOOK — 2178, SECTION 2.2.

(2) “Navy Power Supply Reliability — Design and Manufacturing SPEED NUT
(PART OF SOCKET)
Guidelines” NAVMAT P4855-1, Dec. 1982 NAVPUBFORCEN, EQUIPMENT SOCKET FOR
5801 Tabor Ave., Philadelphia, PA 19120. HEATSINK TO-213AA PACKAGE SHEET METAL SCREW

Figure 7.1. Extreme Case of Improperly Mounting

A Semiconductor (Distortion Exaggerated)

Motorola Thyristor Device Data Theory and Applications

1.7–1
 In many situations the case of the semiconductor must be
TIR = TOTAL INDICATOR READING
electrically isolated from its mounting surface. The isolation
material is, to some extent, a thermal isolator as well, which SAMPLE
raises junction operating temperatures. In addition, the PIECE
possibility of arc-over problems is introduced if high voltages TIR ∆h
are present. Various regulating agencies also impose creep-
age distance specifications which further complicates de-
sign. Electrical isolation thus places additional demands
upon the mounting procedure.
Proper mounting procedures usually necessitate orderly DEVICE MOUNTING AREA
REFERENCE PIECE
attention to the following:
1. Preparing the mounting surface Figure 7.2. Surface Flatness Measurement
2. Applying a thermal grease (if required)
3. Installing the insulator (if electrical isolation is
desired) and does not significantly lower contact resistance. Tests
4. Fastening the assembly conducted by Thermalloy using a copper TO-204 (TO-3)
5. Connecting the terminals to the circuit package with a typical 32-microinch finish, showed that
heatsink finishes between 16 and 64 µ-in caused less than
In this note, mounting procedures are discussed in general ± 2.5% difference in interface thermal resistance when the
terms for several generic classes of packages. As newer voids and scratches were filled with a thermal joint com-
packages are developed, it is probable that they will fit into pound.(3) Most commercially available cast or extruded
the generic classes discussed in this note. Unique require- heatsinks will require spotfacing when used in high-power
ments are given on data sheets pertaining to the particular applications. In general, milled or machined surfaces are
package. The following classes are defined: satisfactory if prepared with tools in good working condition.
Stud Mount
Flange Mount Mounting Holes
Pressfit Mounting holes generally should only be large enough
Plastic Body Mount to allow clearance of the fastener. The large thick flange
Tab Mount type packages having mounting holes removed from the
Surface Mount semiconductor die location, such as the TO-3, may
Appendix A contains a brief review of thermal resistance successfully be used with larger holes to accommodate an
concepts. Appendix B discusses measurement difficulties insulating bushing, but many plastic encapsulated pack-
with interface thermal resistance tests. Appendix C indicates ages are intolerant of this condition. For these packages,
the type of accessories supplied by a number of a smaller screw size must be used such that the hole for
manufacturers. the bushing does not exceed the hole in the package.
Punched mounting holes have been a source of trouble
MOUNTING SURFACE PREPARATION because if not properly done, the area around a punched
hole is depressed in the process. This “crater” in the
heatsink around the mounting hole can cause two
In general, the heatsink mounting surface should have a problems. The device can be damaged by distortion of the
flatness and finish comparable to that of the semiconductor package as the mounting pressure attempts to conform it
package. In lower power applications, the heatsink surface is to the shape of the heatsink indentation, or the device may
satisfactory if it appears flat against a straight edge and is only bridge the crater and leave a significant percentage of
free from deep scratches. In high-power applications, a more its heat-dissipating surface out of contact with the
detailed examination of the surface is required. Mounting heatsink. The first effect may often be detected immediate-
holes and surface treatment must also be considered. ly by visual cracks in the package (if plastic), but usually an
unnatural stress is imposed, which results in an early-life
Surface Flatness failure. The second effect results in hotter operation and is
Surface flatness is determined by comparing the variance not manifested until much later.
in height (∆h) of the test specimen to that of a reference Although punched holes are seldom acceptable in the
standard as indicated in Figure 7.2. Flatness is normally relatively thick material used for extruded aluminum
specified as a fraction of the Total Indicator Reading (TIR). heatsinks, several manufacturers are capable of properly
The mounting surface flatness, i.e., ∆h/TIR, if less than 4 mils utilizing the capabilities inherent in both fine-edge blank-
per inch, normal for extruded aluminum, is satisfactory in ing or sheared-through holes when applied to sheet metal
most cases. as commonly used for stamped heatsinks. The holes are
pierced using Class A progressive dies mounted on
four-post die sets equipped with proper pressure pads and
Surface Finish
holding fixtures.
Surface finish is the average of the deviations both above
and below the mean value of surface height. For minimum
interface resistance, a finish in the range of 50 to 60 (3) Catalog #87-HS-9 (1987), page 8, Thermalloy, Inc., P.O. Box
microinches is satisfactory; a finer finish is costly to achieve 810839, Dallas, Texas 75381-0839.

Theory and Applications Motorola Thyristor Device Data

1.7–2
 When mounting holes are drilled, a general practice with well, they should be evenly applied in a very thin layer using
extruded aluminum, surface cleanup is important. Chamfers a spatula or lintless brush, and wiped lightly to remove
must be avoided because they reduce heat transfer surface excess material. Some cyclic rotation of the package will help
and increase mounting stress. However, the edges must be the compound spread evenly over the entire contact area.
broken to remove burrs which cause poor contact between Some experimentation is necessary to determine the correct
device and heatsink and may puncture isolation material. quantity; too little will not fill all the voids, while too much may
permit some compound to remain between well mated metal
Surface Treatment surfaces where it will substantially increase the thermal
Many aluminium heatsinks are black-anodized to improve resistance of the joint.
radiation ability and prevent corrosion. Anodizing results in To determine the correct amount, several semiconductor
significant electrical but negligible thermal insulation. It need samples and heatsinks should be assembled with different
only be removed from the mounting area when electrical amounts of grease applied evenly to one side of each mating
contact is required. Heatsinks are also available which have surface. When the amount is correct a very small amount of
a nickel plated copper insert under the semiconductor grease should appear around the perimeter of each mating
mounting area. No treatment of this surface is necessary. surface as the assembly is slowly torqued to the recom-
Another treated aluminum finish is iridite, or chromate-acid mended value. Examination of a dismantled assembly
dip, which offers low resistance because of its thin surface, should reveal even wetting across each mating surface. In
yet has good electrical properties because it resists oxida- production, assemblers should be trained to slowly apply the
tion. It need only be cleaned of the oils and films that collect in specified torque even though an excessive amount of grease
the manufacture and storage of the sinks, a practice which appears at the edges of mating surfaces. Insufficient torque
should be applied to all heatsinks. causes a significant increase in the thermal resistance of the
For economy, paint is sometimes used for sinks; removal interface.
of the paint where the semiconductor is attached is usually To prevent accumulation of airborne particulate matter,
required because of paint’s high thermal resistance. How- excess compound should be wiped away using a cloth
ever, when it is necessary to insulate the semiconductor moistened with acetone or alcohol. These solvents should
package from the heatsink, hard anodized or painted not contact plastic-encapsulated devices, as they may enter
surfaces allow an easy installation for low voltage applica- the package and cause a leakage path or carry in sub-
tions. Some manufacturers will provide anodized or painted stances which might attack the semiconductor chip.
surfaces meeting specific insulation voltage requirements, The silicone oil used in most greases has been found to
usually up to 400 volts. evaporate from hot surfaces with time and become deposited
It is also necessary that the surface be free from all foreign on other cooler surfaces. Consequently, manufacturers must
material, film, and oxide (freshly bared aluminum forms an determine whether a microscopically thin coating of silicone
oxide layer in a few seconds). Immediately prior to assembly, oil on the entire assembly will pose any problems. It may be
it is a good practice to polish the mounting area with No. 000 necessary to enclose components using grease. The newer
steel wool, followed by an acetone or alcohol rinse. synthetic base greases show far less tendency to migrate or
creep than those made with a silicone oil base. However,
INTERFACE DECISIONS their currently observed working temperature range are less,
they are slightly poorer on thermal conductivity and dielectric
When any significant amount of power is being dissipated, strength and their cost is higher.
something must be done to fill the air voids between mating Data showing the effect of compounds on several package
surfaces in the thermal path. Otherwise the interface thermal types under different mounting conditions is shown in Table
resistance will be unnecessarily high and quite dependent 7.1. The rougher the surface, the more valuable the grease
upon the surface finishes. becomes in lowering contact resistance; therefore, when
For several years, thermal joint compounds, often called mica insulating washers are used, use of grease is generally
grease, have been used in the interface. They have a mandatory. The joint compound also improves the break-
resistivity of approximately 60°C/W/in whereas air has down rating of the insulator.
1200°C/W/in. Since surfaces are highly pock-marked with
minute voids, use of a compound makes a significant Conductive Pads
reduction in the interface thermal resistance of the joint. Because of the difficulty of assembly using grease and the
However, the grease causes a number of problems, as evaporation problem, some equipment manufacturers will
discussed in the following section. not, or cannot, use grease. To minimize the need for grease,
To avoid using grease, manufacturers have developed dry several vendors offer dry conductive pads which approxi-
conductive and insulating pads to replace the more tradition- mate performance obtained with grease. Data for a greased
al materials. These pads are conformal and therefore bare joint and a joint using Grafoil, a dry graphite compound,
partially fill voids when under pressure. is shown in the data of Figure 7.3. Grafoil is claimed to be a
replacement for grease when no electrical isolation is
Thermal Compounds (Grease) required; the data indicates it does indeed perform as well as
Joint compounds are a formulation of fine zinc or other grease. Another conductive pad available from Aavid is
conductive particles in the silicone oil or other synthetic base called KON-DUX. It is made with a unique, grain oriented,
fluid which maintains a grease-like consistency with time and flake-like structure (patent pending). Highly compressible,
temperature. Since some of these compounds do not spread it becomes formed to the surface roughness of both of the

Motorola Thyristor Device Data Theory and Applications

1.7–3
 Table 7.1
Approximate Values for Interface Thermal Resistance Data from Measurements Performed
in Motorola Applications Engineering Laboratory
Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless otherwise noted the case
temperature is monitored by a thermocouple located directly under the die reached through a hole in the heatsink. (See Appendix B for a
discussion of Interface Thermal Resistance Measurements.)

Package Type and Data Interface Thermal Resistance (°C/W)

Test Metal-to-Metal With Insulator
JEDEC Torque
Torq e See
Outlines Description In-Lb Dry Lubed Dry Lubed Type Note
DO-203AA, TO-210AA 10-32 Stud 15 0.3 0.2 1.6 0.8 3 mil
TO-208AB 7/16″ Hex Mica
DO-203AB, TO-210AC 1/4-28 Stud 25 0.2 0.1 0.8 0.6 5 mil
TO-208 11/16″ Hex Mica
DO-208AA Pressfit, 1/2″ — 0.15 0.1 — — —
TO-204AA Diamond Flange 6 0.5 0.1 1.3 0.36 3 mil 1
(TO-3) Mica
TO-213AA Diamond Flange 6 1.5 0.5 2.3 0.9 2 mil
(TO-66) Mica
TO-126 Thermopad 6 2.0 1.3 4.3 3.3 2 mil
1/4″ x 3/8″ Mica
TO-220AB Thermowatt 8 1.2 1.0 3.4 1.6 2 mil 1, 2
Mica
NOTES: 1. See Figures 3 and 4 for additional data on TO-3 and TO-220 packages.
2. Screw not insulated. See Figure 12.

heatsink and semiconductor. Manufacturer’s data shows it to mica, have a hard, markedly uneven surface. With many
provide an interface thermal resistance better than a metal isolation materials reduction of interface thermal resistance
interface with filled silicone grease. Similar dry conductive of between 2 to 1 and 3 to 1 are typical when grease is used.
pads are available from other manufacturers. They are a Data obtained by Thermalloy, showing interface resistance
fairly recent development; long term problems, if they exist, for different insulators and torques applied to TO-204 (TO-3)
have not yet become evident. and TO-220 packages, are shown in Figure 7.3, for bare and
greased surfaces. Similar materials to those shown are
INSULATION CONSIDERATIONS available from several manufacturers. It is obvious that with
some arrangements, the interface thermal resistance ex-
Since most power semiconductors use are vertical device ceeds that of the semiconductor (junction to case).
construction it is common to manufacture power semicon- Referring to Figure 7.3, one may conclude that when high
ductors with the output electrode (anode, collector or drain) power is handled, beryllium oxide is unquestionably the best.
electrically common to the case; the problem of isolating this However, it is an expensive choice. (It should not be cut or
terminal from ground is a common one. For lowest overall abraided, as the dust is highly toxic.) Thermafilm is filled
thermal resistance, which is quite important when high power polyimide material which is used for isolation (variation of
must be dissipated, it is best to isolate the entire heatsink/ Kapton). It is a popular material for low power applications
semiconductor structure from ground, rather than to use an because of its low cost ability to withstand high temperatures,
insulator between the semiconductor and the heatsink. and ease of handling in contrast to mica which chips and
Heatsink isolation is not always possible, however, because flakes easily.
of EMI requirements, safety reasons, instances where a A number of other insulating materials are also shown.
chassis serves as a heatsink or where a heatsink is common They cover a wide range of insulation resistance, thermal
to several non-isolated packages. In these situations insula- resistance and ease of handling. Mica has been widely used
tors are used to isolate the individual components from the in the past because it offers high breakdown voltage and
heatsink. Newer packages, such as the Motorola Fully fairly low thermal resistance at a low cost but it certainly
Isolated TO-220, contain the electrical isolation material should be used with grease.
within, thereby saving the equipment manufacturer the Silicone rubber insulators have gained favor because they
burden of addressing the isolation problem. are somewhat conformal under pressure. Their ability to fill in
most of the metal voids at the interface reduces the need for
Insulator Thermal Resistance thermal grease. When first introduced, they suffered from
When an insulator is used, thermal grease is of greater cut-through after a few years in service. The ones presently
importance than with a metal-to-metal contact, because two available have solved this problem by having imbedded pads
interfaces exist instead of one and some materials, such as of Kapton of fiberglass. By comparing Figures 7.3(c) and

Theory and Applications Motorola Thyristor Device Data

1.7–4
 2 1

THERMAL RESISTANCE FROM TRANSISTOR CASE

THERMAL RESISTANCE FROM TRANSISTOR CASE

TO MOUNTING SURFACE, R θ CS ( ° C/WATT)
0.9

TO MOUNTING SURFACE, R θ CS ( ° C/WATT)

1.6 0.8
(1)
1.4 (1) Thermalfilm, .002 (.05) thick. 0.7
(2) (2) Mica, .003 (.08) thick.
1.2 (3) (3) Mica, .002 (.05) thick. 0.6
(4) (4) Hard anodized, .020 (.51) thick. (1)
1 (5) 0.5
(5) Aluminum oxide, .062 (1.57) thick.
0.8 (6) Beryllium oxide, .062 (1.57) thick. 0.4
(7) Bare joint — no finish. (2)
(3)
0.6 (6) 0.3 (5)
(8) Grafoil, .005 (.13) thick.* (4)
(7)
0.4 *Grafoil is not an insulating material. 0.2
(6)
0.2 (7)
0.1
(8)
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
MOUNTING SCREW TORQUE (IN-LBS) MOUNTING SCREW TORQUE (IN-LBS)

0 72 145 217 290 362 435 0 72 145 217 290 362 435
INTERFACE PRESSURE (psi) INTERFACE PRESSURE (psi)

(a). TO-204AA (TO-3) (b). TO-204AA (TO-3)

Without Thermal Grease With Thermal Grease
5 5

THERMAL RESISTANCE FROM TRANSISTOR CASE

THERMAL RESISTANCE FROM TRANSISTOR CASE

(1)

TO MOUNTING SURFACE, R θ CS ( ° C/WATT)

TO MOUNTING SURFACE, R θ CS ( ° C/WATT)

4 4
(1) Thermalfilm, .022 (.05) thick.
(2)
(2) Mica, .003 (.08) thick.
(3)
(3) Mica, .002 (.05) thick.
3 (4) 3
(4) Hard anodized, .020 (.51) thick.
(5) Thermalsil II, .009 (.23) thick.
(6) Thermalsil III, .006 (.15) thick. (1)
2 (7) Bare joint — no finish. 2
(2)
(5) (8) Grafoil, .005 (.13) thick* (3)
(6) *Grafoil is not an insulating material. (4)
(7)
1 (8) 1 (7)

0 0
0 1 2 (IN-LBS) 4 5 6 0 1 2 3 4 5 6
MOUNTING SCREW TORQUE MOUNTING SCREW TORQUE
(IN-LBS) (IN-LBS)

(c). TO-220 (d). TO-220

Without Thermal Grease With Thermal Grease

Figure 7.3. Interface Thermal Resistance for TO-204, TO-3 and TO-220 Packages using Different Insulating Materials
as a Function of Mounting Screw Torque (Data Courtesy Thermalloy)

7.3(d), it can be noted that Thermasil, a filled silicone rubber, Table 7.2 Thermal Resistance of Silicone Rubber Pads
without grease has about the same interface thermal RθCS @ RθCS @
resistance as greased mica for the TO-220 package. Manufacturer Product 3 Mils* 7.5 Mils*
A number of manufacturers offer silicone rubber insulators.
Table 7.2 shows measured performance of a number of these Wakefield Delta Pad 173-7 .790 1.175
Bergquist Sil Pad K-4 .752 1.470
insulators under carefully controlled, nearly identical conditions.
Stockwell Rubber 1867 .742 1.015
The interface thermal resistance extremes are over 2:1 for the Bergquist Sil Pad 400-9 .735 1.205
various materials. It is also clear that some of the insulators are Thermalloy Thermalsil II .680 1.045
much more tolerant than others of out-of-flat surfaces. Since the Shin-Etsu TC-30AG .664 1.260
tests were performed, newer products have been introduced. Bergquist Sil Pad 400-7 .633 1.060
The Bergquist K-10 pad, for example, is described as having Chomerics 1674 .592 1.190
about 2/3 the interface resistance of the Sil Pad 1000 which Wakefield Delta Pad 174-9 .574 .755
would place its performance close to the Chomerics 1671 pad. Bergquist Sil Pad 1000 .529 .935
AAVID also offers an isolated pad called Rubber-Duc, however Ablestik Thermal Wafers .500 .990
it is only available vulcanized to a heatsink and therefore was Thermalloy Thermalsil III .440 1.035
Chomerics 1671 .367 .655
not included in the comparison. Published data from AAVID
* Test Fixture Deviation from flat from Thermalloy EIR86-1010.

Motorola Thyristor Device Data Theory and Applications

1.7–5
shows RθCS below 0.3°C/W for pressures above 500 psi. The conclusions to be drawn from all this data is that some
However, surface flatness and other details are not specified types of silicon rubber pads, mounted dry, will out perform the
so a comparison cannot be made with other data in this note. commonly used mica with grease. Cost may be a determin-
The thermal resistance of some silicone rubber insulators ing factor in making a selection.
is sensitive to surface flatness when used under a fairly rigid
Insulation Resistance
base package. Data for a TO-204AA (TO-3) package
When using insulators, care must be taken to keep the
insulated with Thermasil is shown on Figure 7.4. Observe
mating surfaces clean. Small particles of foreign matter can
that the “worst case” encountered (7.5 mils) yields results
puncture the insulation, rendering it useless or seriously
having about twice the thermal resistance of the “typical
lowering its dielectric strength. In addition, particularly when
case” (3 mils), for the more conductive insulator. In order for
voltages higher than 300 V are encountered, problems with
Thermasil III to exceed the performance of greased mica,
creepage may occur. Dust and other foreign material can
total surface flatness must be under 2 mils, a situation that
shorten creepage distances significantly; so having a clean
requires spot finishing.
assembly area is important. Surface roughness and humidity
also lower insulation resistance. Use of thermal grease
usually raises the withstand voltage of the insulating system
but excess must be removed to avoid collecting dust.
1.2
Because of these factors, which are not amenable to
analysis, hi-pot testing should be done on prototypes and a
INTERFACE THERMAL RESISTANCE (° C/W)

1 (1) large margin of safety employed.

(2)
Insulated Electrode Packages
0.8 Because of the nuisance of handling and installing the
accessories needed for an insulated semiconductor mount-
ing, equipment manufacturers have longed for cost-effective
0.6
insulated packages since the 1950’s. The first to appear
were stud mount types which usually have a layer of
0.4 beryllium oxide between the stud hex and the can. Although
effective, the assembly is costly and requires manual
(1) Thermalsil II, .009 inches (.23 mm) thick.
mounting and lead wire soldering to terminals on top of the
0.2 (2) Thermalsil III, .006 inches (.15 mm) thick. case. In the late eighties, a number of electrically isolated
parts became available from various semiconductor
0 manufacturers. These offerings presently consist of multiple
0 0.002 0.004 0.006 0.008 0.01 chips and integrated circuits as well as the more convention-
al single chip devices.
TOTAL JOINT DEVIATION FROM FLAT OVER
TO-3 HEADER SURFACE AREA (INCHES) The newer insulated packages can be grouped into two
categories. The first has insulation between the semiconduc-
Data courtesy of Thermalloy tor chips and the mounting base; an exposed area of the
Figure 7.4. Effect of Total Surface Flatness on Interface mounting base is used to secure the part. Case 806
Resistance Using Silicon Rubber Insulators (ICePAK) and Case 388A (TO-258AA) (see Figure 7.11) are
examples of parts in this category. The second category
contains parts which have a plastic overmold covering the
metal mounting base. The Fully Isolated, Case 221C,

Silicon rubber insulators have a number of unusual Table 7.3 Performance of Silicon Rubber Insulators
characteristics. Besides being affected by surface flatness Tested per MIL-I-49456
and initial contact pressure, time is a factor. For example, in a
study of the Cho-Therm 1688 pad thermal interface imped- Measured Thermal Resistance (°C/W)
ance dropped from 0.90°C/W to 0.70°C/W at the end of 1000 Material Thermalloy Data(1) Berquist Data(2)
hours. Most of the change occurred during the first 200 hours
Bare Joint
Joint, greased 0 033
0.033 0 008
0.008
where RθCS measured 0.74°C/W. The torque on the conven- BeO,
BeO greased 0.082
0 082 —
tional mounting hardware had decreased to 3 in-lb from an Cho-Therm 1617
Cho-Therm, 0 233
0.233 —
initial 6 in-lb. With non-conformal materials, a reduction in Q Pad (non-insulated) — 0 009
0.009
torque would have increased the interface thermal resis- Sil-Pad,
Sil Pad K-10
K 10 0.263
0 263 0.200
0 200
tance. Thermasil III 0 267
0.267 —
Because of the difficulties in controlling all variables Mica,
Mica greased 0.329
0 329 0.400
0 400
affecting tests of interface thermal resistance, data from Sil Pad 1000
Sil-Pad 0 400
0.400 0 300
0.300
different manufacturers is not in good agreement. Table 7.3 Cho-therm
Cho therm 1674 0.433
0 433 —
Th
Thermasilil II 0 500
0.500 —
shows data obtained from two sources. The relative perfor-
Sil P d 400
Sil-Pad 0 533
0.533 0 440
0.440
mance is the same, except for mica which varies widely in
Sil-Pad
Sil P d K-4
K4 0.583
0 583 0.440
0 440
thickness. Appendix B discusses the variables which need to
be controlled. At the time of this writing ASTM Committee D9 1. From Thermalloy EIR 87-1030
is developing a standard for interface measurements. 2. From Berquist Data Sheet

Theory and Applications Motorola Thyristor Device Data

1.7–6
illustrated in figure 7.13, is an example of parts in the second Clips
category. Fast assembly is accomplished with clips. When only a few
Parts in the first category — those with an exposed metal watts are being dissipated, the small board mounted or
flange or tab — are mounted the same as their non-insulated free-standing heat dissipators with an integral clip, offered by
counterparts. However, as with any mounting system where several manufacturers, result in a low cost assembly. When
pressure is bearing on plastic, the overmolded type should higher power is being handled, a separate clip may be used
be used with a conical compression washer, described later with larger heatsinks. In order to provide proper pressure, the
in this note. clip must be specially designed for a particular heatsink
thickness and semiconductor package.
FASTENER AND HARDWARE CHARACTERISTICS Clips are especially popular with plastic packages such as
Characteristics of fasteners, associated hardware, and the the TO-220 and TO-126. In addition to fast assembly, the clip
tools to secure them determine their suitability for use in provides lower interface thermal resistance than other
mounting the various packages. Since many problems have assembly methods when it is designed for proper pressure to
arisen because of improper choices, the basic characteristics bear on the top of the plastic over the die. The TO-220
of several types of hardware are discussed next. package usually is lifted up under the die location when
mounted with a single fastener through the hole in the tab
Compression Hardware
because of the high pressure at one end.
Normal split ring lock washers are not the best choice for
mounting power semiconductors. A typical #6 washer Machine Screws
flattens at about 50 pounds, whereas 150 to 300 pounds is Machine screws, conical washers, and nuts (or syncnuts)
needed for good heat transfer at the interface. A very useful can form a trouble-free fastener system for all types of
piece of hardware is the conical, sometimes called a packages which have mounting holes. However, proper
Belleville washer, compression washer. As shown in Figure torque is necessary. Torque ratings apply when dry; there-
7.5, it has the ability to maintain a fairly constant pressure fore, care must be exercised when using thermal grease to
over a wide range of its physical deflection — generally 20% prevent it from getting on the threads as inconsistent torque
to 80%. When installing, the assembler applies torque until readings result. Machine screw heads should not directly
the washer depresses to half its original height. (Tests should contact the surface of plastic packages types as the screw
be run prior to setting up the assembly line to determine the heads are not sufficiently flat to provide properly distributed
proper torque for the fastener used to achieve 50% deflec- force. Without a washer, cracking of the plastic case may
tion.) The washer will absorb any cyclic expansion of the occur.
package, insulating washer or other materials caused by
temperature changes. Conical washers are the key to Self-Tapping Screws
successful mounting of devices requiring strict control of the Under carefully controlled conditions, sheet-metal screws
mounting force or when plastic hardware is used in the are acceptable. However, during the tapping process with a
mounting scheme. They are used with the large face standard screw, a volcano-like protrusion will develop in the
contacting the packages. A new variation of the conical metal being threaded; an unacceptable surface that could
washer includes it as part of a nut assembly. Called a Sync increase the thermal resistance may result. When standard
Nut, the patented device can be soldered to a PC board and sheet metal screws are used, they must be used in a
the semiconductor mounted with 6-32 machine screw.(4) clearance hole to engage a speednut. If a self tapping
process is desired, the screw type must be used which
280 roll-forms machine screw threads.
PRESSURE ON PACKAGE (LB-F)

240 Rivets
Rivets are not a recommended fastener for any of the
200 plastic packages. When a rugged metal flange-mount
package is being mounted directly to a heatsink, rivets can
160
be used provided press-riveting is used. Crimping force must
be applied slowly and evenly. Pop-riveting should never be
120
used because the high crimping force could cause deforma-
80 tion of most semiconductor packages. Aluminum rivets are
much preferred over steel because less pressure is required
40 to set the rivet and thermal conductivity is improved.
The hollow rivet, or eyelet, is preferred over solid rivets. An
0 adjustable, regulated pressure press is used such that a
0 20 40 60 80 100
gradually increasing pressure is used to pan the eyelet. Use
DEFLECTION OF WASHER DURING MOUNTING (%) of sharp blows could damage the semiconductor die.
Figure 7.5. Characteristics of the Conical Compression
Solder
Washers Designed for Use with Plastic Body Mounted
Until the advent of the surface mount assembly technique,
Semiconductors
solder was not considered a suitable fastener for power
semiconductors. However, user demand has led to the
development of new packages for this application. Accept-
(4) ITW Shakeproof, St. Charles Road, Elgin, IL 60120. able soldering methods include conventional beltfurnace,

Motorola Thyristor Device Data Theory and Applications

1.7–7
irons, vapor-phase reflow, and infrared reflow. It is important To prevent galvanic action from occurring when devices
that the semiconductor temperature not exceed the specified are used on aluminum heatsinks in a corrosive atmosphere,
maximum (usually 260°C) or the die bond to the case could many devices are nickel- or gold-plated. Consequently,
be damaged. A degraded die bond has excessive thermal precautions must be taken not to mar the finish.
resistance which often leads to a failure under power cycling. Another factor to be considered is that when a copper
based part is rigidly mounted to an aluminium heatsink, a
Adhesives
bimetallic system results which will bend with temperature
Adhesives are available which have coefficients of expan-
changes. Not only is the thermal coefficient of expansion
sion compatible with copper and aluminum.(5) Highly con-
different for copper and aluminium, but the temperature
ductive types are available; a 10 mil layer has approximately
gradient through each metal also causes each component to
0.3°C/W interface thermal resistance. Different types are
bend. If bending is excessive and the package is mounted
offered: high strength types for non-field-serviceable systems
by two or more screws the semiconductor chip could be
or low strength types for field-serviceable systems. Adhesive
damaged. Bending can be minimized by:
bonding is attractive when case mounted parts are used in
wave soldering assembly because thermal greases are not 1. Mounting the component parallel to the heatsink fins to
compatible with the conformal coatings used and the provide increased stiffness.
greases foul the solder process. 2. Allowing the heatsink holes to be a bit oversized so that
some slip between surfaces can occur as temperature
Plastic Hardware changes.
Most plastic materials will flow, but differ widely in this 3. Using a highly conductive thermal grease or mounting
characteristic. When plastic materials form parts of the pad between the heatsink and semicondutor to minimize
fastening system, compression washers are highly valuable the temperature gradient and allow for movement.
to assure that the assembly will not loosen with time and
temperature cycling. As previously discussed, loss of contact Stud Mount
pressure will increase interface thermal resistance. Parts which fall into the stud-mount classification are
shown in Figure 7.6. Mounting errors with non-insulated
stud-mounted parts are generally confined to application of
FASTENING TECHNIQUES

(5) Robert Batson, Elliot Fraunglass and James P. Moran, “Heat

Each of the various classes of packages in use requires
Dissipation Through Thermalloy Conductive Adhesives, ”EMTAS
different fastening techniques. Details pertaining to each type ’83. Conference, February 1–3, Phoenix, AZ; Society of
are discussed in following sections. Some general consider- Manufacturing Engineers, One SME Drive, P.O. Box 930,
ations follow. Dearborn, MI 48128.

CASE 42A CASE 56-03 CASE 245 CASE 257 CASE 263-04
(DO-5) DO-203AA (DO-4) DO-203AB
(DO-4) (DO-5) CASE 311-02

6a. Standard Non-Isolated Types 6b. Isolated Type

CASE 144B-05 CASE 145A-09 CASE 145A-10 CASE 244-04 CASE 305-01 CASE 332-04
(.380″ STUD) (.380″ STUD) (.500″ STUD) (.280″ STUD) (.204″ STUD) (.380″ STUD)

6c. RF Stripline Opposed Emitter (SOE) Series

Figure 7.6 A Variety of Stud-Mount Parts

Theory and Applications Motorola Thyristor Device Data

1.7–8
excessive torque or tapping the stud into a threaded heatsink
hole. Both these practices may cause a warpage of the hex
base which may crack the semiconductor die. The only CHAMFER
recommended fastening method is to use a nut and washer;
.01 NOM.
the details are shown in Figure 7.7.
SHOULDER RING
Insulated electrode packages on a stud mount base
require less hardware. They are mounted the same as their .501 .01 NOM.
non-insulated counterparts, but care must be exercised to .505 DIA.
HEATSINK
avoid applying a shear or tension stress to the insulation .24
layer, usually a berrylium oxide (BeO) ceramic. This require-
ment dictates that the leads must be attached to the circuit 0.0499 ± 0.001 DIA.
with flexible wire. In addition, the stud hex should be used to
hold the part while the nut is torqued. Heat Sink Mounting
R.F. transistors in the stud-mount stripline opposed emitter
(SOE) package impose some additional constraints because
of the unique construction of the package. Special tech- RIVET ADDITIONAL
niques to make connections to the stripline leads and to HEATSINK PLATE
mount the part so no tension or shear forces are applied to
any ceramic — metal interface are discussed in the section
entitled “Connecting and Handling Terminals.” COMPLETE THIN CHASSIS
INTIMATE
KNURL CONTACT
CONTACT AREA
AREA
Thin-Chassis Mounting

The hole edge must be chamfered as shown to prevent

shearing off the knurled edge of the case during press-in. The
INSULATOR pressing force should be applied evenly on the shoulder ring to
avoid tilting or canting of the case in the hole during the pressing
TEFLON BUSHING operation. Also, the use of a thermal joint compound will be of
considerable aid. The pressing force will vary from 250 to 1000
pounds, depending upon the heatsink material. Recommended
hardnesses are: copper-less than 50 on the Rockwell F scale;
CHASSIS aluminum-less than 65 on the Brinell scale. A heatsink as thin as
1/8″ may be used, but the interface thermal resistance will
INSULATOR increase in direct proportion to the contact area. A thin chasis
requires the addition of a backup plate.

FLAT STEEL WASHER

SOLDER TERMINAL
Figure 7.8. Press-Fit Package

CONICAL WASHER Flange Mount

A large variety of parts fit into the flange mount category as
shown in Figure 7.9. Few known mounting difficulties exist
with the smaller flange mount packages, such as the TO-204
HEX NUT
(TO-3). The rugged base and distance between die and
mounting holes combine to make it extremely difficult to
cause any warpage unless mounted on a surface which is
badly bowed or unless one side is tightened excessively
Figure 7.7. Isolating Hardware Used for a Non-Isolated before the other screw is started. It is therefore good practice
Stud-Mount Package to alternate tightening of the screws so that pressure is
evenly applied. After the screws are finger-tight the hardware
should be torqued to its final specification in at least two
Press Fit sequential steps. A typical mounting installation for a popular
For most applications, the press-fit case should be flange type part is as shown in Figure 7.10. Machine screws
mounted according to the instructions shown in Figure 7.8. A (preferred) self-tapping screws, eyelets, or rivets may be
special fixture meeting necessary requirements must be used to secure the package using guidelines in the previous
used. section. “Fastener and Hardware Characteristics.”

Motorola Thyristor Device Data Theory and Applications

1.7–9
 CASE 211-07 CASE 211-11 CASE 215-02

CASE 357C-03
CASE 1, 11
TO-204AA CASE 383-01
(TO-3)

(a). TO-3 Variations (b). Plastic Power Tap

CASE 316-01 CASE 319-07 CASE 328A-03
(CS-12)

CASE 333-04 CASE 333A-02 CASE 336-03

(MAAC PAC)

CASE 337-02 CASE 744A-01 CASE 368-02

(HOG PAC)

(d). RF Stripline Isolated Output Opposed Emitter

(SOE) Series

Figure 7.9. A Large Array of Parts Fit into the Flange-Mount Classification

Some packages specify a tightening procedure. For Although the data sheets contain information on recom-
example, with the Power Tap package, Figure 7.9(b), final mended mounting procedures, experience indicates that
torque should be applied first to the center position. they are often ignored. For example, the recommended
The RF power modules (MHW series) are more sensitive maximum torque on the 4-40 mounting screws is 5 in/lbs.
to the flatness of the heatsink than other packages because Spring and flat washers are recommended. Over torquing is
a ceramic (BeO) substrate is attached to a relatively thin, a common problem. In some parts returned for failure
fairly long, flange. The maximum allowable flange bending to analysis, indentions up to 10 mils deep in the mounting screw
avoid mechanical damage has been determined and pres- areas have been observed.
ented in detail in EB107 “Mounting Considerations for
Calculations indicate that the length of the flange in-
Motorola RF Power Modules.” Many of the parts can handle
creases in excess of two mils with a temperature change of
a combined heatsink and flange deviation from flat of 7 to 8
mils which is commonly available. Others must be held to 1.5 75°C. In such cases, if the mounting screw torque is
mils, which requires that the heatsink have nearly perfect excessive, the flange is prevented from expanding in length,
flatness. instead it bends upwards in the mid-section, cracking the
Specific mounting recommendations are critical to RF BeO and the die. A similar result can also occur during the
devices in isolated packages because of the internal ceramic initial mounting of the device if an excessive amount of
substrate. The large area Case 368-02 (HOG PAC) will be thermal compound is applied. With sufficient torque, the
used to illustrate problem areas. It is more sensitive to proper thermal compound will squeeze out of the mounting hole
mounting techniques that most other RF power devices. areas, but will remain under the center of the flange,

Theory and Applications Motorola Thyristor Device Data

1.7–10
 inch (6–32 clearance). Larger holes are needed to accom-
NO.6 SHEET METAL SCREWS modate the lower insulating bushing when the screw is
electrically connected to the case; however, the holes should
not be larger than necessary to provide hardware clearance
and should never exceed a diameter of 0.250 inch. Flange
distortion is also possible if excessive torque is used during
mounting. A maximum torque of 8 inch-pounds is suggested
when using a 6–32 screw.
Care should be exercised to assure that the tool used to
drive the mounting screw never comes in contact with the
POWER plastic body during the driving operation. Such contact can
TRANSISTOR
result in damage to the plastic body and internal device
INSULATOR
connections. To minimize this problem, Motorola TO-220
packages have a chamfer on one end. TO-220 packages of
other manufacturers may need a spacer or combination
spacer and isolation bushing to raise the screw head above
the top surface of the plastic.
The popular TO-220 Package and others of similar con-
struction lift off the mounting surface as pressure is applied
INSULATING
BUSHING
to one end. (See Appendix B, Figure B1.) To counter this
HEAT tendency, at least one hardware manufacturer offers a hard
SINK plastic cantilever beam which applies more even pressure on
the tab.(6) In addition, it separates the mounting screw from

(6) Catalog, Edition 18, Richco Plastic Company, 5825 N. Tripp Ave.,
Chicago, IL 60546.

SOCKET

Figure 7.10. Hardware Used for a TO-204AA (TO-3)

Flange Mount Part
CASE 221A-04 221B-03
(TO-220AB) (TO-220AC)

deforming it. Deformations of 2–3 mils have been measured

between the center and the ends under such conditions
(enough to crack internal ceramic).
Another problem arises because the thickness of the
flange changes with temperature. For the 75°C temperature
excursion mentioned, the increased amount is around 0.25
mils which results in further tightening of the mounting
screws, thus increasing the effective torque from the initial
value. With a decrease in temperature, the opposite effect CASE 314B CASE 314D CASE 339
occurs. Therefore thermal cycling not only causes risk of (5 PIN TO-220)
structural damage but often causes the assembly to loosen
which raises the interface resistance. Use of compression
hardware can eliminate this problem.

Tab Mount
The tab mount class is composed of a wide array of
packages as illustrated in Figure 7.11. Mounting consider-
ations for all varieties are similar to that for the popular CASE 340-02 CASE 387-01 CASE 806-05
TO-220 package, whose suggested mounting arrangements (TO-218) (TO-254AA) (ICePAK)
and hardware are shown in Figure 7.12. The rectangular CASE 388A-01
(TO-258AA)
washer shown in Figure 7.12(a) is used to minimize distortion
of the mounting flange; excessive distortion could cause
damage to the semiconductor chip. Use of the washer is only
important when the size of the mounting hole exceeds 0.140 Figure 7.11. Several Types of Tab-Mount Parts

Motorola Thyristor Device Data Theory and Applications

1.7–11
 Plastic Body Mount
(a). Preferred Arrangement (b). Alternate Arrangement The Thermopad and fully isolated plastic power packages
for Isolated or Non-Isolated for Isolated Mounting when
shown in Figure 7.13 are typical of packages in this group.
Mounting. Screw is at Screw must be at Heat Sink
Potential. 4-40 Hardware is They have been designed to feature minimum size with no
Semiconductor Case
Potential. 6-32 Hardware is used. compromise in thermal resistance. For the Thermopad (Case
Used. 77) parts this is accomplished by die-bounding the silicon
Use Parts Listed below. chip on one side of a thin copper sheet; the opposite side is
Use Parts Listed exposed as a mounting surface. The copper sheet has a hole
Below for mounting; plastic is molded enveloping the chip but
leaving the mounting hole open. The low thermal resistance
4-40 PAN OR HEX HEAD SCREW
of this construction is obtained at the expense of a
requirement that strict attention be paid to the mounting
6-32 HEX
HEAD SCREW procedure.
FLAT WASHER The fully isolated power package (Case 221C-02) is
similar to a TO-220 except that the tab is encased in plastic.
INSULATING BUSHING
Because the mounting force is applied to plastic, the
mounting procedure differs from a standard TO-220 and is
similar to that of the Thermopad.
(1) RECTANGULAR STEEL
Several types of fasteners may be used to secure these
WASHER packages; machine screws, eyelets, or clips are preferred.
SEMICONDUCTOR
(CASE 221, 221A) With screws or eyelets, a conical washer should be used
which applies the proper force to the package over a fairly
SEMICONDUCTOR
(CASE 221,221A) wide range of deflection and distributes the force over a fairly
large surface area. Screws should not be tightened with any
(2) RECTANGULAR type of air-driven torque gun or equipment which may cause
INSULATOR
high impact. Characteristics of a suitable conical washer is
HEATSINK RECTANGULAR
shown in Figure 7.5.
INSULATOR Figure 7.14 shows details of mounting Case 77 devices.
Clip mounting is fast and requires minimum hardware,
(2) BUSHING however, the clip must be properly chosen to insure that the
HEATSINK
proper mounting force is applied. When electrical isolation is
required with screw mounting, a bushing inside the mounting
(3) FLAT WASHER hole will insure that the screw threads do not contact the
COMPRESSION WASHER metal base.
(4) CONICAL WASHER The fully isolated power package, (Case 221C, 221D and
340B) permits the mounting procedure to be greatly simpli-
6-32 HEX NUT fied over that of a standard TO-220. As shown in Figure
4-40 HEX NUT
7.15(c), one properly chosen clip, inserted into two slotted
holes in the heatsink, is all the hardware needed. Even
though clip pressure is much lower than obtained with a
(1) Used with thin chassis and/or large hole. screw, the thermal resistance is about the same for either
(2) Used when isolation is required. method. This occurs because the clip bears directly on top of
(3) Required when nylon bushing is used. the die and holds the package flat while the screw causes the
package to lift up somewhat under the die. (See Figure B1 of
Appendix B.) The interface should consist of a layer of
Figure 7.12. Mounting Arrangements for Tab Mount TO-220 thermal grease or a highly conductive thermal pad. Of
course, screw mounting shown in Figure 7.15(b) may also be
used but a conical compression washer should be included.
the metal tab. Tab mount parts may also be effectively Both methods afford a major reduction in hardware as
mounted with clips as shown in Figure 7.51(c). To obtain high compared to the conventional mounting method with a
pressure without cracking the case, a pressure spreader bar TO-220 package which is shown in Figure 7.15(a).
should be used under the clip. Interface thermal resistance
with the cantilever beam or clips can be lower than with
screw mounting.
The ICePAK (Case 806-05) is basically an elongated
TO-220 package with isolated chips. The mounting precau-
tions for the TO-220 consequently apply. In addition, since
two mounting screws are required, the alternate tightening
CASE 77 CASE 221C-02 CASE 221D-02 CASE 340B-03
procedure described for the flange mount package should be (TO-225AA/ (Fully Isolated) (Fully Isolated) (Fully Isolated)
used. TO-126)
(THERMOPAD)
In situations where a tab mount package is making direct
contact with the heatsink, an eyelet may be used, provided Figure 7.13. Plastic Body-Mount Packages
sharp blows or impact shock is avoided.

Theory and Applications Motorola Thyristor Device Data

1.7–12
 MACHINE SCREW OR
SHEET METAL SCREW
4-40 SCREW

HEAT SINK COMPRESSION WASHER

SURFACE PLAIN WASHER
THERMOPAD PACKAGE INSULATING BUSHING

INSULATING WASHER
(OPTIONAL)

MACHINE OR SPEED
NUT INSULATOR

HEATSINK
(a). Machine Screw Mounting
COMPRESSION WASHER

NUT
EYELET

(a). Screw-Mounted TO-220

COMPRESSION WASHER
6-32 SCREW

PLAIN WASHER

INSULATING WASHER
(OPTIONAL)

HEATSINK

(b). Eyelet Mounting

COMPRESSION WASHER

NUT

(b). Screw-Mounted Fully Isolated

CLIP

(c). Clips

Figure 7.14. Recommended Mounting Arrangements

for TO-225AA (TO-126) Thermopad Packages

Surface Mount HEATSINK

Although many of the tab mount parts have been surface
mounted, special small footprint packages for mounting
power semiconductors using surface mount assembly tech- (c). Clip-Mounted Fully Isolated
niques have been developed. The DPAK, shown in Figure
16, for example, will accommodate a die up to 112 mils x 112
mils, and has a typical thermal resistance around 2°C/W Figure 7.15. Mounting Arrangements for the Fully Iso-
junction to case. The thermal resistance values of the solder lated Power Package as Compared to a Conventional TO-220

Motorola Thyristor Device Data Theory and Applications

1.7–13
 interface is well under 1°C/W. The printed circuit board also metal power packages are not designed to support the
serves as the heatsink. packages; their cases must be firmly supported to avoid the
Standard Glass-Epoxy 2-ounce boards do not make very possibility of cracked seals around the leads. Many plastic
good heatsinks because the thin foil has a high thermal packages may be supported by their leads in applications
resistance. As Figure 7.17 shows, thermal resistance assym- where high shock and vibration stresses are not encountered
totes to about 20°C/W at 10 square inches of board area, and where no heatsink is used. The leads should be as short
although a point of diminishing returns occurs at about 3 as possible to increase vibration resistance and reduce
square inches. thermal resistance. As a general practice however, it is better
Boards are offered that have thick aluminium or copper to support the package. A plastic support for the TO-220
substrates. A dielectric coating designed for low thermal Package and other similar types is offered by heatsink
resistance is overlayed with one or two ounce copper foil for accessory vendors.
the preparation of printed conductor traces. Tests run on In many situations, because its leads are fairly heavy, the
such a product indicate that case to substrate thermal CASE 77 (TO-225AA)(TO-127) package has supported a
resistance is in the vicinity of 1°C/W, exact values depending small heatsink; however, no definitive data is available. When
upon board type.(7) The substrate may be an effective using a small heatsink, it is good practice to have the sink
heatsink itself, or it can be attached to a conventional finned rigidly mounted such that the sink or the board is providing
heatsink for improved performance. total support for the semiconductor. Two possible arrange-
Since DPAK and other surface mount packages are ments are shown in Figure 7.18. The arrangement of part (a)
designed to be compatible with surface mount assembly could be used with any plastic package, but the scheme of
techniques, no special precautions are needed other than to
insure that maximum temperature/time profiles are not
exceeded. HEATSINK

TO-225AA
CASE 77
HEATSINK SURFACE

CASE 369-06 CASE 369A-12 TWIST LOCKS

OR
CIRCUIT BOARD SOLDERABLE
LEGS
Figure 7.16. Surface Mount D-PAK Parts
(a). Simple Plate, Vertically Mounted
100
Rθ JA, THERMAL RESISTANCE ( ° C/W)

HEATSINK
PCB, 1/16 IN THICK
80
G10/FR4, 2 OUNCE
EPOXY GLASS BOARD,
DOUBLE SIDED
60

40

20 TO-225AA
CASE 77
HEATSINK
0 SURFACE
2 4 6 8 10 CIRCUIT BOARD

PCB PAD AREA (IN2)

Figure 7.17. Effect of Footprint Area on Thermal

Resistance of DPAK Mounted on a Glass-Epoxy Board

FREE AIR AND SOCKET MOUNTING

In applications where average power dissipation is on the (b). Commercial Sink, Horizontally Mounted
order of a watt or so, most power semiconductors may be
mounted with little or no heatsinking. The leads of the various

(7) Herb Fick, “Thermal Management of Surface Mount Power

Figure 7.18. Methods of Using Small Heatsinks With
Devices,” Power conversion and Intelligent Motion, August 1987. Plastic Semiconductor Packages

Theory and Applications Motorola Thyristor Device Data

1.7–14
part (b) is more practical with Case 77 Thermopad devices. When wires are used for connections, care should be
With the other package types, mounting the transistor on top exercised to assure that movement of the wire does not
of the heatsink is more practical. cause movement of the lead at the lead-to-plastic junctions.
In certain situations, in particular where semiconductor Highly flexible or braided wires are good for providing strain
testing is required or prototypes are being developed, relief.
sockets are desirable. Manufacturers have provided sockets Wire-wrapping of the leads is permissible, provided that
for many of the packages available from Motorola. The user the lead is restrained between the plastic case and the point
is urged to consult manufacturers’ catalogs for specific of the wrapping. The leads may be soldered; the maximum
details. Sockets with Kelvin connections are necessary to
obtain accurate voltage readings across semiconductor
terminals.

CERAMIC
CONNECTING AND HANDLING TERMINALS TRANSISTOR CAP
CHIP

Pins, leads, and tabs must be handled and connected

properly to avoid undue mechanical stress which could
cause semiconductor failure. Change in mechanical dimen- LEADS METALLIC
sions as a result of thermal cycling over operating tempera- PATTERN

ture extremes must be considered. Standard metal, plastic,

and RF stripline packages each have some special consider-
ations.
BeO
SURFACE S
DISC
WRENCH
FLAT
Metal Packages
The pins and lugs of metal packaged devices using glass (a). Component Parts of a Stud Mount Stripline
to metal seals are not designed to handle any significant Package. Flange Mounted Packages
bending or stress. If abused, the seals could crack. Wires are Similarly Constructed
may be attached using sockets, crimp connectors or solder,
provided the data sheet ratings are observed. When wires
are attached directly to the pins, flexible or braided leads are
“D” FLAT
recommended in order to provide strain relief.

Plastic Packages PRINTED PRINTED

The leads of the plastic packages are somewhat flexible CIRCUIT TOP CONDUCTOR
BOARD VIEW PATTERN
and can be reshaped although this is not a recommended
procedure. In many cases, a heatsink can be chosen which HEAT
SINK
makes lead-bending unnecessary. Numerous-lead and tab- SURFACE H METAL
HEAT
forming options are available from Motorola on large quantity “D” FLAT SINK
orders. Preformed leads remove the users risk of device
SIDE VIEW
damage caused by bending. CROSS SECTION
If, however, lead-bending is done by the user, several
(b). Typical Stud Type SOE Transistor
basic considerations should be observed. When bending the
Mounting Method
lead, support must be placed between the point of bending
and the package. For forming small quantities of units, a pair
of pliers may be used to clamp the leads at the case, while
MOUNTING
bending with the fingers or another pair of pliers. For HOLES
production quantities, a suitable fixture should be made.
The following rules should be observed to avoid damage METAL
HEATSINK
to the package. SURFACE

1. A leadbend radius greater than 1/16 inch is advisable for COPPER

CIRCUIT TOP VIEW
MOUNTING CONDUCTORS
TO-225AA (CASE 77) and 1/32 inch for TO-220. BOARD
HOLES
2. No twisting of leads should be done at the case. H
ALIGNMENT
3. No axial motion of the lead should be allowed with re- SPACER
spect to the case.
METAL HEAT SIDE VIEW
The leads of plastic packages are not designed to SINK SURFACE CROSS SECTION
withstand excessive axial pull. Force in this direction greater
than 4 pounds may result in permanent damage to the (c). Flange Type SOE Transistor Mounting Method
device. If the mounting arrangement imposes axial stress on
the leads, a condition which may be caused by thermal
cycling, some method of strain relief should be devised. Figure 7.19. Mounting Details for SOE Transistors

Motorola Thyristor Device Data Theory and Applications

1.7–15
soldering temperature, however, must not exceed 260°C and devices, since they do not damage the package. Hydrocar-
must be applied for not more than 5 seconds at a distance bons such as gasoline and chlorinated Freon may cause the
greater than 1/8 inch from the plastic case. encapsulant to swell, possibly damaging the transistor die.
When using an ultrasonic cleaner for cleaning circuit
Stripline Packages boards, care should be taken with regard to ultrasonic energy
The leads of stripline packages normally are soldered into and time of application. This is particularly true if any
a board while the case is recessed to contact a heatsink as packages are free-standing without support.
shown in Figure 7.19. The following rules should be
observed: THERMAL SYSTEM EVALUATION
1. The device should never be mounted in such a manner
Assuming that a suitable method of mounting the semicon-
as to place ceramic-to-metal joints in tension.
ductor without incurring damage has been achieved, it is
2. The device should never be mounted in such a manner
important to ascertain whether the junction temperature is
as to apply force on the strip leads in a vertical direction
within bounds.
towards the cap.
In applications where the power dissipated in the semicon-
3. When the device is mounted in a printed circuit board
ductor consists of pulses at a low duty cycle, the instanta-
with the copper stud and BeO portion of the header
neous or peak junction temperature, not average
passing through a hole in the circuit boards, adequate
temperature, may be the limiting condition. In this case, use
clearance must be provided for the BeO to prevent shear
must be made of transient thermal resistance data. For a full
forces from being applied to the leads.
explanation of its use, see Motorola Application Note,
4. Some clearance must be allowed between the leads and
AN569.
the circuit board when the device is secured to the heat-
Other applications, notably RF power amplifiers or
sink.
switches driving highly reactive loads, may create severe
5. The device should be properly secured into the heat-
current crowding conditions which render the traditional
sinks before its leads are attached into the circuit.
concepts of thermal resistance or transient thermal imped-
6. The leads on stud type devices must not be used to pre-
ance invalid. In this case, transistor safe operating area,
vent device rotation during stud torque application. A
thyristor di/dt limits, or equivalent ratings as applicable, must
wrench flat is provided for this purpose.
be observed.
Figure 7.19(b) shows a cross-section of a printed circuit
Fortunately, in many applications, a calculation of the
board and heatsink assembly for mounting a stud type strip-
average junction temperature is sufficient. It is based on the
line device. H is the distance from the top surface of the
concept of thermal resistance between the junction and a
printed circuit board to the D-flat heatsink surface. If H is less
temperature reference point on the case. (See Appendix A.)
than the minimum distance from the bottom of the lead
A fine wire thermocouple should be used, such as #36 AWG,
material to the mounting surface of the package, there is no
to determine case temperature. Average operating junction
possibility of tensile forces in the copper stud — BeO ceramic
temperature can be computed from the following equation:
joint. If, however, H is greater than the package dimension,
considerable force is applied to the cap to BeO joint and the + )
TJ T C R qJC PD
BeO to stud joint. Two occurrences are possible at this point. where TJ = junction temperature (°C)
The first is a cap joint failure when the structure is heated, as TC = case temperature (°C)
might occur during the lead-soldering operation; while the RθJC = thermal resistance junction-
second is BeO to stud failure if the force generated is high to-case as specified on the
enough. Lack of contact between the device and the heat- data sheet (°C/W)
sink surface will occur as the differences between H and the PD = power dissipated in the device (W)
package dimension become larger, this may result in device The difficulty in applying the equation often lies in
failure as power is applied. determining the power dissipation. Two commonly used
Figure 7.19(c) shows a typical mounting technique for empirical methods are graphical integration and substitution.
flange-type stripline transistors. Again, H is defined as the
distance from the top of the printed circuit board to the Graphical Integration
heatsink surface. If distance H is less than the minimum Graphical integration may be performed by taking oscillo-
distance from the bottom of transistor lead to the bottom scope pictures of a complete cycle of the voltage and current
surface of the flange, tensile forces at the various joints in the waveforms, using a limit device. The pictures should be
package are avoided. However, if distance H exceeds the taken with the temperature stabilized. Corresponding points
package dimension, problems similar to those discussed for are then read from each photo at a suitable number of time
the stud type devices can occur. increments. Each pair of voltage and current values are
multiplied together to give instantaneous values of power.
CLEANING CIRCUIT BOARDS The results are plotted on linear graph paper, the number of
squares within the curve counted, and the total divided by the
It is important that any solvents or cleaning chemicals used number of squares along the time axis. The quotient is the
in the process of degreasing or flux removal do not affect the average power dissipation. Oscilloscopes are available to
reliability of the devices. Alcohol and unchlorinated Freon perform these measurements and make the necessary
solvents are generally satisfactory for use with plastic calculations.

Theory and Applications Motorola Thyristor Device Data

1.7–16
 temperature is monitored. By throwing the switch to the “test”
position, the device under test is connected to a dc power
supply, while another pole of the switch supplies the normal
power to the load to keep it operating at full power level. The
dc supply is adjusted so that the semiconductor case
Substitution temperature remains approximately constant when the
This method is based upon substituting an easily measur- switch is thrown to each position for about 10 seconds. The
able, smooth dc source for a complex waveform. A switching dc voltage and current values are multiplied together to
arrangement is provided which allows operating the load with obtain average power. It is generally necessary that a Kelvin
the device under test, until it stabilizes in temperature. Case connection be used for the device voltage measurement.

APPENDIX A
THERMAL RESISTANCE CONCEPTS

The basic equation for heat transfer under steady-state where TJ = junction temperature,
conditions is generally written as: PD = power dissipation
q+ hADT (1) RθJC = semiconductor thermal resistance
where q = rate of heat transfer or power (junction to case),
dissipation (PD) RθCS = interface thermal resistance
h = heat transfer coefficient, (case to heatsink),
A = area involved in heat transfer, RθSA = heatsink thermal resistance
∆T = temperature difference between (heatsink to ambient),
regions of heat transfer. TA = ambient temperature.
However, electrical engineers generally find it easier to
work in terms of thermal resistance, defined as the ratio of The thermal resistance junction to ambient is the sum of
temperature to power. From Equation 1, thermal resistance, the individual components. Each component must be mini-
Rθ, is mized if the lowest junction temperature is to result.
Rq + ń + ń
DT q 1 hA (2) The value for the interface thermal resistance, RθCS, may
be significant compared to the other thermal-resistance
The coefficient (h) depends upon the heat transfer mecha-
terms. A proper mounting procedure can minimize RθCS.
nism used and various factors involved in that particular
The thermal resistance of the heatsink is not absolutely
mechanism.
constant; its thermal efficiency increases as ambient temper-
An analogy between Equation (2) and Ohm’s Law is often
ature increases and it is also affected by orientation of the
made to form models of heat flow. Note that T could be
thought of as a voltage thermal resistance corresponds to sink. The thermal resistance of the semiconductor is also
electrical resistance (R); and, power (q) is analogous to variable; it is a function of biasing and temperature. Semicon-
current (I). This gives rise to a basic thermal resistance model ductor thermal resistance specifications are normally at
for a semiconductor as indicated by Figure A1. conditions where current density is fairly uniform. In some
The equivalent electrical circuit may be analyzed by using applications such as in RF power amplifiers and short-pulse
Kirchoff’s Law and the following equation results: applications, current density is not uniform and localized
TJ + PD(RqJC ) RqCS ) RqSA) ) TA(3) heating in the semiconductor chip will be the controlling
factor in determining power handling ability.

TJ, JUNCTION TEMPERATURE

DIE RθJC
PD
TC, CASE TEMPERATURE
INSULATORS
RθCS
TS, HEATSINK
HEATSINK TEMPERATURE
RθSA
TA, AMBIENT
FLAT WASHER TEMPERATURE

SOLDER TERMINAL

NUT REFERENCE TEMPERATURE

Figure A1. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor

Motorola Thyristor Device Data Theory and Applications

1.7–17
 APPENDIX B
MEASUREMENT OF INTERFACE THERMAL RESISTANCE

Measuring the interface thermal resistance RθCS appears semiconductor case temperature. Consider the TO-220
deceptively simple. All that’s apparently needed is a thermo- package shown in Figure B1. The mounting pressure at one
couple on the semiconductor case, a thermocouple on the end causes the other end — where the die is located — to lift
heatsink, and a means of applying and measuring DC power. off the mounting surface slightly. To improve contact,
However, RθCS is proportional to the amount of contact area Motorola TO-220 Packages are slightly concave. Use of a
between the surfaces and consequently is affected by spreader bar under the screw lessens the lifting, but some is
surface flatness and finish and the amount of pressure on the inevitable with a package of this structure. Three thermocou-
surfaces. The fastening method may also be a factor. In ple locations are shown:
addition, placement of the thermocouples can have a a. The Motorola location is directly under the die reached
significant influence upon the results. Consequently, values through a hole in the heatsink. The thermocouple is held in
for interface thermal resistance presented by different place by a spring which forces the thermocouple into intimate
manufacturers are not in good agreement. Fastening meth- contact with the bottom of the semi’s case.
ods and thermocouple locations are considered in this b. The JEDEC location is close to the die on the top
Appendix. surface of the package base reached through a blind hole
When fastening the test package in place with screws, drilled through the molded body. The thermocouple is
thermal conduction may take place through the screws, for swaged in place.
example, from the flange ear on a TO-3 package directly to c. The Thermalloy location is on the top portion of the tab
the heatsink. This shunt path yields values which are between the molded body and the mounting screw. The
artificially low for the insulation material and dependent upon thermocouple is soldered into position.
screw head contact area and screw material. MIL-I-49456
Temperatures at the three locations are generally not the
allows screws to be used in tests for interface thermal
same. Consider the situation depicted in the figure. Because
resistance probably because it can be argued that this is
the only area of direct contact is around the mounting screw,
“application oriented.”
nearly all the heat travels horizontally along the tab from the
Thermalloy takes pains to insulate all possible shunt
die to the contact area. Consequently, the temperature at the
conduction paths in order to more accurately evaluate
JEDEC location is hotter than at the Thermalloy location and
insulation materials. The Motorola fixture uses an insulated
the Motorola location is even hotter. Since junction-to-sink
clamp arrangement to secure the package which also does
thermal resistance must be constant for a given test setup,
not provide a conduction path.
the calculated junction-to-case thermal resistance values
As described previously, some packages, such as a
decrease and case-to-sink values increase as the “case”
TO-220, may be mounted with either a screw through the tab
temperature thermocouple readings become warmer. Thus
or a clip bearing on the plastic body. These two methods
the choice of reference point for the “case” temperature is
often yield different values for interface thermal resistance.
quite important.
Another discrepancy can occur if the top of the package is
There are examples where the relationship between the
exposed to the ambient air where radiation and convection
thermocouple temperatures are different from the previous
can take place. To avoid this, the package should be covered
situation. If a mica washer with grease is installed between
with insulating foam. It has been estimated that a 15 to 20%
the semiconductor package and the heatsink, tightening the
error in RθCS can be incurred from this source.
screw will not bow the package; instead, the mica will be
Another significant cause for measurement discrepancies
deformed. The primary heat conduction path is from the die
is the placement of the thermocouple to measure the
through the mica to the heatsink. In this case, a small
temperature drop will exist across the vertical dimension of
E.I.A.
the package mounting base so that the thermocouple at the
DIE THERMALLOY EIA location will be the hottest. The thermocouple tempera-
ture at the Thermalloy location will be lower but close to the
temperature at the EIA location as the lateral heat flow is
generally small. The Motorola location will be coolest.
The EIA location is chosen to obtain the highest tempera-
ture on the case. It is of significance because power ratings
are supposed to be based on this reference point. Unfortu-
nately, the placement of the thermocouple is tedious and
leaves the semiconductor in a condition unfit for sale.
The Motorola location is chosen to obtain the highest
temperature of the case at a point where, hopefully, the case
MOTOROLA is making contact to the heatsink. Once the special heatsink
to accommodate the thermocouple has been fabricated, this
Figure B1. JEDEC TO-220 Package Mounted to
method lends itself to production testing and does not mark
Heatsink Showing Various Thermocouple Locations
the device. However, this location is not easily accessible to
and Lifting Caused by Pressure at One End
the user.

Theory and Applications Motorola Thyristor Device Data

1.7–18
 The Thermalloy location is convenient and is often chosen tures utilizes a soft copper washer (thermal grease is used)
by equipment manufacturers. However, it also blemishes the between the semiconductor package and the heatsink. The
case and may yield results differing up to 1°C/W for a TO-220 washer is flat to within 1 mil/inch, has a finish better than 63
package mounted to a heatsink without thermal grease and µ-inch, and has an imbedded thermocouple near its center.
no insulator. This error is small when compared to the This reference includes the interface resistance under nearly
thermal resistance of heat dissipaters often used with this ideal conditions and is therefore application-oriented. It is
package, since power dissipation is usually a few watts. also easy to use but has not become widely accepted.
When compared to the specified junction-to-case values of A good way to improve confidence in the choice of case
some of the higher power semiconductors becoming avail- reference point is to also test for junction-to-case thermal
able, however, the difference becomes significant and it is resistance while testing for interface thermal resistance. If the
important that the semiconductor manufacturer and equip- junction-to-case values remain relatively constant as insula-
ment manufacturer use the same reference point. tors are changed, torque varied, etc., then the case reference
Another EIA method of establishing reference tempera- point is satisfactory.

APPENDIX C
Sources of Accessories

Insulators
Joint Plastic Silicone
Manufacturer Compound Adhesives BeO AIO2 Anodize Mica Film Rubber Heatsinks Clips
Aavid Eng. — — — — — — X X X X
AHAM-TOR — — — — — — — — X —
Asheville- X
— — — — — — — — —
Schoonmaker
Astrodynamics X — — — — — — — X —
Delbert Blinn — — X — X X X X X —
IERC X — — — — — — — X —
Staver — — — — — — — — X —
Thermalloy X X X X X X X X X X
Tran-tec X — X X X X — X X —
Wakefield Eng. X X X — X — — X X X
Other sources for silicone rubber pads: Chomerics, Berquist

Suppliers Addresses
Aavid Engineering, Inc., P.O. Box 400, Laconia, New Delbert Blinn Company, P.O. Box 2007, Pomona, California
Hampshire 03247 (603) 528-1478 91769 (714) 623-1257
AHAM-TOR Heatsinks, 27901 Front Street, Rancho, International Electronic Research Corporation, 135 West
California 92390 (714) 676-4151 Magnolia Boulevard, Burbank, California 91502
(213) 849-2481
Asheville-Schoonmaker, 900 Jefferson Ave., Newport News,
VA 23607 (804) 244-7311 The Staver Company, Inc., 41-51 Saxon Avenue, Bay Shore,
Long Island, New York 11706 (516) 666-8000
Astro Dynamics, Inc., 2 Gill St., Woburn, Massachusetts Thermalloy, Inc., P.O. Box 34829, 2021 West Valley View
01801 (617) 935-4944 Lane, Dallas, Texas 75234 (214) 243-4321
Berquist, 5300 Edina Industrial Blvd., Minneapolis, Minnesota Tran-tec Corporation, P.O. Box 1044, Columbus, Nebraska
55435 (612) 835-2322 68601 (402) 564-2748
Chomerics, Inc., 16 Flagstone Drive, Hudson, New Hamp- Wakefield Engineering, Inc., Wakefield, Massachusetts
shire 03051 1-800-633-8800 01880 (617) 245-5900

Motorola Thyristor Device Data Theory and Applications

1.7–19
 PACKAGE INDEX

PREFACE

When the JEDEC registration system for package outlines designations were re-registered to the new system as time
started in 1957, numbers were assigned sequentially when- permitted.
ever manufacturers wished to establish a package as an For example the venerable TO-3 has many variations. Can
industry standard. As minor variations developed from these heights differ and it is available with 30, 40, 50, and 60 mil
industry standards, either a new, non-related number was pins, with and without lugs. It is now classified in the TO-204
issued by JEDEC or manufacturers would attempt to relate family. The TO-204AA conforms to the original outline for the
the part to an industry standard via some appended TO-3 having 40 mil pins while the TO-204AE has 60 mil pins,
description. for example.
In an attempt to ease confusion, JEDEC established the The new numbers for the old parts really haven’t caught on
present system in late 1968 in which new packages are very well. It seems that the DO-4, DO-5 and TO-3 still convey
assigned into a category, based on their general physical sufficient meaning for general verbal communication.
appearance. Differences between specific packages in a
category are denoted by suffix letters. The older package

JEDEC Outline JEDEC Outline JEDEC Outline

Motorola Motorola Motorola
Case Original Revised Mounting Case Original Revised Mounting Case Original Revised Mounting
Number System System Notes Class Number System System Notes Class Number System System Notes Class

001 TO-3 TO-204AA Flange 175-03 Stud 314D-03 Tab

003 TO-3 2 Flange 197 — TO-204AE — Flange 316-01 Flange
009 TO-61 TO-210AC Stud 211-07 Flange 319-06 Flange
011 TO-3 TO-204AA — Flange 211-11 Flange 328A-03 Flange
011A TO-3 — 2 Flange 215-02 Flange 332-04 Stud
012 TO-3 — 2 Flange 221 — TO-220AB — Tab 333-04 Flange
036 TO-60 TO-210AB — Stud 221C-02 Plastic 333A-02 Flange
042A DO-5 DO-203AB — Stud 221D-02 — — Isolated Plastic 336-03 Flange
044 DO-4 DO-203AA — Stud TO-220 337-02 Flange
054 TO-3 — 2 Flange 235 — TO-208 1 Stud 340 TO-218AC Tab
056 DO-4 — — Stud 235-03 Stud 340A-02 Plastic
058 DO-5 — 2 Stud 238 — TO-208 1 Stud 340B-03 Isolated Plastic
61-04 Flange 239 — TO-208 — Stud TO-218
63-02 TO-64 TO-208AB Stud 244-04 Stud 342-01 Flange
63-03 TO-64 TO-2088AB Stud 245 DO-4 — — Stud 357B-01 Flange
077 TO-126 TO-225AA — Plastic 257-01 DO-5 — — Stud 361-01 Flange
080 TO-66 TO-213AA — Flange 263 — TO-208 — Stud 368-02 Flange
086 — TO-208 1 Stud 263-04 Stud 369-06 TO-251 Insertion
086L — TO-298 1 Stud 283 DO-4 — — Stud 369A-12 TO-252 Surface
144B-05 Stud 289 — TO-209 1 Stud 373-01 Isolated Flange
145A-09 Stud 305-01 Stud 383-01 Isolated Flange
145A-10 Stud 310-02 Pressfit 387-01 TO-254AA Isolated 2 Tab
145C TO-232 1 Stud 311-02 Isolated Stud 388A-01 TO-258AA Isolated 2 Tab
157 — DO-203 1 Stud 311-02 Pressfit 744-02 Flange
160-03 TO-59 TO-210AA — Stud 311-02 Stud 744A-01 Flange
167 — DO-203 1 Stud 314B-03 Tab 043-07 DO-21 DO-208AA Pressfit
174-04 Pressfit
Notes: 1. Would fit within this family outline if
registered with JEDEC.
2. Not within all JEDEC dimensions.

Theory and Applications Motorola Thyristor Device Data

1.7–20
 CHAPTER 8
RELIABILITY AND QUALITY

USING TRANSIENT THERMAL RESISTANCE stable. However, for pulses in the microsecond and millisec-
DATA IN HIGH POWER PULSED THYRISTOR ond region, the use of steady–state values will not yield true
APPLICATIONS power capability because the thermal response of the
system has not been taken into account.
Note, however, that semiconductors also have pulse
INTRODUCTION power limitations which may be considerably lower – or even
For a certain amount of dc power dissipated in a greater – than the allowable power as deduced from thermal
semiconductor, the junction temperature reaches a value response information. For transistors, the second breakdown
which is determined by the thermal conductivity from the portion of the pulsed safe operating area defines power limits
junction (where the power is dissipated) to the air or heat while surge current or power ratings are given for diodes and
sink. When the amount of heat generated in the junction thyristors. These additional ratings must be used in conjunc-
equals the heat conducted away, a steady–state condition is tion with the thermal response to determine power handling
reached and the junction temperature can be calculated by capability.
the simple equation: To account for thermal capacity, a time dependent factor
r(t) is applied to the steady–state thermal resistance.
TJ = PD RθJR + TR (1a) Thermal resistance, at a given time, is called transient
where TJ = junction temperature thermal resistance and is given by:
TR = temperature at reference point
PD = power dissipated in the junction
RθJR = steady–state thermal resistance from
RθJR(t) = r(t) @ RθJR (2)

RθJR = junction to the temperature reference The mathematical expression for the transient thermal
RθJR = point. resistance has been determined to be extremely complex.
The response is, therefore, plotted from empirical data.
Power ratings of semiconductors are based upon steady– Curves, typical of the results obtained, are shown in Figure
state conditions, and are determined from equation (1a) 8.1. These curves show the relative thermal response of the
under worst case conditions, i.e.: junction, referenced to the case, resulting from a step
function change in power. Observe that during the fast part of

PD(max) + TJ(max) – TR
RqJR(max)
(1b)
the response, the slope is 1/2 for most of the devices; (i.e.,
Ǹ
TJ a t), a characteristic generally found true of metal
package devices. The curves shown are for a variety of
TJ(max) is normally based upon results of an operating life transistor types ranging from rather small devices in TO–5
test or serious degradation with temperature of an important packages to a large 10 ampere transistor in a TO–3
package. Observe that the total percentage difference is
device characteristic. TR is usually taken as 25°C, and RθJR
can be measured using various techniques. The reference Ǹ
about 10:1 in the short pulse ( t) region. However, the
point may be the semiconductor case, a lead, or the ambient values of thermal resistance vary over 20:1. As an aid to
air, whichever is most appropriate. Should the reference estimating response, Appendix C provides data for a number
temperature in a given application exceed the reference of packages having different die areas.
temperature of the specification, PD must be correspondingly Many Motorola data sheets have a graph similar to that of
reduced. Figure 8.2. It shows not only the thermal response to a step
Thermal resistance allows the designer to determine change in power (the D = 0, or single pulse curve) but also
power dissipation under steady state conditions. Steady has other curves which may be used to obtain an effective
state conditions between junction and case are generally r(t) value for a train of repetitive pulses with different duty
achieved in one to ten seconds while minutes may be cycles. The mechanics of using the curves to find TJ at the
required for junction to ambient temperature to become end of the first pulse in the train, or to find TJ(pk) once steady

Motorola Thyristor Device Data Theory and Applications

1.8–1
state conditions have been achieved, are quite simple and The temperature is desired, a) at the end of the first pulse
require no background in the subject. However, problems b) at the end of a pulse under steady state conditions.
where the applied power pulses are either not identical in For part (a) use:
amplitude or width, or the duty cycle is not constant, require
a more thorough understanding of the principles illustrated in TJ = r(5 ms) RθJCPD + TC
the body of this report.

USE OF TRANSIENT THERMAL RESISTANCE DATA The term r(5 ms) is read directly from the graph of Figure
Part of the problem in applying thermal response data 8.2 using the D = 0 curve,
stems from the fact that power pulses are seldom rectangu-
lar, therefore to use the r(t) curves, an equivalent rectangular ∴ TJ = 0.49  1.17  50 + 75 = 28.5 + 75 = 103.5
model of the actual power pulse must be determined.
Methods of doing this are described near the end of this note. The peak junction temperature rise under steady conditions
Before considering the subject matter in detail, an example is found by:
will be given to show the use of the thermal response data
sheet curves. Figure 8.2 is a representative graph which TJ = r(t, D) RθJC PD + TC
applies to a 2N5632 transistor.

Pulse power PD = 50 Watts D = t/τp = 5/20 – 0.25. A curve for D= 0.25 is not on the
Duration t = 5 milliseconds graph; however, values for this duty cycle can be interpo-
Period τp = 20 milliseconds lated between the D = 0.2 and D = 0.5 curves. At 5 ms,
Case temperature, TC = 75°C read r(t) ≈ 0.59.
Junction to case thermal resistance,
RθJC = 1.17°C/W TJ = 0.59  1.17  50 + 75 = 34.5 + 75 = 109.5°C

1.0
0.7
r (t) , Transient Thermal Resistance

0.5 1 DIE SIZE

CASE (Sq. Mils)
0.3 2
4 5 1 TO–61 10,000
(Normalized)

0.2 2 TO–3, TO–66 3,600

6 3 Case 77 3,600
0.1 4 TO–3, TO–66 16,800
3 7
0.07 5 Case 77 8,000
0.05 8 6 TO–5 (Kovar) 3,600
0.03 7 TO–5 (Steel) 3,600
8 TO–5 (Steel) 14,400
0.02
TO–3 & TO–66 packages are all copper
0.01 or have a copper slug under die
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000
t, Time (ms)

Figure 8.1. Thermal Response, Junction to Case, of Various Semiconductor Types For a Step of Input Power

1.0
0.7 D = 0.5
r (t) , Transient Thermal Resistance

0.5
0.3 0.2
0.2
(Normalized)

0.1
0.1 0.05
0.07 0.02
0.05
0.03 0.01
0.02 SINGLE PULSE
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000
t, Time (ms)

Figure 8.2. Thermal Response Showing the Duty Cycle Family of Curves

Theory and Applications Motorola Thyristor Device Data

1.8–2
 The average junction temperature increase above
ambient is: Pin
P2
(a)
TJ(average) – TC = RθJC PD D Input P1 P4
Power
= (1.17) (50) (0.25) (3) P3
= 14.62°C
t0 t1 t2 t3 t4 t5 t6 t7 Time
Note that TJ at the end of any power pulse does not equal Pin
the sum of the average temperature rise (14.62°C in the P2
(b)
example) and that due to one pulse (28.5°C in example), Power P1
because cooling occurs between the power pulses. Pulses
P4
While junction temperature can be easily calculated for a Separated P3
steady pulse train where all pulses are of the same amplitude Into
Components –P3
and pulse duration as shown in the previous example, a –P4 Time
simple equation for arbitrary pulse trains with random –P1
variations is impossible to derive. However, since the heating
and cooling response of a semiconductor is essentially the –P2
same, the superposition principle may be used to solve (c)
problems which otherwise defy solution. TJ
Using the principle of superposition each power interval is Change
considered positive in value, and each cooling interval Caused
by
negative, lasting from time of application to infinity. By Components
Time
multiplying the thermal resistance at a particular time by the
magnitude of the power pulse applied, the magnitude of the
junction temperature change at a particular time can be
obtained. The net junction temperature is the algebraic sum TJ
(d)
of the terms. Composite
The application of the superposition principle is most TJ
easily seen by studying Figure 8.3. Time
Figure 8.3(a) illustrates the applied power pulses. Figure
8.3(b) shows these pulses transformed into pulses lasting Figure 8.3. Application of Superposition Principle
from time of application and extending to infinity; at to, P1
starts and extends to infinity; at t1, a pulse (– P1) is
considered to be present and thereby cancels P1 from time
t1, and so forth with the other pulses. The junction 50
P PK1 Peak Power

temperature changes due to these imagined positive and 40 P1 P3

(Watts)

negative pulses are shown in Figure 8.3(c). The actual 30

P2
junction temperature is the algebraic sum as shown in Figure 20
8.3(d). 10
Problems may be solved by applying the superposition 0
t0 t1 t2 t3 t4 t5
principle exactly as described; the technique is referred to as 0 1.0 2.0 3.0 4.0
Method 1, the pulse–by–pulse method. It yields satisfactory t, Time (ms)
results when the total time of interest is much less than the
time required to achieve steady state conditions, and must Figure 8.4. Non–Repetitive Pulse Train (Values Shown
be used when an uncertainty exists in a random pulse train Apply to Example in Appendix)
as to which pulse will cause the highest temperature.
Examples using this method are given in Appendix A under
Method 1.
For uniform trains of repetitive pulses, better answers t T5
result and less work is required by averaging the power
pulses to achieve an average power pulse; the temperature Po
is calculated at the end of one or two pulses following the
average power pulse. The essence of this method is shown t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
in Figure 8.6. The duty cycle family of curves shown in Figure t

8.2 and used to solve the example problem is based on this 2t

method; however, the curves may only be used for a uniform Po = 5 Watts
(Conditions for numerical examples t = 5 ms
train after steady state conditions are achieved. Method 2 in
t = 20 ms
Appendix A shows equations for calculating the temperature
at the end of the nth or n + 1 pulse in a uniform train. Where a Figure 8.5. A Train of Equal Repetitive Pulses
duty cycle family of curves is available, of course, there is no
need to use this method.

Motorola Thyristor Device Data Theory and Applications

1.8–3
 ÉÉÉÉÉÉ
nth n+1
pulse pulse

ÉÉÉÉÉÉ
P1
Po

ÉÉÉÉÉÉ
(a) P1T1 = A
Pavg A

t
t
t
ÉÉÉÉÉÉ T1

Figure 8.6. Model For a Repetitive Equal Pulse Train

PP PP
Temperature rise at the end of a pulse in a uniform train
before steady state conditions are achieved is handled by 0.7 PP 0.7 PP
Method 3 (a or b) in the Appendix. The method is basically (b) 0.91 t
0.71 t
the same as for Method 2, except the average power is
modified by the transient thermal resistance factor at the time
t t
when the average power pulse ends.
A random pulse train is handled by averaging the pulses
applied prior to situations suspected of causing high peak
temperatures and then calculating junction temperature at

ÉÉÉÉÉÉÉÉÉÉÉ
the end of the nth or n + 1 pulse. Part c of Method 3 shows an
P1 (t1 – t0) + P2 (t2 – t1) = A

ÉÉÉÉÉÉÉÉÉÉÉ
example of solving for temperature at the end of the 3rd P1
pulse in a three pulse burst.

ÉÉÉÉÉÉÉÉÉÉÉ P2

ÉÉÉÉÉÉÉÉÉÉÉ
HANDLING NON–RECTANGULAR PULSES (c)
The thermal response curves, Figure 8.1, are based on a A
step change of power; the response will not be the same for
other waveforms. Thus far in this treatment we have
assumed a rectangular shaped pulse. It would be desirable
ÉÉÉÉÉÉÉÉÉÉÉ
t0 t1 t2

to be able to obtain the response for any arbitrary waveform,

but the mathematical solution is extremely unwieldy. The
simplest approach is to make a suitable equivalent rectangu- Figure 8.7. Modeling of Power Pulses
lar model of the actual power pulse and use the given
thermal response curves; the primary rule to observe is that
the energy of the actual power pulse and the model are As an example, the case of a transistor used in a dc to ac
equal. power converter will be analyzed. The idealized waveforms
Experience with various modeling techniques has lead to of collector current, IC, collector to emitter voltage, VCE, and
the following guidelines: power dissipation PD, are shown in Figure 8.8.
A model of the power dissipation is shown in Figure 8.8(d).
For a pulse that is nearly rectangular, a pulse model This switching transient of the model is made, as was
having an amplitude equal to the peak of the actual pulse, suggested, for a triangular pulse.
with the width adjusted so the energies are equal, is a For example, TJ at the end of the rise, on, and fall times,
conservative model. (See Figure 8.7(a)). T1, T2 and T3 respectively, will be found.

Sine wave and triangular power pulses model well with the Conditions:
amplitude set at 70% of the peak and the width adjusted to TO–3 package,
91% and 71%, respectively, of the baseline width (as
shown on Figure 8.7(b)). RθJC = 0.5°C/W, IC = 60A, VCE(off) = 60 V
TA = 50°C
A power pulse having a sin2 shape models as a triangular tf = 80 µs, tr = 20 µs
waveform. VCE(sat) = 0.3 V @ 60 A
Frequency = 2 kHz∴τ = 500 µs
Pon = (60) (0.3) = 18 W
Power pulses having more complex waveforms could be
modeled by using two or more pulses as shown in Figure
Pf = 30  30 = 900 W = Pr
8.7(c).
A point to remember is that a high amplitude pulse of a Assume that the response curve in Figure 8.1 for a die
given amount of energy will produce a higher rise in junction area of 58,000 square mils applies. Also, that the device is
temperature than will a lower amplitude pulse of longer mounted on an MS–15 heat sink using Dow Corning
duration having the same energy. DC340 silicone compound with an air flow of 1.0 lb/min

Theory and Applications Motorola Thyristor Device Data

1.8–4
flowing across the heat–sink. (From MS–15 Data Sheet,
RθCS = 0.1°C/W and RθSA = 0.55°C/W).

Collector–Emitter Voltage
toff ton
tf tr
Procedure: Average each pulse over the period using
equation 1–3 (Appendix A, Method 2), i.e., (a) VCE

Pavg + 0.7 Pr 0.71 tr ) Pon ton ) 0.7 Pf 0.71 tf

t t t
Time
+ (0.7) (900) (0.71) (20)
500
) (18) (150)
500
t

Collector Current
) (0.7) (900) (0.71) 500
80
(b) IC

+ 17.9 ) 5.4 ) 71.5

+ 94.8 W Time

Power Dissipation
From equation 1–4, Method 2A: PD

T1 = [Pavg + (0.7 Pr – Pavg) @ r(t1 – to)] RθJC (c)

Pf Pr

Pon
At this point it is observed that the thermal response
curves of Figure 8.1 do not extend below 100 µs. Heat t(Time)
transfer theory for one dimensional heat flow indicates that
Ǹ
the response curve should follow the t law at small times.
Using this as a basis for extending the curve, the response at T1 T2T3
PD 0.7 Pf 0.7 Pr 0.7 Pf
14.2 µs is found to be 0.023. (d)
Pon

We then have: t(Time)

0.7 tr ton 0.7 tf
T1 = [94.8 + (630 – 94.8).023] (0.5) t0 t1 t2 t3

T1 = (107.11)(0.5) = 53.55°C
Figure 8.8. Idealized Waveforms of IC, VCE and PD in a

@ @
For T2 we have, by using superposition:
DC to AC Inverter

@ @
T2 = [Pavg – Pavg r(t2 – to) + 0.7 Pr
T2 = r(t2 – to) – 0.7 Pr r(t2 – t1) + Pon
For the final point T3 we have:

@ @ @
T2 = r(t2 – t1)] RθJC

@ @
T3 = [Pavg – Pavg r(t3 – to) + 0.7 Pr
@
T2 = [Pavg + (0.7 Pr – Pavg) r(t2 – to) +

@
T2 = (Pon – 0.7 Pr) r(t2 – t1)] RθJC T3 = r(t3 – to) – 0.7 Pr r(t3 – t1) + Pon
@ r(164 µs) + (18 – 630)
@
T3 = r(t3 – t1) – Pon r(t3 – t2)
@
T2 = [94.8 + (630 – 94.8)

@
T2 = r(150 µs)] (0.5) T3 = + 0.7 Pf r(t3 – t2)] RθJC

@
T2 = [94.8 + (535.2)(.079) – (612)(.075)] (0.5) T3 = [Pavg + (0.7 Pr – Pavg) r(t3 – to) +

@
T2 = [94.8 + 42.3 – 45.9] (0.5) T3 = (Pon – 0.7 Pr) r(t3 – t1) + (0.7 Pf – Pon)

@ @
T2 = (91.2)(0.5) = 45.6°C T3 = r(t3 – t2)] RθJC
r(221 µs) + (–612) r(206.8 µs)
@
T3 = [94.8 + (535.2)
T3 = + (612) r(56.8µs)] (0.5)
T3 = [94.8 + (535.2)(0.09) – (612) (0.086) +
T3 = (612)(0.045)] (0.5)
T3 = [94.8 + 481.7– 52.63 + 27.54] (0.5)
T3 = (117.88)(0.5) = 58.94°C

Motorola Thyristor Device Data Theory and Applications

1.8–5
 The junction temperature at the end of the rise, on, and fall r(tn – tk) = transient thermal resistance factor at
times, TJ1, TJ2, and TJ3, is as follows: r(tn – tk) = end of time interval (tn – tk).

TJ1 = T1 + TA + RθCA Pavg@ Table 8.1. Several Possible Methods of Solutions

RθCA = RθCS = RθSA = 0.1 + 0.55 1Junction Temperature Rise Using Pulse–By–Pulse Method
A. Temperature rise at the end of the nth pulse for pulses

@
TJ1 = 53.55 + 50 + (0.65)(94.8) = 165.17°C
with unequal amplitude, spacing, and duration.
TJ2 = T2 + TA + RθCA Pavg
B. Temperature rise at the end of the nth pulse for pulses
TJ2 = 45.6 + 50 + (0.65)(94.8) with equal amplitude, spacing, and duration.
2Temperature Rise Using Average Power Concept Under
@
TJ2 = 157.22°C
Steady State Conditions For Pulses Of Equal Amplitude,
TJ3 = T3 + TA + RθCA Pavg Spacing, And Duration
TJ3 = 58.94 + 50 + (0.65)(94.8) A. At the end of the nth pulse.
TJ3 = 170.56°C B. At the end of the (n + 1) pulse.
3Temperature Rise Using Average Power Concept Under
TJ(avg) = Pavg (RθJC + RθCS + RθSA) + TA
Transient Conditions.
TJ(avg) = (94.8)(0.5 + 0.1 + 0.55) + 50 A. At the end of the nth pulse for pulses of equal amplitude,
TJ(avg) = (94.8)(1.15) + 50 = 159.02°C spacing and duration.
B. At the end of the n + 1 pulse for pulses of equal ampli-
tude, spacing and duration.
Inspection of the results of the calculations T1, T2, and T3 C. At the end of the nth pulse for pulses of unequal ampli-
reveal that the term of significance in the equations is the tude, spacing and duration.
average power. Even with the poor switching times there was D. At the end of the n + 1 pulse for pulses of unequal ampli-
a peak junction temperature of 11.5°C above the average tude, spacing and duration.
value. This is a 7% increase which for most applications
could be ignored, especially when switching times are METHOD 1A – FINDING TJ AT THE END OF THE Nth
considerably less. Thus the product of average power and PULSE IN A TRAIN OF UNEQUAL AMPLITUDE,
steady state thermal resistance is the determining factor for SPACING, AND DURATION
junction temperature rise in this application.

ȍ
General Equation:
SUMMARY
+
n
This report has explained the concept of transient thermal Tn Pi [r(t2n–1 – t2i–2) (1–1)
resistance and its use. Methods using various degrees of
approximations have been presented to determine the
+
i 1
– r(tn–1 – t2i–1)]RθJC
junction temperature rise of a device. Since the thermal
response data shown is a step function response, modeling where n is the number of pulses and Pi is the peak value of
of different wave shapes to an equivalent rectangular pulse the ith pulse.
of pulses has been discussed.
The concept of a duty cycle family of curves has also been To find temperature at the end of the first three pulses,
covered; a concept that can be used to simplify calculation of Equation 1–1 becomes:
the junction temperature rise under a repetitive pulse train.
T1 = P1 r(t1) RθJC (1–1A)
T2 = [P1 r(t3) – P1 r(t3 – t1) (1–1B)
APPENDIX A METHODS OF SOLUTION T2 = + P2 r(t3 – t2)] RθJC
In the examples, a type 2N3647 transistor will be used; its
steady state thermal resistance, RθJC, is 35°C/W and its T3 = [P1 r(t5) – P1 r(t5 – t1) + P2 r(t5 – t2) (1–1C)
value for r(t) is shown in Figure A1. T3 = – P2 r(t5 – t3) + P3 r(t5 – t4)] RθJC

Example:
Definitions: Conditions are shown on Figure 4 as:
P1 = 40 W t0 = 0 t3 = 1.3 ms
P1, P2, P3 ... Pn = power pulses (Watts) P2 = 20 W t1 = 0.1 ms t4 = 3.3 ms
P3 = 30 W t2 = 0.3 ms t5 = 3.5 ms
Therefore,
T1, T2, T3 ... Tn = junction to case temperature at t1 – t0 = 0.1 ms t3 – t1 = 1.2 ms
T1, T2, T3 ... Tn = end of P1, P2, P3 ... Pn t2 – t1 = 0.2 ms t5 – t1 = 3.4 ms
t3 – t2 = 1 ms t5 – t2 = 3.2 ms
t0, t1, t2, ... tn = times at which a power pulse t4 – t3 = 2 ms t5 – t3 = 2.2 ms
t0, t1, t2, ... tn = begins or ends t5 – t4 = 0.2 ms

Theory and Applications Motorola Thyristor Device Data

1.8–6
Procedure: For 5 pulses, equation 1–2A is written:
Find r(tn – tk) for preceding time intervals from Figure 8.2,
then substitute into Equations 1–1A, B, and C. T5 = PD RθJC [r(4 τ + t) – r(4τ) + r(3τ + t)]
T1 = P1 r(t1) RθJC = 40 @ @ 0.05 35 = 70°C T5 = – r(3τ) + r(2τ + t) – r(2τ) + r(τ + t)
T5 = – r(τ) + r(t)]
T2 = [P1 r(t3) – P1 r(t3 – t1) + P2 r(t3 – t2)] RθJC
T2 = [40 (0.175) – 40 (0.170) + 20 (0.155)] 35
Example:
T2 = [40 (0.175 – 0.170) + 20 (0.155)] 35
Conditions are shown on Figure 8.5 substituting values
T2 = [0.2 + 3.1] 35 = 115.5°C into the preceding expression:
T3 = [P1 r(t5) – P1 r(t5 – t1) + P2 r(t5 – t2)
T5 = (5) (35) [r(4.20 + 5) – r(4.20) + r(3.20 + 5)
T3 = – P2 r(t5 – t3) + P3 r(t5 – t4)] θJC
T5 = + r(3.20) + r(2.20 + 5) – r(2.20) + r(20 + 5)
T3 = [40 (0.28) – 40 (0.277) + 20 (0.275) – 20 (0.227)
T5 = – r(20) + r(5)]
T3 = + 30 (0.07)] 35 T5 = (5) (35) [0.6 – 0.76 + 0.73 – 0.72 + 0.68
T3 = [40 (0.28 – 0.277) + 20 (0.275 – 0.227) T5 = – 0.66 + 0.59 – 0.55 + 0.33] – (5)(35)(0.40)

@
T3 = + 30 (0.07)] 35 T5 = 70.0°C
T3 = [0.12 + 0.96 + 2.1]{ 35 = 3.18 35 = 111.3°C
Note that the solution involves the difference between
Note, by inspecting the last bracketed term in the terms nearly identical in value. Greater accuracy will be
equations above that very little residual temperature is left obtained with long or repetitive pulse trains using the
from the first pulse at the end of the second and third pulse. technique of an average power pulse as used in Methods 2
Also note that the second pulse gave the highest value of and 3.
junction temperature, a fact not so obvious from inspection of
the figure. However, considerable residual temperature from METHOD 2 – AVERAGE POWER METHOD, STEADY
the second pulse was present at the end of the third pulse. STATE CONDITION
The essence of this method is shown in Figure 8.6. Pulses
METHOD 1B – FINDING TJ AT THE END OF THE Nth previous to the nth pulse are averaged. Temperature due to
PULSE IN A TRAIN OF EQUAL AMPLITUDE, SPACING, the nth or n + 1 pulse is then calculated and combined
AND DURATION properly with the average temperature.
The general equation for a train of equal repetitive pulses Assuming the pulse train has been applied for a period of
can be derived from Equation 1–1. Pi = PD, ti = t, and the time (long enough for steady state conditions to be
spacing between leading edges or trailing edges of adjacent established), we can average the power applied as:
pulses is τ.
General Equation: Pavg + PD tt
(1–3)

Tn = PDRθJC ȍ+
n
r[(n – i) τ +
i 1 t]
(1–2) METHOD 2A – FINDING TEMPERATURE AT THE END
OF THE Nth PULSE
– r[(n – i) τ]
Applicable Equation:
Expanding:
Tn = [Pavg + (PD – Pavg) r(t)] RθJC (1–4)
Tn = PD RθJC r[(n – 1) τ + t] – r[(n – 1) τ]
or, by substituting Equation 1–3 into 1–4,

ƪ ǒ Ǔ ƫ
Tn = + r[(n – 2) τ + t) – r[(n – 2) τ] + r[(n – 3)
Tn = τ + t] – r[(n – 3) τ] + . . . + r[(n – i) τ + t]
Tn = – r[(n – i) τ] . . . . . + r(t)] (1–2A) Tn + t)
t
1– tt r(t) PD RqJC (1–5)

The result of this equation will be conservative as it adds a

temperature increase due to the pulse (PD – Pavg) to the
average temperature. The cooling between pulses has not
{ Relative amounts of temperature residual from P1, P2, and been accurately accounted for; i.e., TJ must actually be less
P3 respectively are indicated by the terms in brackets. than TJ(avg) when the nth pulse is applied.

Motorola Thyristor Device Data Theory and Applications

1.8–7
Example: Find Tn for conditions of Figure 8.5. METHOD 3 – AVERAGE POWER METHOD,
Procedure: Find Pavg from equation (1–3) and TRANSIENT CONDITIONS
substitute values in equation (1–4) or The idea of using average power can also be used in the
(1–5). transient condition for a train of repetitive pulses. The
previously developed equations are used but Pavg must be
Tn = [(1.25) + (5.0 – 1.25)(0.33)] (35) modified by the thermal response factor at time t(2n – 1).
Tn = 43.7 + 43.2 = 86.9°C
METHOD 3A – FINDING TEMPERATURE AT THE END
OF THE Nth PULSE FOR PULSES OF EQUAL
METHOD 2B – FINDING TEMPERATURE AT THE END AMPLITUDE, SPACING AND DURATION
OF THE N + 1 PULSE
Applicable Equation:

ƪ ǒ Ǔƫ
Applicable Equation:

Tn + tr t
t (2n–1) ) 1 – tt r(t) PD RθJC (1–8)
Tn + 1 = [Pavg + (PD – Pavg) r(t + τ)
(1–6)
Tn + 1 + PD r(t) – PD r(τ)] RθJC
Conditions: (See Figure 8.5)
or, by substituting equation 1–3 into 1–6, Procedure: At the end of the 5th pulse (See Figure

ǒ Ǔ
8.7 . . .

Tn + 1 = t
t
) 1– tt r(t ) t) @
T5 = [5/20 r(85) + (1 – 5/20)r(5)] (5)(35)
(1–7) T5 = [(0.25)(0765) + (0.75)(0.33)] (175)
) r(t) * r( )t PDRθJC T5 = 77°C

This value is a little higher than the one calculated by

summing the results of all pulses; indeed it should be,
Example: Find Tn for conditions of Figure 8.5. because no cooling time was allowed between Pavg and the
Procedure: Find Pavg from equation (1–3) and nth pulse. The method whereby temperature was calculated
substitute into equation (1–6) or (1–7). at the n + 1 pulse could be used for greater accuracy.

METHOD 3B – FINDING TEMPERATURE AT THE END

Tn + 1 = [(1.25) + (5 – 1.25)(0.59) + (5)(0.33) OF THE N + 1 PULSE FOR PULSES OF EQUAL
Tn + 1 – (5)(0.56)] (35) = 80.9°C AMPLITUDE, SPACING AND DURATION

Applicable Equation:
Equation (1–6) gives a lower and more accurate value for

ǒ Ǔ
temperature than equation (1–4). However, it too gives a
higher value than the true TJ at the end of the n + 1th pulse.
The error occurs because the implied value for TJ at the end
Tn + 1 = t
) 1–t
t r(t
2n–1) t
of the nth pulse, as was pointed out, is somewhat high. (1–9)
Adding additional pulses will improve the accuracy of the r(t ) ) ) r(t) * r( ) PD RθJC
t t
calculation up to the point where terms of nearly equal value
are being subtracted, as shown in the examples using the
pulse by pulse method. In practice, however, use of this Example: Conditions as shown on Figure 8.5. Find
method has been found to yield reasonable design values temperature at the end of the 5th pulse.
and is the method used to determine the duty cycle of family
of curves – e.g., Figure 8.2. For n + 1 = 5, n = 4, t2n–1 = t7 = 65 ms,

ǒ Ǔ
Note that the calculated temperature of 80.9°C is 10.9°C
higher than the result of example 1B, where the temperature
was found at the end of the 5th pulse. Since the thermal T5 = 5 r(65 ms)
20
) 1 – 5 r(25 ms)
20
response curve indicates thermal equilibrium in 1 second, 50
pulses occurring 20 milliseconds apart will be required to
) r(5 ms) * r(20 ms) (5)(35)
achieve stable average and peak temperatures; therefore, T5 = [(0.25)(0.73) + (0.75)(0.59) + 0.33 – 0.55](5)(35)
steady state conditions were not achieved at the end of the
5th pulse. T5 = 70.8°C

Theory and Applications Motorola Thyristor Device Data

1.8–8
 The answer agrees quite well with the answer of Method This result is high because in the actual case considerable
1B where the pulse–by–pulse method was used for a cooling time occurred between P2 and P3 which allowed TJ
repetitive train. to become very close to TC. Better accuracy is obtained
when several pulses are present by using equation 1–10 in
METHOD 3C – FINDING TJ AT THE END OF THE Nth order to calculate TJ – tC at the end of the nth + 1 pulse. This
PULSE IN A RANDOM TRAIN technique provides a conservative quick answer if it is easy
The technique of using average power does not limit itself to determine which pulse in the train will cause maximum
to a train of repetitive pulses. It can be used also where the junction temperature.
pulses are of unequal magnitude and duration. Since the
method yields a conservative value of junction temperature
rise it is a relatively simple way to achieve a first approxima- METHOD 3D – FINDING TEMPERATURE AT THE END
tion. For random pulses, equations 1–4 through 1–7 can be OF THE N + 1 PULSE IN A RANDOM TRAIN
modified. It is necessary to multiply Pavg by the thermal The method is similar to 3C and the procedure is identical.
response factor at time t(2n – 1). Pavg is determined by Pavg is calculated from Equation 1–10 modified by r(t2n – 1)
averaging the power pulses from time of application to the and substituted into equation 1–6, i.e.,
time when the last pulse starts.
Applicable Equations:

ȍ
Tn + 1 = [Pavg r(t2n–1) + (PD – Pave) r(t2n–1 –
n t(2i–1)–t(2i–2) Tn + 1 = t2n–2) + PD r(t2n+1 – t2n) – PD r(t2n+1
General: Pavg = Pi (1–10) Tn + 1 = – t2n–1)] RθJC
+
i 1
t(2n)–t(2i–2)

For 3 Pulses: The previous example cannot be worked out for the n + 1
pulse because only 3 pulses are present.
t1 – t0 t3 – t2
Pavg = P1 + P2 (1–11)
t4 – t0 t4 – t2

Example: Conditions are shown on Figure 8.4 (refer to

Method 1A). Table 8.2. Summary Of Numerical Solution For The
Procedure: Find Pavg from equation 1–3 and the junction Repetitive Pulse Train Of Figure 5
temperature rise from equation 1–4. Temperature Obtained, °C
Conditions: Figure 8.4 Tempera
Tempera-
ture Average Power Average Power

@
Desired Pulse by Pulse Nth Pulse N + 1 Pulse
Pavg = 40 0.1 20 1
3.3 3
)
1.21 6.67 + ) At End of 70.0 (1B) 77 (3A) 70.8 (3B)
= 7.88 Watts 5th Pulse

@
T3 = [Pavg r(t5) + (P3 – Pavg) r(t5 – t4)] RθJC Steady State – 86.9 (2A) 80.9 (2B)
= [7.88 (0.28) + (30 – 7.88) 0.07] 35 Peak
= [2.21 + 1.56] 35 = 132°C Note: Number in parenthesis is method used.

1.0
0.7
r (t) , Transient Thermal Resistance

0.5
0.3
0.2
(Normalized)

0.1
0.07
0.05
0.03
0.02

0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000
t, Time (ms)

Figure 8.9. 2N3467 Transient Thermal Response

Motorola Thyristor Device Data Theory and Applications

1.8–9
 1.0
0.7

r (t) , Transient Thermal Resistance

0.5
0.3
(Normalized) DIE SIZE
0.2 1 (Sq. Mils) DEVICE TYPE

0.1 2 3 1 1,200 MJE170, MJE180

4 5 Thermowatt Case 221 2 2,000 MJE210, MJE200
0.07
3 3,600 2N4918, 2N4921
0.05 All other curves are for Case 77
4 6,300 2N5190, 2N5193
0.03 6 5 8,100 MCR106
0.02 6 16,900 2N6342

0.01
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000
t, Time (ms)
Figure 8.10. Case 77 (Thermopad) and TO–220 (Thermowatt) Thermal Response

1.0
0.7
r (t) , Transient Thermal Resistance

0.5
0.3
0.2
(Normalized)

0.1 DIE SIZE

0.07 1 (Sq. Mils) DEVICE TYPE
2 1
0.05 850 MM4005, 2N4406
3 2 1,225 MM3006
0.03
3 3,600 2N3719, 2N5334
0.02 4
4 14,400 No Standard Devices

0.01
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000
t, Time (ms)
Figure 8.11. TO–5 (Solid Steel Header) Thermal Response

1.0
0.7
r (t) , Transient Thermal Resistance

0.5
0.3
0.2
(Normalized)

0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000
t, Time (ms)
Figure 8.12. TO–92 (Unibloc) Thermal Response, Applies to All Commonly Used Die

Theory and Applications Motorola Thyristor Device Data

1.8–10
 100
50 1

R q JC , Thermal Resistance Junction

2
20

to Case ( °C/W)
10
5.0
3
2.0
1.0
0.5 1 Kovar Header
2 Steel Header
0.2
3 Copper Header
0.1
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100
Die Area x 1000 (mil2)

Figure 8.13. Typical Thermal Resistance As a Function

of Case Material and Die Area. Data Applies to Solid
Header Parts Only. Use Copper Curve for Aluminum
and Steel Packages With a Copper Slug Under the Die,
Which is the Standard Motorola Design.

Motorola Thyristor Device Data Theory and Applications

1.8–11
 As the price of semiconductor devices decreases, reliabil- Quality and reliability are two essential elements in order
ity and quality have become increasingly important in for a semiconductor company to be successful in the
selecting a vendor. In many cases these considerations even marketplace today. Quality and reliability are interrelated
outweigh price, delivery and service. because reliability is quality extended over the expected life
The reason is that the cost of device fallout and warranty of the product.
repairs can easily equal or exceed the original cost of the Quality is the assurance that a product will fulfill custom-
devices. Consider the example shown in Figure 8.14. ers’ expectations.
Although the case is simplistic, the prices and costs are Reliability is the probability that a product will perform its
realistic by today’s standards. In this case, the cost of failures intended function satisfactorily for a prescribed life under
raised the device cost from 15 cents to 21 cents, an increase certain stated conditions.
of 40%. Clearly, then, investing in quality and reliability can The quality and reliability of Motorola thyristors are
pay big dividends. achieved with a four step program:
With nearly three decades of experience as a major 1. Thoroughly tested designs and materials
semiconductor supplier, Motorola is the largest manufacturer 2. Stringent in–process controls and inspections
of discrete semiconductors in the world today. Since 3. Process average testing along with 100% quality
semiconductor prices are strongly influenced by manufactur- assurance redundant testing
ing volume, this leadership has permitted Motorola to be 4. Reliability verifications through audits and reliability
strongly competitive in the marketplace while making mas- studies
sive investments in equipment, processes and procedures to
guarantee that the company’s after–purchase costs will be ESSENTIALS OF RELIABILITY
among the lowest in the industry. As a result of the Paramount in the mind of every semiconductor user is the
procedures, Motorola is projecting an outgoing quality level question of device performance versus time. After the
of less than 3 PPM by 1992. applicability of a particular device has been established, its
effectiveness depends on the length of trouble free service it
can offer. The reliability of a device is exactly that — an
expression of how well it will serve the customer. Reliability
can be redefined as the probability of failure free perfor-
Given: mance, under a given manufacturer’s specifications, for a
Purchase = 100,000 components @ 15¢ each given period of time. The failure rate of semiconductors in
Assumptions: Line Fallout = 0.1% general, when plotted versus a long period of time, exhibit
Assumptions: Warranty Failures = 0.01% what has been called the “bath tub curve” (Figure 8.15).

Components Cost =100,000 

15¢ = $15,000
Line Fallout Cost = 100 
$40 = 4,000
@ $40 per repair
Warranty Cost = 10 
$200 = 2,000
@ $200 per repair INFANT RANDOM FAILURE WEAROUT
$21,000 MORTALITY MECHANISM PHENOMENON
Adjusted Cost

FAILURE RATE

Per Component = $21,000 100,000 = 21¢

Definitions:
Line Fall out = Module or subassembly failure
requiring troubleshooting, parts
replacement and retesting
Warranty Failure = System field failure requir-
ing in warranty repair

Figure 8.14. Component Costs to the User

(including line fallout and warranty costs) Figure 8.15. Failure Rate of Semiconductor

Theory and Applications Motorola Thyristor Device Data

1.8–12
RELIABILITY MECHANICS Years of semiconductor device testing have shown that
Since reliability evaluations usually involve only samples temperature will accelerate failures and that this behavior fits
of an entire population of devices, the concept of the central the form of the Arrhenius equation:
limit theorem applies and a failure rate is calculated using the
λ2 distribution through the equation: R(t) = Ro(t)e– o/KT

λ ≤ l (a, 2r 2)
2 ) Where R(t) = reaction rate as a function of time and
2 nt
temperature
λ2 = chi squared distribution
Ro = A constant
where a + 100100– cl t = Time
T = Absolute temperature, °Kelvin (°C + 273°)
λ = Failure rate
o = Activation energy in electron volts (ev)
cl
r
=
=
Confidence limit in percent
Number of rejects

K = Boltzman’s constant = 8.62 10–5 ev/°K
This equation can also be put in the form:
n = Number of devices
AF = Acceleration factor
t = Duration of tests
T2 = User temperature
T1 = Actual test temperature
The confidence limit is the degree of conservatism desired
in the calculation. The central limit theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is The Arrhenius equation states that reaction rate increases
termed the best estimate, and is the mean of this distribution. exponentially with the temperature. This produces a straight
A 90% confidence limit is a very conservative value and line when plotted on log–linear paper with a slope expressed
results in a higher λ which represents the point at which 90% by o. o may be physically interpreted as the energy threshold
of the area of the distribution is to the left of that value (Figure of a particular reaction or failure mechanism. The overall
8.16). activation energy exhibited by Motorola thyristors is 1 ev.

RELIABILITY QUALIFICATIONS/EVALUATIONS
50% CL OUTLINE:
X Some of the functions of Motorola Reliability and Quality
FREQUENCY

Assurance Engineering are to evaluate new products for

90% CL introduction, process changes (whether minor or major), and
product line updates to verify the integrity and reliability of
conformance, thereby ensuring satisfactory performance in
the field. The reliability evaluations may be subjected to a
series of extensive reliability testing, such as in the tests
l, FAILURE RATE performed section, or special tests, depending on the nature
of the qualification requirement.
Figure 8.16. Confidence Limits and the Distribution of
Sample Failure Rates AVERAGE OUTGOING QUALITY (AOQ)
With the industry trend to average outgoing qualities
The term (2r + 2) is called the degrees of freedom and is (AOQ) of less than 100 PPM, the role of device final test, and
an expression of the number of rejects in a form suitable to final outgoing quality assurance have become a key
λ2 tables. The number of rejects is a critical factor since the ingredient to success. At Motorola, all parts are 100% tested
definition of rejects often differs between manufacturers. Due to process average limits then the yields are monitored
to the increasing chance of a test not being representative of closely by product engineers, and abnormal areas of fallout
the entire population as sample size and test time are are held for engineering investigation. Motorola also 100%
decreased, the λ2 calculation produces surprisingly high redundant tests all dc parameters again after marking the
values of λ for short test durations even though the true long device to further reduce any mixing problems associated
term failure rate may be quite low. For this reason relatively with the first test. Prior to shipping, the parts are again
large amounts of data must be gathered to demonstrate the sampled, tested to a tight sampling plan by our Quality
real long term failure rate. Since this would require years of Assurance department, and finally our outgoing final inspec-
testing on thousands of devices, methods of accelerated tion checks for correct paperwork, mixed product, visual and
testing have been developed. mechanical inspections prior to packaging to the customers.

Motorola Thyristor Device Data Theory and Applications

1.8–13
 AVERAGE OUTGOING QUALITY (AOQ)
AOQ = Process Average 
Probability of Acceptance 
106 (PPM)
Case 29–04/TO–226AA

Process Average + No. of Reject Devices

No. of Devices Tested
(TO–92)
Devices Available:
SCRs, TRIACs,

+ (1– No.
PUTs, SBSs
of Lots Rejected
Probability of Acceptance ) Current Range: to 0.8 A
No. of Lots Tested Voltage Range: 25 to 600 V

106 = To Convert to Parts Per Million

AOQ + No.
No. of Reject Devices
of Devices Tested
No. of Lots Rejected
(1 – ) 106(PPM) Case 77–08/TO–225AA
No. of Lots Tested (TO–126)
Devices Available:
Current AOQ levels (1988) are less than 50 PPM. The SCRs, TRIACs
projected goal, by 1992, is less than 3 PPM, a defect rate so Current Range: to 4 A
Voltage Range: 25 to 600 V
low that it becomes virtually invisible to the user. Figure 8.17
shows AOQ of Motorola Thyristors.

4000 THYRISTOR PPM

3000

2000

*PROJECTION Case 267–03/Axial Lead

1000 (Surmetic 50)
Devices Available:
SIDAC
1979 1980 1981 1982 1983 1984 1985* 1986* 1987* Voltage Range: 104 to 240 V
3264 2561 1546 1057 644 200 100 50 0

Figure 8.17. Average Outgoing Quality (AOQ) of

Motorola Thyristors

THYRISTOR RELIABILITY
The reliability data described herein applies to Motorola’s
extensive offering of thyristor products for low and medium
Case 221A–04/TO–220AB
current applications. The line includes not only the pervasive Devices Available:
Silicon Controlled Rectifiers (SCRs) and TRIACs, but also a SCRs, TRIACs
variety of Programmable Unijunction Transistors (PUTs), Current Range: to 40 A
Silicon Bidirectional Switches (SBSs), SIDACs and other Voltage Range: 50 to 1000 V

associated devices used for SCR and TRIAC triggering

purposes. Moreover, these devices are available in different
package styles with overlapping current ranges to provide an
integral chip–and–package structure that yields lowest cost,
consistent with the overriding consideration of high reliability.
The various packages and the range of electrical specifi-
cations associated with the resultant products are shown in Figure 8.18. Motorola Thyristor Packages
Figure 8.18.

To evaluate the reliability of these structures, production

line samples from each type of package are being subjected both meaningful and impressive. They are detailed on the
to a battery of accelerated reliability tests deliberately following pages in the hope that they will provide for the
designed to induce long–term failure. Though the tests are readers a greater awareness of the potential for thyristors in
being conducted on a continuing basis, the results so far are their individual application.

Theory and Applications Motorola Thyristor Device Data

1.8–14
THYRISTOR CONSTRUCTION THROUGH A could affect long–term reliability. At Motorola, piece–part
TIME TESTED DESIGN AND ADVANCED control involves the services of three separate laborato-
PROCESSING METHODS ries . . . Radiology, Electron Optics and Product Analysis. All
three are utilized to insure product integrity:
Raw Wafer Quality, in terms of defects, orientation,
flatness and resistivity;
Physical Dimensions, to tightly specified tolerances;
A pioneer in discrete semiconductor components and the
Metal Hardness, to highly controlled limits;
world’s largest supplier thereof, Motorola has pyramided
Gaseous Purity and Doping Level;
continual process and material improvements into thyristor
Mold Compounds, for void–free plastic encapsulation.
products whose inherent reliability meets the most critical
requirements of the market. IN–PROCESS INSPECTIONS
These improvements are directed towards long–term As illustrated in Figure 8.19, every major manufacturing
reliability in the most strenuous applications and the most step is followed by an appropriate in–process QA inspection.
adverse environments. Quality control in wafer processing, assembly and final test
impart to Motorola standard thyristors a reliability level that
DIE GLASSIVATION easily exceeds most industrial, consumer and military
All Motorola thyristor die are glass–sealed with a Motorola requirements . . . built–in quality assurance aimed at insuring
patented passivation process making the sensitive junctions failure–free shipments of Motorola products.
impervious to moisture and impurity penetration. This
RELIABILITY AUDITS
imparts to low–cost plastic devices the same freedom from
Reliability audits are performed following assembly. Reli-
external contamination formerly associated only with hermet-
ability audits are used to detect process shifts which can
ically sealed metal packages. Thus, metal encapsulation is
have an adverse effect on long–term reliability. Extreme
required primarily for higher current devices that would
stress testing on a real–time basis, for each product run,
normally exceed the power–dissipation capabilities of plastic
uncovers process abnormalities that may have escaped the
packages — or for applications that specify the hermetic
stringent in–process controls. Typical tests include HTRB/FB
package.
(high–temperature reverse bias and forward bias) storage
life and temperature cycling. When abnormalities are de-
VOID–FREE PLASTIC ENCAPSULATION tected, steps are taken to correct the process.
A fifth generation plastic package material, combined with
improved copper piece–part designs, maximize package OUTGOING QC
integrity during thermal stresses. The void–free encapsula- The most stringent in–process controls do not guarantee
tion process imparts to the plastic package a mechanical strict adherence to tight electrical specifications. Motorola’s
reliability (ability to withstand shock and vibration) even 100% electrical parametric test does — by eliminating all
beyond that of metal packaged devices. devices that do not conform to the specified characteristics.
Additional parametric tests, on a sampling basis, provide
data for continued improvement of product quality. And to
IN–PROCESS CONTROLS AND INSPECTIONS help insure safe arrival after shipment, antistatic handling
and packaging methods are employed to assure that the
INCOMING INSPECTIONS product quality that has been built in stays that way.
Apparently routine procedures, inspection of incoming From rigid incoming inspection of piece parts and materi-
parts and materials, are actually among the most critical als to stringent outgoing quality verification, assembly and
segments of the quality and reliability assurance program. process controls encompass an elaborate system of test and
That’s because small deviations from materials specifica- inspection stations that ensure step–by–step adherence to a
tions can traverse the entire production cycle before being prescribed procedure designed to yield a high standard of
detected by outgoing Quality Control, and, if undetected, quality.

Motorola Thyristor Device Data Theory and Applications

1.8–15
 IN– DIFFUSION, METALLIZATION,
COMING MOAT ETCH, RESIS– 100% DIE ELECT, TESTS ELEC.
INSP. PHOTOGLASS TIVITY SCRIBE & BREAK & VISUAL
WAFER & INSPECTION INSPECTION
CHEMICALS

INC.
INSP. LEAD
FORM & DIE BOND QA QA
ATTACHMENT
CLEAN INSPECTION INSPECTION
PC. PARTS
QA INSPECTION

100% ELECT.
INJECTION MOLD SELECTION, 100% 100%
& DEFLASH PLASTIC, BIN SPECIFICATION ANTISTATIC
CLEAN & SOLDER RELIA– TEST, 100% QA OUTGOING HANDLING/PACKAGING
DIP LEADS, BILITY INSPECTION QC
CURE PLASTIC AUDITS LASER MARKING SAMPLING

FINAL
VISUAL SHIPPING
&
MECHANICAL

Figure 8.19. In–Process Quality Assurance Inspection Points for Thyristors

RELIABILITY TESTS BLOCKING LIFE TEST

Only actual use of millions of devices, under a thousand This test is used as an indicator of long–term operating
different operating conditions, can conclusively establish the reliability and overall junction stability (quality). All semicon-
reliability of devices under the extremes of time, tempera- ductor junctions exhibit some leakage current under
ture, humidity, shock, vibration and the myriads of other reverse–bias conditions. Thyristors, in addition, exhibit
adverse variables likely to be encountered in practice. But leakage current under forward–bias conditions in the off
thorough testing, in conjunction with rigorous statistical state. As a normal property of semiconductors, this junction
analysis, is the next–best thing. The series of torture tests leakage current increases proportionally with temperature in
described in this document instills a high confidence level a very predictable fashion.
regarding thyristor reliability. The tests are conducted at Leakage current can also change as a function of time —
maximum device ratings and are designed to deliberately particularly under high–temperature operation. Moreover,
stress the devices in their most susceptible failure models. this undesirable “drift” can produce catastrophic failures
The severity of the tests compresses into a relatively short when devices are operated at, or in excess of, rated
test cycle the equivalent of the stresses encountered during temperature limits for prolonged periods.
years of operation under more normal conditions. The results The blocking life test operates representative numbers of
not only indicate the degree of reliability in terms of devices at rated (high) temperature and reverse–bias
anticipated failures; they trigger subsequent investigations voltage limits to define device quality (as measured by
into failure modes and failure mechanisms that serve as the leakage drifts) and reliability (as indicated by the number of
basis of continual improvements. And they represent a catastrophic failures*). The results of these tests are shown
clear–cut endorsement that, for Motorola thyristors, low–cost in Table 8.3. Table 8.4 shows leakage–current drift after 1000
and high quality are compatible attributes. hours HTRB.

Theory and Applications Motorola Thyristor Device Data

1.8–16
 Table 8.3. Blocking Life Test long periods at actual storage temperatures. Results of this
High Temperature Reverse Bias (HTRB) test are shown in Table 8.5.
and High Temperature Forward Bias (HTFB)
Test Conditions Total Table 8.5. High Temperature Storage Life
Sample Duration Catastrophic
Case TA Device
Size (Hours) Failures* Total
@ Rated Voltage Hours Test Sample Duration Catastrophic
Case Device
Conditions Size (Hours) Failures*
29–04/TO–226AA 100°C 1000 1000 1,000,000 1 Hours
(TO–92)
29–04/TO–226AA TA = 150°C 1000- 400 1,500,000 0
77–08/TO–225AA 110°C 1000 1000 1,000,000 0 (TO–92) 2000
(TO–126)
77–08/TO–225AA ** 1000- 350 550,000 0
221A–04/TO–220AB 100°C 1000 1000 1,000,000 0 (TO–126) 2000

267–03/Axial Lead 125°C 150 1000 150,000 0 221A–04/TO–220 1000 300 300,000 0
(Surmetic 50)
267–03/Axial Lead 1000 100 100,000 0
(Surmetic 50)
* Failures are at maximum rated values. The severe nature of these tests
is normally not seen under actual conditions. * Failures are at maximum rated values. The severe nature of these tests
is normally not seen under actual conditions.
** Same for all.

Table 8.4. Leakage–Current Drift after 1000 Hours HTRB

STRESS TESTING — POWER CYCLING AND
THERMAL SHOCK
VDRM = 400 V
POWER CYCLING TEST
How do the devices hold up when they are repeatedly
TA = 100°C cycled from the off state to the on state and back to the off
state under conditions that force them to maximum rated
junction temperature during each cycle? The Power Cycling
Test was devised to provide the answers.
In this test, devices are subjected to intermittent operating
file (IOL), on–state power until the junction temperature (TJ)
has increased to 100°C. The devices are then turned off and
TJ decreases to near ambient, at which time the cycle is
repeated.
This test is important to determine the integrity of the chip
and lead frame assembly since it repeatedly stresses the
devices. It is unlikely that these worst–case conditions would
be continuously encountered in actual use. Any reduction in
TJ results in an exponential increase in operating longevity.
Table 8.6 shows the results of IOL testing.

–40 µA –20 µA 0 +20 µA +40 µA THERMAL SHOCK

Leakage Shift from Initial Value CONDITIONS BEYOND THE NORM
The favorable blocking–life–test drift results shown here are attributed to Excesses in temperature not only cause variations in
Motorola’s unique “glassivated junction” process which imparts a high degree electrical characteristics, they can raise havoc with the
of stability to the devices. mechanical system. Under temperature extremes, contrac-
tion and expansion of the chip and package can cause
HIGH TEMPERATURE STORAGE LIFE TEST physical dislocations of mechanical interfaces and induce
This test consists of placing devices in a high–temperature catastrophic failure.
chamber. Devices are tested electrically prior to exposure to To evaluate the integrity of Motorola thyristors under the
the high temperature, at various time intervals during the most adverse temperature conditions, they are subjected to
test, and at the completion of testing. Electrical readout thermal shock testing.
results indicate the stability of the devices, their potential to
withstand high temperatures, and the internal manufacturing AIR–TO–AIR (TEMPERATURE CYCLING)
integrity of the package. Readouts at the various intervals This thermal shock test is conducted to determine the
offer information as to the time period in which failures occur. ability of the devices to withstand exposure to extreme high
Although devices are not exposed to such extreme high and low temperature environments and to the shock of
temperatures in the field, the purpose of this test is to alternate exposures to the temperature extremes. Results of
accelerate any failure mechanisms that could occur during this test are shown in Table 8.6.

Motorola Thyristor Device Data Theory and Applications

1.8–17
 Table 8.6. Air–to–Air
Total
Sample Number Catastrophic
Case Test Conditions Device
Size of cycles Failures*
Cycles
29–04/TO–226AA (TO–92) –40°C or –65°C 900 400 360,000 0
77–08/TO–225AA (TO–126) to +150°C 500 400 200,000 0
D ll 15 minutes
Dwell—15 i t att each
h extreme
t
221A–04/TO–220 400 400 160,000 0
Immediate Transfer
267–03/Axial Lead (Surmetic 50) 100 400 40,000 0

* Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions.

ENVIRONMENTAL TESTING junction “glassivation” process and selection of package

materials. The resistance to moisture–related failures is
MOISTURE TESTS indicated by the tests described here.
Humidity has been a traditional enemy of semiconductors, BIASED HUMIDITY TEST
particularly plastic packaged devices. Most moisture–related This test was devised to determine the resistance of
degradations result, directly or indirectly, from penetration of component parts and constituent materials to the combined
moisture vapor through passivating materials, and from deteriorative effects of prolonged operation in a high–tem-
surface corrosion. At Motorola, this erstwhile problem has perature/high–humidity environment. H3TRB test results are
been effectively controlled through the use of a unique shown in Table 8.7.

Table 8.7. Biased Humidity Test

High humidity, high Temperature, reverse bias (H3TRB)
Total
Sample Duration Catastrophic
Case Test Conditions Device
Size Hours Failures*
Cycles
29–04/TO–226AA Relative Humidity 85% 400 500–1000 300,000 0
(TO–92) TA = 85°C

77–08/TO–225AA Reverse Voltage–Rated 200 500–1000 150,000 0

or 200 V Maximum
221A–04/TO–220 100 500–1000 75,000 0
267–03/Axial Lead (Surmetic 50) 30 1000 30,000 0

* Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions.

Theory and Applications Motorola Thyristor Device Data

1.8–18
 CHAPTER 9
APPENDICES
APPENDIX I
USING THE TWO TRANSISTOR ANALYSIS

DEFINITIONS: Equation (3) relates IA to IG, and note that as α1 + α2 = 1, IA

IC5 Collector current goes to infinity. IA can be put in terms of IK and α’s as follows:
IB5 Base current
5
IB1 = IC2
ICS Collector leakage current
(saturation component) Combining equations (1) and (2):
IA5 Anode current
+ ICS1 ) ICS2
IK5 Cathode current
IA
5
I
α Current amplification factor 1 – a 1 – ( K) a 2
IG 5 Gate current
IA
IA — ∞ if denominator approaches zero, i.e., if
The subscript “i” indicates the
appropriate transistor. IK
IA
+
1 – a1
a2

Note that just prior to turn–on there is a majority carrier

build–up in the P2 “base.” If the gate bias is small there will
actually be hole current flowing out from P2 into the gate
circuit so that IG is negative, IK = IA + IG is less than IA so:
FOR TRANSISTOR #1: (see Figure 3.2 for the directions of current components)
IC1 = α1 IA + ICSI IK
< 1 which corresponds to α1 + α2 > 1
and IA
IB1 = IA – IC1
Combining these equations, A
IB1 = (1 – α1) IA – ICS1 (1) IA

P1 IB1
DEVICE #1 N1 IC2
P2
N1
IC1
LIKEWISE, FOR TRANSISTOR #2 G N2 DEVICE #2
IC2 = α2IK + ICS2 (2) IG IB2 P2
IB1 = IC2
IK
and by combining Equations (1) and
(2) and substituting IK = IA + IG, it
K
is found that

IA+ ) )
a2IG ICS1 ICS2
(3)
Figure 9.1. Schematic Diagram of the Two Transistor
1 – a1 – a2 Model of a Thyristor

Motorola Thyristor Device Data Theory and Applications

1.9–1
 APPENDIX II
CHARGE AND PULSE WIDTH

In the region of large pulse widths using current triggering, Assume life time at the temperature range of operation
where transit time effects are not a factor, we can consider increases as some power of temperature
the input gate charge for triggering, Qin, as consisting of
τ1 = KTm (5)
three components:
1. Triggering charge Qtr, assumed to be constant. where K and m are positive real numbers. Combining
2. Charge lost in recombination, Qr, during current regen- Equations (4) and (5), we can get the slope of Qin with
eration prior to turn–on. respect to temperature to be
3. Charge drained, Qdr, which is by–passed through the
built–in gate cathode shunt resistance (the presence of
slope + dQdTin + – m(Qtr ) VRGCs ) t
t exp.
ń
t t1
(6)
this shunting resistance is required to increase the dv/dt t1 T
capability of the device).
Mathematically, we have In reality, Qtr is not independent of temperature, in which
case the Equation (6) must be modified by adding an
Qin = Qtr + Qdr + Qr = IGτ (1)
additional term to become:

ń )dQtr
Qr is assumed to be proportional to Qin; to be exact,
Qr = Qin (1 – exp–τ/τ1) (2) slope + – m(Qtr ) VRGCs )t
t exp.
t1 T
t t1
dT
expt t1ń (7)
where IG = gate current,
τ = pulse width of gate current, Physically, not only does Qtr decrease with temperature so
τ1 = effective life time of minority carriers in the that dQtr/dT is a negative number, but also |dQtr/dTI
bases decreased with temperature as does |dα/dTI in the tempera-
ture range of interest.
The voltage across the gate to cathode P–N junction during
forward bias is given by VGK (usually 0.6 V for silicon).* The Equation (6) [or (7)] indicates two things:
gate shunt resistance is Rs (for the MCR729, typically 100
1. The rate of change of input trigger charge decreases as
ohms), so the drained charge can be expressed by
temperature (life time) increases.

+ VRGCs
2. The larger the pulse width of gate trigger current, the
Qdr t (3) faster the rate of change of Qin with respect to change in
temperature. Figure 3.11 shows these trends.
Combining equations (1), (2), and (3), we get

Qin + IG + (Qtr ) VRGCs

t t) exp. ń
t t1 (4)

Note that at region A and C of Figure 3.3(c) Qin has an *VGC is not independent of IG. For example, for the MCR729
increasing trend with pulse width as qualitatively described the saturation VGC is typically 1 V, but at lower IG’s the VGC is
by Equation (4). also smaller, e.g. for IG = 5 mA, VGC is typically 0.3 V.

Theory and Applications Motorola Thyristor Device Data

1.9–2
 APPENDIX III
TTL SOA TEST CIRCUIT

Using the illustrated test circuit, the two TTL packages example, VCC could be at 5 V for 90 ms and 10 V for 10 ms,
(quad, 2–input NAND gates) to be tested were powered by simulating a transient on the bus or a possibly shorted power
the simple, series regulator that is periodically shorted by the supply pass transistor for that duration. These energy levels
clamp transistor, Q2, at 10% duty cycle rate. By varying the are progressively increased until the gate (or gates) fail, as
input to the regulator V1 and the clamp pulse width, various detected by the status of the output LEDs, the voltage and
power levels can be supplied to the TTL load. Thus, as an current waveforms and the device case temperature.

VCC
MJE220 LED
V1 VCC 1k 300
Q1
220 5.6 V V1 1k V2 = 10 V 220
2N3904 1A
2W 1W 2A
10 k VCC
100 µF G4 Q4 VCC
G3
10 V LED
1N4739 1N5240 0.1 µF
10 M 3.9 M 10 k 300
220
Q2 1D
MJE230 2D
MC14011

1k
[
SQUARE WAVE GENERATOR
f 1 Hz (2) MC7400
DUT
470
V2 V2

10 k
2N3904 Q3 G1 T1 T2
G2

10 k 10 k 100 k
5 ms < T2 < 250 ms
50 ms < T2 < 1.9 s
0.47 µF
2.2 M
500 k 5M
1N914 1N914

10% DUTY CYCLE GENERATOR

Figure 9.2. TTL SOA Test Circuit

Motorola Thyristor Device Data Theory and Applications

1.9–3
 APPENDIX IV
SCR CROWBAR LIFE TESTING

This crowbar life test fixture can simultaneously test ten time, SCR gate triggers, IGT. IGT is set by the collector
SCRs under various crowbar energy and gate drive condi- resistors of the respective gate drivers and the supply
tions and works as follows. voltage, VCC2; thus, for IGT ≈ 100 mA, VCC2 ≈ 30 V, etc.
The CMOS Astable M.V. (Gates 1 and 2) generate an The LEDs across the storage capacitors show the state of
asymmetric Gate 2 output of about ten seconds high, one the voltage on the capacitors and help determine whether
second low. This pulse is amplified by Darlington Q22 to turn the circuit is functioning properly. The timing sequence would
on the capacitor charging transistors Q1–Q10 for the ten be an off LED for the one–second capacitor dump period
seconds. The capacitors for crowbarring are thus charged in followed by an increasingly brighter LED during the capacitor
about four seconds to whatever power supply voltage to charge time. Monitoring the current of VCC1 will also indicate
which VCC1 is set. The charging transistors are then turned proper operation.
off for one second and the SCRs are fired by an approxi- The fixture’s maximum energy limits are set by the working
mately 100 µs delayed trigger derived from Gates 3 and 4. voltage of the capacitors and breakdown voltage of the
The R–C network on Gate 3 input integrates the complemen- transistors. For this illustration, the 60 V, 8400 µF capacitors
tary pulse from Gate 1, resulting in the delay, thus insuring (ESR ≈ 20 mΩ) produced a peak current of about 2500 A
non–coincident firing of the test circuit. The shaped pulse out lasting for about 0.5 ms when VCC1 equals 60 V. Other
of Gate 4 is differentiated and the positive–going pulse is energy values (lower ipk, greater tw) can be obtained by
amplified by Q21 and the following ten SCR gate drivers placing a current limiting resistor between the positive side of
(Q11–Q20) to form the approximate 2 ms wide, 1 µs rise the capacitor and the crowbar SCR anode.

VDD
+ 15 V
0.1 µF 10 k
Q21
100 k 4
3
MJE803
VSS 1N914
0.001 µF

MC14011B VCC1
470 VCC2
+15 V 2.2 k MJE250
+15 V
2W
Q1
1 10 k MJE250
2 Q22
470
2.2 k 100
VCC1 R1
2W 5W Q11
470 2.7 k 2.2 k
22 M 22 M 2.2 M
MJE803 1W 8400 µF
1N914 C1 270
2.2 k Q10
2W
0.47 µF MJE250 DUT #1
100
2.7 k VCC2
5W
1W 470
8400 µF MJE250
(10) LED C10 2.2 k
Q20

270
DUT #10
Figure 9.3. Schematic for SCR Crowbar Life Test

Theory and Applications Motorola Thyristor Device Data

1.9–4
 APPENDIX V APPENDIX VI

DERIVATION OF THE RMS CURRENT DERIVATION OF I2t FOR VARIOUS TIMES

OF AN EXPONENTIALLY DECAYING
CURRENT WAVEFORM

Thermal Equation ∆t = Z(θ)PD

i = Ipke–t/τ where Z(θ) = r(t)RθJC
Ipk
and r(t) = K t Ǹ

Ǹŕ
T=5τ Therefore, for the same ∆t,

Dt + K Ǹt1 RqJCPD + K Ǹt2 RqJC PD 2,

Ǹ
1
+
T
1 i2(t)dt
+ + II12RR ,
Irms PD 2
t2

ŕ
T 0 1

ń
PD

Ǹ
t1 2
12 2
+ 1
T
ń 2
(I e–t t)2dt
T 0 pk I1
I22
+ t2

ń
t1
1 2

+ ń
Ipk2 e–2t t T
ń
ǒ Ǔ ń +ǒ Ǔ ń
Multiplying both sides by (t1/t2),
T (–2 t)

ǒǓ
2
+ t2 1 2 t1 t1 1 2
0 I1 t1
ń
Ǹ
,
1 2 I22t2 t1 t2 t2
+ Ipk2 –t
(e–2T ń t – e0)
T 2
I12t1 + I22t2 t1
t2
where T = 5τ,
1 2 ń
+ –
Ipk2
10
(e–10 – 1)

Irms + ǸIpk10 + 0.316 Ipk

Motorola Thyristor Device Data Theory and Applications

1.9–5
 APPENDIX VII
THERMAL RESISTANCE CONCEPTS

The basic equation for heat transfer under steady–state The equivalent electrical circuit may be analyzed by using
conditions is generally written as: Kirchoff’s Law and the following equation results:

q = hA∆T (1) TJ = PD(RθJC + RθCS + RθSA) + TA (3)

where TJ = junction temperature,

where q = rate of heat transfer or power dissipation (PD), PD = power dissipation,
h = heat transfer coefficient, RθJC = semiconductor thermal resistance
A = area involved in heat transfer, (junction to case),
∆T = temperature difference between regions of heat RθCS = interface thermal resistance
transfer. (case to heat sink),
RθSA = heat sink thermal resistance
However, electrical engineers generally find it easier to work (heat sink to ambient),
in terms of thermal resistance, defined as the ratio of TA = ambient temperature.
temperature to power. From Equation (1), thermal resis-
tance, Rθ, is The thermal resistance junction to ambient is the sum of
the individual components. Each component must be
minimized if the lowest junction temperature is to result. The
Rθ = ∆T/q = 1/hA (2) value for the interface thermal resistance, RθCS, is affected
by the mounting procedure and may be significant compared
The coefficient (h) depends upon the heat transfer mecha- to the other thermal–resistance terms.
nism used and various factors involved in that particular The thermal resistance of the heat sink is not constant; it
mechanism. decreases as ambient temperature increases and is affected
An analogy between Equation (2) and Ohm’s Law is often by orientation of the sink. The thermal resistance of the
made to form models of heat flow. Note that ∆T could be semiconductor is also variable; it is a function of biasing and
thought of as a voltage; thermal resistance corresponds to temperature. In some applications such as in RF power
electrical resistance (R); and, power (q) is analogous to amplifiers and short–pulse applications, the concept may be
current (l). This gives rise to a basic thermal resistance invalid because of localized heating in the semiconductor
model for a semiconductor (indicated by Figure 9.4). chip.

TJ, JUNCTION TEMPERATURE

DIE RθJC
PD
TC, CASE TEMPERATURE
MICA INSULATORS
RθCS
TS, HEAT SINK
HEAT SINK TEMPERATURE
RθSA
TA, AMBIENT
FLAT WASHER TEMPERATURE

SOLDER TERMINAL

NUT REFERENCE TEMPERATURE

Figure 9.4. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor

Theory and Applications Motorola Thyristor Device Data

1.9–6
 APPENDIX VIII
DERIVATION OF RFI DESIGN EQUATIONS

df where:
The relationship of flux to voltage and time is E = N or
dt N is total turns
E = NAc dB since φ = BAc and Ac is a constant. Rearranging Erms is line voltage
dt tr is allowable current rise time in seconds

ŕ
this equation and integrating we get: BMAX is maximum usable flux density of core material
Ac is usable core area in square inches
Window area necessary is:
E dt = NAc (B2 – B1) = NAc ∆ B

(1)
Aw = N Awire 3 (4)

which says that the volt–second integral required determines The factor of 3 is an approximation which allows for
the size of the core. In an L–R circuit such as we have with a insulation and winding space not occupied by wire. Substitut-
thyristor control circuit, the volt–second characteristic is the ing equation (3) in (4):
area under an exponential decay. A conservative estimate of
the area under the curve may be obtained by considering a
triangle whose height is the peak line voltage and the base is Aw + 10.93BEMAX
rms tr
Ac
106
Awire 3
Eptr
the allowable switching time. The area is then 1/2 bh or .
2 (The factor 10.93 may be rounded to 11 since two significant
Substituting in Equation (1): digits are all that are necessary.)
The factor AcAw can easily be found for most cores and is an
Eptr
2
+ N Ac D B (2) easy method for selecting a core.

where: Ac Aw + 33 ErmsBtMAX
rAwire 106

Ep is the peak line voltage

tr is the allowable current rise time
In this equation, the core area is in in2. To work with circular
N is the number of turns on the coil
Ac is the usable core area in cm2
mils, multiply by 0.78 
10–6 so that:
∆ B is the maximum usable flux density of the core material
in W/m2 Ac Aw + 26 Erms
BMAX
trAwire
Rewriting Equation (2) to change ∆B from W/m2 to gauss,
Ǹ
substituting 2 Erms for Ep and solving for N, we get: where Awire is the wire area in circular mils.
Inductance of an iron core inductor is

+ Ǹ22 AEcrmsD Btr 108 + 0.707BEMAX

rms tr 108
+ 3.19 N2 A1cc 10–8
N
Ac L
Ig ) m
Ac in this equation is in cm2. To change to in2, multiply Ac
by 6.452. Then:
Rearranging terms,

N + 10.93BMAX
Erms tr 106
Ac
(3)
Ig + 3.19 N LAc 10
2 –8 1
– mc

APPENDIX IX

BIBLIOGRAPHY ON RFI
Electronic Transformers and Circuits, Reuben Lee, John Wiley and Sons, Inc., New York, 1955.
Electrical Interference, Rocco F. Ficchi, Hayden Book Company, Inc., New York, 1964.
“Electromagnetic–Interference Control,” Norbert J. Sladek, Electro Technology, November, 1966, p. 85.
“Transmitter–Receiver Pairs in EMI Analysis,” J. H. Vogelman, Electro Technology, November, 1964, p. 54.
“Radio Frequency Interference,” Onan Division of Studebaker Corporation, Minneapolis, Minnesota.
“Interference Control Techniques,” Sprague Electric Company, North Adams, Massachusetts, Technical Paper 62–1, 1962.
“Applying Ferrite Cores to the Design of Power Magnetics,” Ferroxcube Corporation of America, Saugerties, New York, 1966.

Motorola Thyristor Device Data Theory and Applications

1.9–7
Theory and Applications Motorola Thyristor Device Data
1.9–8
 In Brief . . .
Selector Guide
Motorola’s broad line of Thyristors includes. . . . Page
• A full line of TRIACs and SCRs covering a forward New Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
current range from 0.5 to 55 amperes and blocking Silicon Controlled Rectifiers . . . . . . . . . . . . . . . . . . . . . . 5.7–2
voltages from 15 to 800 volts. TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7–7
• Plastic package for lowest cost which includes the fully General Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7–7
insulated plastic Case 221C (TO–220 Isolated). Thyristor Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7–14
• An extensive line of trigger devices that includes SIDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7–14
SIDACs, PUTs and SBS. Programmable Unijunction Transistors — PUT . . 5.7–14
Then there are the special applications devices for Silicon Bidirectional Switch (SBS) . . . . . . . . . . . . . 5.7–14
Ignition circuits and Crowbar applications. Also included are High Voltage Bidirectional TVS Devices . . . . . . . . 5.7–14
isolated packaged devices for appliances and surface
mount packages for surface mounting in space–saving
requirements.
Finally, there is the continued Motorola investment in
discrete–product R & D producing new capabilities such as
transient SIDACs for use in circuits sensitive to high voltage
transients.

2–1
Numeric Index

Device Page Device Page Device Page

2N Devices MAC Devices (TRIACs) MCR Devices (SCRs)

2N3870–73 2–8 MAC08BT1 2–10 MCR08BT1 2–3
2N5060–64 2–3 MAC08DT1 2–10 MCR08DT1 2–3
2N6027–28 2–21 MAC08MT1 2–10 MCR08MT1 2–3
2N6071 Series 2–11 MAC8 Series MCR8 Series
2N6071A Series 2–11 MAC9 Series MCR8S Series
2N6071B Series 2–11 MAC12 Series MCR12 Series
2N6171–74 2–8 MAC15 Series 2–16 MCR16 Series
2N6237–41 2–4 MAC15A Series 2–16 MCR22 Series 2–3
2N6342–45 2–13 MAC15AFP Series 2–17 MCR25 Series
2N6346A–49A 2–16 MAC15FP Series 2–17 MCR63A Series 2–9
2N6394–99 2–6 MAC16 Series 2–16 MCR64 2–9
2N6400 Series 2–7 MAC97,A,B Series 2–10 MCR65 Series 2–9
2N6504–09 2–7 MAC210 Series 2–14 MCR68 Series 2–6
MAC210A Series 2–14 MCR69 Series 2–7
European Part Numbers MAC210AFP Series 2–15 MCR72 Series 2–6
BRX44–49 2–3 MAC210FP Series 2–15 MCR100 Series 2–3
BRY55–30 2–3 MAC212 Series 2–15 MCR102–103 2–3
BRY55–60 2–3 MAC212A 2–15 MCR106 Series 2–4
BRY55–100 2–3 MAC212AFP Series 2–15 MCR218 Series 2–5
BRY55–200 2–3 MAC210FP Series 2–15 MCR218FP 2–5
BRY55–400 2–3 MAC213 Series 2–16 MCR225FP Series 2–7
BRY55–500 2–3 MAC218 Series 2–12 MCR264 Series 2–8
BRY55–600 2–3 MAC218A Series 2–12 MCR265 2–9
MAC218AFP Series 2–13 MCR310 Series 2–6
“C” Devices (SCRs) MAC218FP Series 2–13 MCR506 Series 2–5
C106 Series 2–4 MAC219 Series 2–13 MCR703A Series 2–5
C122 Series 2–5 MAC223 Series 2–18 MCR703A1 Series 2–4
MAC223A Series 2–18
MAC223AFP Series 2–17 “S” Devices (SCRs)
MAC223FP Series 2–17 S2800 Series 2–6
MAC224 Series 2–18
MAC224A Series 2–18 “T” Devices (TRIACs)
MAC228 Series 2–14 T2322 Series 2–10
MAC228A Series 2–14 T2323 Series 2–11
MAC228AFP Series 2–14 T2500 Series 2–11
MAC228FP Series 2–14 T2500FP Series 2–12
MAC229 Series 2–14 T2800 Series 2–13
MAC229A Series 2–14
MAC229AFP Series 2–14 MK Devices (SIDACs)
MAC229FP Series 2–14 MKP1V Series 2–21
MAC310 Series 2–15 MKP3V Series 2–21
MAC310A Series 2–15
MAC320 Series 2–17 MBS Devices (SBS)
MAC320A Series 2–17 MBS4991 Series 2–21
MAC320AFP Series 2–17
MAC320FP Series 2–17
MMT Devices
MAC321 Series 2–17
MMT10V275
MMT10V400

Selector Guide Motorola Thyristor Device Data

2–2
 New Products
High Performance T0–220
• Snubberless Triacs

This new series of devices is designed for high performance full–wave ac control applications where noise immunity
and high dv/dt capability are required. Snubber networks can be reduced or eliminated in many cases which saves
design time and money. Two levels of gate sensitivity and dv/dt are offered. Combined with our low cost / high quality
ATLAS package these new triacs set a performance standard for the industry. Offerings include MAC8, MAC9,
MAC12, MAC15, MAC16 series which are available at 400 – 800 volts.

• High Performance SCR’S

The MCR8, MCR8S, MCR12, MCR16, MCR25 series are the latest high performance, new generation thyristors from
Motorola. The devices are rated at 8, 12, 16, 25 Amperes and are available with voltage ranges of 400, 600, 800 Volts.
They are designed primarily for half–wave a/c control applications, such as motor controls, heating controls and
power supplies or wherever half–wave silicon gate–controlled devices are needed. Minimum and maximum values
are specified on critical parameters such as IGT, VGT, IH. The MCR8S series offers 200 µA IGT for applications where
drive current is limited such as direct drive from an integrated circuit.

More to come . . . . . . . We have more planned for this exciting new series of High Performance Thyristors in
’95 . . . 4 quadrant Triacs at 8 – 25 Amperes, sensitive gate 8 and 12 Ampere triacs, and sensitive gate 12 Ampere
SCR’s . . . look for the next edition of this data book!!

High Voltage Bidirectional TVS Devices

MMT10V275 and MMT10V400 are designed to protect sensitive telecom switching equipment from overvoltage
damage induced by lightning, power line crossings, electrostatic discharge and induction. Designed to protect primary
lines, applications include current loop lines in telephony and control systems, central office stations, repeaters,
building and residence entrance terminals and electronic telecom equipment. These new devices offer surge
capability up to 100 amperes peak, high holding current and extended temperature operation in the blocking or
conducting state of –40°C to +125°C. These surge suppressors are also immune from the wearout mechanisms that
can be present in other non solid state technologies.

For more information . . . . . . . on any of these new products see sections 2 & 3 of this data book.

Motorola Thyristor Device Data Selector Guide

2–3
 I (+)

SCRs REVERSE IT
BLOCKING VT
REGION
IH
VRRM IDRM
V (–) V (+)
IRRM VDRM
Silicon FORWARD
FORWARD
BREAKOVER
Controlled REVERSE
BLOCKING
REGION
POINT
AVALANCHE REGION I (–)
Rectifiers
Table 1. SCRs — General Purpose Plastic Packages
0.8 to 55 Amperes RMS, 25 to 800 Volts

On–State (RMS) Current

0.8 AMP 1.5 AMPS

TC = 58°C TC = 80°C TC = 50°C

K
A
K G K
G A G A

Sensitive Gate
VDRM
Case 29–04 Case 318E Case 29–04 VRRM (Volts)
TO–226AA (TO–92) Style 10 SOT–223 STYLE 10 TO–226AA (TO–92)
Style 10
MCR102 BRX44/BRY55–30(4) 25
2N5060
MCR103 BRX45/BRY55–60(4) MCR22–2 50
2N5061
MCR100–3 BRX46/BRY55–100(4) MCR22–3 100
2N5062
MCR100–4 BRX47/BRY55–200(4) MCR08BT1 MCR22–4 200
2N5064
MCR100–6 BRX49/BRY55–400(4) MCR08DT1 MCR22–6 400

BRY55–500(4) 500

MCR100–8 BRY55–600(4) MCR08MT1 MCR22–8 600

Maximum Electrical Characteristics

10 15 10 15 ITSM (Amps)
(1)150(3) (1)150(3) 60 Hz

0.2 IGT (mA)

0.8 VGT (V)

– 65 to – 40 to – 40 to – 40 to TJ Operating
+110 +125 +110 +125 Range (°C)

(3) Exponential decay 2 µs wide at 5 time constants, f = 12 Hz.

(4) European Part Numbers. Package is Case 29 with
Leadform 18. Case style is 3.
Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola Thyristor Device Data

2–2
SCRs (continued)

Table 1. SCRs — General Purpose Plastic Packages (continued)

On–State (RMS) Current

4 AMPS 6 AMPS
TC = 93°C TC = 30°C
A
A A A

G
A
K
G GA
GA K
K A
K

Sensitive Gate Surface Mount Sensitive Gate

VDRM Case 77 Case 369 Case 369A Case 77
VRRM TO–225AA (TO–126) Style 5 Style 5 TO–225AA (TO–126)
(Volts) Style 2 Style 2
50 MCR106–2 C106F MCR506–2
2N6237
100 MCR106–3 C106A MCR703A1 MCR703A (5) MCR506–3
2N6238
200 MCR106–4 C106B MCR704A1 MCR704A (5) MCR506–4
2N6239
400 MCR106–6 C106D MCR706A1 MCR706A (5) MCR506–6
2N6240
600 MCR106–8 C106M MCR708A1 MCR708A (5) MCR506–8
2N6241
800

Maximum Electrical Characteristics

ITSM (Amps) 25 20 25 40
60 Hz

IGT (mA) 0.2 0.075 0.2

VGT (V) 1 0.8 1

TJ Operating – 40 to
Range (°C) +110

(5) Available in tape and reel — add RL suffix to part number.

Indicates UL Recognized — File #E69369

Devices listed in bold, italic are Motorola preferred devices.

Motorola Thyristor Device Data Selector Guide

2–3
SCRs (continued)

Table 1. SCRs — General Purpose Plastic Packages (continued)

On–State (RMS) Current

8 AMPS 10 AMPS
TC = 70°C TC = 83°C TC = 80°C TC = 75°C
A A
A

K K
A K A K
G A A
G
G G

High Performance
Isolated Sensitive Gate Sensitive Gate
Case 221C–02 Case 221A–04 Case 221A–06 Case 221A–04 VDRM
Style 2 TO–220AB TO–220AB TO–220AB VRRM
Style 3 Style 3 Style 3 (Volts)

MCR72–2 50

MCR72–3 MCR310–3 100

MCR218–4FP MCR72–4 MCR310–4 200

MCR218–6FP MCR72–6 MCR8D MCR8SD MCR310–6 400

MCR218–8FP MCR72–8 MCR8M MCR8SM MCR310–8 600

MCR218–10FP MCR72–10 MCR8N MCR8SN MCR310–10 800

Maximum Electrical Characteristics

80 100 80 100 ITSM (Amps)

60 Hz

25 0.2 15 0.2 IGT (mA)

1.5 1 1.5 VGT (V)

– 40 to – 40 to – 40 to – 40 to TJ Operating
+125 +110 +125 +110 Range (°C)

(5) Available in tape and reel — add RL suffix to part number.

Indicates UL Recognized — File #E69369

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola Thyristor Device Data

2–4
SCRs (continued)

Table 1. SCRs — General Purpose Plastic Packages (continued)

On–State (RMS) Current

10 AMPS 12 AMPS 16 AMPS 25 AMPS

TC = 75°C TC = 80°C TC = 85°C

A A
A

K K
K
A A
G G A
G
Sensitive Gate High Performance
VDRM Case 221A–04 Case 221A–06 Case 221A–04
VRRM TO–220AB TO–220AB TO–220AB
(Volts) Style 3 Style 3 Style 3

50 2N6504

100 S2800A 2N6505

200 S2800B 2N6506

400 S2800D MCR12D MCR16D MCR25D 2N6507

600 S2800M MCR12M MCR16M MCR25M 2N6508

800 S2800N MCR12N MCR16N MCR25N 2N6509

Maximum Electrical Characteristics

ITSM (Amps) 100 150 300

60 Hz

IGT (mA) 15 20 30 40

VGT (V) 1.5 2.2 1.7 1 1.5

TJ Operating – 40 to – 40 to
Range (°C) +100 +125

Devices listed in bold, italic are Motorola preferred devices.

Motorola Thyristor Device Data Selector Guide

2–5
SCRs (continued)

Table 1. SCRs — General Purpose Plastic Packages (continued)

On–State (RMS) Current

25 AMPS 40 AMPS 55 AMPS

TC = 85°C TC = 80°C TC = 70°C

A A

K
A
K G K
A A
G Isolated G

Case 221A–04 Case 221C–02 Case 221A–04 VDRM

TO–220AB Style 2 TO–220AB VRRM
Style 3 Style 3 (Volts)

MCR69–2 MCR225–2FP 50

MCR69–3 100

MCR225–4FP MCR264–4 MCR265–4 200

MCR69–6 MCR225–6FP MCR264–6 MCR265–6 400

MCR225–8FP MCR264–8 MCR265–8 600

MCR225–10FP MCR264–10 MCR265–10 800

Maximum Electrical Characteristics

(1)750(2) 300 400 550 ITSM (Amps)

60 Hz

30 40 50 IGT (mA)

1.5 VGT (V)

– 40 to TJ Operating
+125 Range (°C)

(2) Peak capacitor discharge current for tw = 1 ms. tw is defined as five time constants of an exponentially decaying current pulse
(crowbar applications).
Indicates UL Recognized — File #E69369

TRIACs
Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola Thyristor Device Data

2–6
Table 2. TRIACs — General Purpose Plastic Packages
0.6 to 40 Amperes, 200 to 800 Volts

On–State (RMS) Current

0.6 AMP 0.8 AMPS 2.5 AMPS

TC = 50°C TC = 80°C TC = 70°C

MT2

MT2

MT1
MT2
G
MT1 G
G MT2 MT1
MT2
Sensitive Gate
Case 29–04 Case 318E Case 77
VDRM TO–226AA (TO–92) Style 11 TO–225AA (TO–126)
(Volts) Style 12 SOT–223 Style 5

200 MAC97–4 MAC97A4 MAC97B4 MAC08BT1 T2322B

400 MAC97–6 MAC97A6 MAC97B6 MAC08DT1 T2322D

600 MAC97–8 MAC97A8 MAC97B8 MAC08MT1 T2322M

Maximum Electrical Characteristics

ITSM (Amps) 8 10 25

IGT @ 25°C (mA)

MT2(+)G(+) 10 5 3 10 10
MT2(+)G(–) 10 5 3 10 10
MT2(–)G(–) 10 5 3 10 10
MT2(–)G(+) 10 7 5 10 10
VGT @ 25°C (V) 0.8
MT2(+)G(+) 2 2 2.2
MT2(+)G(–) 2 2 2.2
MT2(–)G(–) 2 2 2.2
MT2(–)G(+) 2.5 2 2.2
TJ Operating – 40 to
Range (°C) +110

Devices listed in bold, italic are Motorola preferred devices.

Motorola Thyristor Device Data Selector Guide

2–7
TRIACs (continued)

Table 2. TRIACs (continued)

On–State (RMS) Current

2.5 AMPS 4 AMPS 6 AMPS

TC = 70°C TC = 85°C TC = 80°C

MT2 MT2

G
MT2 MT1 MT1
MT2
Sensitive Gate G
Case 77 Case 221A–04
TO–225AA (TO–126) TO–220AB VDRM
Style 5 Style 4 (Volts)

T2323B 2N6071 2N6071A 2N6071B T2500B 200

T2323D 2N6073 2N6073A 2N6073B T2500D 400

T2323M 2N6075 2N6075A 2N6075B T2500M 600

T2500N 800

Maximum Electrical Characteristics

25 30 60 ITSM (Amps)

IGT @ 25°C (mA)

25 30 5 3 25 MT2(+)G(+)
40 — 5 3 60 MT2(+)G(–)
25 30 5 3 25 MT2(–)G(–)
40 — 10 5 60 MT2(–)G(+)
@ – 40°C @ – 40°C VGT @ 25°C (V)
2.2 2.5 2.5 2.5 MT2(+)G(+)
2.2 — 2.5 2.5 MT2(+)G(–)
2.2 2.5 2.5 2.5 MT2(–)G(–)
2.2 — 2.5 2.5 MT2(–)G(+)
– 40 to – 40 to TJ Operating
+110 +100 Range (°C)

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola Thyristor Device Data

2–8
TRIACs (continued)

Table 2. TRIACs (continued)

On–State (RMS) Current

6 AMPS 8 AMPS
TC = 80°C TC = 80°C TC = 70°C TC = 80°C

MT2

MT1 MT1 MT1

MT2 MT2 MT2
G G G

Sensitive Gate

Isolated High Performance Isolated

Case 221A–04 Case 221A–06
VDRM Case 221C–02 Case 221C–02
TO–220AB TO–220AB
(Volts) Style 3
Style 4 Style 4
Style 3

MAC218–4 MAC218–4FP
200 T2500BFP MAC218A4 MAC218A4FP
MAC218–6 MAC8SD MAC8D MAC9D MAC218–6FP
400 T2500DFP MAC218A6 MAC218A6FP
MAC218–8 MAC8SM MAC8M MAC9M MAC218–8FP
600 T2500MFP MAC218A8 MAC218A8FP
MAC218–10 MAC8SN MAC8N MAC9N MAC218–10FP
800 T2500NFP MAC218A10FP
MAC218A10

Maximum Electrical Characteristics

ITSM (Amps) 100 70 80 100

Min. Max.
IGT @ 25
25°C
C (mA)
MT2(+)G(+) 25 50 0.8 5.0 35 50 50
MT2(+)G(–) 60 50 0.8 5.0 35 50 50
MT2(–)G(–) 25 50 0.8 5.0 35 50 50
MT2(–)G(+) 60 (1)75(1) — — — — (1)75(1)
VGT @ 25°C (V)
MT2(+)G(+) 2.5 2 0.45 1.5 1.5 2
MT2(+)G(–) 2.5 2 0.45 1.5 1.5 2
MT2(–)G(–) 2.5 2 0.45 1.5 1.5 2
MT2(–)G(+) 2.5 (1)2.5(1) — — — (1)2.5(1)
TJ Operating – 40 to – 40 to – 40 to – 40 to
Range (°C) +100 +125 +110 +125
(1) Applied to A–version only. Non A–version is unspecified.
Indicates UL Recognized — File #E69369

Devices listed in bold, italic are Motorola preferred devices.

Motorola Thyristor Device Data Selector Guide

2–9
TRIACs (continued)

Table 2. TRIACs (continued)

On–State (RMS) Current

8 AMPS
TC = 80°C
MT2

MT1
MT1 MT2
MT2 G
G
Isolated

Sensitive Gate
Case 221A–04 Case 221C–02 VDRM
TO–220AB Style 3
Style 4 (Volts)
2N6342 T2800B MAC228–4 MAC229–4 MAC228–4FP MAC229–4FP 200
2N6346 MAC228A4 MAC229A4 MAC228A4FP MAC229A4FP

2N6343 T2800D MAC228–6 MAC229–6 MAC228–6FP MAC229–6FP 400

2N6347 MAC228A6 MAC229A6 MAC228A6FP MAC229A6FP
2N6344 T2800M MAC228–8 MAC229–8 MAC228–8FP MAC229–8FP 600
2N6348 MAC228A8 MAC229A8 MAC228A8FP MAC229A8FP
2N6345 MAC228–10 MAC229–10 MAC228–10FP MAC229–10FP 800
2N6349 MAC228A10 MAC229A10 MAC228A10FP MAC229A10FP

Maximum Electrical Characteristics

100 80 ITSM (Amps)

IGT @ 25°C (mA)

50 25 5 10 5 10 MT2(+)G(+)
(6)75(6) 60 5 10 5 10 MT2(+)G(–)
50 25 5 10 5 10 MT2(–)G(–)
(6)75(6) 60 (1)10(1) (1)20(1) (1)10(1) (1)20(1) MT2(–)G(+)
VGT @ 25°C (V)
2 2.5 2 MT2(+)G(+)
(6)2.5(6) 2.5 2 MT2(+)G(–)
2.5 2.5 2 MT2(–)G(–)
(6)2.5(6) 2.5 (1)2.5(1) MT2(–)G(+)
– 40 to – 40 to – 40 to TJ Operating
+125 +100 +110 Range (°C)
(1) Applied to A–version only. Non A–version is unspecified.
(6) Denotes 2N6346–49 Series only.
Indicates UL Recognized — File #E69369

Selector Guide Motorola Thyristor Device Data

2–10
TRIACs (continued)

Table 2. TRIACs (continued)

On–State (RMS) Current

10 AMPS 12 AMPS
TC = 70°C TC = 75°C TC = 85°C
MT2
MT2 MT2

MT1 MT1 MT1

MT2 MT1 MT2 MT2
MT1 G MT2 G
G
MT2 G
G
Isolated Sensitive Gate Isolated

VDRM Case 221A–04 Case 221C–02 Case 221A–04 Case 221C–02 Case 221A–04
TO–220AB Style 3 TO–220AB Style 3 TO–220AB
(Volts) Style 4 Style 4 Style 4

200 MAC210–4 MAC210–4FP MAC310–4 MAC212–4FP MAC212–4

MAC210A4 MAC210A4FP MAC310A4 MAC212A4FP MAC212A4

400 MAC210–6 MAC210–6FP MAC310–6 MAC212–6FP MAC212–6

MAC210A6 MAC210A6FP MAC310A6 MAC212A6FP MAC212A6

600 MAC210–8 MAC210–8FP MAC310–8 MAC212–8FP MAC212–8

MAC210A8 MAC210A8FP MAC310A8 MAC212A8FP MAC212A8
800 MAC210–10 MAC210–10FP MAC310–10 MAC212–10FP MAC212–10
MAC210A10 MAC210A10FP MAC310A10 MAC212A10FP MAC212A10

Maximum Electrical Characteristics

ITSM (Amps) 100

IGT @ 25°C (mA)

MT2(+)G(+) 50 5 50
MT2(+)G(–) 50 5 50
MT2(–)G(–) 50 5 50
MT2(–)G(+) (1)75(1) (1)10(1) (1)75(1)

VGT @ 25°C (V)

MT2(+)G(+) 2
MT2(+)G(–) 2
MT2(–)G(–) 2
MT2(–)G(+) (1)2.5(1)
TJ Operating – 40 to
Range (°C) +125
(1) Applied to A–version only. Non A–version is unspecified.
Indicates UL Recognized — File #E69369

Motorola Thyristor Device Data Selector Guide

2–11
TRIACs (continued)

Table 2. TRIACs (continued)

On–State (RMS) Current

12 AMPS 15 AMPS
TC = 80°C TC = 70°C TC = 90°C TC = 80°C TC = 90°C

MT2

MT1
MT1
MT2
G MT2
G
Sensitive Gate

High
High Performance Isolated
Performance
Case 221A–04 Case 221A–06 Case 221A–04 Case 221A–06 Case 221C–02
TO–220AB TO–220AB TO–220AB TO–220AB Style 3 VDRM
Style 4 Style 4 Style 4 Style 4 (Volts)
2N6346A MAC15–4 MAC15–4FP 200
MAC15A4 MAC15A4FP
2N6347A MAC12D MAC15D MAC15SD MAC15–6 MAC16D MAC15–6FP 400
MAC15A6 MAC15A6FP
2N6348A MAC12M MAC15M MAC15SM MAC15–8 MAC16M MAC15–8FP 600
MAC15A8 MAC15A8FP

2N6349A MAC12N MAC15N MAC15SN MAC15–10 MAC16N MAC15–10FP 800

MAC15A10 MAC15A10FP

Maximum Electrical Characteristics

120 150 120 150 ITSM (Amps)

Min. Max.
IGT @ 25°C
25 C (mA)
50 35 0.8 5.0 50 50 50 MT2(+)G(+)
75 35 0.8 5.0 50 50 50 MT2(+)G(–)
50 35 0.8 5.0 50 50 50 MT2(–)G(–)
75 — — — 75(1) — (1)75(1) MT2(–)G(+)
VGT @ 25°C (V)
2 1.5 0.45 1.5 2 1.5 2 MT2(+)G(+)
2.5 1.5 0.45 1.5 2 1.5 2 MT2(+)G(–)
2 1.5 0.45 1.5 2 1.5 2 MT2(–)G(–)
2.5 — — — 2.5(1) — (1)2.5(1) MT2(–)G(+)
– 40 to – 40 to – 40 to TJ Operating
+125 +110 +125 Range (°C)
(1) Applied to A–version only. Non A–version is unspecified.
Indicates UL Recognized — File #E69369

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola Thyristor Device Data

2–12
TRIACs (continued)

Table 2. TRIACs (continued)

On–State (RMS) Current

20 AMPS 25 AMPS 40 AMPS

TC = 75°C TC = 80°C TC = 75°C

MT2 MT2

MT1 MT1
MT2 MT2
G MT1 G MT1
MT2 MT2
Isolated G Isolated G

Case 221C–02 Case 221A–04 Case 221C–02 Case 221A–04

VDRM Style 3 TO–220AB Style 3 TO–220AB
(Volts) Style 4 Style 4

200 MAC320–4FP MAC320–4 MAC321–4 MAC223–4FP MAC223–4 MAC224–4

MAC320A4FP MAC320A4 MAC223A4FP MAC223A4 MAC224A4
400 MAC320–6FP MAC320–6 MAC321–6 MAC223–6FP MAC223–6 MAC224–6
MAC320A6FP MAC320A6 MAC223A6FP MAC223A6 MAC224A6
600 MAC320–8FP MAC320–8 MAC321–8 MAC223–8FP MAC223–8 MAC224–8
MAC320A8FP MAC320A8 MAC223A8FP MAC223A8 MAC224A8
800 MAC320–10FP MAC320–10 MAC321–10 MAC223–10FP MAC223–10 MAC224–10
MAC320A10FP MAC320A10 MAC223A10FP MAC223A10 MAC224A10

Maximum Electrical Characteristics

ITSM (Amps) 150 250 350

IGT @ 25°C (mA)

MT2(+)G(+) 50 100 50
MT2(+)G(–) 50 100 50
MT2(–)G(–) 50 100 50
MT2(–)G(+) (1)75(1) — (1)75(1)
VGT @ 25°C (V)
MT2(+)G(+) 2 2 2
MT2(+)G(–) 2 2 2
MT2(–)G(–) 2 2 2
MT2(–)G(+) (1)2.5(1) — (1)2.5(1)
TJ Operating – 40 to
Range (°C) +125
(1) Applied to A–version only. Non A–version is unspecified.
Indicates UL Recognized — File #E69369

Devices listed in bold, italic are Motorola preferred devices.

Motorola Thyristor Device Data Selector Guide

2–13
Thyristor Triggers
I (+)
I (+)
ITM VTM VS
IS IH
IH
IDRM I (BO) V (–) IS
VS
V (–) V (+) IS V (+)
IH
VDRM V(BO) VS
Table 3. SIDACs Table 5. Silicon
I (–) Table 7. Bidirectional
High voltage trigger devices similar in operation to a Triac. I (–)
Table 7. Switch (SBS)
Upon reaching the breakover voltage in either direction, the
device switches to a low–voltage on–state. This versatile trigger device exhibits highly symmetrical bi-
directional switching characteristics which can be modified
VBO Volts
by means of a gate lead. Requires a gate trigger current of
Device Type ITSM Amps Min Max only 250 µAdc for triggering.
Case 267–03/1
VS
MKP3V110 20 100 120 Volts
Device IS IH
MKP3V120 20 110 130
Type Min Max µA Max mA Max
MKP3V130 20 120 140
Case 59–04/1 Plastic TO–92/TO–226AA (Case 29–04/12)

MKP1V120 4 110 130 MBS4991 6 10 500 1.5

MKP1V130 4 120 140 MBS4992 7.5 9 120 0.5
MBS4993 7.5 9 250 0.75

PEAK POINT
VP
Table 4. Programmable VS
Table 6. Unijunction VAK VALLEY POINT
Table 6. Transistor VF
Table 6. — PUT VV

Similar to UJTs, except that IIGAO

V, IP andIP intrinsic
IV standoff
IF
voltage are programmable (adjustable)
(0,0) by
IAmeans of external
voltage divider. This stabilizes circuit performance for
variations in device parameters. General operating
frequency range is from 0.01 Hz to 10 kHz, making them
suitable for long–duration timer circuits.
IP IV
IGAO
Device RG = RG = RG = RG =
@ 40 V
Type 10 kΩ 1 MΩ 10 kΩ 1 MΩ
nA Max
µA Max µA Min µA Max

Plastic TO–92 (Case 29–04/16)

2N6027 5 2 10 70 50
2N6028 1 0.15 10 25 25

Table 6. High Voltage Bidirectional TVS Devices Case 416A–01

Primary Protection
MMT10V275 100 200 275
Transient Voltage Suppression (TVS) devices are break- MMT10V400 100 265 400
over–triggered crowbar protectors. Turn–off occurs when the
Thyristor Surge Suppressors–Secondary Protection
surge current falls below the holding current value.
Package SO–8
VBR Volts VBO Volts
Device Type ITSM Amps (Min) (Max) MGSS150–1 30 AMP, 150 mA lh, Programmable Bidirectional
Surge Suppressor
Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola Thyristor Device Data

2–14
Package 8 Pin PDIP
MGSS150–2 30 AMP, 150 mA lh, Programmable Bidirectional
Surge Suppressor

• Telecom Line Card Protection

• Dual Line Protection in a Single Package
• 2 Package Choices
• Bidirectional Capability
• 30 AMP Surge
• 150 mA lh
• Low Gate Trigger Current

Motorola Thyristor Device Data Selector Guide

2–15
 Data Sheets

1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2N5060
2N5061
Silicon Controlled Rectifiers 2N5062 *
Reverse Blocking Triode Thyristors 2N5064 *
*Motorola preferred devices
. . . Annular PNPN devices designed for high volume consumer applications such as
relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and
sensing and detection circuits. Supplied in an inexpensive plastic TO-226AA (TO-92) SCRs
package which is readily adaptable for use in automatic insertion equipment. 0.8 AMPERES RMS
30 thru 200 VOLTS
• Sensitive Gate Trigger Current — 200 µA Maximum
• Low Reverse and Forward Blocking Current — 50 µA Maximum, TC = 125°C
• Low Holding Current — 5 mA Maximum
• Passivated Surface for Reliability and Uniformity
G
A K

K
GA
CASE 29-04
(TO-226AA)
STYLE 10
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
*Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = 25 to 125°C) or
(RGK = 1000 ohms) 2N5060 VRRM 30
2N5061 60
2N5062 100
2N5064 200
On-State Current RMS IT(RMS) 0.8 Amp
(All Conduction Angles)
*Average On-State Current IT(AV) Amp
(TC = 67°C) 0.51
(TC = 102°C) 0.255
*Peak Non-repetitive Surge Current, TA = 25°C ITSM 10 Amps
(1/2 cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations I2t 0.4 A2s
(t = 8.3 ms)
*Peak Gate Power, TA = 25°C PGM 0.1 Watt
*Average Gate Power, TA = 25°C PG(AV) 0.01 Watt
*Peak Forward Gate Current, TA = 25°C IFGM 1 Amp
(300 µs, 120 PPS)
*Peak Reverse Gate Voltage VRGM 5 Volts
*Indicates JEDEC Registered Data. (cont.)
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1

2 Motorola Thyristor Device Data

 2N5060 2N5061 2N5062 2N5064
MAXIMUM RATINGS — continued
Rating Symbol Value Unit
*Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –65 to +125 °C
*Storage Temperature Range Tstg –65 to +150 °C
*Lead Solder Temperature — +230* °C
(Lead Length q1/16″ from case, 10 s Max)

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
*Thermal Resistance, Junction to Case(1) RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise noted.), (2)
Characteristic Symbol Min Typ Max Unit
*Peak Repetitive Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM) TC = 25°C – – 10 µA
TC = 125°C – – 50 µA
*Forward “On” Voltage(3) VTM – – 1.7 Volts
(ITM = 1.2 A peak @ TA = 25°C)
Gate Trigger Current (Continuous dc)(4) IGT µA
*(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = 25°C – – 200
TC = –65°C – – 350
Gate Trigger Voltage (Continuous dc) TC = 25°C VGT – 0.8 Volts
*(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –65°C – 1.2
(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C VGD 0.1 –
Holding Current TC = 25°C IH – – 5 mA
*(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –65°C – – 10
Turn-On Time µs
Delay Time td – 3 –
Rise Time tr – 0.2 –
(IGT = 1 mA, VD = Rated VDRM,
Forward Current = 1 A, di/dt = 6 A/µs
Turn-Off Time tq µs
(Forward Current = 1 A pulse,
Pulse Width = 50 µs,
0.1% Duty Cycle, di/dt = 6 A/µs,
dv/dt = 20 V/µs, IGT = 1 mA) 2N5060, 2N5061 – 10 –
2N5062, 5063, 5064 – 30 –
Forward Voltage Application Rate dv/dt – 30 – V/µs
(Rated VDRM, Exponential)
*Indicates JEDEC Registered Data.
1. This measurement is made with the case mounted “flat side down” on a heat sink and held in position by means of a metal clamp over the
curved surface.
2. For electrical characteristics for gate-to-cathode resistance other than 1000 ohms see Motorola Bulletin EB-30.
3. Forward current applied for 1 ms maximum duration, duty cycle p 1%.
4. RGK current is not included in measurement.

Motorola Thyristor Device Data 3

 2N5060 2N5061 2N5062 2N5064
CURRENT DERATING

FIGURE 1 – MAXIMUM CASE TEMPERATURE FIGURE 2 – MAXIMUM AMBIENT TEMPERATURE

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)

130 α 130
α = CONDUCTION ANGLE α

TA , MAXIMUM ALLOWABLE AMBIENT

120 α = CONDUCTION ANGLE
CASE MEASUREMENT
POINT – CENTER OF 110
110
FLAT PORTION

TEMPERATURE ( °C)
TYPICAL PRINTED
100 CIRCUIT BOARD
dc 90
MOUNTING
90

80 70 dc
α = 30° 120° 180°
60° 90°
70
50
60
α = 30° 60° 90° 120° 180°
50 30
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

FIGURE 3 – TYPICAL FORWARD VOLTAGE FIGURE 4 – MAXIMUM NON-REPETITIVE SURGE CURRENT

5.0 10
ITSM , PEAK SURGE CURRENT (AMP)

7.0
3.0
5.0
2.0 TJ = 125°C

25°C
3.0

1.0
i T , INSTANTANEOUS ON-STATE CURRENT (AMP)

2.0
0.7

0.5
1.0
1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
0.3 NUMBER OF CYCLES

0.2

FIGURE 5 – POWER DISSIPATION

0.8
180°
0.1 120°
P(AV), MAXIMUM AVERAGE POWER

α 90°
0.07 60°
0.6 α = CONDUCTION ANGLE
DISSIPATION (WATTS)

0.05 α = 30°

0.4
0.03 dc

0.02
0.2

0.01 0
0 0.5 1.0 1.5 2.0 2.5 0 0.1 0.2 0.3 0.4 0.5
vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

4 Motorola Thyristor Device Data

 2N5060 2N5061 2N5062 2N5064
FIGURE 6 – THERMAL RESPONSE
1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.5

0.2
NORMALIZED

0.1

0.05

0.02

0.01
0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20
t, TIME (SECONDS)

TYPICAL CHARACTERISTICS

FIGURE 7 – GATE TRIGGER VOLTAGE FIGURE 8 – GATE TRIGGER CURRENT

0.8 I GT , GATE TRIGGER CURRENT (NORMALIZED) 200
VAK = 7.0 V
VG , GATE TRIGGER VOLTAGE (VOLTS)

100 VAK = 7.0 V

RL = 100 RL = 100
0.7 RGK = 1.0 k 50
2N5062-64
20
0.6
10
5.0
0.5 2N5060-61
2.0

0.4 1.0
0.5
0.3 0.2
– 75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 9 – HOLDING CURRENT FIGURE 10 – CHARACTERISTICS AND SYMBOLS

4.0 TYPICAL V – I CHARACTERISTICS ON STATE
VAK = 7.0 V BLOCKING
I H , HOLDING CURRENT (NORMALIZED)

IH A+ STATE
3.0 RL = 100 VRRM
RGK = 1.0 k V i
–V +V
2.0 i V I
VDRM
A–
A
1.0 2N5060,61 LOAD

0.8 G 120V
2N5062-64 60 ~
0.6

0.4
–75 –50 –25 0 25 50 75 100 125
K
TJ, JUNCTION TEMPERATURE (°C)

Motorola Thyristor Device Data 5

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2N6027
Programmable 2N6028
Unijunction Transistors
Silicon Programmable Unijunction Transistors
PUTs
. . . designed to enable the engineer to ”program’’ unijunction characteristics such as 40 VOLTS
RBB, η, IV, and IP by merely selecting two resistor values. Application includes 300 mW
thyristor–trigger, oscillator, pulse and timing circuits. These devices may also be used
in special thyristor applications due to the availability of an anode gate. Supplied in an
inexpensive TO–92 plastic package for high–volume requirements, this package is
readily adaptable for use in automatic insertion equipment.
G
• Programmable — RBB, η, IV and IP.
• Low On–State Voltage — 1.5 Volts Maximum @ IF = 50 mA A K
• Low Gate to Anode Leakage Current — 10 nA Maximum
• High Peak Output Voltage — 11 Volts Typical
• Low Offset Voltage — 0.35 Volt Typical (RG = 10 k ohms)

A
G
K
CASE 29-04
(TO-226AA)
STYLE 16

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
*Power Dissipation PF 300 mW
Derate Above 25°C 1/θJA 4 mW/°C
*DC Forward Anode Current IT 150 mA
Derate Above 25°C 2.67 mA/°C
*DC Gate Current IG "50 mA
Repetitive Peak Forward Current ITRM Amps
100 µs Pulse Width, 1% Duty Cycle 1
*20 µs Pulse Width, 1% Duty Cycle 2

Non–repetitive Peak Forward Current ITSM 5 Amps

10 µs Pulse Width
*Gate to Cathode Forward Voltage VGKF 40 Volts
*Gate to Cathode Reverse Voltage VGKR –5 Volts
*Gate to Anode Reverse Voltage VGAR 40 Volts
*Anode to Cathode Voltage(1) VAK "40 Volts
Operating Junction Temperature Range TJ –50 to +100 °C
*Storage Temperature Range Tstg –55 to +150 °C
*Indicates JEDEC Registered Data
1. Anode positive, RGA = 1000 ohms
Anode negative, RGA = open

6 Motorola Thyristor Device Data

 2N6027 2N6028
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Fig. No. Symbol Min Typ Max Unit
*Peak Current 2,9,11 IP µA
(VS = 10 Vdc, RG = 1 MΩ) 2N6027 — 1.25 2
2N6028 — 0.08 0.15
(VS = 10 Vdc, RG = 10 k ohms) 2N6027 — 4 5
2N6028 — 0.70 1
*Offset Voltage 1 VT Volts
(VS = 10 Vdc, RG = 1 MΩ) 2N6027 0.2 0.70 1.6
2N6028 0.2 0.50 0.6
(VS = 10 Vdc, RG = 10 k ohms) (Both Types) 0.2 0.35 0.6
*Valley Current 1,4,5 IV µA
(VS = 10 Vdc, RG = 1 MΩ) 2N6027 — 18 50
2N6028 — 18 25
(VS = 10 Vdc, RG = 10 k ohms) 2N6027 70 150 —
2N6028 25 150 —
(VS = 10 Vdc, RG = 200 ohms) 2N6027 1.5 — — mA
2N6028 1 — —
*Gate to Anode Leakage Current — IGAO nAdc
(VS = 40 Vdc, TA = 25°C, Cathode Open) — 1 10
(VS = 40 Vdc, TA = 75°C, Cathode Open) — 3 —
Gate to Cathode Leakage Current — IGKS — 5 50 nAdc
(VS = 40 Vdc, Anode to Cathode Shorted)
*Forward Voltage (IF = 50 mA Peak) 1,6 VF — 0.8 1.5 Volts
*Peak Output Voltage 3,7 Vo 6 11 — Volt
(VG = 20 Vdc, CC = 0.2 µF)
Pulse Voltage Rise Time 3 tr — 40 80 ns
(VB = 20 Vdc, CC = 0.2 µF)
*Indicates JEDEC Registered Data.

FIGURE 1 – ELECTRICAL CHARACTERIZATION

+VB IA VA
IA A RG = R1 R2
R2 R1 + R2
G R1 + –VP
– VS = V VS
R1 + R2 B RG VT = VP – VS
VAK R1 VAK
VS
K
VF
VV
IA
IGAO IP IV IF
1A – Programmable Unijunction 1B – Equivalent Test Circuit for
with “Program” Resistors Figure 1A used for electrical IC – Electrical Characteristics
R1 and R2 characteristics testing
(also see Figure 2)

FIGURE 2 – PEAK CURRENT (IP) TEST CIRCUIT FIGURE 3 – Vo AND tr TEST CIRCUIT
+VB
–
Adjust 100k IP (SENSE) +V
for 1.0% 100 µV = 1.0 nA
Turn–on 510k Vo
+ 16k
Threshold
6V
2N5270
R
VB RG = R/2
0.01 µF VS = VB/2 CC vo 27k
Scope (See Figure 1) 20 Ω 0.6 V t
Put tf
20 Under
Test R

Motorola Thyristor Device Data 7

 2N6027 2N6028
TYPICAL VALLEY CURRENT BEHAVIOR
FIGURE 4 – EFFECT OF SUPPLY VOLTAGE FIGURE 5 – EFFECT OF TEMPERATURE

1000 500
IV, VALLEY CURRENT (µ A)

IV, VALLEY CURRENT (µ A)

RG = 10 kΩ
100 RG = 10 kΩ

100
100 kΩ
100 kΩ
1 MΩ
10 1 MΩ

10 5
5 10 15 20 –50 –25 0 +25 +50 +75 +100
VS, SUPPLY VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (°C)

FIGURE 6 – FORWARD VOLTAGE FIGURE 7 – PEAK OUTPUT VOLTAGE

10 25
TA = 25°C CC = 0.2 µF
TA = 25°C
V F, PEAK FORWARD VOLTAGE (VOLTS)

5.0
Vo, PEAK OUTPUT VOLTAGE (VOLTS) (SEE FIGURE 3)
2.0 20

1.0
15
0.5

0.2
10
0.1 1000 pF

0.05
5.0
0.02
0.01 0
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 0 5.0 10 15 20 25 30 35 40

IF, PEAK FORWARD CURRENT (AMP) VS, SUPPLY VOLTAGE (VOLTS)

FIGURE 8
PROGRAMMABLE UNIJUNCTION
+
B2
A
A E RT
R2 R2
P RBB = R1 + R2 A G
G G
N R1
η=
P R1 + R2
R1 R1
N CC
K
K K
B1
Equivalent Circuit Typical Application
Circuit Symbol
with External “Program”
Resistors R1 and R2

8 Motorola Thyristor Device Data

 2N6027 2N6028
TYPICAL PEAK CURRENT BEHAVIOR

2N6027

FIGURE 9 – EFFECT OF SUPPLY VOLTAGE AND RG FIGURE 10 – EFFECT OF TEMPERATURE AND RG

10 100
50
5.0
IP, PEAK CURRENT ( µA)

IP, PEAK CURRENT ( µA)

20 VS = 10 VOLTS
3.0
10 (SEE FIGURE 2)
2.0
5.0
1.0
RG = 10 kΩ 2.0
0.5 100 kΩ 1.0 RG = 10 kΩ
TA = 25°C
0.3 1.0 MΩ (SEE FIGURE 2) 0.5 100 kΩ
0.2 1.0 MΩ
0.2
0.1 0.1
5.0 10 15 20 –50 –25 0 +25 +50 +75 +100

VS, SUPPLY VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (°C)

2N6028

FIGURE 11 – EFFECT OF SUPPLY VOLTAGE AND RG FIGURE 12 – EFFECT OF TEMPERATURE AND RG

1.0 10
0.7 5.0
0.5
IP, PEAK CURRENT ( µA)

IP, PEAK CURRENT ( µA)

RG = 10 kΩ 2.0 VS = 10 VOLTS
0.3
100 kΩ 1.0 (SEE FIGURE 2)
0.2
0.5
0.1
0.07 0.2 RG = 10 kΩ
0.05 0.1
1.0 MΩ
0.03 TA = 25°C 100 kΩ
0.05
0.02 (SEE FIGURE 2)
0.02 1.0 MΩ

0.01 0.01
5.0 10 15 20 –50 –25 0 +25 +50 +75 +100

VS, SUPPLY VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (°C)

Motorola Thyristor Device Data 9

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2N6071,A,B*
Sensitive Gate Triacs 2N6073,A,B*
Silicon Bidirectional Thyristors 2N6075,A,B*
*Motorola preferred devices

. . . designed primarily for full-wave ac control applications, such as light dimmers,

motor controls, heating controls and power supplies; or wherever full-wave silicon
gate controlled solid-state devices are needed. Triac type thyristors switch from a TRIACs
blocking to a conducting state for either polarity of applied anode voltage with positive 4 AMPERES RMS
or negative gate triggering. 200 thru 600 VOLTS
• Sensitive Gate Triggering (A and B versions) Uniquely Compatible for Direct
Coupling to TTL, HTL, CMOS and Operational Amplifier Integrated Circuit Logic
Functions
• Gate Triggering 2 Mode — 2N6071, 2N6073, 2N6075
4 Mode — 2N6071,A,B, 2N6073,A,B, 2N6075,A,B MT1
• Blocking Voltages to 600 Volts MT2 G
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat
Dissipation and Durability MT2

CASE 77-08
G
(TO-225AA)
MT2 MT1 STYLE 5

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
*Peak Repetitive Off-State Voltage(1) VDRM Volts
(Gate Open, TJ = 25 to 110°C) 2N6071,A,B 200
2N6073,A,B 400
2N6075,A,B 600
*On-State Current RMS (TC = 85°C) IT(RMS) 4 Amps
*Peak Surge Current ITSM 30 Amps
(One Full cycle, 60 Hz, TJ = –40 to +110°C)
Circuit Fusing Considerations I2t 3.7 A2s
(t = 8.3 ms)
*Peak Gate Power PGM 10 Watts
*Average Gate Power PG(AV) 0.5 Watt
*Peak Gate Voltage VGM 5 Volts
*Indicates JEDEC Registered Data.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

10 Motorola Thyristor Device Data

 2N6071,A,B 2N6073,A,B 2N6075,A,B

MAXIMUM RATINGS
Rating Symbol Value Unit
*Operating Junction Temperature Range TJ –40 to +110 °C
*Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque (6-32 Screw)(1) — 8 in. lb.
*Indicates JEDEC Registered Data.
1. Torque rating applies with use of compression washer (B52200F006). Mounting torque in excess of 6 in. lb. does not appreciably lower
case-to-sink thermal resistance. Main terminal 2 and heatsink contact pad are common.
For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C, for 10 seconds.
Consult factory for lead bending options.

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
*Thermal Resistance, Junction to Case RθJC 3.5 °C/W
Thermal Resistance, Junction to Ambient RθJA 75 °C/W
*Indicates JEDEC Registered Data.

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit
*Peak Blocking Current IDRM
(VD = Rated VDRM, gate open, TJ = 25°C) — — 10 µA
(TJ = 110°C) — — 2 mA
*On-State Voltage (Either Direction) VTM — — 2 Volts
(ITM = 6 A Peak)
*Peak Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms, TJ = –40°C)
MT2(+), G(+); MT2(–), G(–) All Types — 1.4 2.5
MT2(+), G(–); MT2(–), G(+) 2N6071,A,B, 2N6073,A,B 2N6075,A,B — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 k ohms,
TJ = 110°C)
MT2(+), G(+); MT2(–), G(–) All Types 0.2 — —
MT2(+), G(–); MT2(–), G(+) 2N6071,A,B, 2N6073,A,B, 2N6075,A,B 0.2 — —
*Holding Current (Either Direction) IH mA
(Main Terminal Voltage = 12 Vdc, Gate Open, TJ = –40°C)
(Initiating Current = 1 Adc) 2N6071, 2N6073, 2N6075, — — 70
2N6071A,B, 2N6073A,B, 2N6075A,B — — 30
(TJ = 25°C) 2N6071, 2N6073, 2N6075 — — 30
2N6071A,B, 2N6073A,B, 2N6075A,B — — 15
Turn-On Time (Either Direction) ton — 1.5 — µs
(ITM = 14 Adc, IGT = 100 mAdc)
Blocking Voltage Application Rate at Commutation dv/dt(c) — 5 — V/µs
@ VDRM, TJ = 85°C, Gate Open, ITM = 5.7 A,
Commutating di/dt = 2.0 A/ms
*Indicates JEDEC Registered Data.

Motorola Thyristor Device Data 11

2N6071,A,B 2N6073,A,B 2N6075,A,B

QUADRANT
(See Definition Below)
IGT I II III IV
Type
@ TJ mA mA mA mA

Gate Trigger Current (Continuous dc) 2N6071 +25°C 30 — 30 —

(Main Terminal Voltage = 12 Vdc
Vdc, RL = 100 ohms) 2N6073
2N6075 –40°C 60 — 60 —

2N6071A +25°C 5 5 5 10
Maximum Value 2N6073A
2N6075A –40°C 20 20 20 30

2N6071B +25°C 3 3 3 5
2N6073B
2N6075B –40°C 15 15 15 20

*Indicates JEDEC Registered Data.

SAMPLE APPLICATION:
TTL-SENSITIVE GATE 4 AMPERE TRIAC
TRIGGERS IN MODES II AND III

14
0V
MC7400 LOAD
4 510 2N6071A
–VEE 7 Ω 115 VAC
VEE = 5.0 V 60 Hz
+

QUADRANT DEFINITIONS Trigger devices are recommended for gating on Triacs. They provide:
MT2(+) 1. Consistent predictable turn-on points.
QUADRANT II QUADRANT I 2. Simplified circuitry.
3. Fast turn-on time for cooler, more efficient and reliable operation.
For 2N6071, 2N6073, 2N6075
MT2(+), G(–) MT2(+), G(+) ELECTRICAL CHARACTERISTICS of RECOMMENDED
BIDIRECTIONAL SWITCHES

Usage General Lamp Dimmer

G(–) G(+) Part Number MBS4991 MBS4993 MBS100

QUADRANT III QUADRANT IV VS 6.0 – 10 V 7.5 – 9.0 V 3.0 – 5.0 V
IS 350 µA Max 250 µA Max 100 – 400 µA

VS1 – VS2 0.5 V Max 0.2 V Max 0.35 V Max

MT2(–), G(–) MT2(–), G(+)
Temperature
0.02%/°C Typ
MT2(–) Coefficient

SENSITIVE GATE LOGIC REFERENCE

Firing Quadrant
IC Logic
g
Functions I II III IV

TTL 2N6071A 2N6071A

Series Series

HTL 2N6071A 2N6071A

Series Series

CMOS (NAND) 2N6071B 2N6071B

Series Series

CMOS (Buffer) 2N6071B 2N6071B

Series Series

Operational 2N6071A 2N6071A

Amplifier Series Series

Zero Voltage 2N6071A 2N6071A

Switch Series Series

12 Motorola Thyristor Device Data

 2N6071,A,B 2N6073,A,B 2N6075,A,B

FIGURE 1 – AVERAGE CURRENT DERATING FIGURE 2 – RMS CURRENT DERATING

110 110
α = 30°
60°
TC , CASE TEMPERATURE (° C)

TC , CASE TEMPERATURE (° C)
90°
100 100

α = 30°
60°
90 90° 120°
90
120°
180° 180°
dc
α α dc
80 80
α α

α = CONDUCTION ANGLE α = CONDUCTION ANGLE

70 70
0 1.0 2.0 3.0 4.0 0 1.0 2.0 3.0 4.0
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

FIGURE 3 – POWER DISSIPATION FIGURE 4 – POWER DISSIPATION

8.0 8.0
α α dc
P(AV) , AVERAGE POWER (WATTS)

P(AV) , AVERAGE POWER (WATTS)

180°
α α
6.0 120° dc 6.0
α = 180°
α = CONDUCTION ANGLE 90° α = CONDUCTION ANGLE
60° 120°
4.0 4.0
α = 30°

30°
2.0 2.0 60°
90°

0 0
0 1.0 2.0 3.0 4.0 0 1.0 2.0 3.0 4.0
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

FIGURE 5 – TYPICAL GATE-TRIGGER VOLTAGE FIGURE 6 – TYPICAL GATE-TRIGGER CURRENT

VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)

I GTM , GATE TRIGGER CURRENT (NORMALIZED)

3.0 3.0
OFF-STATE VOLTAGE = 12 Vdc OFF-STATE VOLTAGE = 12 Vdc
ALL MODES ALL MODES
2.0 2.0

1.0 1.0

0.7 0.7

0.5 0.5

0.3 0.3
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Motorola Thyristor Device Data 13

 2N6071,A,B 2N6073,A,B 2N6075,A,B

FIGURE 7 – MAXIMUM ON-STATE CHARACTERISTICS FIGURE 8 – TYPICAL HOLDING CURRENT

40
3.0
GATE OPEN

IH, HOLDING CURRENT (NORMALIZED)

30 APPLIES TO EITHER DIRECTION
2.0

20

1.0
10
0.7
7.0
0.5
ITM , ON-STATE CURRENT (AMP)

5.0

0.3
TJ = 110°C –60 –40 –20 0 20 40 60 80 100 120 140
3.0
TJ, JUNCTION TEMPERATURE (°C)

2.0

TJ = 25°C FIGURE 9 – MAXIMUM ALLOWABLE SURGE CURRENT

1.0 34
32
0.7
PEAK SINEWAVE CURRENT (AMP)
30

0.5 28
26
24
0.3
TJ = –40 to +110°C
22
f = 60 Hz
0.2 20
18
16
0.1 14
0 1.0 2.0 3.0 4.0 5.0 1.0 2.0 3.0 4.0 5.0 7.0 10

VTM, ON-STATE VOLTAGE (VOLTS) NUMBER OF FULL CYCLES

FIGURE 10 – THERMAL RESPONSE

Z θJC(t), TRANSIENT THERMAL IMPEDANCE (°C/W)

10

5.0
MAXIMUM
3.0
2.0
TYPICAL
1.0

0.5
0.3
0.2

0.1
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k

t, TIME (ms)

14 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2N6237
thru
Silicon Controlled Rectifiers 2N6241
Reverse Blocking Triode Thyristors
. . . PNPN devices designed for high volume consumer applications such as
temperature, light, and speed control; process and remote control, and warning SCRs
systems where reliability of operation is important. 4 AMPERES RMS
• Passivated Surface for Reliability and Uniformity 50 thru 600 VOLTS
• Power Rated at Economical Prices
• Practical Level Triggering and Holding Characteristics
• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat A
Dissipation and Durability
• Recommended Electrical Replacement for C106

G CASE 77-08
A K G (TO-225AA)
A
K STYLE 2

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
*Repetitive Peak Forward and Reverse Blocking Voltage(1) VDRM Volts
(1/2 Sine Wave) 2N6237 or 50
(RGK = 1000 ohms, TC = –40 to +110°C) 2N6238 VRRM 100
2N6239 200
2N6240 400
2N6241 600
*Non–repetitive Peak Reverse Blocking Voltage VRSM Volts
(1/2 Sine Wave, RGK = 1000 ohms, 2N6237 100
TC = –40° to +110°C) 2N6238 150
2N6239 250
2N6240 450
2N6241 650
*Average On–State Current IT(AV) Amps
(TC = –40 to + 90°C) 2.6
(TC = +100°C) 1.6
*Surge On–State Current ITSM Amps
(1/2 Sine Wave, 60 Hz, TC = +90°C) 25
(1/2 Sine Wave, 1.5 ms, TC = +90°C) 35
Circuit Fusing I2t 2.6 A2s
(t = 8.3 ms)
*Peak Gate Power PGM 0.5 Watts
(Pulse Width = 10 µs, TC = 90°C)
*Indicates JEDEC Registered Data. (continued)
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 15

2N6237 thru 2N6241
MAXIMUM RATINGS — continued (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
*Average Gate Power PG(AV) 0.1 Watt
(t = 8.3 ms, TC = 90°C)
Peak Forward Gate Current IGM 0.2 Amp
Peak Reverse Gate Voltage VRGM 6 Volts
*Operating Junction Temperature Range TJ –40 to +110 °C
*Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque(1)  6 in. lb.
THERMAL CHARACTERISTICS
Characteristic Symbol Min Max Unit
*Thermal Resistance, Junction to Case RθJC — 3 °C/W
Thermal Resistance, Junction to Ambient RθJA — 75 °C/W
*Indicates JEDEC Registered Data.
ELECTRICAL CHARACTERISTICS (TC = 25°C and RGK = 1000 ohms unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
* Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM) TC = 25°C — — 10 µA
TC = 110°C — — 200 µA
*Peak Forward “On” Voltage VTM — — 2.2 Volts
(ITM = 8.2 A Peak, Pulse Width = 1 to 2 ms, 2% Duty Cycle)
Gate Trigger Current (Continuous dc)(2) IGT µA
(VAK = 12 Vdc, RL = 24 Ohms) — — 200
*(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C) — — 500
Gate Trigger Voltage (Continuous dc) VGT — — 1 Volts
(Source Voltage = 12 V, RS = 50 Ohms)
*(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C)
Gate Non–Trigger Voltage VGD 0.2 — — Volts
(VAK = Rated VDRM, RL = 100 Ohms, TC = 110°C)
Holding Current IH mA
(VAK = 12 Vdc, IGT = 2 mA) TC = 25°C — — 5
*(Initiating On–State Current = 200 mA) TC = –40°C — — 10
*Total Turn–On Time tgt — 2 — µs
(Source Voltage = 12 V, RS = 6 k Ohms)
(ITM = 8.2 A, IGT = 2 mA, Rated VDRM)
(Rise Time = 20 ns, Pulse Width = 10 µs)
Forward Voltage Application Rate dv/dt — 10 — V/µs
(VD = Rated VDRM, TC = 110°C)
*Indicates JEDEC Registered Data.
1. Torque rating applies with use of compression washer (B52200F006 or equivalent). Mounting torque in excess of 6 in. lb. does not appreciably
lower case-to-sink thermal resistance. Anode lead and heatsink contact pad are common. (See AN–209 B)
For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C. For optimum
results an activated flux (oxide removing) is recommended.
2. Measurement does not include RGK current.

16 Motorola Thyristor Device Data

 2N6237 thru 2N6241
FIGURE 1 – MAXIMUM CASE TEMPERATURE FIGURE 2 – MAXIMUM AMBIENT TEMPERATURE
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)
110 110

TA, MAXIMUM ALLOWABLE AMBIENT

106

90
102 π
0

TEMPERATURE ( °C)
α
98 f = 60 Hz 0 π
70 α
94 f = 60 Hz

90
α = 30° 60° 90° 120° 180° dc 50
86
α = 30° 60° 90° 180° dc
82 30
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
IT(AV), AVERAGE FORWARD CURRENT (AMP) IT(AV), AVERAGE FORWARD CURRENT (AMP)

Motorola Thyristor Device Data 17

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2N6342
Triacs thru
Silicon Bidirectional Triode Thyristors 2N6349
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies; or wherever full–wave silicon
TRIACs
gate controlled solid–state devices are needed. Triac type thyristors switch from a
8 AMPERES RMS
blocking to a conducting state for either polarity of applied anode voltage with positive
200 thru 800 VOLTS
or negative gate triggering.
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability MT1
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
MT2
Dissipation and Durability
• Gate Triggering Guaranteed in Two Modes (2N6342, 2N6343, 2N6344, 2N6345) G
or Four Modes (2N6346, 2N6347, 2N6348, 2N6349)
• For 400 Hz Operation, Consult Factory
• 12 Ampere Devices Available as 2N6342A thru 2N6349A

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
* Peak Repetitive Off–State Voltage(1) VDRM Volts
(Gate Open, TJ = –40 to +110°C)
1/2 Sine Wave 50 to 60 Hz, Gate Open 2N6342, 2N6346 200
2N6343, 2N6347 400
2N6344, 2N6348 600
2N6345, 2N6349 800
*RMS On–State Current (TC = +80°C) IT(RMS) 8 Amps
Full Cycle Sine Wave 50 to 60 Hz (TC = +90°C) 4
*Peak Non-repetitive Surge Current ITSM 100 Amps
(One Full Cycle, 60 Hz, TC = +80°C)
Preceded and followed by Rated Current
Circuit Fusing I2t 40 A2s
(t = 8.3 ms)
*Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 20 Watts
*Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt
*Peak Gate Current IGM 2 Amps
*Peak Gate Voltage VGM 10 Volts
*Operating Junction Temperature Range TJ –40 to +125 °C
*Storage Temperature Range Tstg –40 to +150 °C
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

REV 1

18 Motorola Thyristor Device Data

 2N6342 thru 2N6349
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
*Thermal Resistance, Junction to Case RθJC 2.2 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, and Either Polarity of MT2 to MT1 Voltage, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
* Peak Blocking Current IDRM
(VD = Rated VDRM, gate open) TJ = 25°C — — 10 µA
TJ = 100°C — — 2 mA
* Peak On–State Voltage VTM — 1.3 1.55 Volts
(ITM = 11 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 100 Ohms)
(Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) All Types — 12 50
MT2(+), G(–) 2N6346 thru 49 — 12 75
MT2(–), G(–) All Types — 20 50
MT2(–), G(+) 2N6346 thru 49 — 35 75
*MT2(+), G(+); MT2(–), G(–) TC = –40°C All Types — — 100
*MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346 thru 49 — — 125
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 Vdc, RL = 100 Ohms)
(Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) All Types — 0.9 2
MT2(+), G(–) 2N6346 thru 49 — 0.9 2.5
MT2(–), G(–) All Types — 1.1 2
MT2(–), G(+) 2N6346 thru 49 — 1.4 2.5
*MT2(+), G(+); MT2(–), G(–) TC = –40°C All Types — — 2.5
*MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346 thru 49 — — 3
(VD = Rated VDRM, RL = 10 k Ohms, TJ = 100°C)
*MT2(+), G(+); MT2(–), G(–) All Types 0.2 — —
*MT2(+), G(–); MT2(–), G(–) 2N6346 thru 49 0.2 — —
* Holding Current IH mA
(VD = 12 Vdc, Gate Open) TC = 25°C — 6 40
(IT = 200 mA) *TC = –40°C — — 75
* Turn-On Time tgt — 1.5 2 µs
(VD = Rated VDRM, ITM = 11 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11 A, Commutating di/dt = 4.0 A/ms,
Gate Unenergized, TC = 80°C)
*Indicates JEDEC Registered Data.

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON-STATE POWER DISSIPATION

100 10
dc
α = 30° α α = 180°
PAV , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE ( °C)

96 60° 8.0 120°

α
90° 90°
α = CONDUCTION ANGLE
92 120°
180°
6.0
[
TJ 100°C
30°
60°

88 α 4.0
α
84 2.0
α = CONDUCTION ANGLE dc

80 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
IT(RMS), RMS ON-STATE CURRENT, (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 19

 2N6342 thru 2N6349
FIGURE 3 – TYPICAL GATE TRIGGER VOLTAGE FIGURE 4 – TYPICAL GATE TRIGGER CURRENT
1.8 50
Vgt , GATE TRIGGER VOLTAGE (VOLTS)

OFF-STATE VOLTAGE = 12 V OFF-STATE VOLTAGE = 12 V

I GT , GATE TRIGGER CURRENT (mA)

1.6
30
1.4
QUADRANT 4 20
1.2

1.0
1
0.8 1 10 2
QUADRANT
QUADRANTS 2 3
0.6 7.0 4
3
0.4 5.0
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 – ON-STATE CHARACTERISTICS FIGURE 6 – TYPICAL HOLDING CURRENT

100 20
GATE OPEN
70
MAIN TERMINAL #1

I H , HOLDING CURRENT (mA)

50 POSITIVE
10

30 7.0

20 5.0
MAIN TERMINAL #2
i TM , INSTANTANEOUS ON-STATE CURRENT (AMP)

POSITIVE
TJ = 100°C 25°C
10 3.0

7.0 2.0
–60 –40 –20 0 20 40 60 80 100 120 140
5.0
TJ, JUNCTION TEMPERATURE (°C)

3.0

2.0 FIGURE 7 – MAXIMUM NON-REPETITIVE SURGE CURRENT

100
I TSM , PEAK SURGE CURRENT (AMP)

1.0 80
0.7

0.5 60

0.3 40 CYCLE

0.2 TJ = 100°C
20 f = 60 Hz
Surge is preceded and followed by rated current
0.1 0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 1.0 2.0 3.0 5.0 7.0 10
vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) NUMBER OF CYCLES

20 Motorola Thyristor Device Data

 2N6342 thru 2N6349
FIGURE 8 – TYPICAL THERMAL RESPONSE
1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.5

0.2
(NORMALIZED)

ZθJC(t) = r(t) • RθJC

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1.0 2.0 5.0 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
t,TIME (ms)

Motorola Thyristor Device Data 21

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triacs 2N6346A
Silicon Bidirectional Triode Thyristors
thru
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies; or wherever full-wave silicon 2N6349A
gate controlled solid-state devices are needed. Triac type thyristors switch from a
blocking to a conducting state for either polarity of applied anode voltage with positive
or negative gate triggering. TRIACs
• Blocking Voltage to 800 Volts 12 AMPERES RMS
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity 200 thru 800 VOLTS
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Gate Triggering Guaranteed in Four Modes (2N6346A, 2N6347A, 2N6348A, MT1
2N6349A) MT2
• For 400 Hz Operation, Consult Factory
G
• 8 Ampere Devices Available as 2N6342 thru 2N6349

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
*Peak Repetitive Off-State Voltage(1) VDRM Volts
(Gate Open, TJ = –40 to +110°C
1/2 Sine Wave 50 to 60 Hz, Gate Open
2N6346A 200
2N6347A 400
2N6348A 600
2N6349A 800
*RMS On-State Current (TC = +80°C) IT(RMS) 12 Amps
(Full Cycle Sine Wave 50 to 60 Hz) (TC = +95°C) 6
*Peak Non-repetitive Surge Current ITSM 120 Amps
(One Full Cycle, 60 Hz, TC = +80°C)
Preceded and Followed by Rated Current
Circuit Fusing (t = 8.3 ms) I2t 59 A2s
*Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 20 Watts
*Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt
*Peak Gate Current IGM 2 Amps
*Peak Gate Voltage VGM ±10 Volts
*Operating Junction Temperature Range TJ –40 to +125 °C
*Storage Temperature Range Tstg –40 to +150 °C
*Indicates JEDEC Registered Data.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

22 Motorola Thyristor Device Data

 2N6346A thru 2N6349A
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
*Thermal Resistance, Junction to Case RθJC 2 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
*Peak Blocking Current IDRM
(VD = Rated VDRM, gate open) TJ = 25°C — — 10 µA
TJ = 110°C — — 2 mA
*Peak On-State Voltage (Either Direction) VTM — 1.3 1.75 Volts
(ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 6 50
MT2(+), G(–) 2N6346A thru 2N6349A — 6 75
MT2(–), G(–) — 10 50
MT2(–), G(+) 2N6346A thru 2N6349A — 25 75
*MT2(+), G(+); MT2(–), G(–) TC = –40°C — — 100
*MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346A thru 2N6349A — — 125
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 Vdc, RL = 100 ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) 2N6346A thru 2N6349A — 0.9 2.5
MT2(–), G(–) — 1.1 2
MT2(–), G(+) 2N6346A thru 2N6349A — 1.4 2.5
*MT2(+), G(+); MT2(–), G(–) TC = –40°C — — 2.5
*MT2(+), G(–); MT2(–), G(+) TC = –40°C 2N6346A thru 2N6349A — — 3
(VD = Rated VDRM, RL = 10 k ohms, TJ = 100°C)
*MT2(+), G(+); MT2(–), G(–) 0.2 — —
*MT2(+), G(–); MT2(–), G(–) 2N6346A thru 2N6349A 0.2 — —
Holding Current (Either Direction) IH mA
(VD = 12 Vdc, Gate Open) TC = 25°C — 6 40
(IT = 200 mA) *TC = –40°C — — 75
*Turn-On Time tgt — 1.5 2 µs
(VD = Rated VDRM, ITM = 17 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms,
Gate Unenergized, TC = 80°C)
*Indicates JEDEC Registered Data.

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON-STATE POWER DISSIPATION

110 20
30° dc
PAV , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE ( °C)

60° 16 α
100
90°
α
120° 12
180° α = CONDUCTION ANGLE
90
TJ = 110°C 180°
α 8.0
120°
α 90°
80 60°
4.0
α = CONDUCTION ANGLE α = 30°
dc
70 0
0 2.0 4.0 6.0 8.0 10 12 14 0 2.0 4.0 6.0 8.0 10 12 14
IT(RMS), RMS ON-STATE CURRENT, (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 23

 2N6346A thru 2N6349A
FIGURE 3 – TYPICAL GATE TRIGGER VOLTAGE FIGURE 4 – TYPICAL GATE TRIGGER CURRENT
1.8 50
Vgt , GATE TRIGGER VOLTAGE (VOLTS)

OFF-STATE VOLTAGE = 12 V OFF-STATE VOLTAGE = 12 V

I GT , GATE TRIGGER CURRENT (mA)

1.6
30
1.4
QUADRANT 4 20
1.2

1.0
1
0.8 1 10 2
QUADRANT
QUADRANTS 2 3
0.6 7.0 4
3
0.4 5.0
–60 –40 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
–20
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 – ON-STATE CHARACTERISTICS FIGURE 6 – TYPICAL HOLDING CURRENT

100 20
GATE OPEN
70
MAIN TERMINAL #1

I H , HOLDING CURRENT (mA)

50 POSITIVE
10

30 7.0

20 5.0
MAIN TERMINAL #2
i TM , INSTANTANEOUS ON-STATE CURRENT (AMP)

POSITIVE
TJ = 100°C 25°C
10 3.0

7.0 2.0
–60 –40 –20 0 20 40 60 80 100 120 140
5.0
TJ, JUNCTION TEMPERATURE (°C)

3.0

2.0 FIGURE 7 – MAXIMUM NON-REPETITIVE SURGE CURRENT

100
I TSM , PEAK SURGE CURRENT (AMP)

1.0 80
0.7

0.5 60

0.3 40 CYCLE

0.2 TJ = 100°C
20 f = 60 Hz
Surge is preceded and followed by rated current
0.1 0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 1.0 2.0 3.0 5.0 7.0 10
vTM, MAXIMUM INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) NUMBER OF CYCLES

24 Motorola Thyristor Device Data

 2N6346A thru 2N6349A
FIGURE 8 – TYPICAL THERMAL RESPONSE
1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.5

0.2
(NORMALIZED)

ZθJC(t) = r(t) • RθJC

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1.0 2.0 5.0 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
t,TIME (ms)

Motorola Thyristor Device Data 25

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

2N6504
thru
Thyristors 2N6509*
Silicon Controlled Rectifiers *Motorola preferred devices

. . . designed primarily for half-wave ac control applications, such as motor controls,

heating controls and power supply crowbar circuits. SCRs
• Glass Passivated Junctions with Center Gate Fire for Greater Parameter 25 AMPERES RMS
Uniformity and Stability 50 thru 800 VOLTS
• Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High Heat
Dissipation and Durability
• Blocking Voltage to 800 Volts
G
• 300 A Surge Current Capability
A K

CASE 221A-04
(TO-220AB)
STYLE 3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
* Peak Forward and Reverse Blocking Voltage(1) VDRM, VRRM Volts
(Gate Open, TJ = 25 to 125°C) 2N6504 50
2N6505 100
2N6506 200
2N6507 400
2N6508 600
2N6509 800
Forward Current (TC = 85°C) IT(RMS) 25 Amps
(180° Conduction Angle) IT(AV) 16
Peak Non-repetitive Surge Current — 8.3 ms ITSM 300 Amps
(1/2 Cycle, Sine Wave) 1.5 ms 350
Forward Peak Gate Power PGM 20 Watts
Forward Average Gate Power PG(AV) 0.5 Watt
Forward Peak Gate Current IGM 2 Amps
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
*THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.5 °C/W
*Indicates JEDEC Registered Data.
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1

26 Motorola Thyristor Device Data

 2N6504 thru 2N6509
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
* Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
* Forward “On” Voltage(1) VTM — — 1.8 Volts
(ITM = 50 A)
* Gate Trigger Current (Continuous dc) TC = 25°C IGT — — 40 mA
(Anode Voltage = 12 Vdc, RL = 100 Ohms) TC = –40°C — 25 75
* Gate Trigger Voltage (Continuous dc) VGT — 1 1.5 Volts
(Anode Voltage = 12 Vdc, RL = 100 Ohms, TC = –40°C)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(Anode Voltage = Rated VDRM, RL = 100 Ohms, TJ = 125°C)
* Holding Current IH — 35 40 mA
(Anode Voltage = 12 Vdc, TC = –40°C)
* Turn-On Time tgt — 1.5 2 µs
(ITM = 25 A, IGT = 50 mAdc)
Turn-Off Time (VDRM = rated voltage) tq µs
(ITM = 25 A, IR = 25 A) — 15 —
(ITM = 25 A, IR = 25 A, TJ = 125°C) — 35 —
Critical Rate of Rise of Off-State Voltage dv/dt — 50 — V/µs
(Gate Open, Rated VDRM, Exponential Waveform)
*Indicates JEDEC Registered Data.
1. Pulse Test: Pulse Width p 300 µs, Duty Cycle p 2%.

FIGURE 1 — AVERAGE CURRENT DERATING FIGURE 2 — MAXIMUM ON-STATE POWER DISSIPATION

TC, MAXIMUM CASE TEMPERATURE ( °C)

130 32
P(AV) , AVERAGE POWER (WATTS)

180°
120 α 24 α
α = CONDUCTION ANGLE α = CONDUCTION ANGLE 60° 90° dc
110 α = 30°
16
100
TJ = 125°C
α = 30° 60° 90° 180° dc 8.0
90

80 0
0 4.0 8.0 12 16 20 0 4.0 8.0 12 16 20
IT(AV), ON-STATE FORWARD CURRENT (AMPS) IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)

Motorola Thyristor Device Data 27

 2N6504 thru 2N6509

FIGURE 3 — MAXIMUM FORWARD VOLTAGE FIGURE 4 — MAXIMUM NON-REPETITIVE SURGE CURRENT

100 300
1 CYCLE

I TSM , PEAK SURGE CURRENT (AMP)

70
275
50

30 250
125°C
20 225
TC = 85°C
i F , INSTANTANEOUS FORWARD CURRENT (AMPS)

25°C f = 60 Hz
10 200
SURGE IS PRECEDED AND
7.0 FOLLOWED BY RATED CURRENT
175
5.0 1.0 2.0 3.0 4.0 6.0 8.0 10
NUMBER OF CYCLES

3.0

FIGURE 5 — CHARACTERISTICS AND SYMBOLS

2.0

+I
1.0

0.7
IT FORWARD
0.5 REVERSE BREAKOVER
BLOCKING VT POINT
REGION IH
0.3 IDRM
–V +V
0.2 IRRM VDRM
VRRM
FORWARD
BLOCKING
REVERSE
0.1 –I REGION
AVALANCHE
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 REGION
vF, INSTANTANEOUS VOLTAGE (VOLTS)

FIGURE 6 — THERMAL RESPONSE

1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.7
0.5
0.3
(NORMALIZED)

0.2
ZθJC(t) = RθJC • r(t)
0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1.0 k 2.0 k 3.0 k 5.0 k 10 k
t, TIME (ms)

28 Motorola Thyristor Device Data

 2N6504 thru 2N6509

TYPICAL TRIGGER CHARACTERISTICS

FIGURE 7 — GATE TRIGGER CURRENT FIGURE 8 — GATE TRIGGER VOLTAGE

50 1.1
40

VGT , GATE TRIGGER VOLTAGE (VOLTS)

IGT , GATE TRIGGER CURRENT (mA)

OFF-STATE VOLTAGE = 12 V 1.0 OFF-STATE VOLTAGE = 12 V

30
0.9
20
0.8

0.7

10 0.6

7.0 0.5

5.0 0.4
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 9 — HOLDING CURRENT

50
40
I H, HOLDING CURRENT (mA)

30

20

10

7.0

5.0
–60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)

Motorola Thyristor Device Data 29

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

BRX44 *
Silicon Controlled Rectifiers thru
BRX47 *
PNPN devices designed for high volume, line–powered consumer applications such
as relay and lamp drivers, small motor controls, gate drivers for large thyristors, and
BRX49 *
sensing and detection circuits. Supplied in an inexpensive TO–226AA (TO–92)
package which is readily adaptable for use in automatic insertion equipment.
SCRs
• Sensitive Gate Trigger Current — 200 µA Maximum
0.8 AMPERE RMS
• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 125°C
30 TO 400 VOLTS
• Low Holding Current — 5 mA Maximum
• Glass–Passivated Surface for Reliability and Uniformity

CASE 29-04
(TO-226AA)
STYLE 3
WITH TO–18 LEADFORM*

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage BRX44 VDRM, VRRM 30 Volts
(TJ = 25 to 125°C, RGK = 1000 Ω) BRX45 60
BRX46 100
BRX47 200
BRX49 400
Forward Current RMS IT(RMS) 0.8 Amp
(All Conduction Angles)
Peak Forward Surge Current, TA = 25°C ITSM 8 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations, TA = 25°C I2t 0.15 A2s
(t = 8.3 ms)
Peak Gate Power — Forward, TA = 25°C PGM 0.1 Watt
Peak Gate Current Forward, TA = 25°C IGFM 1 Amp
(300 µs, 120 PPS)
Peak Gate Voltage — Reverse VGRM 5 Volts
Operating Junction Temperature Range @ Rated TJ –40 to +125 °C
VRRM and VDRM
Storage Temperature Range Tstg –40 to +150 °C
Lead Solder Temperature +230 °C
t
( 1.5 mm from case, 10 s max.)
*European part numbers only. Package is Case 29 with Leadform 18.
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

30 Motorola Thyristor Device Data

 BRX44 thru BRX47 BRX49
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise noted.)
Characteristic Symbol Min Max Unit
Peak Forward Blocking Current IDRM — 100 µA
(VD = Rated VDRM @ TC = 125°C)
Peak Reverse Blocking Current IRRM — 100 µA
(VR = Rated VRRM @ TC = 125°C)
Forward “On’’ Voltage(1) VTM — 1.7 Volts
(ITM = 1 A Peak @ TA = 25°C)
Gate Trigger Current (Continuous dc)(2) TC = 25°C IGT — 200 µA
(Anode Voltage = 7 Vdc, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) TC = 25°C VGT — 0.8 Volts
(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –40°C — 1.2
(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C 0.1 —
Holding Current TC = 25°C IH — 5 mA
(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –40°C — 10
1. Forward current applied for 1 ms maximum duration, duty cycle v1%.
2. RGK current is not included in measurement.

FIGURE 1 – CURRENT DERATING FIGURE 2 – CURRENT DERATING

(REFERENCE: CASE TEMPERATURE) (REFERENCE: AMBIENT TEMPERATURE)
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

130 130
α = CONDUCTION ANGLE α α
TC, MAXIMUM ALLOWABLE AMBIENT

120
α = CONDUCTION ANGLE
110
110 CASE MEASUREMENT TYPICAL PRINTED
POINT – CENTER OF CIRCUIT BOARD
TEMPERATURE ( °C)

FLAT PORTION MOUNTING

100 90
dc
90
70
80
α = 30 60
180
90 120
70
50
60 α = 30
60 90 120 180
50 30
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 31

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

BRY55-30*
Silicon Controlled Rectifiers thru 600*
PNPN devices designed for high volume, line–powered consumer applications such
as relay and lamp drivers, small motor controls, gate drivers for large thyristors, and
sensing and detection circuits. Supplied in an inexpensive TO–226AA (TO–92)
package which is readily adaptable for use in automatic insertion equipment. SCRs
0.8 AMPERE RMS
• Sensitive Gate Trigger Current — 200 µA Maximum 30 TO 600 VOLTS
• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 125°C
• Low Holding Current — 5 mA Maximum
• Glass–Passivated Surface for Reliability and Uniformity

CASE 29-04
(TO-226AA)
STYLE 3
WITH TO–18 LEADFORM*

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VRRM, VDRM Volts
(RGK = 1000 Ω, TJ = 25 to 125°C)
Marking: BRY55–1 . . . BRY55–30 30
Marking: BRY55–2 . . . BRY55–60 60
Marking: BRY55–3 . . . BRY55–100 100
Marking: BRY55–4 . . . BRY55–200 200
Marking: BRY55–6 . . . BRY55–400 400
Marking: BRY55–7 . . . BRY55–500 500
Marking: BRY55–8 . . . BRY55–600 600
Forward Current RMS (All Conduction Angles) IT(RMS) 0.8 Amp
Peak Forward Surge Current, TA = 25°C ITSM 8 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations, TA = 25°C I2t 0.15 A2s
(t = 8.3 ms)
Peak Gate Power — Forward, TA = 25°C PGM 0.1 Watt
Peak Gate Current Forward, TA = 25°C IGFM 1 Amp
(300 µs, 120 PPS)
Peak Gate Voltage — Reverse VGRM 5 Volts
Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
t
Lead Solder Temperature ( 1.5 mm from case, 10 s max.) +230 °C
*European part numbers only. Package is Case 29 with Leadform 18.
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

32 Motorola Thyristor Device Data

 BRY55-30 thru 600

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise noted.)
Characteristic Symbol Min Max Unit
Peak Forward Blocking Current IDRM — 100 µA
(VD = Rated VDRM @ TC = 125°C)
Peak Reverse Blocking Current IRRM — 100 µA
(VR = Rated VRRM @ TC = 125°C)
Forward “On’’ Voltage(1) VTM — 1.7 Volts
(ITM = 1 A Peak @ TA = 25°C)
Gate Trigger Current (Continuous dc)(2) TC = 25°C IGT — 200 µA
(Anode Voltage = 7 Vdc, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) TC = 25°C VGT — 0.8 Volts
(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –40°C — 1.2
(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C 0.1 —
Holding Current TC = 25°C IH — 5 mA
(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –40°C — 10
1. Forward current applied for 1 ms maximum duration, duty cycle v1%.
2. RGK current is not included in measurement.
3. MARKING: BRY55–30 = BRY55–1
BRY55–60 = BRY55–2
BRY55–100 = BRY55–3
BRY55–200 = BRY55–4
BRY55–400 = BRY55–6
BRY55–500 = BRY55–7
BRY55–600 = BRY55–8

FIGURE 1 – CURRENT DERATING FIGURE 2 – CURRENT DERATING

(REFERENCE: CASE TEMPERATURE) (REFERENCE: AMBIENT TEMPERATURE)
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

130 130
α = CONDUCTION ANGLE α α
TC, MAXIMUM ALLOWABLE AMBIENT

120
α = CONDUCTION ANGLE
110
110 CASE MEASUREMENT TYPICAL PRINTED
POINT – CENTER OF CIRCUIT BOARD
TEMPERATURE ( °C)

FLAT PORTION MOUNTING

100 90
dc
90
70
80
α = 30 60
180
90 120
70
50
α = 30
60
60 90 120 180
50 30
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 33

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifier C106

Reverse Blocking Triode Thyristors Series *
*Motorola preferred devices
. . . Glassivated PNPN devices designed for high volume consumer applications such
as temperature, light, and speed control; process and remote control, and warning
systems where reliability of operation is important.
• Glassivated Surface for Reliability and Uniformity SCRs
• Power Rated at Economical Prices 4 AMPERES RMS
• Practical Level Triggering and Holding Characteristics 50 thru 600 VOLTS
• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat
Dissipation and Durability

G
A K

CASE 77-08
G (TO-225AA)
A
K STYLE 2

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(RGK = 1 kΩ) C106F or 50
(TC = –40° to 110°C) C106A VRRM 100
C106B 200
C106D 400
C106M 600
RMS Forward Current IT(RMS) 4 Amps
(All Conduction Angles)
Average Forward Current IT(AV) 2.55 Amps
(TA = 30°C)
Peak Non-repetitive Surge Current ITSM 20 Amps
(1/2 Cycle, 60 Hz, TJ = –40 to +110°C)
Circuit Fusing (t = 8.3 ms) I2t 1.65 A2s
Peak Gate Power PGM 0.5 Watt
Average Gate Power PG(AV) 0.1 Watt
Peak Forward Gate Current IGFM 0.2 Amp
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, (cont.)
positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a
constant current source such that the voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

34 Motorola Thyristor Device Data

 C106 Series
MAXIMUM RATINGS — continued
Rating Symbol Value Unit
Peak Reverse Gate Voltage VGRM 6 Volts
Operating Junction Temperature Range TJ –40 to +110 °C
Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque(1) — 6 in. lb.
1. Torque rating applies with use of compression washer (B52200F006). Mounting torque in excess of 6 in. lb. does not appreciably lower
case-to-sink thermal resistance. Anode lead and heatsink contact pad are common.
For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C. For optimum
results, an activated flux (oxide removing) is recommended.

THERMAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted.)

Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 3 °C/W
Thermal Resistance, Junction to Ambient RθJA 75 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, RGK = 1000 Ohms) TJ = 25°C — — 10 µA
TJ = 110°C — — 100 µA
Forward “On” Voltage VTM — — 2.2 Volts
(IFM = 1 A Peak)
Gate Trigger Current (Continuous dc) IGT µA
(VAK = 6 Vdc, RL = 100 Ohms) — 30 200
(VAK = 6 Vdc, RL = 100 Ohms, TC = –40°C) — 75 500
Gate Trigger Voltage (Continuous dc) VGT Volts
(VAK = 6 Vdc, RL = 100 Ohms, RGK = 1000 Ohms) TJ = 25°C 0.4 — 0.8
(VAK = Rated VDRM, RL = 3000 Ohms, 0.5 — 1
RGK = 1000 Ohms, TJ = 110°C) TJ = –40°C 0.2 — —
Holding Current TJ = 25°C IHX 0.3 — 3 mA
(VD = 12 Vdc, RGK = 1000 Ohms) TJ = –40°C 0.4 — 6
TJ = +110°C 0.14 — 2
Forward Voltage Application Rate dv/dt — 8 — V/µs
(TJ = 110°C, RGK = 1000 Ohms, VD = Rated VDRM)
Turn-On Time tgt — 1.2 — µs
Turn-Off Time tq — 40 — µs

FIGURE 1 – AVERAGE CURRENT DERATING

P(AV), AVERAGE ON-STATE POWER DISSIPATION (WATTS)

FIGURE 2 – MAXIMUM ON-STATE POWER DISSIPATION

110 10
JUNCTION TEMPERATURE ≈ 110°C
100
TC, CASE TEMPERATURE ( °C)

90 8
DC HALF SINE WAVE
80
RESISTIVE OR INDUCTIVE LOAD
70 6 50 TO 400Hz.
60
DC
50 4
HALF SINE WAVE
40 RESISTIVE OR INDUCTIVE LOAD.
30 50 to 400 Hz 2
20
10 0
0 .4 .8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 .4 .8 1.2 1.6 2.0 2.4 2.6 3.2 3.6 4.0
IT(AV) AVERAGE ON-STATE CURRENT (AMPERES) IT(AV) AVERAGE ON-STATE CURRENT (AMPERES)

Motorola Thyristor Device Data 35

C106 Series
Package Interchangeability
The dimensional diagrams below compare the critical dimensions of the Motorola C-106 package
with competitive devices. It has been demonstrated that the smaller dimensions of the Motorola
package make it compatible in most lead-mount and chassis-mount applications. The user is
advised to compare all critical dimensions for mounting compatibility.

.400
____
.295
____ .360
.305 .115
____ .095 .127
____ .135
____ ____ DIA
.145
____ .130 .123 .026
____
.105 .115
.155 .019
.148
____
.158 .520
____
.425
____ 5_ TYP .480
.435
1 2 3 .385
____ .315
____
.365 .285
.050
____
.095 .575
____
.655 .420
____
.400

.105
____
.015
____ .105
____ .095
.040 .095 .190
____
.025
.094 BSC .054
____ .170
.045
____
.025
____ .055 .046
.035
.020
____
.026

Motorola C-106 Package Competitive C-106 Package

36 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

C122( )1
Silicon Controlled Rectifiers
Series
Reverse Blocking Triode Thyristors
. . . designed primarily for full-wave ac control applications, such as motor controls,
heating controls and power supplies; or wherever half–wave silicon gate–controlled,
SCRs
solid–state devices are needed.
8 AMPERES RMS
• Glass Passivated Junctions and Center Gate Fire for Greater Parameter 50 thru 800 VOLTS
Uniformity and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Blocking Voltage to 800 Volts
G
• Different Leadform Configurations, A K
Suffix (2) thru (6) available, see Leadform Options (Section 4) for Information

CASE 221A-04
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off–State Voltage(1) (TJ = 25 to 100°C, Gate Open) VDRM Volts
Repetitive Peak Reverse Voltage C122F1 VRRM 50
C122A1 100
C122B1 200
C122D1 400
C122M1 600
C122N1 800
Peak Non–repetitive Reverse Voltage(1) VRSM Volts
C122F1 75
C122A1 200
C122B1 300
C122D1 500
C122M1 700
C122N1 800
Forward Current RMS TC v75°C IT(RMS) 8 Amps
(All Conduction Angles)
Peak Forward Surge Current ITSM 90 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations I2t 34 A2s
(t = 8.3 ms)
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, (cont.)
positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a
constant current source such that the voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 37

 C122( )1 Series

MAXIMUM RATINGS — continued

Rating Symbol Value Unit
Forward Peak Gate Power (t = 10 µs) PGM 5 Watts
Forward Average Gate Power PG(AV) 0.5 Watt
Forward Peak Gate Current IGM 2 Amps
Operating Junction Temperature Range TJ –40 to +100 °C
Storage Temperature Range Tstg –40 to +125 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.8 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, Gate Open) TC = 25°C — — 10 µA
TC = 100°C — — 0.5 mA
Peak On–State Voltage(1) VTM — — 1.83 Volts
(ITM = 16 A Peak, TC = 25°C)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 6 V, RL = 91 Ohms, TC = 25°C) — — 25
(VD = 6 V, RL = 45 Ohms, TC = –40°C) — — 40
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 6 V, RL = 91 Ohms, TC = 25°C) — — 1.5
(VD = 6 V, RL = 45 Ohms, TC = –40°C) — — 2
(VD = Rated VDRM, RL = 1000 Ohms, TC = 100°C) 0.2 — —
Holding Current IH mA
(VD = 24 Vdc, IT = 0.5 A, 0.1 to 10 ms Pulse,
Gate Trigger Source = 7 V, 20 Ohms) TC = 25°C — — 30
TC = –40°C — — 60
Turn-Off Time (VD = Rated VDRM) tq — 50 — µs
(ITM = 8 A, IR = 8 A)
Critical Rate–of–Rise of Off–State Voltage dv/dt — 50 — V/µs
(VD = Rated VDRM, Linear, TC = 100°C)
1. Pulse Test: Pulse Width = 1 ms, Duty Cycle v2%.

FIGURE 1 – CURRENT DERATING (HALF–WAVE) FIGURE 2 – CURRENT DERATING (FULL–WAVE)

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

100 100 CONDUCTION CONDUCTION

ANGLE ANGLE
95
0 360
90 90
ONE CYCLE OF SUPPLY
FREQUENCY
85

80 80
DC CONDUCTION 120° 180° 240° 360°
75 ANGLE = 60°
CONDUCTION 60° 90° 120° 180°
70 70 RESISTIVE OR
ANGLE = 30° 0 360
INDUCTIVE LOAD.
CONDUCTION 65
ANGLE 50 TO 400 Hz
60 60
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(AV), AVERAGE ON–STATE FORWARD CURRENT (AMPERES) IT(AV), AVERAGE ON–STATE CURRENT (AMPERES)

38 Motorola Thyristor Device Data

 C122( )1 Series

FIGURE 3 – MAXIMUM POWER DISSIPATION FIGURE 4 – MAXIMUM POWER DISSIPATION

P(AV), AVERAGE ON–STATE POWER DISSIPATION (WATTS)

(HALF–WAVE)

TC , AVERAGE ON–STATE POWER DISSIPATION (WATTS)

(FULL–WAVE)
14 10
240° 360°
RESISTIVE OR INDUCTIVE LOAD, 50 TO 400 Hz
12 DC 180°
8
10 120°
CONDUCTION
180° 6
8 ANGLE = 60°
120°
90° CONDUCTION CONDUCTION
CONDUCTION 60°
6 ANGLE ANGLE
ANGLE 30° 4

4 0 360

ONE CYCLE OF SUPPLY

2
FREQUENCY
2
RESISTIVE OR INDUCTIVE LOAD, 50 TO 400 Hz
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(AV), AVERAGE ON–STATE CURRENT (AMPERES) IT(AV), AVERAGE ON–STATE CURRENT (AMPERES)

Motorola Thyristor Device Data 39

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC08BT1
SOT-223 Triac Series*
Silicon Bidirectional Thyristors *Motorola preferred devices

Designed for use in solid state relays, MPU interface, TTL logic and other light
industrial or consumer applications. Supplied in surface mount package for use in
automated manufacturing. TRIAC
• Sensitive Gate Trigger Current in Four Trigger Modes 0.8 AMPERE RMS
200 thru 600 Volts
• Blocking Voltage to 600 Volts
• Glass Passivated Surface for Reliability and Uniformity
• Surface Mount Package
• Devices Supplied on 1 K Reel

CASE 318E–04
(SOT–223)
STYLE 11

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit
Peak Repetitive Blocking Voltage(1) VDRM Volts
(1/2 Sine Wave, Gate Open, TJ = 25 to 110°C)
MAC08BT1 200
MAC08DT1 400
MAC08MT1 600

On–State Current RMS (TC = 80°C) IT(RMS) 0.8 Amps

Peak Non–repetitive Surge Current ITSM 10 Amps

(One Full Cycle, 60 Hz, TC = 25°C)
Circuit Fusing Considerations (t = 8.3 ms) I2t 0.4 A2s
Peak Gate Power (t v2.0 µs) PGM 5.0 Watts

Average Gate Power (TC = 80°C, t = 8.3 ms) PG(AV) 0.1 Watts

Operating Junction Temperature Range TJ –40 to +110 °C

Storage Temperature Range Tstg –40 to +150 °C
Maximum Device Temperature for Soldering Purposes (for 5 Seconds Maximum) TL 260 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Ambient RθJA 156 °C/W
PCB Mounted per Figure 1
Thermal Resistance, Junction to Tab RθJT 25 °C/W
Measured on Anode Tab Adjacent to Epoxy
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

40 Motorola Thyristor Device Data

 MAC08BT1 Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Peak Repetitive Blocking Current IDRM
(VD = Rated VDRM Gate Open) TJ = 25°C — — 10 µA
TJ = 110°C — — 200 µA
Maximum On–State Voltage (Either Direction) VTM — — 1.9 Volts
(IT = 1.1 A Peak, TA = 25°C)
Gate Trigger Current (Continuous dc) All Quadrants IGT — — 10 mA
(VD = 7.0 Vdc, RL = 100 Ω)
Holding Current (Either Direction) IH — — 5.0 mA
(VD = 7.0 Vdc, Gate Open,
Initiating Current = 20 mA, Gate Open)
Gate Trigger Voltage (Continuous dc) All Quadrants VGT — — 2.0 Volts
(VD = 7.0 Vdc, RL = 100 Ω)
Critical Rate of Rise of Commutation Voltage dv/dtc 1.5 — — V/µs
(f = 250 Hz, ITM = 1.0 A, Commutating di/dt = 1.5 A/mS
On–State Current Duration = 2.0 mS, VDRM = 200 V,
Gate Unenergized, TC = 110°C,
Gate Source Resistance = 150 Ω, See Figure 10)
Critical Rate–of–Rise of Off State Voltage dv/dt 10 — — V/µs
(Vpk = Rated VDRM, TC= 110°C, Gate Open, Exponential Method)

0.15
3.8
0.079
2.0

0.244
0.091 0.091 6.2
2.3 2.3
0.079
2.0
inches
0.059 0.059 0.059 BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.
mm
0.984 1.5 1.5 1.5 BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.
25.0 MATERIAL: G10 FIBERGLASS BASE EPOXY

0.096 0.096 0.096

2.44 2.44 2.44

0.059 0.059
1.5 1.5

0.472
12.0

Figure 1. PCB for Thermal Impedance and

Power Testing of SOT-223

Motorola Thyristor Device Data 41

 MAC08BT1 Series

IT, INSTANTANEOUS ON-STATE CURRENT (AMPS

10 160

Rθ JA , JUNCTION TO AMBIENT THERMAL

150 TYPICAL L
140 MAXIMUM
130
DEVICE MOUNTED ON L
120

RESISTANCE, ° C/W
1.0 FIGURE 1 AREA = L2 4
110 PCB WITH TAB AREA
100 AS SHOWN
90 1 2 3
80
0.1
70
TYPICAL AT TJ = 110°C 60
MAX AT TJ = 110°C 50 MINIMUM
MAX AT TJ = 25°C 40 FOOTPRINT = 0.076 cm2
0.01 30
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) FOIL AREA (cm2)

Figure 2. On-State Characteristics Figure 3. Junction to Ambient Thermal

Resistance versus Copper Tab Area

110 110
α
100 100
30° α 30°
AMBIENT TEMPERATURE (°C)

AMBIENT TEMPERATURE (°C)

60° 60°
T A , MAXIMUM ALLOWABLE

T A , MAXIMUM ALLOWABLE
90 90
α = CONDUCTION
90° 90°
ANGLE
80 80
dc dc
70 70
α = 180° α = 180°
60 120° 60 120°
50 50 1.0 cm2 FOIL AREA
MINIMUM FOOTPRINT α
50 OR 60 Hz
40 40 α
50 OR 60 Hz
30 30 α = CONDUCTION
ANGLE
20 20
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IT(RMS), RMS ON-STATE CURRENT (AMPS) IT(RMS), RMS ON-STATE CURRENT (AMPS)

Figure 4. Current Derating, Minimum Pad Size Figure 5. Current Derating, 1.0 cm Square Pad
Reference: Ambient Temperature Reference: Ambient Temperature

110 110
α 30°
100 α 105
30°
AMBIENT TEMPERATURE (°C)

T(tab) , MAXIMUM ALLOWABLE

60°
T A , MAXIMUM ALLOWABLE

dc
60° α = CONDUCTION
TAB TEMPERATURE (° C)

90 dc 90° ANGLE 100

α = 180°
α = 180°
80 95 90°
120° 120°
70 90
REFERENCE: α
4.0 cm2 FOIL AREA FIGURE 1 α
60 85
α = CONDUCTION
ANGLE
50 80
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
IT(RMS), RMS ON-STATE CURRENT (AMPS) IT(RMS), ON-STATE CURRENT (AMPS)

Figure 6. Current Derating, 2.0 cm Square Pad Figure 7. Current Derating

Reference: Ambient Temperature Reference: MT2 Tab

42 Motorola Thyristor Device Data

 MAC08BT1 Series
1.0 1.0
α
0.9
POWER DISSIPATION (WATTS) α

RESISTANCE (NORMALIZED)
0.8

r(t), TRANSIENT THERMAL

P(AV) , MAXIMUM AVERAGE

α = CONDUCTION
0.7
ANGLE
0.6
120°
0.5 0.1
30°
0.4 α = 180°
60°
0.3
dc 90°
0.2
0.1
0 0.01
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0001 0.001 0.01 0.1 1.0 10 100
IT(RMS), RMS ON-STATE CURRENT (AMPS) t, TIME (SECONDS)
Figure 8. Power Dissipation Figure 9. Thermal Response, Device
Mounted on Figure 1 Printed Circuit Board

80 mHY
1N4007
LL
MEASURE I RS 56
75 VRMS,
ADJUST FOR CHARGE
TRIGGER CONTROL

ITM, 60 Hz VAC TRIGGER CONTROL

200 V
2
0.047 CS
ADJUST FOR
+
CHARGE 1N914 dv/dt(c)
5 µF 51
NON-POLAR G 1
CL

Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
Figure 10. Simplified Q1 (dv/dt)c Test Circuit

10 10
60 Hz
80° 60°
180 Hz
400 Hz
COMMUTATING dv/dt

COMMUTATING dv/dt

300 Hz
dv/dt c , (V/ µ S)

dv/dt c , (V/ µ S)

110°
ITM
100° VDRM = 200 V

tw
1
f=
ń +
2 tw 6f I
TM
VDRM (di dt) c 1000
1.0 1.0
1.0 10 60 70 80 90 100 110
di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS) TJ, JUNCTION TEMPERATURE (°C)

Figure 11. Typical Commutating dv/dt versus Figure 12. Typical Commutating dv/dt versus
Current Crossing Rate and Junction Temperature Junction Temperature at 0.8 Amps RMS

Motorola Thyristor Device Data 43

 MAC08BT1 Series
60 10
600 Vpk IGT3

I GT , GATE TRIGGER CURRENT (mA)

TJ = 110°C

50 MAIN TERMINAL #2 IGT2

POSITIVE
STATIC dv/dt (V/ µs)

IGT4
IGT1
40 1.0

30
MAIN TERMINAL #1
POSITIVE
20 0.1
10 100 1000 10,000 – 40 – 20 0 20 40 60 80 100
RG, GATE – MAIN TERMINAL 1 RESISTANCE (OHMS) TJ, JUNCTION TEMPERATURE (°C)

Figure 13. Exponential Static dv/dt versus Figure 14. Typical Gate Trigger Current Variation
Gate – Main Terminal 1 Resistance

6.0 1.1

VGT , GATE TRIGGER VOLTAGE (VOLTS)

5.0
IH , HOLDING CURRENT (mA)

VGT3
4.0 VGT4
MAIN TERMINAL #2
POSITIVE VGT2
3.0
VGT1

2.0
MAIN TERMINAL #1
POSITIVE
1.0

0 0.3
– 40 – 20 0 20 40 60 80 100 – 40 – 20 0 20 40 60 80 100
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 15. Typical Holding Current Variation Figure 16. Gate Trigger Voltage Variation

44 Motorola Thyristor Device Data

 MAC08BT1 Series
INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total interface between the board and the package. With the
design. The footprint for the semiconductor packages must correct pad geometry, the packages will self align when
be the correct size to insure proper solder connection subjected to a solder reflow process.

0.15
3.8

0.079
2.0

0.248
6.3
0.091 0.091
2.3 2.3

0.079
2.0

0.059 0.059 0.059 inches

1.5 1.5 1.5 mm

SOT-223

SOT-223 POWER DISSIPATION

The power dissipation of the SOT-223 is a function of the The 156°C/W for the SOT-223 package assumes the use
MT2 pad size. This can vary from the minimum pad size for of the recommended footprint on a glass epoxy printed circuit
soldering to a pad size given for maximum power dissipation. board to achieve a power dissipation of 550 milliwatts. There
Power dissipation for a surface mount device is determined are other alternatives to achieving higher power dissipation
by TJ(max), the maximum rated junction temperature of the from the SOT-223 package. One is to increase the area of
die, RθJA, the thermal resistance from the device junction to the MT2 pad. By increasing the area of the MT2 pad, the
ambient, and the operating temperature, TA . Using the power dissipation can be increased. Although one can
values provided on the data sheet for the SOT-223 package, almost double the power dissipation with this method, one
PD can be calculated as follows: will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. A
TJ(max) – TA
PD = graph of RθJA versus MT2 pad area is shown in Figure 3.
RθJA
The values for the equation are found in the maximum Another alternative would be to use a ceramic substrate or
ratings table on the data sheet. Substituting these values into an aluminum core board such as Thermal Clad. Using a
the equation for an ambient temperature TA of 25°C, one can board material such as Thermal Clad, an aluminum core
calculate the power dissipation of the device which in this board, the power dissipation can be doubled using the same
case is 550 milliwatts. footprint.

PD = 110°C – 25°C = 550 milliwatts

156°C/W
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed or stainless steel with a typical thickness of 0.008 inches.
circuit board, solder paste must be applied to the pads. A The stencil opening size for the SOT-223 package should be
solder stencil is required to screen the optimum amount of the same as the pad size on the printed circuit board, i.e., a
solder paste onto the footprint. The stencil is made of brass 1:1 registration.

Motorola Thyristor Device Data 45

MAC08BT1 Series
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated • The soldering temperature and time should not exceed
temperature of the device. When the entire device is heated 260°C for more than 5 seconds.
to a high temperature, failure to complete soldering within a • When shifting from preheating to soldering, the
short time could result in device failure. Therefore, the maximum temperature gradient should be 5°C or less.
following items should always be observed in order to • After soldering has been completed, the device should
minimize the thermal stress to which the devices are be allowed to cool naturally for at least three minutes.
subjected. Gradual cooling should be used as the use of forced
• Always preheat the device. cooling will increase the temperature gradient and result
• The delta temperature between the preheat and in latent failure due to mechanical stress.
soldering should be 100°C or less.* • Mechanical stress or shock should not be applied during
• When preheating and soldering, the temperature of the cooling.
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When * Soldering a device without preheating can cause excessive
using infrared heating with the reflow soldering method, thermal shock and stress which can result in damage to the
the difference should be a maximum of 10°C. device.

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control actual temperature that might be experienced on the surface
settings that will give the desired heat pattern. The operator of a test board at or near a central solder joint. The two
must set temperatures for several heating zones, and a profiles are based on a high density and a low density board.
figure for belt speed. Taken together, these control settings The Vitronics SMD310 convection/infrared reflow soldering
make up a heating “profile” for that particular circuit board. system was used to generate this profile. The type of solder
On machines controlled by a computer, the computer used was 62/36/2 Tin Lead Silver with a melting point
remembers these profiles from one operating session to the
between 177 –189°C. When this type of furnace is used for
next. Figure 17 shows a typical heating profile for use when
solder reflow work, the circuit boards and solder joints tend to
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good heat first. The components on the board are then heated by
starting point. Factors that can affect the profile include the conduction. The circuit board, because it has a large surface
type of soldering system in use, density and types of area, absorbs the thermal energy more efficiently, then
components on the board, type of solder used, and the type distributes this energy to the components. Because of this
of board or substrate material being used. This profile shows effect, the main body of a component may be up to 30
temperature versus time. The line on the graph shows the degrees cooler than the adjacent solder joints.

STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7

PREHEAT VENT HEATING HEATING HEATING VENT COOLING
ZONE 1 “SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7
“SPIKE” 205° TO
“RAMP” “RAMP” “SOAK”
219°C
200°C DESIRED CURVE FOR HIGH 170°C PEAK AT
MASS ASSEMBLIES SOLDER
160°C
150°C JOINT

150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
100°C 140°C (DEPENDING ON
MASS OF ASSEMBLY)
100°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES
50°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

Figure 17. Typical Solder Heating Profile

46 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC8
SERIES*
TRIACS *Motorola preferred devices

Silicon Bidirectional Thyristors

TRIACS
Designed for high performance full-wave ac control applications where high 8 AMPERES RMS
noise immunity and high commutating di/dt are required. 400 thru 800
• Blocking Voltage to 800 Volts VOLTS
• On-State Current Rating of 8.0 Amperes RMS at 100°C
• Uniform Gate Trigger Currents in Three Modes
• High Immunity to dv/dt — 250 V/µs minimum at 125°C MT2

• Minimizes Snubber Networks for Protection

• Industry Standard TO-220AB Package
• High Commutating di/dt — 6.5 A/ms minimum at 125°C

MT1
MT2
G

CASE 221A–06
(TO-220AB)
Style 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Symbol Parameter Value Unit
VDRM Peak Repetitive Off-State Voltage (1) Volts
(– 40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC8D 400
MAC8M 600
MAC8N 800
IT(RMS) On-State RMS Current 8.0 A
(60 Hz, TC = 100°C)
ITSM Peak Non-repetitive Surge Current 80 A
(One Full Cycle, 60 Hz, TJ = 125°C)
I2t Circuit Fusing Consideration (t = 8.3 ms) 26 A2sec
PGM Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) 16 Watts
PG(AV) Average Gate Power (t = 8.3 ms, TC = 80°C) 0.35 Watts
TJ Operating Junction Temperature Range – 40 to +125 °C
Tstg Storage Temperature Range – 40 to +150 °C

THERMAL CHARACTERISTICS
RθJC Thermal Resistance — Junction to Case 2.2 °C/W
RθJA Thermal Resistan ce — Junction to Ambient 62.5
TL Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds 260 °C
(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 47

 MAC8 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol Characteristic Min Typ Max Unit
OFF CHARACTERISTICS
IDRM Peak Repetitive Blocking Current mA
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 0.01
TJ = 125°C — — 2.0

ON CHARACTERISTICS
VTM Peak On-State Voltage* Volts
(ITM = ± 11 A Peak) — 1.2 1.6
IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω) mA
MT2(+), G(+) 5.0 13 35
MT2(+), G(–) 5.0 16 35
MT2(–), G(–) 5.0 18 35
IH Hold Current mA
(VD = 12 V, Gate Open, Initiating Current = ±150 mA) — 20 40
IL Latch Current (VD = 24 V, IG = 35 mA) mA
MT2(+), G(+); MT2(–), G(–) — 20 50
MT2(+), G(–) — 30 80
VGT Gate Trigger Voltage (VD = 12 V, RL = 100 Ω) Volts
MT2(+), G(+) 0.5 0.69 1.5
MT2(+), G(–) 0.5 0.77 1.5
MT2(–), G(–) 0.5 0.72 1.5
DYNAMIC CHARACTERISTICS
(di/dt)c Rate of Change of Commutating Current* See Figure 10. 6.5 — — A/ms
(VD = 400 V, ITM = 4.4 A, Commutating dv/dt = 18 V/µs, CL = 10 µF
Gate Open, TJ = 125°C, f = 250 Hz, No Snubber) LL = 40 mH
dv/dt Critical Rate of Rise of Off-State Voltage 250 — — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

125 12
DC
PAV, AVERAGE POWER (WATTS)

10
TC, CASE TEMPERATURE (°C)

120
180°
α = 120, 90, 60, 30°
8
115 120°

α = 180° 6
110
60°
4
DC 90°
105 α = 30°
2

100 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), ON-STATE CURRENT (AMP)

Figure 1. RMS Current Derating Figure 2. On-State Power Dissipation

48 Motorola Thyristor Device Data

 MAC8 SERIES
100 1

r(t), TRANSIENT THERMAL RESISTANCE

TYPICAL AT
TJ = 25°C

(NORMALIZED)
MAXIMUM @ TJ = 125°C
0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)

10
0.01
0.1 1 10 100 1000 1 · 104
t, TIME (ms)

Figure 4. Thermal Response

MAXIMUM @ TJ = 25°C 40
1
I H, HOLD CURRENT (mA) 35

30
MT2 POSITIVE
25

20

15
MT2 NEGATIVE
10

0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 – 50 – 30 – 10 10 30 50 70 90 110 130
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. On-State Characteristics Figure 5. Hold Current Variation

100 1
0.95 Q2
VGT, GATE TRIGGER VOLTAGE (VOLT)
IGT, GATE TRIGGER CURRENT (mA)

Q2 0.9
Q3
0.85
Q3 0.8
Q1 075
10 0.7 Q1
0.65
0.6
0.55
0.5
0.45
1 0.4
– 50 – 30 – 10 10 30 50 70 90 110 130 – 50 – 30 – 10 10 30 50 70 90 110 130
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation

Motorola Thyristor Device Data 49

 MAC8 SERIES
dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE
5000 100
4.5K

(dv/dt) c , CRITICAL RATE OF RISE OF

4K

COMMUTATING VOLTAGE (V/µ s)

3.5K
MT2 NEGATIVE
3K TJ = 125°C 100°C 75°C
(V/µ s)

2.5K 10
2K
1.5K 1
f=
tw 2 tw
1K
6f I
MT2 POSITIVE (di/dt)c = TM
500 VDRM 1000

0 1
1 10 100 1000 10 15 20 25 30 35 40 45 50 55 60
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)

Figure 8. Critical Rate of Rise of Off-State Figure 9. Critical Rate of Rise of

Voltage (Exponential) Commutating Voltage

LL 1N400
200 VRMS 7
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
TRIGGER CONTROL

CHARGE
TRIGGER –
CHARGE CONTROL 400
+ V
2
1N91 51
NON-POLAR 4
G 1
CL

Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage

50 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC9
SERIES*
TRIACS *Motorola preferred devices

Silicon Bidirectional Thyristors

TRIACS
Designed for high performance full-wave ac control applications where high 8.0 AMPERES RMS
noise immunity and high commutating di/dt are required. 400 thru 800
• Blocking Voltage to 800 Volts VOLTS
• On-State Current Rating of 8.0 Amperes RMS at 100°C
• Uniform Gate Trigger Currents in Three Modes
• High Immunity to dv/dt — 500 V/µs minimum at 125°C MT2
• Minimizes Snubber Networks for Protection
• Industry Standard TO-220AB Package
• High Commutating di/dt — 6.5 A/ms minimum at 125°C

MT1
MT2
G

CASE 221A-06
(TO-220AB)
Style 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Symbol Parameter Value Unit
VDRM Peak Repetitive Off-State Voltage (1) Volts
(– 40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC9D 400
MAC9M 600
MAC9N 800
IT(RMS) On-State RMS Current 8.0 A
(60 Hz, TC = 100°C)
ITSM Peak Non-repetitive Surge Current 80 A
(One Full Cycle, 60 Hz, TJ = 125°C)
I2t Circuit Fusing Consideration (t = 8.3 ms) 26 A2sec
PGM Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) 16 Watts
PG(AV) Average Gate Power (t = 8.3 ms, TC = 80°C) 0.35 Watts
TJ Operating Junction Temperature Range – 40 to +125 °C
Tstg Storage Temperature Range – 40 to +150 °C
THERMAL CHARACTERISTICS
RθJC Thermal Resistance — Junction to Case 2.2 °C/W
RθJA Thermal Resistance — Junction to Ambient 62.5
TL Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds 260 °C
(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 1

 MAC9 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol Characteristic Min Typ Max Unit
OFF CHARACTERISTICS
IDRM Peak Repetitive Blocking Current mA
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 0.01
TJ = 125°C — — 2.0

ON CHARACTERISTICS
VTM Peak On-State Voltage* Volts
(ITM = ± 11 A Peak) — 1.2 1.6
IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω) mA
MT2(+), G(+) 10 16 50
MT2(+), G(–) 10 18 50
MT2(–), G(–) 10 22 50
IH Hold Current mA
(VD = 12 V, Gate Open, Initiating Current = ±150 mA) — 30 50
IL Latch Current (VD = 24 V, IG = 50 mA) mA
MT2(+), G(+); MT2(–), G(–) — 20 50
MT2(+), G(–) — 30 80
VGT Gate Trigger Voltage (VD = 12 V, RL = 100 Ω) Volts
MT2(+), G(+) 0.5 0.69 1.5
MT2(+), G(–) 0.5 0.77 1.5
MT2(–), G(–) 0.5 0.72 1.5
DYNAMIC CHARACTERISTICS
(di/dt)c Rate of Change of Commutating Current* See Figure 10. 6.5 — — A/ms
(VD = 400 V, ITM = 4.4 A, Commutating dv/dt = 18 V/µs, CL = 10 µF
Gate Open, TJ = 125°C, f = 250 Hz, No Snubber) LL = 40 mH
dv/dt Critical Rate of Rise of Off-State Voltage 500 — — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

125 12
DC
PAV, AVERAGE POWER (WATTS)

10
TC, CASE TEMPERATURE (°C)

120
180°
α = 120, 90, 60, 30°
8
115 120°

α = 180° 6
110
60°
4
DC 90°
105 α = 30°
2

100 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), ON-STATE CURRENT (AMP)

Figure 1. RMS Current Derating Figure 2. On-State Power Dissipation

2 Motorola Thyristor Device Data

 MAC9 SERIES
100 1

r(t), TRANSIENT THERMAL RESISTANCE

TYPICAL AT
TJ = 25°C

(NORMALIZED)
MAXIMUM @ TJ = 125°C 0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)

10
0.01
0.1 1 10 100 1000 1 · 104
t, TIME (ms)

Figure 4. Thermal Response

MAXIMUM @ TJ = 25°C 40
1
35
I H, HOLD CURRENT (mA)

30

25 MT2 POSITIVE

20

15
MT2 NEGATIVE
10

0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 – 50 – 30 – 10 10 30 50 70 90 110 130
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. On-State Characteristics Figure 5. Hold Current Variation

100 1
0.95
VGT, GATE TRIGGER VOLTAGE (VOLT)
IGT, GATE TRIGGER CURRENT (mA)

Q2 0.9
0.85 Q3
Q3 0.8
0.75 Q1
Q1
10 0.7 Q2
0.65
0.6
0.55
0.5
0.45
1 0.4
– 50 – 30 – 10 10 30 50 70 90 110 130 – 50 – 30 – 10 10 30 50 70 90 110 130
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation

Motorola Thyristor Device Data 3

 MAC9 SERIES
dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE
5000 100
4.5K

(dv/dt) c , CRITICAL RATE OF RISE OF

4K

COMMUTATING VOLTAGE (V/µ s)

3.5K
MT2 NEGATIVE
3K TJ = 125°C 100°C 75°C
(V/µ s)

2.5K 10
2K
1.5K 1
f=
tw 2 tw
1K
6f I
MT2 POSITIVE (di/dt)c = TM
500 VDRM 1000

0 1
1 10 100 1000 10 15 20 25 30 35 40 45 50 55 60
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)

Figure 8. Critical Rate of Rise of Off-State Voltage Figure 9. Critical Rate of Rise of
(Exponential) Commutating Voltage

LL 1N400
200 VRMS 7
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
TRIGGER CONTROL

CHARGE
TRIGGER –
CHARGE CONTROL 400
+ V
2
1N91 51
NON-POLAR 4
G 1
CL

Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage

4 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC12
Advance Information SERIES*
TRIACS *Motorola preferred devices

Silicon Bidirectional Thyristors

TRIACS
12 AMPERES RMS
Designed for high performance full–wave ac control applications where high
400 thru 800
noise immunity and commutating di/dt are required.
VOLTS
• Blocking Voltage to 800 Volts
• On–State Current Rating of 12 Amperes RMS at 70°C
MT2
• Uniform Gate Trigger currents in Three Modes
• High Immunity to dv/dt — 250 V/µs minimum at 125°C
• High Commutating di/dt — 6.5 A/ms minimum at 125°C
• Industry Standard TO–220 AB Package
• High Surge Current Capability — 120 Amperes
MT1
MT2
G CASE 221A-06
(TO-220AB)
Style 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit
Peak Repetitive Off–State Voltage(1) VDRM Volts
(TJ = –40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC12D 400
MAC12M 600
MAC12N 800
On–State RMS Current IT(RMS) 12 A
(Full Cycle Sine Wave, 60 Hz, TC = 70°C)
Peak Non–repetitive Surge Current ITSM 100 A
(One Full Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 41 A2sec
Peak Gate Power (Pulse Width v1.0 µs, TC = 80°C) PGM 16 Watts
Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.35 Watts
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case RθJC 2.2 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current TJ = 25°C IDRM — — 0.01 mA
(VD = Rated VDRM, Gate Open) TJ = 125°C — — 2.0
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola Thyristor Device Data 5

MAC12 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
ON CHARACTERISTICS
Peak On–State Voltage* (ITM = "17 A) VTM — — 1.85 Volts
Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω) IGT mA
MT2(+), G(+) 5.0 13 35
MT2(+), G(–) 5.0 16 35
MT2(–), G(–) 5.0 18 35
Hold Current (VD = 12 V, Gate Open, Initiating Current = "150 mA) IH — 20 40 mA
Latch Current (VD = 24 V, IG = 35 mA) IL mA
MT2(+), G(+); MT2(–), G(–) — 20 50
MT2(+), G(–) — 30 80
Gate Trigger Voltage (VD = 12 V, RL = 100 Ω) VGT Volts
MT2(+), G(+) 0.5 0.69 1.5
MT2(+), G(–) 0.5 0.77 1.5
MT2(–), G(–) 0.5 0.72 1.5
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current* (dv/dt)c 6.5 — — A/ms
(VD = 400 V, ITM = 4.4A, Commutating dv/dt = 18 V/µs, Gate Open,
TJ = 125°C, f = 250 Hz, No Snubber)
Critical Rate of Rise of Off–State Voltage dv/dt 250 — — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width v2.0 ms, Duty Cycle v2%.

6 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC15
SERIES *
TRIACS *Motorola preferred devices

Silicon Bidirectional Thyristors

TRIACS
Designed for high performance full-wave ac control applications where high 15 AMPERES RMS
noise immunity and high commutating di/dt are required. 400 thru 800
• Blocking Voltage to 800 Volts VOLTS
• On-State Current Rating of 15 Amperes RMS at 80°C
• Uniform Gate Trigger Currents in Three Modes
• High Immunity to dv/dt — 250 V/µs minimum at 125°C MT2
• Minimizes Snubber Networks for Protection
• Industry Standard TO-220AB Package
• High Commutating di/dt — 9.0 A/ms minimum at 125°C

MT1
MT2
G

CASE 221A-06
(TO–220AB)
Style 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Symbol Parameter Value Unit
VDRM Peak Repetitive Off-State Voltage (1) Volts
(– 40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC15D 400
MAC15M 600
MAC15N 800
IT(RMS) On-State RMS Current 15 A
(60 Hz, TC = 80°C)
ITSM Peak Non-repetitive Surge Current 150 A
(One Full Cycle, 60 Hz, TJ = 125°C)
I2t Circuit Fusing Consideration (t = 8.3 ms) 93 A2sec
PGM Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) 20 Watts
PG(AV) Average Gate Power (t = 8.3 ms, TC = 80°C) 0.5 Watts
TJ Operating Junction Temperature Range – 40 to +125 °C
Tstg Storage Temperature Range – 40 to +150 °C
THERMAL CHARACTERISTICS
RθJC Thermal Resistance — Junction to Case 2.0 °C/W
RθJA Thermal Resistance — Junction to Ambient 62.5
TL Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds 260 °C
(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 1

 MAC15 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol Characteristic Min Typ Max Unit
OFF CHARACTERISTICS
IDRM Peak Repetitive Blocking Current mA
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 0.01
TJ = 125°C — — 2.0

ON CHARACTERISTICS
VTM Peak On-State Voltage* Volts
(ITM = ± 21 A Peak) — 1.2 1.6
IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω) mA
MT2(+), G(+) 5.0 13 35
MT2(+), G(–) 5.0 16 35
MT2(–), G(–) 5.0 18 35
IH Hold Current mA
(VD = 12 V, Gate Open, Initiating Current = ±150 mA) — 20 40
IL Latch Current (VD = 24 V, IG = 35 mA) mA
MT2(+), G(+) — 33 50
MT2(+), G(–) — 36 80
MT2(–), G(–) — 33 50
VGT Gate Trigger Voltage (VD = 12 V, RL = 100 Ω) Volts
MT2(+), G(+) 0.5 0.75 1.5
MT2(+), G(–) 0.5 0.72 1.5
MT2(–), G(–) 0.5 0.82 1.5
DYNAMIC CHARACTERISTICS
(di/dt)c Rate of Change of Commutating Current* See Figure 10. 9.0 — — A/ms
(VD = 400 V, ITM = 6.0 A, Commutating dv/dt = 24 V/µs, CL = 10 µF
Gate Open, TJ = 125°C, f = 250 Hz, No Snubber) LL = 40 mH
dv/dt Critical Rate of Rise of Off-State Voltage 250 — — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

125 20 DC
180°
120 18
PAV, AVERAGE POWER (WATTS)

120°
TC, CASE TEMPERATURE (°C)

115 16
α = 30 and 60° 14
90°
110 60°
α = 90° 12
105
α = 180° α = 120° 10
100 α = 30°
8
95
DC 6
90 4
85 2
80 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), ON-STATE CURRENT (AMP)

Figure 11. RMS Current Derating Figure 12. On-State Power Dissipation

2 Motorola Thyristor Device Data

 MAC15 SERIES
100 1

r(t), TRANSIENT THERMAL RESISTANCE

TYPICAL AT MAXIMUM @ TJ = 125°C
TJ = 25°C

(NORMALIZED)
0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)

10
0.01
0.1 1 10 100 1000 1 · 104
t, TIME (ms)

Figure 14. Thermal Response

MAXIMUM @ TJ = 25°C 40
1
I H, HOLD CURRENT (mA)

MT2 POSITIVE

MT2 NEGATIVE

0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 – 40 – 10 20 50 80 110 125
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 13. On-State Characteristics Figure 15. Hold Current Variation

100 1
OFF-STATE VOLTAGE = 12 V
VGT, GATE TRIGGER VOLTAGE (VOLT)
IGT, GATE TRIGGER CURRENT (mA)

RL = 140 Ω
Q2
Q3

Q1 Q1
Q3

Q2

OFF-STATE VOLTAGE = 12 V
RL = 140 Ω

1 0.5
– 40 – 10 20 50 80 110 125 – 40 – 10 +20 50 80 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 16. Gate Trigger Current Variation Figure 17. Gate Trigger Voltage Variation

Motorola Thyristor Device Data 3

 MAC15 SERIES
dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE
5000 100
VD = 800 Vpk

(dv/dt) c , CRITICAL RATE OF RISE OF

TJ = 125°C
4K

COMMUTATING VOLTAGE (V/µ s)

3K TJ = 125°C 100°C 75°C
(V/µ s)

10
2K
ITM
1
f=
tw 2 tw
1K
6f I
(di/dt)c = TM
VDRM 1000

0 1
10 100 1000 10000 10 20 30 40 50 60 70 80 90 100
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)

Figure 18. Critical Rate of Rise of Off-State Figure 19. Critical Rate of Rise of
Voltage (Exponential) Commutating Voltage

LL 1N400
200 VRMS 7
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
TRIGGER CONTROL

CHARGE
TRIGGER –
CHARGE CONTROL 400
+ V
2
1N91 51
NON-POLAR 4
G 1
CL

Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

Figure 20. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage

4 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC15
Series
Triacs MAC15A
Silicon Bidirectional Triode Thyristors
Series
. . . designed primarily for full-wave ac control applications, such as solid–state relays,
motor controls, heating controls and power supplies; or wherever full–wave silicon
gate controlled solid–state devices are needed. Triac type thyristors switch from a TRIACs
blocking to a conducting state for either polarity of applied anode voltage with positive 15 AMPERES RMS
or negative gate triggering. 200 thru 800 VOLTS
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat MT2 MT1
Dissipation and Durability G
• Gate Triggering Guaranteed in Three Modes (MAC15 Series) or Four Modes
(MAC15A Series)

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off–State Voltage(1) VDRM Volts
(Gate Open, TJ = –40 to +125°C) MAC15–4, MAC15A4 200
MAC15–6, MAC15A6 400
MAC15–8, MAC15A8 600
MAC15–10, MAC15A10 800
Peak Gate Voltage VGM 10 Volts
On–State Current RMS IT(RMS) 15 Amps
Full Cycle Sine Wave 50 to 60 Hz (TC = +90°C)
Circuit Fusing (t = 8.3 ms) I2t 93 A2s
Peak Surge Current ITSM 150 Amps
(One Full Cycle, 60 Hz, TC = +80°C)
Preceded and followed by rated current
Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 20 Watts
Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current IGM 2 Amps
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

REV 1

Motorola Thyristor Device Data 5

 MAC15 Series MAC15A Series
ELECTRICAL CHARACTERISTICS (TC = 25°C, and either polarity of MT2 to MT1 Voltage, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak On–State Voltage VTM — 1.3 1.6 Volts
(ITM = 21 A Peak; Pulse Width = 1 or 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — — 50
MT2(+), G(–) — — 50
MT2(–), G(–) — — 50
MT2(–), G(+) “A’’ SUFFIX ONLY — — 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A’’ SUFFIX ONLY — 1.4 2.5
(VD = Rated VDRM, RL = 10 k Ohms, TJ = 110°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
MT2(–), G(+) “A’’ SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 40 mA
(VD = 12 Vdc, Gate Open)
(IT = 200 mA)
Turn-On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 17 A)
(IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 21 A, Commutating di/dt = 7.6 A/ms,
Gate Unenergized, TC = 80°C)

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON–STATE POWER DISSIPATION

130 20
α = 180°
PAV, AVERAGE POWER (WATTS)

α = 30° 120°
TJ ≈ 125°
TC, CASE TEMPERATURE (°C)

120 16
α = 60° dc
90°
α = 90° α 60°
110 12
α
30°
α = 180°
100 8 α = CONDUCTION ANGLE
dc
α
90 α 4
TJ ≈ 125°
α = CONDUCTION ANGLE
80 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
IT(RMS), RMS ON–STATE CURRENT (AMP) IT(RMS), ON–STATE CURRENT (AMP)

6 Motorola Thyristor Device Data

 MAC15 Series MAC15A Series
FIGURE 3 – TYPICAL GATE TRIGGER VOLTAGE FIGURE 4 – TYPICAL GATE TRIGGER CURRENT
1.8 50
OFF–STATE VOLTAGE = 12 V OFF–STATE VOLTAGE = 12 V
VGT, GATE TRIGGER VOLTAGE (VOLTS)

IGT, GATE TRIGGER CURRENT (mA)

1.6
30
1.4
QUADRANT 4 20
1.2

1.0

10 1
0.8 1
2
QUADRANTS 2 QUADRANT 3
0.6 3 7.0
4
0.4 5.0
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 – ON–STATE CHARACTERISTICS FIGURE 6 – TYPICAL HOLDING CURRENT

100 20
GATE OPEN
70 MAIN TERMINAL #1
POSITIVE
50 I H, HOLDING CURRENT (mA)
TJ = 25°C 10
125°C
30 7.0

20 5.0

MAIN TERMINAL #2
POSITIVE
i TM, INSTANTANEOUS FORWARD CURRENT (AMP)

3.0
10

7 2.0
–60 –40 –20 0 20 40 60 80 100 120 140
5 TJ, JUNCTION TEMPERATURE (°C)

2
FIGURE 7 – MAXIMUM NON–REPETITIVE SURGE CURRENT
300
TSM, PEAK SURGE CURRENT (AMP)

1
200
0.7

0.5

100
0.3
70
0.2
TC = 80°C
50
T f = 60 Hz
Surge is preceded and followed by rated current
0.1 30
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 1 2 3 5 7 10
vTM, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS) NUMBER OF CYCLES

Motorola Thyristor Device Data 7

MAC15 Series MAC15A Series

FIGURE 8 – THERMAL RESPONSE

1
r(t) TRANSIENT THERMAL RESISTANCE

0.5

0.2 ZθJC(t) = r(t) • RθJC

(NORMALIZED)

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

8 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC15FP
Triacs Series
Silicon Bidirectional Thyristors MAC15AFP
. . . designed primarily for full-wave ac control applications, such as solid-state relays, Series
motor controls, heating controls and power supplies; or wherever full-wave silicon
gate controlled solid-state devices are needed. Triac type thyristors switch from a
blocking to a conducting state for either polarity of applied anode voltage with positive ISOLATED TRIACs
or negative gate triggering. THYRISTORS
• Blocking Voltage to 800 Volts 15 AMPERES RMS
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity 200 thru 800 VOLTS
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Gate Triggering Guaranteed in Three Modes (MAC15FP Series) or Four Modes
(MAC15AFP Series)

MT2 MT1
CASE 221C-02
G
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC15-4FP, MAC15A4FP 200
MAC15-6FP, MAC15A6FP 400
MAC15-8FP, MAC15A8FP 600
MAC15-10FP, MAC15A10FP 800
On-State RMS Current (TC = +80°C )(2) IT(RMS) 15 Amps
Full Cycle Sine Wave 50 to 60 Hz (TC = +95°C ) 12
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, T C = +80°C) ITSM 150 Amps
preceded and followed by rated current
Peak Gate Power (T C = +80°C, Pulse Width = 2 µs) PGM 20 Watts
Average Gate Power (T C = +80°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current IGM 2 Amps
Peak Gate Voltage VGM 10 Volts
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

Motorola Thyristor Device Data 9

MAC15FP Series MAC15AFP Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current (Either Direction) TJ = 25°C IDRM — — 10 µA
(VD = Rated VDRM, TJ = 125°C, Gate Open) — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.3 1.6 Volts
(ITM = 21 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — — 50
MT2(+), G(–) — — 50
MT2(–), G(–) — — 50
MT2(–), G(+) “A” SUFFIX ONLY — — 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +110°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 40 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 200 mA)
Turn-On Time t gt — 1.5 — µs
(VD = Rated VDRM, ITM = 17 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 21 A, Commutating di/dt = 7.6 A/ms,
Gate Unenergized, TC = 80°C)

Trigger devices are recommended for gating on Triacs. They provide:

QUADRANT DEFINITIONS
1. Consistent predictable turn–on points.
MT2(+) 2. Simplified circuitry.

QUADRANT II QUADRANT I 3. Fast turn–on time for cooler, more efficient and reliable operation.

MT2(+), G(–) MT2(+), G(+)

ELECTRICAL CHARACTERISTICS of RECOMMENDED
BIDIRECTIONAL SWITCHES

G(–) G(+) Usage General

QUADRANT III QUADRANT IV Part Number MBS4991 MBS4992

VS 6–10 V 7.5–9 V
MT2(–), G(–) MT2(–), G(+) IS 350 µA Max 120 µA Max
VS1–VS2 0.5 V Max 0.2 V Max
MT2(–)
Temperature 0.02%/°C Typ
Coefficient

1. Ratings apply for open gate conditions. Thyristor devices shall not be tested with a constant current source for blocking capability such that the
voltage applied exceeds the rated blocking voltage.

10 Motorola Thyristor Device Data

 MAC15FP Series MAC15AFP Series
TYPICAL CHARACTERISTICS

IGTM , GATE TRIGGER CURRENT (NORMALIZED)

130 3
OFF–STATE VOLTAGE = 12 Vdc
30° 2 ALL MODES
TC, CASE TEMPERATURE (°C)

120
60°
90°
110
125°C 1
150° to 180°
100 0.7
dc
α
0.5
90 α

α = CONDUCTION ANGLE
80 0.3
0 2 4 6 8 10 12 14 16 –60 –40 –20 0 20 40 60 80 100 120 140
IT(RMS), RMS ON–STATE CURRENT (AMP) TJ, JUNCTION TEMPERATURE (°C)

Figure 21. RMS Current Derating Figure 24. Typical Gate Trigger Current
PD(AV), AVERAGE POWER DISSIPATION (WATTS)

20 100
TJ = 125°C α = 180° 70
16 120°
dc 50 TJ = 25°C
90°
α 60° 125°C
12
30
α 30°
8 α = CONDUCTION ANGLE 20

4
i F, INSTANTANEOUS FORWARD CURRENT (AMP)

10
0 7
0 2 4 6 8 10 12 14 16
IT(RMS), RMS ON–STATE CURRENT (AMP) 5

Figure 22. On–State Power Dissipation

3

2
VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)

3
OFF–STATE VOLTAGE = 12 Vdc
1
2 ALL MODES
0.7

0.5
1
0.3
0.7

0.2
0.5

0.3 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
TJ, JUNCTION TEMPERATURE (°C) vT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

Figure 23. Typical Gate Trigger Voltage Figure 25. Maximum On–State Characteristics

Motorola Thyristor Device Data 11

MAC15FP Series MAC15AFP Series

3 300
I H, HOLDING CURRENT (NORMALIZED) GATE OPEN

I TSM, PEAK SURGE CURRENT (AMP)

2 APPLIES TO EITHER DIRECTION
200

1
100

0.7 70

0.5
50 TC = 80°C
f = 60 Hz
SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT
0.3 30
–60 –40 –20 0 20 40 60 80 100 120 140 1 2 3 5 7 10
TJ, JUNCTION TEMPERATURE (°C) NUMBER OF CYCLES

Figure 26. Typical Holding Current Figure 27. Maximum Nonrepetitive Surge Current

1
r(t) TRANSIENT THERMAL RESISTANCE

0.5

0.2 ZθJC(t) = r(t) • RθJC

(NORMALIZED)

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

Figure 28. Thermal Response

12 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC16
SERIES *
*Motorola preferred devices

TRIACS
Silicon Bidirectional Thyristors TRIACS
15 AMPERES RMS
400 thru 800
Designed for high performance full-wave ac control applications where high VOLTS
noise immunity and high commutating di/dt are required.
• Blocking Voltage to 800 Volts
• On-State Current Rating of 15 Amperes RMS at 80°C MT2
• Uniform Gate Trigger Currents in Three Modes
• High Immunity to dv/dt — 500 V/µs minimum at 125°C
• Minimizes Snubber Networks for Protection
• Industry Standard TO-220AB Package
• High Commutating di/dt — 9.0 A/ms minimum at 125°C MT1
MT2
G

CASE 221A-06
(TO-220AB)
Style 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Symbol Parameter Value Unit
VDRM Peak Repetitive Off-State Voltage (1) Volts
(– 40 to 125°C, Sine Wave, 50 to 60 Hz, Gate Open) MAC16D 400
MAC16M 600
MAC16N 800
IT(RMS) On-State RMS Current 15 A
(60 Hz, TC = 80°C)
ITSM Peak Non-repetitive Surge Current 150 A
(One Full Cycle, 60 Hz, TJ = 125°C)
I2t Circuit Fusing Consideration (t = 8.3 ms) 93 A2sec
PGM Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) 20 Watts
PG(AV) Average Gate Power (t = 8.3 ms, TC = 80°C) 0.5 Watts
TJ Operating Junction Temperature Range – 40 to +125 °C
Tstg Storage Temperature Range – 40 to +150 °C

THERMAL CHARACTERISTICS
RθJC Thermal Resistance — Junction to Case 2.0 °C/W
RθJA Thermal Resistance — Junction to Ambient 62.5
TL Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds 260 °C
(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 1

 MAC16 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol Characteristic Min Typ Max Unit
OFF CHARACTERISTICS
IDRM Peak Repetitive Blocking Current mA
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 0.01
TJ = 125°C — — 2.0

ON CHARACTERISTICS
VTM Peak On-State Voltage* Volts
(ITM = ± 21 A Peak) — 1.2 1.6
IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω) mA
MT2(+), G(+) 10 16 50
MT2(+), G(–) 10 18 50
MT2(–), G(–) 10 22 50
IH Hold Current mA
(VD = 12 V, Gate Open, Initiating Current = ±150 mA) — 20 50
IL Latch Current (VD = 24 V, IG = 50 mA) mA
MT2(+), G(+) — 33 50
MT2(+), G(–) — 36 80
MT2(–), G(–) — 33 50
VGT Gate Trigger Voltage (VD = 12 V, RL = 100 Ω) Volts
MT2(+), G(+) 0.5 0.75 1.5
MT2(+), G(–) 0.5 0.72 1.5
MT2(–), G(–) 0.5 0.82 1.5
DYNAMIC CHARACTERISTICS
(di/dt)c Rate of Change of Commutating Current* See Figure 10. 9.0 — — A/ms
(VD = 400 V, ITM = 6.0 A, Commutating dv/dt = 24 V/µs, CL = 10 µF
Gate Open, TJ = 125°C, f = 250 Hz, No Snubber) LL = 40 mH
dv/dt Critical Rate of Rise of Off-State Voltage 500 — — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

125 20 DC
180°
120 18
PAV, AVERAGE POWER (WATTS)

120°
TC, CASE TEMPERATURE (°C)

115 16
α = 30 and 60° 14
90°
110 60°
α = 90° 12
105
α = 180° α = 120° 10
100 α = 30°
8
95
DC 6
90 4
85 2
80 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), ON-STATE CURRENT (AMP)

Figure 1. RMS Current Derating Figure 2. On-State Power Dissipation

2 Motorola Thyristor Device Data

 MAC16 SERIES
100 1

r(t), TRANSIENT THERMAL RESISTANCE

TYPICAL AT MAXIMUM @ TJ = 125°C
TJ = 25°C

(NORMALIZED)
0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)

10
0.01
0.1 1 10 100 1000 1 · 104
t, TIME (ms)

Figure 4. Thermal Response

MAXIMUM @ TJ = 25°C 40
1
I H, HOLD CURRENT (mA)

MT2 POSITIVE

MT2 NEGATIVE

0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 – 40 – 10 20 50 80 110 125
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. On-State Characteristics Figure 5. Hold Current Variation

100 1
OFF-STATE VOLTAGE = 12 V
VGT, GATE TRIGGER VOLTAGE (VOLT)
IGT, GATE TRIGGER CURRENT (mA)

RL = 140 Ω
Q2
Q3

Q1 Q1
Q3

Q2

OFF-STATE VOLTAGE = 12 V
RL = 140 Ω

1 0.5
– 40 – 10 20 50 80 110 125 – 40 – 10 +20 50 80 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation

Motorola Thyristor Device Data 3

 MAC16 SERIES
dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE
5000 100
VD = 800 Vpk

(dv/dt) c , CRITICAL RATE OF RISE OF

TJ = 125°C
4K

COMMUTATING VOLTAGE (V/µ s)

3K TJ = 125°C 100°C 75°C
(V/µ s)

10
2K
ITM
1
f=
tw 2 tw
1K
6f I
(di/dt)c = TM
VDRM 1000

0 1
10 100 1000 10000 10 20 30 40 50 60 70 80 90 100
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)

Figure 8. Critical Rate of Rise of Off-State Voltage Figure 9. Critical Rate of Rise of
(Exponential) Commutating Voltage

LL 1N400
200 VRMS 7
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
TRIGGER CONTROL

CHARGE
TRIGGER –
CHARGE CONTROL 400
+ V
2
1N91 51
NON-POLAR 4
G 1
CL

Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage

4 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC97,A
Silicon Bidirectional
IMPROVED
Triode Thyristors
SERIES
. . . designed for use in solid state relays, MPU interface, TTL logic and any other light
industrial or consumer application. Supplied in an inexpensive TO–92 package which (Device Date Code
is readily adaptable for use in automatic insertion equipment. 9625 and Up)

• One–Piece, Injection–Molded Unibloc Package Motorola preferred devices

• Sensitive Gate Triggering in Four Trigger Modes for all possible Combinations of
Trigger Sources, and Especially for Circuits that Source Gate Drives
• All Diffused and Glassivated Junctions for Maximum Uniformity of Parameters
and Reliability TRIACs
0.8 AMPERE RMS
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 200 — 600 VOLTS
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage VDRM Volts
(Gate Open, TJ = –40 to +110°C)(1)
1/2 Sine Wave 50 to 60 Hz, Gate Open
MT1
MAC97–4, MAC97A4 200
MAC97–6, MAC97A6 400 MT2
MAC97–8, MAC97A8 600
G
On-State RMS Current IT(RMS) 0.8 Amp
Full Cycle Sine Wave 50 to 60 Hz (TC = +50°C)
Peak Non–repetitive Surge Current ITSM 8.0 Amps
(One Full Cycle, 60 Hz, TA = 110°C)
Circuit Fusing Considerations I2t 0.26 A2s
TJ = –40 to +110°C (t = 8.3 ms)
v 2.0 ms)
Peak Gate Voltage (t VGM 5.0 Volts
MT1
Peak Gate Power (t v 2.0 ms) PGM 5.0 Watts G
Average Gate Power (TC = 80°C, t v 8.3 ms) PG(AV) 0.1 Watt
MT2

Peak Gate Current (t v 2.0 ms) IGM 1.0 Amp

CASE 29–04
Operating Junction Temperature Range TJ –40 to +110 °C TO–226AA, STYLE 12
Storage Temperature Range Tstg –40 to +150 °C (TO–92)

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
1 VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be
tested with a constant current source such that the voltage ratings of the devices are
exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola Thyristor Device Data 5

MAC97,A IMPROVED SERIES

ELECTRICAL CHARACTERISTICS (TC = 25°C, and Either Polarity of MT2 to MT1 Voltage unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current(1) IRRM — — 0.1 mA
(VD = Rated VDRM, TJ = 110°C, Gate Open)
Peak On-State Voltage (Either Direction) VTM — — 1.65 Volts
(ITM = 1.1 A Peak; Pulse Width v 2.0 ms, Duty Cycle v 2.0%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — — 10
MT2(+), G(–) — — 10
MT2(–), G(–) — — 10
MT2(–), G(+) MAC97 — — 10

MT2(+), G(+) — — 5.0

MT2(+), G(–) — — 5.0
MT2(–), G(–) — — 5.0
MT2(–), G(+) MAC97A — — 7.0
Gate Trigger Voltage, (Continuous dc) VGT Volts
(VD = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) All Types — — 2.0
MT2(+), G(–) All Types — — 2.0
MT2(–), G(–) All Types — — 2.0
MT2(–), G(+) All Types — — 2.5
(VD = Rated VDRM, RL = 10 k Ohms, TJ = 110°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) All Types 0.1 — —
MT2(–), G(+) All Types 0.1 — —
Holding Current IH — — 5.0 mA
(VD = 12 Vdc, ITM = 200 mA, Gate Open)
Gate Controlled Turn–On Time tgt — 2.0 — ms
(VD = Rated VDRM, ITM = 1.0 A pk, IG = 25 mA)
Critical Rate–of–Rise of Commutation Voltage dv/dtc 1.5 — — V/ms
(f = 250 Hz, ITM = 1.0 A, Commutating di/dt = 1.5 A/mS,
On–State Current Duration = 2.0 mS, VDRM = 200 V,
Gate Unenergized, TC = 110°C,
Gate Source Resistance = 150 W, See Figure 13)
Critical Rate–of–Rise of Off State Voltage dv/dt 10 — — V/ms
(Vpk = Rated VDRM, TC = 110°C, Gate Open, Exponential Method)

6 Motorola Thyristor Device Data

 MAC97,A IMPROVED SERIES

TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (°C

110 110
T = 30°
100 T = 30° 100

I T(RMS) , MAXIMUM ALLOWABLE

AMBIENT TEMPERATURE (°C)
90 60°
90 60°
DC DC 90°
90° 80
80
180° 70 180°
70 120° 120°
60
60
α 50 α
50
α 40 α
40 30
α = CONDUCTION ANGLE α = CONDUCTION ANGLE
30 20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
IT(RMS), RMS ON–STATE CURRENT (AMPS) IT(RMS), RMS ON–STATE CURRENT (AMPS)

Figure 1. RMS Current Derating Figure 2. RMS Current Derating

P(AV), MAXIMUM AVERAGE POWER DISSIPATION (WATTS)

IT, INSTANTANEOUS ON–STATE CURRENT (AMPS)

1.2 10
TYPICAL @ TJ = 25°C
1.0 α
MAXIMUM @ TJ = 110°C
α
0.8 1.0
α = CONDUCTION ANGLE
0.6
MAXIMUM @ TJ = 25°C
0.4 0.1

0.2
MAXIMUM @ TJ = 110°C
0 0.01
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IT(RMS), RMS ON–STATE CURRENT (AMPS) VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

Figure 3. Power Dissipation Figure 4. On–State Characteristics

R(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 10
I TSM , PEAK SURGE CURRENT (AMPS)

5.0
Q Q
Z JC(t) = R JC(t) @ r(t)

0.1 3.0

TJ = 110°C
2.0 f = 60 Hz
CYCLE

Surge is preceded and followed by rated current.

0.01 1.0
0.1 1.0 10 100 1S103 1S104 1.0 2.0 3.0 5.0 10 30 50 100
t, TIME (ms) NUMBER OF CYCLES

Figure 5. Transient Thermal Response Figure 6. Maximum Allowable Surge Current

Motorola Thyristor Device Data 7

 MAC97,A IMPROVED SERIES

6.0 10
Q3

I GT, GATE TRIGGER CURRENT (mA)

5.0
I H, HOLDING CURRENT (mA)

Q2
4.0 MAIN TERMINAL Q4
#2 POSITIVE Q1
3.0 1.0

2.0 MAIN TERMINAL

#2 NEGATIVE

1.0

0 0.1
–40 –20 0 20 40 60 80 100 110 –40 –20 0 20 40 60 80 100 110
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 7. Typical Holding Current Variation Figure 8. Typical Gate Trigger Current
Variation

1.1 60
VGT, GATE TRIGGER VOLTAGE (VOLTS)

600 Vpk
TJ = 110°C
0.9 Q3 50 MAIN TERMINAL

STATIC dv/dt (V/mS)

Q4 #2 POSITIVE
Q2
Q1 MAIN TERMINAL
0.7 40
#2 NEGATIVE

0.5 30

0.3 20
–40 –20 0 20 40 60 80 100 10 100 1000 10,000
TJ, JUNCTION TEMPERATURE (°C) RGK, GATE – MT1 RESISTANCE (OHMS)

Figure 9. Gate Trigger Voltage Variation Figure 10. Exponential Static dv/dt versus
Gate ć MT1 Resistance

10 10
60 Hz

180 Hz
60°C
COMMUTATING dv/dt

COMMUTATING dv/dt

ITM 80°C 300 Hz

dv/dtc , (V/mS)

dv/dtc , (V/mS)

100°C 400 Hz
110°C
tw

f + 2t1
ń + 6f1000I
w VDRM = 200 V
TM
VDRM (di dt) c
1.0 1.0
1.0 10 60 70 80 90 100 110
di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS) TJ, JUNCTION TEMPERATURE (°C)

Figure 11. Typical Commutating dv/dt versus Figure 12. Typical Commutating dv/dt versus
Current Crossing Rate and Junction Temperature Junction Temperature at 0.8 Amps RMS

8 Motorola Thyristor Device Data

 MAC97,A IMPROVED SERIES

80 mHY 1N4007
LL

75 VRMS
MEASURE
ADJUST FOR RS 56
I
ITM, 60 Hz VAC

TRIGGER CONTROL
TRIGGER –
CHARGE
CS 0.047 CS 200 V
CHARGE CONTROL 2 +
ADJUST FOR
dv/dt(c)
1N914 1
51
5 mF
NON–POLAR G
CL

NOTE: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.

Figure 13. Simplified Q1 (dv/dt)c Test Circuit

Motorola Thyristor Device Data 9

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC210
Series
Triacs MAC210A
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies; or wherever full-wave silicon
gate controlled solid-state devices are needed. Triac type thyristors switch from a
TRIACs
blocking to a conducting state for either polarity of applied anode voltage with positive
10 AMPERES RMS
or negative gate triggering.
200 thru 800 VOLTS
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
MT2 MT1
Dissipation and Durability
• Gate Triggering Guaranteed in Three Modes (MAC210 Series) or Four Modes G
(MAC210A Series)

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) VDRM Volts
(TJ = –40 to +125°C,
1/2 Sine Wave 50 to 60 Hz, Gate Open) MAC210-4, MAC210A4 200
MAC210-6, MAC210A6 400
MAC210-8, MAC210A8 600
MAC210-10, MAC210A10 800
On-State Current RMS (TC = +70°C) IT(RMS) 10 Amps
Full Cycle Sine Wave 50 to 60 Hz
Peak Non-repetitive Surge Current ITSM 100 Amps
(One Full Cycle, 60 Hz, TC = +70°C)
Preceded and followed by Rated Current
Circuit Fusing Considerations I2t 40 A2s
(t = 8.3 ms)
Peak Gate Power PGM 20 Watts
(TC = +70°C, Pulse Width = 10 µs)
Average Gate Power (TC = +70°C, t = 8.3 ms) PG(AV) 0.35 Watt
Peak Gate Current IGM 2 Amps
(TC = +70°C, Pulse Width = 10 µs)
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +125 °C
(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that
the voltage ratings of the devices are exceeded.

10 Motorola Thyristor Device Data

 MAC210 Series MAC210A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = +125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.2 1.65 Volts
(ITM = 14 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 12 50
MT2(+), G(–) — 12 50
MT2(–), G(–) — 20 50
MT2(–), G(+) “A” SUFFIX ONLY — 35 75
Gate Trigger Voltage (Continuous dc) VGT volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 k ohms,
TJ = +125°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 50 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 500 mA, TC = +25°C)
Turn-On Time tgt — 1.5 — µs
(Rated VDRM, ITM = 14 A)
(IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 14 A, Commutating di/dt = 5.0 A/ms,
Gate Unenergized, TC = 70°C)
Critical Rate of Rise of Off-State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise,
Gate Open, TC = +70°C)

Motorola Thyristor Device Data 11

 MAC210 Series MAC210A Series
FIGURE 1 — CURRENT DERATING FIGURE 2 — POWER DISSIPATION
130 14.0

P (AV) , AVERAGE POWER DISSIPATION

CONDUCTION ANGLE = 360° CONDUCTION ANGLE = 360°
12.0
TC, MAXIMUM ALLOWABLE CASE

120

10.0
TEMPERATURE (° C)

110

100 8.0

90 6.0

80 4.0

70 2.0

60 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
IT(RMS), RMS ON-STATE CURRENT (AMPS) IT(RMS), RMS ON-STATE CURRENT (AMPS)

FIGURE 3 — MAXIMUM ON-STATE CHARACTERISTICS FIGURE 4 — MAXIMUM NON-REPETITIVE SURGE CURRENT

100 100

ITSM , PEAK SURGE CURRENT (AMP)

50
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS)

80

20
60
10
40 CYCLE
5.0
TC = 70°C
TJ = 25°C
20 f = 60 Hz
2.0 TJ = 125°C
Surge is preceded and followed by rated current

1.0 0
1.0 2.0 3.0 5.0 7.0 10
0.5 NUMBER OF CYCLES

0.2
FIGURE 5 — TYPICAL GATE TRIGGER VOLTAGE
VGT , GATE TRIGGER VOLTAGE (NORMALIZED)

0.1 2.0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
OFF-STATE VOLTAGE = 12 Vdc
1.6
ALL MODES

1.2

0.8

0.4

0
–60 –40 –20 0 20 40 60 80
TC, CASE TEMPERATURE (°C)

12 Motorola Thyristor Device Data

 MAC210 Series MAC210A Series
FIGURE 6 — TYPICAL GATE TRIGGER CURRENT FIGURE 7 — TYPICAL HOLDING CURRENT
I GT, GATE TRIGGER CURRENT (NORMALIZED)
2.0 2.8

IH , HOLDING CURRENT (NORMALIZED)

2.4
1.6 OFF-STATE VOLTAGE = 12 Vdc OFF-STATE VOLTAGE = 12 Vdc
ALL MODES ALL MODES
2.0

1.2 1.6

1.2
0.8
0.8
0.4
0.4

0 0
–60 –40 –20 0 20 40 60 80 –60 –40 –20 0 20 40 60 80
TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C)

FIGURE 8 – THERMAL RESPONSE

1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.5
(NORMALIZED)

0.2
ZθJC(t) = r(t) • RθJC
0.1

0.05

0.02

0.01
0.1 0.2 0.5 1.0 2.0 5.0 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
t, TIME (ms)

Motorola Thyristor Device Data 13

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC210FP
Series
Triacs MAC210AFP
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies; or wherever full-wave silicon ISOLATED TRIACs
gate controlled solid-state devices are needed. Triac type thyristors switch from a THYRISTORS
blocking to a conducting state for either polarity of applied anode voltage with positive 10 AMPERES RMS
or negative gate triggering. 200 thru 800 VOLTS
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Gate Triggering Guaranteed in Three Modes (MAC210FP Series)
or Four Modes (MAC210AFP Series)

MT2 MT1 CASE 221C-02

STYLE 3
G

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) (TJ = –40 to +125°C) VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open
MAC210-4FP, MAC210A4FP 200
MAC210-6FP, MAC210A6FP 400
MAC210-8FP, MAC210A8FP 600
MAC210-10FP, MAC210A10FP 800
On-State RMS Current (TC = +70°C ) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 10 Amps
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +70°C) ITSM 100 Amps
preceded and followed by rated current
Circuit Fusing (t = 8.3 ms) I2t 40 A2s
Peak Gate Power (TC = +70°C, Pulse Width = 10 µs) PGM 20 Watts
Average Gate Power (TC = +70°C, t = 8.3 ms) PG(AV) 0.35 Watt
Peak Gate Current (TC = +70°C, Pulse Width = 10 µs) IGM 2 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +125 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic body.

14 Motorola Thyristor Device Data

 MAC210FP Series MAC210AFP Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current (Either Direction) IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = +125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.2 1.65 Volts
(ITM = 14 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms
Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) — 12 50
MT2(+), G(–) — 12 50
MT2(–), G(–) — 20 50
MT2(–), G(+) “A” SUFFIX ONLY — 35 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms
Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 50 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 500 mA, TC = +25°C)
Turn-On Time t gt — 1.5 — µs
(Rated VDRM, ITM = 14 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 14 A, Commutating di/dt = 5.0 A/ms,
Gate Unenergized, TC = +70°C)
Critical Rate of Rise of Off–State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,
TC = +70°C)

Motorola Thyristor Device Data 15

 MAC210FP Series MAC210AFP Series
TYPICAL CHARACTERISTICS
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

PD(AV), AVERAGE POWER DISSIPATION (WATTS)

130 14
CONDUCTION ANGLE = 360° CONDUCTION ANGLE = 360°
120 12

110 10

100 8

90 6

80 4

70 2

60 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
IT(RMS), RMS ON–STATE CURRENT (AMPS) IT(RMS), RMS ON–STATE CURRENT (AMPS)

Figure 1. Current Derating Figure 2. Power Dissipation

100 100

ITSM , PEAK SURGE CURRENT (AMP)

i T, INSTANTANEOUS ON–STATE CURRENT (AMPS)

50
80
20
60
10

5 TJ = 25°C CYCLE
40

2 TJ = 125°C TC = 70°C
20
1 f = 60 Hz
SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT
0.5 0
1 2 3 5 7 10
NUMBER OF CYCLES
0.2
Figure 4. Maximum Nonrepetitive Surge Current
0.1
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
vT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)
VGT, GATE TRIGGER VOLTAGE (NORMALIZED)

2
Figure 3. Maximum On–State Characteristics
OFF–STATE VOLTAGE = 12 Vdc
1.6
ALL MODES

1.2

0.8

0.4

0
– 60 – 40 – 20 0 20 40 60 80
TC, CASE TEMPERATURE (°C)

Figure 5. Typical Gate Trigger Voltage

16 Motorola Thyristor Device Data

 MAC210FP Series MAC210AFP Series

I GT, GATE TRIGGER CURRENT (NORMALIZED)

2 2.8

I H , HOLDING CURRENT (NORMALIZED)

OFF–STATE VOLTAGE = 12 Vdc 2.4 OFF–STATE VOLTAGE = 12 Vdc
1.6 ALL MODES
ALL MODES
2

1.2
1.6

1.2
0.8
0.8
0.4
0.4

0 0
– 60 – 40 – 20 0 20 40 60 80 – 60 – 40 – 20 0 20 40 60 80
TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C)

Figure 6. Typical Gate Trigger Current Figure 7. Typical Holding Current

1
r(t), TRANSIENT THERMAL RESISTANCE

0.5
(NORMALIZED)

0.2
ZθJC(t) = r(t) • RθJC
0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

Figure 8. Thermal Response

Motorola Thyristor Device Data 17

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC212
Series
Triacs MAC212A
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies; or wherever full-wave silicon
gate controlled solid-state devices are needed. Triac type thyristors switch from a TRIACs
blocking to a conducting state for either polarity of applied anode voltage with positive 12 AMPERES RMS
or negative gate triggering. 200 thru 800 VOLTS
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat MT1
Dissipation and Durability
• Gate Triggering Guaranteed in Three Modes (MAC212 Series) or Four Modes MT2 G
(MAC212A Series)

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC212-4, MAC212A4 200
MAC212-6, MAC212A6 400
MAC212-8, MAC212A8 600
MAC212-10, MAC212A10 800
On-State Current RMS (TC = +85°C) IT(RMS) 12 Amp
Full Cycle Sine Wave 50 to 60 Hz
Peak Non-repetitive Surge Current (One Full Cycle, 60 Hz, TC = +85°C) ITSM 100 Amp
preceded and followed by Rated Current
Circuit Fusing Considerations (t = 8.3 ms) I2t 40 A2s
Peak Gate Power (TC = +85°C, Pulse Width = 10 µs) PGM 20 Watts
Average Gate Power (TC = +85°C, t = 8.3 ms) PG(AV) 0.35 Watt
Peak Gate Current (TC = +85°C, Pulse Width = 10 µs) IGM 2 Amp
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

18 Motorola Thyristor Device Data

 MAC212 Series MAC212A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.1 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current (Either Direction) IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = +125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.3 1.75 Volts
ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 12 50
MT2(+), G(–) — 12 50
MT2(–), G(–) — 20 50
MT2(–), G(+) “A” SUFFIX ONLY — 35 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 50 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 500 mA)
Turn-On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 17 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms,
Gate Unenergized, TC = +85°C)
Critical Rate of Rise of Off-State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,
TC = +85°C)

FIGURE 1 — CURRENT DERATING

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( ° C)

FIGURE 2 — POWER DISSIPATION

PD(AV), AVERAGE POWER DISSIPATION (WATT)

125 28

24
115 α
20 α dc
105 α = 30° α = 180°
16 α = CONDUCTION ANGLE
90°
60° 12 60°
95 α 90° 30°
α 180° 8.0
85 dc
α = CONDUCTION ANGLE 4.0

75 0
0 2.0 4.0 6.0 8.0 10 12 14 0 2.0 4.0 6.0 8.0 10 12 14
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 19

 MAC212 Series MAC212A Series
FIGURE 3 — MAXIMUM ON-STATE CHARACTERISTICS FIGURE 4 — MAXIMUM NON-REPETITIVE SURGE CURRENT
100 100

ITSM , PEAK SURGE CURRENT (AMP)

50
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) 80

20
60
10
40 CYCLE
5.0

TJ = 25°C TC = 70°C
20
2.0 f = 60 Hz
TJ = 125°C
Surge is preceded and followed by rated current
1.0 0
1.0 2.0 3.0 5.0 7.0 10
0.5 NUMBER OF CYCLES

0.2

0.1 FIGURE 5 — TYPICAL GATE TRIGGER VOLTAGE

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4

VGT , GATE TRIGGER VOLTAGE (NORMALIZED)

2.0
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

1.6 OFF-STATE VOLTAGE = 12 Vdc

ALL MODES

1.2

0.8

0.4

0
–60 –40 –20 0 20 40 60 80
TC, CASE TEMPERATURE (°C)

FIGURE 6 — TYPICAL GATE TRIGGER CURRENT FIGURE 7 — TYPICAL HOLDING CURRENT

I GT, GATE TRIGGER CURRENT (NORMALIZED)

2.0 2.8
IH , HOLDING CURRENT (NORMALIZED)

2.4
OFF-STATE VOLTAGE = 12 Vdc
1.6 OFF-STATE VOLTAGE = 12 Vdc
ALL MODES
2.0 ALL MODES

1.2 1.6

1.2
0.8
0.8
0.4
0.4

0 0
–60 –40 –20 0 20 40 60 80 –60 –40 –20 0 20 40 60 80
TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C)

20 Motorola Thyristor Device Data

 MAC212 Series MAC212A Series
FIGURE 8 – THERMAL RESPONSE
r(t), TRANSIENT THERMAL RESISTANCE 1.0

0.5

0.2
(NORMALIZED)

ZθJC(t) = r(t) • RθJC

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1.0 2.0 5.0 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
t, TIME (ms)

Motorola Thyristor Device Data 21

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC212FP
Series
Triacs MAC212AFP
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies; or wherever full-wave silicon ISOLATED TRIACs
gate controlled solid-state devices are needed. Triac type thyristors switch from a THYRISTORS
blocking to a conducting state for either polarity of applied anode voltage with positive 12 AMPERES RMS
or negative gate triggering. 200 thru 800 VOLTS
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Gate Triggering Guaranteed in Three Modes (MAC212FP Series) or
Four Modes (MAC212AFP Series)

MT2 MT1 CASE 221C-02

G STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC212-4FP, MAC212A4FP 200
MAC212-6FP, MAC212A6FP 400
MAC212-8FP, MAC212A8FP 600
MAC212-10FP, MAC212A10FP 800
On-State RMS Current (TC = +85°C ) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 12 Amps
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +85°C) ITSM 100 Amps
preceded and followed by rated current
Circuit Fusing (t = 8.3 ms) I2t 40 A2s
Peak Gate Power (TC = +85°C, Pulse Width = 10 µs) PGM 20 Watts
Average Gate Power (TC = +85°C, t = 8.3 ms) PG(AV) 0.35 Watt
Peak Gate Current (TC = +85°C, Pulse Width = 10 µs) IGM 2 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.1 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

22 Motorola Thyristor Device Data

 MAC212FP Series MAC212AFP Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current (Either Direction) IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = +125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.3 1.75 Volts
(ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms,
Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) — 12 50
MT2(+), G(–) — 12 50
MT2(–), G(–) — 20 50
MT2(–), G(+) “A” SUFFIX ONLY — 35 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms,
Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 50 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 500 mA)
Turn-On Time t gt — 1.5 — µs
(VD = Rated VDRM, ITM = 17 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms,
Gate Unenergized, TC = +85°C)
Critical Rate of Rise of Off–State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,
TC = +85°C)

TYPICAL CHARACTERISTICS
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

PD(AV), AVERAGE POWER DISSIPATION (WATTS)

125 28

24 α
115 α
20 dc
α = CONDUCTION ANGLE
105 α = 30° 16 α = 180°
90°
60° 60°
95 α 12
90° 30°
α
180° 8.0
85 α = CONDUCTION ANGLE dc
4.0

75 0
0 2.0 4.0 6.0 8.0 10 12 14 0 2.0 4.0 6.0 8.0 10 12 14
IT(RMS), RMS ON–STATE CURRENT (AMPS) IT(RMS), RMS ON–STATE CURRENT (AMPS)

Figure 1. Current Derating Figure 2. Power Dissipation

Motorola Thyristor Device Data 23

 MAC212FP Series MAC212AFP Series
100 100

ITSM , PEAK SURGE CURRENT (AMP)

i T, INSTANTANEOUS ON–STATE CURRENT (AMPS)
50
80
20
60
10

5 TJ = 25°C CYCLE
40

2 TJ = 125°C TC = 70°C
20
1 f = 60 Hz
SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT
0.5 0
1 2 3 5 7 10
NUMBER OF CYCLES
0.2
Figure 4. Maximum Nonrepetitive Surge Current
0.1
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
vT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

VGT, GATE TRIGGER VOLTAGE (NORMALIZED)

2
Figure 3. Maximum On–State Characteristics
OFF–STATE VOLTAGE = 12 Vdc
1.6
ALL MODES

1.2

0.8

0.4

0
– 60 – 40 – 20 0 20 40 60 80
TC, CASE TEMPERATURE (°C)

Figure 5. Typical Gate Trigger Voltage

I GT, GATE TRIGGER CURRENT (NORMALIZED)

2 2.8
I H , HOLDING CURRENT (NORMALIZED)

OFF–STATE VOLTAGE = 12 Vdc 2.4 OFF–STATE VOLTAGE = 12 Vdc

1.6 ALL MODES
ALL MODES
2

1.2
1.6

1.2
0.8
0.8
0.4
0.4

0 0
– 60 – 40 – 20 0 20 40 60 80 – 60 – 40 – 20 0 20 40 60 80
TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C)

Figure 6. Typical Gate Trigger Current Figure 7. Typical Holding Current

24 Motorola Thyristor Device Data

 MAC212FP Series MAC212AFP Series
1

r(t), TRANSIENT THERMAL RESISTANCE 0.5

(NORMALIZED)

0.2
ZθJC(t) = r(t) • RθJC
0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

Figure 8. Thermal Response

Motorola Thyristor Device Data 25

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC218
Series
Triacs MAC218A
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies. TRIACs
• Blocking Voltage to 800 Volts 8 AMPERES RMS
• Glass Passivated Junctions for Greater Parameter Uniformity and Stability 200 thru 800 VOLTS
• TO-220 Construction Low Thermal Resistance, High Heat Dissipation and
Durability
• Gate Triggering Guaranteed in Three Modes (MAC218 Series) or Four Modes
(MAC218A Series)
MT2 MT1
G

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(Gate Open, TJ = 25 to 125°C) MAC218-4, MAC218A4 200
MAC218-6, MAC218A6 400
MAC218-8, MAC218A8 600
MAC218-10, MAC218A10 800
On-State Current RMS IT(RMS) 8 Amps
(Conduction Angle = 360°, TC = +80°C)
Peak Non-repetitive Surge Current ITSM 100 Amps
(One Full Cycle, 60 Hz, TC = 80°C, preceded and followed by rated current)
Fusing Current I2t 40 A2s
(t = 8.3 ms)
Peak Gate Power PGM 16 Watts
(TC = +80°C, Pulse Width = 2 µs)
Average Gate Power PG(AV) 0.35 Watt
(TC = +80°C, t = 8.3 ms)
Peak Gate Trigger Current IGTM 4 Amps
(Pulse Width = 1 µs)
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

26 Motorola Thyristor Device Data

 MAC218 Series MAC218A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(V D = Rated V DRM , gate open) T J = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.7 2 Volts
(ITM = 11.3 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle t 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 12Ω)
Trigger Mode
MT2(+), Gate(+); MT2(+), Gate(–); MT2(–), Gate(–) — — 50
MT2(–), Gate(+) “A” SUFFIX ONLY — — 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — — 50 mA
(VD = 24 Vdc, Gate Open,
Initiating Current = 200 mA)
Critical Rate of Rise of Commutating Off-State Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11.3 A, Commutating
di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)
Critical Rate of Rise of Off-State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,
TJ = 125°C)

FIGURE 1 — CURRENT DERATING FIGURE 2 — POWER DISSIPATION

P(AV), AVERAGE POWER DISSIPATION (WATTS)

125 10
TC, MAXIMUM ALLOWABLE CASE

115 8.0
TEMPERATURE (° C)

105 6.0

95 4.0

85 2.0

75 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
IT(RMS), RMS ON STATE CURRENT (AMPS) IT(RMS) RMS ON STATE CURRENT (AMPS)

Motorola Thyristor Device Data 27

 MAC218 Series MAC218A Series
FIGURE 3 — NORMALIZED GATE TRIGGER CURRENT FIGURE 4 — NORMALIZED GATE TRIGGER VOLTAGE

VGT , NORMALIZED GATE TRIGGER VOLTAGE (VOLTS)

IGT, NORMALIZED GATE TRIGGER CURRENT (mA)
5.0 1.8
OFF-STATE VOLTAGE = 12 V
OFF-STATE VOLTAGE = 12 V
1.6
3.0
1.4
2.0 QUADRANT 4
1.2

1 1.0
2
QUADRANT 1
1.0 3 0.8
4 QUADRANTS 2
0.7 0.6 3

0.5 0.4
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 — NORMALIZED HOLDING CURRENT

2.0
I H , NORMALIZED HOLDING CURRENT (mA)

GATE OPEN
MAIN TERMINAL #1
POSITIVE
1.0

0.7

0.5
MAIN TERMINAL #2
POSITIVE
0.3

0.2
–60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)

28 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC218FP
Series
MAC218AFP
Triacs Series
Silicon Bidirectional Thyristors
. . . designed primarily for full-wave ac control applications, such as light dimmers, ISOLATED TRIACs
motor controls, heating controls and power supplies. THYRISTORS
• Blocking Voltage to 800 Volts 8 AMPERES RMS
• Glass Passivated Junctions for Greater Parameter Uniformity and Stability 200 thru 800 VOLTS
• Isolated TO–220 Type Package for Ease of Mounting
• Gate Triggering in Three Modes (MAC218FP Series) or
Four Modes (MAC218AFP Series)

MT2 MT1

CASE 221C-02
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C) VDRM Volts
(1/2 Sine Wave 50 to 60 Hz, Gate Open) MAC218-4FP, MAC218A4FP 200
MAC218-6FP, MAC218A6FP 400
MAC218-8FP, MAC218A8FP 600
MAC218-10FP, MAC218A10FP 800
On-State RMS Current (TC = +80°C ) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 8 Amps
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, ITSM 100 Amps
preceded and followed by rated current, TC = +80°C)
Circuit Fusing (t = 8.3 ms) I2t 40 A2s
Peak Gate Power (TC = +80°C, Pulse Width = 2 µs) PGM 16 Watts
Average Gate Power (TC = +80°C, t = 8.3 ms) PG(AV) 0.35 Watt
Peak Gate Current (Pulse Width = 1 µs) IGM 4 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

Motorola Thyristor Device Data 29

 MAC218FP Series MAC218AFP Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Off–State Current (Either Direction) IDRM — — 2 mA
(VD = Rated VDRM @ TJ = 125°C, Gate Open)
Peak On-State Voltage (Either Direction) VTM — 1.7 2 Volts
(ITM = 11.3 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) (V D = 12 Vdc, R L = 12 Ω) IGT mA
Trigger Mode
MT2(+), G(+) — — 50
MT2(+), G(–) — — 50
MT2(–), G(–) — — 50
MT2(–), G(+) “A” SUFFIX ONLY — — 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — — 50 mA
(VD = 24 Vdc, Gate Open, Initiating Current = 200 mA)
Critical Rate of Rise of Commutating Off–State Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11.3 A, Commutating
di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)
Critical Rate of Rise of Off–State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise, Gate Open,
TJ = 125°C)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

PD(AV), AVERAGE POWER DISSIPATION (WATTS)

125 10

115 8

105 6

95 4

85 2

75 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(RMS), RMS ON–STATE CURRENT (AMPS) IT(RMS), RMS ON–STATE CURRENT (AMPS)

Figure 1. Current Derating Figure 2. Power Dissipation

30 Motorola Thyristor Device Data

 MAC218FP Series MAC218AFP Series

VGT, NORMALIZED GATE TRIGGER VOLTAGE (VOLTS)

I GT, NORMALIZED GATE TRIGGER CURRENT (mA)
5 1.8
OFF–STATE VOLTAGE = 12 V
OFF–STATE VOLTAGE = 12 V 1.6
3
1.4
2 QUADRANT 4
1.2

1 1 0.8 1
2 QUADRANTS 2
QUADRANT
0.7 3 0.6 3
4
0.5 0.4
– 60 – 40 – 20 0 20 40 60 80 100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. Normalized Gate Trigger Current Figure 4. Normalized Gate Trigger Voltage

2
I H , NORMALIZED HOLDING CURRENT (mA)

GATE OPEN

MAIN TERMINAL #1
POSITIVE
1

0.7

0.5
MAIN TERMINAL #2
POSITIVE
0.3

0.2
– 60 – 40 – 20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Normalized Holding Current

Motorola Thyristor Device Data 31

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC223
Series
Triacs MAC223A
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications such as lighting systems,
heater controls, motor controls and power supplies; or wherever full–wave silicon–
gate–controlled devices are needed. TRIACs
• Off–State Voltages to 800 Volts 25 AMPERES RMS
• All Diffused and Glass Passivated Junctions for Parameter Uniformity and Stability 200 thru 800 VOLTS
• Small, Rugged, Thermowatt Construction for Thermal Resistance and High Heat
Dissipation
• Gate Triggering Guaranteed in Three Modes (MAC223 Series) or Four Modes
(MAC223A Series)

MT2 G MT1

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage VDRM Volts
(TJ = –40 to 125°C)(1)
(1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC223-4, MAC223A4 200
MAC223-6, MAC223A6 400
MAC223-8, MAC223A8 600
MAC223–10, MAC223A10 800
On-State RMS Current (TC = 80°C) IT(RMS) 25 Amps
(Full Cycle Sine Wave 50 to 60 Hz)
Peak Non-repetitive Surge Current ITSM 250 Amps
(One Full Cycle, 60 Hz, TC = 80°C, preceded and followed by rated current)
Circuit Fusing I2t 260 A2s
(t = 8.3 ms)
Peak Gate Current (t v 2 µs) IGM 2 Amps
Peak Gate Voltage (t v 2 µs) VGM "10 Volts
Peak Gate Power (t v 2 µs) PGM 20 Watts
Average Gate Power (TC = 80°C, t v 8.3 ms) PG(AV) 0.5 Watts
Operating Junction Temperature Range TJ –40 to 125 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque — 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

32 Motorola Thyristor Device Data

 MAC223 Series MAC223A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current(1) IDRM
(V D = Rated V DRM ) T J = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak On-State Voltage VTM — 1.4 1.85 Volts
(ITM = 35 A Peak, Pulse Width v 2 ms, Duty Cycle v 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(–), G(–); MT(+), G(–) — 20 50
MT2(–), G(+) “A” SUFFIX ONLY — 30 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(–), G(–); MT(+), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.3 2.5
(VD = Rated VDRM, TJ = 125°C, RL = 10 k) 0.2 0.4 —
MT(+), G(+); MT2(–), G(–); MT2(+), G(–)
MT2(–), G(+) “A” SUFFIX ONLY 0.2 0.4 —
Holding Current IH — 10 50 mA
(VD = 12 V, ITM = 200 mA, Gate Open)
Gate Controlled Turn–On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 35 A Peak, IG = 200 mA)
Critical Rate of Rise of Off-State Voltage dv/dt — 40 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 125°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 35 A Peak, Commutating
di/dt = 12.6 A/ms, Gate Unenergized, TC = 80°C)
1. Ratings apply for open gate conditions. Devices shall not be tested with a constant current source for blocking voltage such that the voltage
applied exceeds the rated blocking voltage.

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON-STATE POWER DISSIPATION

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

125
PD, AVERAGE POWER DISSIPATION (WATTS)

40

115
30
105

95 20

85
10
75

0
0 5.0 10 15 20 25 0 5.0 10 15 20 25
IT(RMS), RMS ON–STATE CURRENT (AMPS) IT(RMS), RMS ON–STATE CURRENT (AMPS)

Motorola Thyristor Device Data 33

 MAC223 Series MAC223A Series
FIGURE 3 – GATE TRIGGER CURRENT FIGURE 4 – GATE TRIGGER VOLTAGE

NORMALIZED GATE CURRENT

NORMALIZED GATE VOLTAGE

3.0 3.0
2.0 VD = 12 V 2.0 VD = 12 V
RL = 100 Ω RL = 100 Ω
1.0 1.0

0.5 0.5

0.3 0.3
0.2 0.2

0.1 0.1
– 60 – 40 – 20 0 20 40 60 80 100 120 140 – 60 – 40 – 20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 – HOLD CURRENT FIGURE 6 – TYPICAL ON–STATE CHARACTERISTICS

i TM, INSTANTANEOUS ON–STATE CURRENT (AMPS)

200
NORMALIZED HOLD CURRENT

100
2.0 ITM = 200 mA 50
Gate Open TJ = 25°C
1.0 10
5.0
0.5

0.3 1.0
0.2 0.5

0.1 0.1
– 60 – 40 – 20 0 20 40 60 80 100 120 140 0 1.0 2.0 3.0 4.0
TJ, JUNCTION TEMPERATURE (°C) VTM, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

34 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC223FP
Series
Triacs MAC223AFP
Silicon Bidirectional Triode Thyristors
Series
. . . designed primarily for full-wave ac control applications, such as lighting systems, ISOLATED TRIACs
heater controls, motor controls and power supplies; or wherever full–wave silicon– THYRISTORS
gate–controlled devices are needed. 25 AMPERES RMS
• Off–State Voltages to 800 Volts 200 thru 800 VOLTS
• All Diffused and Glass Passivated Junctions for Parameter Uniformity and Stability
• Small, Rugged Thermowatt Construction for Thermal Resistance and High Heat
Dissipation
• Gate Triggering Guaranteed in Three Modes (MAC223FP Series) or
Four Modes (MAC223AFP Series)

MT2 MT1

G
CASE 221C-02
STYLE 3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC223-4FP, MAC223A4FP 200
MAC223-6FP, MAC223A6FP 400
MAC223-8FP, MAC223A8FP 600
MAC223-10FP, MAC223A10FP 800
On-State RMS Current (TC = +80°C) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 25 Amps
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = 80°C, ITSM 250 Amps
preceded and followed by rated current)
Circuit Fusing (t = 8.3 ms) I2t 260 A2s
Peak Gate Power (t p 2 µs) PGM 20 Watts
Average Gate Power (TC = +80°C, t p 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current (t p 2 µs) IGM 2 Amps
Peak Gate Voltage (t p 2 µs) VGM "10 Volts
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque — 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W

Motorola Thyristor Device Data 35

 MAC223FP Series MAC223AFP Series
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current(1) TJ = 25°C IDRM — — 10 µA
(VD = Rated VDRM, Gate Open) TJ = 125°C — — 2 mA
Peak On-State Voltage VTM — 1.4 1.85 Volts
(ITM = 35 A Peak, Pulse Width p 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(V D = 12 V, R L = 100 Ω)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) — 20 50
MT2(–), G(+) “A” SUFFIX ONLY — 30 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(V D = 12 V, R L = 100 Ω)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.3 2.5
(VD = Rated VDRM, TJ = 125°C, RL = 10 k) 0.2 0.4 —
MT(+), G(+); MT2(–), G(–); MT2(+), G(–)
MT2(–), G(+) “A” SUFFIX ONLY 0.2 0.4 —
Holding Current IH — 10 50 mA
(VD = 12 V, ITM = 200 mA, Gate Open)
Gate Controlled Turn–On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 35 A Peak, IG = 200 mA)
Critical Rate of Rise of Off–State Voltage dv/dt — 40 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 125°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 35 A Peak, Commutating
di/dt = 12.6 A/ms, Gate Unenergized, TC = 80°C)
1. Ratings apply for open gate conditions. Devices shall not be tested with a constant current source for blocking voltage such that the voltage
applied exceeds the rated blocking voltage.
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

PD(AV) , AVERAGE POWER DISSIPATION (WATTS)

125 40

115
30
105

95 20

85
10
75

0
0 5 10 15 20 25 0 5 10 15 20 25
IT(RMS), RMS ON–STATE CURRENT (AMPS) IT(RMS), RMS ON–STATE CURRENT (AMPS)

Figure 1. RMS Current Derating Figure 2. On–State Power Dissipation

36 Motorola Thyristor Device Data

 MAC223FP Series MAC223AFP Series
TYPICAL CHARACTERISTICS

NORMALIZED GATE CURRENT

NORMALIZED GATE VOLTAGE

3 3
2 VD = 12 V 2 VD = 12 V
RL = 100 W RL = 100 W
1 1

0.5 0.5

0.3 0.3
0.2 0.2

0.1 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 3. Gate Trigger Current Figure 4. Gate Trigger Voltage

i TM , INSTANTANEOUS ON–STATE CURRENT (AMPS) 200

NORMALIZED HOLD CURRENT

100
2 ITM = 200 mA 50
TJ = 25°C
GATE OPEN
1 10
5
0.5

0.3 1
0.2 0.5

0.1 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 0 1 2 3 4
TJ, JUNCTION TEMPERATURE (°C) vTM, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

Figure 5. Hold Current Figure 6. Typical On–State Characteristics

Motorola Thyristor Device Data 37

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC224
Series
Triacs MAC224A
Silicon Bidirectional 40 Amperes RMS
Triode Thyristors Series
. . . designed primarily for full-wave ac control applications such as lighting systems,
heater controls, motor controls and power supplies. TRIACs
• Blocking Voltage to 800 Volts 40 AMPERES RMS
• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability 200 thru 800 VOLTS
• Gate Triggering Guaranteed in Three Modes (MAC224 Series) or Four Modes
(MAC224A Series)

MT2 G MT1

CASE 221A-04
(TO-220AB)
STYLE 4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(TJ = –40 to 125°C,
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC224-4, MAC224A4 200
MAC224-6, MAC224A6 400
MAC224-8, MAC224A8 600
MAC224-10, MAC224A10 800
On-State RMS Current (TC = 75°C)(2) IT(RMS) 40 Amps
(Full Cycle Sine Wave 50 to 60 Hz)
Peak Non-repetitive Surge Current ITSM 350 Amps
(One Full Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing (t = 8.3 ms) I2t 500 A2s
Peak Gate Current (t p 2 µs) IGM ±2 Amps
Peak Gate Voltage (t p 2 µs) VGM ±10 Volts
Peak Gate Power (t p 2 µs) PGM 20 Watts
Average Gate Power (TC = 75°C, t p 8.3 ms) PG(AV) 0.5 Watts
Operating Junction Temperature Range TJ –40 to 125 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque — 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source (cont.)
such that the voltage ratings of the devices are exceeded.
2. This device is rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device
is to be used at high sustained currents. (See Figure 1 for maximum case temperatures.)

38 Motorola Thyristor Device Data

 MAC224 Series MAC224A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak On-State Voltage VTM — 1.4 1.85 Volts
(ITM = 56 A Peak, Pulse Width p 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(+), G(–) — 25 50
MT2(–), G(+) “A” SUFFIX ONLY — 40 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(–), G(–); MT(+), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.3 2.5
Gate Non-Trigger Voltage VGD Volts
(VD = Rated VDRM, TJ = 125°C, RL = 10 k)
MT2(+), G(+); MT2(–), G(–); MT(+), G(–) 0.2 — —
MT2(–), G(+) 0.2 — —
Holding Current (VD = 12 Vdc, Gate Open) IH — 30 75 mA
Gate Controlled Turn-On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 56 A Peak, IG = 200 mA)
Critical Rate of Rise of Off-State Voltage dv/dt — 50 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 125°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 56 A Peak, Commutating
di/dt = 20.2 A/ms, Gate Unenergized, TC = 75°C)

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON-STATE POWER DISSIPATION

T C, MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

125 60
PD , AVERAGE POWER DISSIPATION (WATTS)

120 54

115 48
110 42
105 36
100 30
95 24
90 18
85 12
80 6.0
75 0
0 5.0 10 15 20 25 30 35 40 0 5.0 10 15 20 25 30 35 40
IT(RMS), RMS ON-STATE CURRENT (AMPS)* IT(RMS), RMS ON-STATE CURRENT (AMPS)*

*This device is rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device is to
be used at high sustained currents.

Motorola Thyristor Device Data 39

 MAC224 Series MAC224A Series
FIGURE 3 – GATE TRIGGER CURRENT FIGURE 4 – GATE TRIGGER VOLTAGE

NORMALIZED GATE CURRENT

NORMALIZED GATE VOLTAGE

3.0 3.0
2.0 2.0
VD = 12 V VD = 12 V
RL = 100 Ω RL = 100 Ω
1.0 1.0

0.5 0.5
0.3 0.3
0.2 0.2

0.1 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 – HOLDING CURRENT FIGURE 6 – TYPICAL ON-STATE CHARACTERISTICS

I TM, INSTANTANEOUS ON-STATE CURRENT (AMPS)

1000
NORMALIZED HOLD CURRENT

2.0 100
ITM = 200 mA
Gate Open
1.0 TJ = 25°C

0.5 10

0.3
0.2

0.1 1.0
–60 –40 –20 0 20 40 60 80 100 120 140 0 1.0 2.0 3.0
TJ, JUNCTION TEMPERATURE (°C) VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

FIGURE 7 – THERMAL RESPONSE

1
r(t), TRANSIENT THERMAL RESISTANCE

0.5
(NORMALIZED)

0.2
ZθJC(t) = r(t) • RθJC
0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

40 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC228
Series
Triacs MAC228A
Silicon Bidirectional Triode Thyristors Series
. . . designed primarily for industrial and consumer applications for full wave control of
ac loads such as appliance controls, heater controls, motor controls, and other power
switching applications. TRIACs
• Sensitive Gate Triggering in 3 Modes for AC Triggering on Sinking Current 8 AMPERES RMS
Sources (MAC228 Series) 200 thru 800 VOLTS
• Four Mode Triggering for Drive Circuits that Source Current (MAC228A Series)
• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and
Stability
• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High
Heat Dissipation
• Center Gate Geometry for Uniform Current Spreading MT2 G MT1

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(TJ = –40 to 110°C
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC228-4, MAC228A4 200
MAC228-6, MAC228A6 400
MAC228-8, MAC228A8 600
MAC228–10, MAC228A10 800
On-State RMS Current (TC = 80°C) IT(RMS) 8 Amps
Full Cycle Sine Wave 50 to 60 Hz
Peak Non-repetitive Surge Current ITSM 80 Amps
(One Full Cycle 60 Hz, TJ = 110°C)
Circuit Fusing I2t 26 A2s
(t = 8.3 ms)
v 2 µs)
Peak Gate Current (t IGM "2 Amps
v 2 µs)
Peak Gate Voltage (t VGM "10 Volts
Peak Gate Power (t v 2 µs) PGM 20 Watts
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current (continued)
source such that the voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 41

MAC228 Series MAC228A Series
MAXIMUM RATINGS — continued
Rating Symbol Value Unit
Average Gate Power (TC = 80°C, t v 8.3 ms) PG(AV) 0.5 Watts
Operating Junction Temperature Range TJ –40 to 110 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque 8 in. lb.
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(V D = Rated V DRM ) T J = 25°C — — 10 µA
TJ = 110°C — — 2 mA
Peak On-State Voltage VTM — — 1.8 Volts
(ITM = 11 A Peak, Pulse Width v 2 ms, Duty Cycle v 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 5
MT2(–), G(+) “A” Suffix Only — — 10
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 2
MT2(–), G(+) “A” Suffix Only — — 2.5
(VD = Rated VDRM, TC = 110°C, RL = 10 k)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) 0.2 — —
MT2(–), G(+) “A” Suffix Only 0.2 — —
Holding Current IH — — 15 mA
(VD = 12 Vdc, ITM = 200 mA, Gate Open)
Gate–Controlled Turn–On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)
Critical Rate of Rise of Off-State Voltage dv/dt — 25 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 110°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11.3 A,
Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON–STATE POWER DISSIPATION

110 10
dc
α
a = 30° a = 180°
P(AV) , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE (° C)

104 8.0
60° α
90°
α = CONDUCTION ANGLE 120°
98 120° 6.0
90°
180° TJ ≈ 110°C
60°
92 4.0
α 30°

α
86 2.0
dc
α = CONDUCTION ANGLE
80 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
IT(RMS), RMS ON–STATE CURRENT (AMP) IT(RMS), RMS ON–STATE CURRENT (AMP)

42 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC228FP
Triacs Series
MAC228AFP
Silicon Bidirectional Triode Thyristors
Series
. . . designed primarily for industrial and consumer applications for full wave control of
ac loads such as appliance controls, heater controls, motor controls, and other power
switching applications. TRIACs
• Four Mode Triggering for Drive Circuits that Source Current 8 AMPERES RMS
• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and Stability 200 thru 800 VOLTS
• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High
Heat Dissipation
• Center Gate Geometry for Uniform Current Spreading
MT2 MT1
G

CASE 221C-02
STYLE 3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(TJ = –40 to 110°C
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC228-4FP, MAC228A4FP 200
MAC228-6FP, MAC228A6FP 400
MAC228-8FP, MAC228A8FP 600
MAC228-10FP, MAC228A10FP 800
On-State RMS Current (TC = 80°C) IT(RMS) 8 Amps
Full Cycle Sine Wave 50 to 60 Hz
Peak Non–repetitive Surge Current ITSM 80 Amps
(One Full Cycle 60 Hz, TJ = 110°C)
Circuit Fusing I2t 26 A2s
(t = 8.3 ms)
Peak Gate Current (t p 2 µs) IGM "2 Amps
Peak Gate Voltage (t p 2 µs) VGM "10 Volts
Peak Gate Power (t p 2 µs) PGM 20 Watts
Average Gate Power (TC = 80°C, t p 8.3 ms) PG(AV) 0.5 Watts
Operating Junction Temperature Range TJ –40 to 110 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

Motorola Thyristor Device Data 43

MAC228FP Series MAC228AFP Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 110°C — — 2 mA
Peak On-State Voltage VTM — — 1.8 Volts
(ITM = 11 A Peak, Pulse Width p 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 5
MT2(–), G(+) “A” Suffix Only — — 10
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 2
MT2(–), G(+) “A” Suffix Only — — 2.5
(VD = Rated VDRM, TC = 110°C, RL = 10 k)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) 0.2 — —
MT2(–), G(+) “A” Suffix Only 0.2 — —
Holding Current IH — — 15 mA
(VD = 12 Vdc, ITM = 200 mA, Gate Open)
Gate–Controlled Turn–On Time t gt — 1.5 — µs
(VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)
Critical Rate of Rise of Off–State Voltage dv/dt — 25 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 110°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11.3 A,
Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)

FIGURE 1 – RMS CURRENT DERATING FIGURE 2 – ON–STATE POWER DISSIPATION

110 10
dc
α
a = 30° a = 180°
P(AV) , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE (° C)

104 8.0
60° α
90°
α = CONDUCTION ANGLE 120°
98 120° 6.0
90°
180° TJ ≈ 110°C
60°
92 4.0
α 30°

α
86 2.0
dc
α = CONDUCTION ANGLE
80 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
IT(RMS), RMS ON–STATE CURRENT (AMP) IT(RMS), RMS ON–STATE CURRENT (AMP)

44 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC229
Triacs Series
Silicon Bidirectional Triode Thyristors MAC229A
. . . designed primarily for industrial and consumer applications for full wave control of Series
ac loads such as appliance controls, heater controls, motor controls, and other power
switching applications.
• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and
TRIACs
Stability
8 AMPERES RMS
• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High
200 thru 800 VOLTS
Heat Dissipation
• Center Gate Geometry for Uniform Current Spreading
• Gate Triggering Guaranteed in Three Modes (MAC229 Series) or Four Modes
(MAC229A Series)

MT2 G MT1

CASE 221A-04
(TO-220AB)
STYLE 4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(TJ = –40 to 110°C
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC229-4, MAC229A4 200
MAC229-6, MAC229A6 400
MAC229-8, MAC229A8 600
MAC229–10, MAC229A10 800
On-State RMS Current (TC = 80°C) IT(RMS) 8 Amps
Full Cycle Sine Wave 50 to 60 Hz
Peak Non-repetitive Surge Current ITSM 80 Amps
(One Full Cycle 60 Hz, TJ = 110°C)
Circuit Fusing I2t 26 A2s
(t = 8.3 ms)
Peak Gate Current (t v 2 µs) IGM "2 Amps
Peak Gate Voltage (t v 2 µs) VGM "10 Volts
Peak Gate Power (t v 2 µs) PGM 20 Watts
Average Gate Power PG(AV) 0.5 Watts
(TC = 80°C, t v
8.3 ms)
Operating Junction Temperature Range TJ –40 to 110 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source (cont.)
such that the voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 45

MAC229 Series MAC229A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current(1) IDRM
(V D = Rated V DRM , Gate Open) T J = 25°C — — 10 µA
TJ = 110°C — — 2 mA
Peak On-State Voltage VTM — — 1.8 Volts
(ITM = 11 A Peak, Pulse Width v 2 ms, Duty Cycle v 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 10
MT2(–), G(+) “A” SUFFIX ONLY — — 15
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 2
MT2(–), G(+) “A” SUFFIX ONLY — — 2.5
(VD = Rated VDRM, TC = 110°C, RL = 10 k)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) All Types 0.2 — —
MT2(–), G(+) “A” SUFFIX ONLY MAC229 series 0.2 — —
Holding Current IH — — 15 mA
(VD = 12 Vdc, ITM = 200 mA, Gate Open)
Gate–Controlled Turn–On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)
Critical Rate of Rise of Off-State Voltage dv/dt — 25 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 110°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11.3 A,
Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)
1. Ratings apply for open gate conditions. Devices shall not be tested with a constant current source for blocking voltage such that the voltage
applied exceeds the rated blocking voltage.

110 10
dc
α
a = 30° a = 180°
P(AV) , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE (° C)

104 8.0
60° α
90°
α = CONDUCTION ANGLE 120°
98 120° 6.0
90°
180° TJ ≈ 110°C
60°
92 4.0
α 30°

α
86 2.0
dc
α = CONDUCTION ANGLE
80 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
IT(RMS), RMS ON–STATE CURRENT (AMP) IT(RMS), RMS ON–STATE CURRENT (AMP)

46 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC229FP
Triacs Series
MAC229AFP
Silicon Bidirectional Triode Thyristors
Series
. . . designed primarily for industrial and consumer applications for full wave control of
ac loads such as appliance controls, heater controls, motor controls, and other power
switching applications. TRIACs
• All Diffused and Glass–Passivated Junctions for Parameter Uniformity and Stability 8 AMPERES RMS
• Small, Rugged, Thermowatt Construction for Low Thermal resistance and High 200 thru 800 VOLTS
Heat Dissipation
• Center Gate Geometry for Uniform Current Spreading
• Gate Triggering Guaranteed in Three Modes (MAC229FP Series) or Four Modes
(MAC229AFP Series)
MT2 MT1
G

CASE 221C-02
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(TJ = –40 to 110°C,
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC229-4FP, MAC229A4FP 200
MAC229-6FP, MAC229A6FP 400
MAC229-8FP, MAC229A8FP 600
MAC229-10FP, MAC229A10FP 800
On-State RMS Current (TC = 80°C) IT(RMS) 8 Amps
Full Cycle Sine Wave 50 to 60 Hz
Peak Non–repetitive Surge Current ITSM 80 Amps
(One Full Cycle 60 Hz, TJ = 110°C)
Circuit Fusing I2t 26 A2s
(t = 8.3 ms)
Peak Gate Current (t p 2 µs) IGM "2 Amps
Peak Gate Voltage (t p 2 µs) VGM "10 Volts
Peak Gate Power (t p 2 µs) PGM 20 Watts
Average Gate Power PG(AV) 0.5 Watts
(TC = 80°C, t p
8.3 ms)
Operating Junction Temperature Range TJ –40 to 110 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

Motorola Thyristor Device Data 47

MAC229FP Series MAC229AFP Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current (1) IDRM
(VD = Rated VDRM, Open Gate) TJ = 25°C — — 10 µA
TJ = 110°C — — 2 mA
Peak On-State Voltage VTM — — 1.8 Volts
(ITM = 11 A Peak, Pulse Width p 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 5
MT2(–), G(+) “A” Suffix Only — — 10
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 2
MT2(–), G(+) “A” Suffix Only — — 2.5
(VD = Rated VDRM, TC = 110°C, RL = 10 k)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) 0.2 — —
MT2(–), G(+) “A” Suffix Only 0.2 — —
Holding Current IH — — 15 mA
(VD = 12 Vdc, ITM = 200 mA, Gate Open)
Gate–Controlled Turn–On Time t gt — 1.5 — µs
(VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)
Critical Rate of Rise of Off–State Voltage dv/dt — 25 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 110°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 11.3 A,
Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80°C)
1. Ratings apply for open gate conditions. Devices shall not be tested with a constant current source for blocking voltage such that the voltage
applied exceeds the rated blocking voltage.

110 10
dc
α
a = 30° a = 180°
P(AV) , AVERAGE POWER (WATTS)
TC , CASE TEMPERATURE (° C)

104 8.0
60° α
90°
α = CONDUCTION ANGLE 120°
98 120° 6.0
90°
180° TJ ≈ 110°C
60°
92 4.0
α 30°

α
86 2.0
dc
α = CONDUCTION ANGLE
80 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
IT(RMS), RMS ON–STATE CURRENT (AMP) IT(RMS), RMS ON–STATE CURRENT (AMP)

48 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triacs MAC310
Series
MAC310A
Silicon Bidirectional Triode Thyristors
. . . designed primarily for industrial and consumer applications for full wave control of
ac loads such as appliance controls, heater controls, motor controls, and other power Series
switching applications.
• Sensitive Gate Triggering in Three Trigger Modes for AC Triggering on Sinking
Current Sources (MAC310 Series)
TRIACs
• Four Mode Triggering (10 mA) for Drive Circuits that Source Current (MAC310A
10 AMPERES RMS
Series)
200 thru 600 VOLTS
• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation
• Center Gate Geometry for Uniform Current Spreading
MT2 MT1
G

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TC = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) (TJ = –40 to 110°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open) MAC310-4, MAC310A4 200
MAC310-6, MAC310A6 400
MAC310-8, MAC310A8 600
On-State RMS Current (TC = 80°C) IT(RMS) 10 Amps
Full Cycle Sine Wave 50 to 60 Hz
Peak Non-repetitive Surge Current ITSM 100 Amps
(One Full Cycle 60 Hz, TJ = 110°C)
Circuit Fusing (t = 8.3 ms) I2t 40 A2s
Peak Gate Current (t p 2 µs) IGM ±2 Amps
Peak Gate Voltage (t p 2 µs) VGM ±10 Volts
Peak Gate Power (t p 2 µs) PGM 20 Watts
Average Gate Power (TC = 80°C, t p 8.3 ms) PG(AV) 0.5 Watts
Operating Junction Temperature Range TJ –40 to 110 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque — 8 in-lb
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant (continued)
current source such that the voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 49

 MAC310 Series MAC310A Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current TJ = 25°C IDRM — — 10 mA
(VD = Rated VDRM, TJ = 110°C) — — 2
Peak On-State Voltage VTM — — 2 Volts
(ITM = 14 A Peak, Pulse Width p 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 5
MT2(–), G(+) “A” Suffix Only — — 10
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω)
MT2(+), G(+); MT2(+), G(–); MT2(–), G(–) — — 2
MT2(–), G(+) “A” Suffix Only — — 2.5
(VD = Rated VDRM, TC = 110°C, RL = 10 k)
All Trigger Modes 0.2 — —
Holding Current IH — — 15 mA
(VD = 12 V, ITM = 200 mA, Gate Open)
Gate-Controlled Turn-On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 14 A Peak, IG = 30 mA)
Critical Rate of Rise of Off-State Voltage dv/dt — 25 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 110°C)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 14 A Peak,
Commutating di/dt = 5 A/ms, Gate Unenergized, TC = 80°C)

20
PAV , AVERAGE POWER (WATTS)
TC, CASE TEMPERATURE ( °C)

120 16
dc
110 12 180°
120°
90°
60°
100 8
30°
30°
60°
90 90° 4
180°
80 dc 0
0 2 4 6 8 10 0 2 4 6 8 10
IT(RMS), RMS ON-STATE CURRENT (AMPS) IT(RMS), RMS ON-STATE CURRENT (AMPS)

Figure 7. RMS Current Derating Figure 8. On-State Power Dissipation

50 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC320
Triacs Series
Silicon Bidirectional Thyristors MAC320A
. . . designed primarily for full-wave ac control applications, such as solid-state relays, Series
motor controls, heating controls and power supplies; or wherever full-wave silicon
gate controlled solid-state devices are needed. Triac type thyristors switch from a
blocking to a conducting state for either polarity of applied anode voltage with positive TRIACs
or negative gate triggering. 20 AMPERES RMS
• Blocking Voltage to 800 Volts 200 thru 800 VOLTS
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability MT1
• Gate Triggering Guaranteed in Three Modes (MAC320 Series) or Four Modes MT2 G
(MAC320A Series)

CASE 221A-04
(TO-220AB)
STYLE 4
MAXIMUM RATINGS (TC = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open)
200
MAC320-4, MAC320A4 400
MAC320-6, MAC320A6 600
MAC320-8, MAC320A8 800
MAC320-10, MAC320A10
Peak Gate Voltage VGM 10 Volts
On-State Current RMS (TC = +75°C) IT(RMS) 20 Amp
(Full Cycle, Sine Wave, 50 to 60 Hz)
Peak Surge Current (One Full Cycle, 60 Hz, T C = +75°C) ITSM 150 Amp
preceded and followed by rated current
Peak Gate Power (T C = +75°C, Pulse Width = 2 µs) PGM 20 Watts
Average Gate Power (T C = +75°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current IGM 2 Amp
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.8 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 51

MAC320 Series MAC320A Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = +125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.4 1.7 Volts
(ITM = 28 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2 (+), G(+); MT2 (+), G(–); MT2 (–), G(–) — — 50
MT2 (–), G(+) “A” SUFFIX ONLY — — 75
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) — 0.9 2
MT2 (+), G(+); MT2 (+), G(–); MT2 (–), G(–) — 1.4 2.5
MT2 (–), G(+) “A” SUFFIX ONLY
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ =+110°C)
MT2 (+), G(+); MT2 (–), G(–); MT2 (+), G(–); 0.2 — —
MT2 (–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 40 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 200 mA)
Turn-On Time t gt — 1.5 — µs
(VD = Rated VDRM, ITM = 28 A,
IGT = 120 mA, Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(C) — 5 — V/µs
(VD = Rated VDRM, ITM = 28 A, Commutating
di/dt = 10 A/ms, Gate Unenergized, TC = +75°C)

FIGURE 1 — RMS CURRENT DERATING FIGURE 2 — ON-STATE POWER DISSIPATION

TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)

130 40

120 α
PD(AV) , AVERAGE POWER (WATT)

35
α = 30° α dc
110 60° 30 180°
90° α = Conduction 90°
100 25 Angle
90 20

80 α 15
180° 60°
70 α dc 10 α = 30°
60 α = Conduction 5.0
Angle
50 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

52 Motorola Thyristor Device Data

 MAC320 Series MAC320A Series
FIGURE 3 — TYPICAL GATE TRIGGER VOLTAGE FIGURE 5 — MAXIMUM ON-STATE CHARACTERISTICS
VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)
3 100
OFF-STATE VOLTAGE = 12 Vdc
ALL MODES 70
2
50
TJ = 25°C
125°C
30
1
20
0.7

i TM , INSTANTANEOUS FORWARD CURRENT (AMP)

0.5
10

7
0.3
–60 –40 –20 0 20 40 60 80 100 120 140 5
TJ, JUNCTION TEMPERATURE (°C)

3
FIGURE 4 — TYPICAL GATE TRIGGER CURRENT
2
I GTM , GATE TRIGGER CURRENT (NORMALIZED)

3
OFF-STATE VOLTAGE = 12 Vdc
ALL MODES
2 1

0.7

0.5
1

0.3
0.7

0.2
0.5

0.3 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
TJ, JUNCTION TEMPERATURE(°C) vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

Motorola Thyristor Device Data 53

 MAC320 Series MAC320A Series
FIGURE 6 — TYPICAL HOLDING CURRENT FIGURE 7 — MAXIMUM ON-REPETITIVE SURGE CURRENT
3 300
GATE OPEN
I H , HOLDING CURRENT (NORMALIZED)

TSM , PEAK SURGE CURRENT (AMP)

APPLIES TO EITHER DIRECTION
2 200

1 100

0.7 70

0.5 50
TC = 80°C
f = 60 Hz
Surge is preceded and followed by rated current
0.3 30
–60 –40 –20 0 20 40 60 80 100 120 140 1 2 3 5 7 10
NUMBER OF CYCLES
TJ, JUNCTION TEMPERATURE (°C)

FIGURE 8 — THERMAL RESPONSE

1
r(t), TRANSIENT THERMAL RESISTANCE

0.5
(NORMALIZED)

0.2
ZθJC(t) = r(t) • RθJC
0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

54 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MAC320FP
Triacs Series
Silicon Bidirectional Thyristors MAC320AFP
. . . designed primarily for full-wave ac control applications, such as solid-state relays, Series
motor controls, heating controls and power supplies; or wherever full-wave silicon
gate controlled solid-state devices are needed. Triac type thyristors switch from a
blocking to a conducting state for either polarity of applied anode voltage with positive ISOLATED TRIACs
or negative gate triggering. THYRISTORS
• Blocking Voltage to 800 Volts 20 AMPERES RMS
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity 200 thru 800 VOLTS
and Stability
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Gate Triggering Guaranteed in Three Modes (MAC320FP Series) or
Four Modes (MAC320AFP Series)

MT2 MT1
CASE 221C-02
G
STYLE 3

MAXIMUM RATINGS (TC = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Gate Open)
MAC320-4FP, MAC320A4FP 200
MAC320-6FP, MAC320A6FP 400
MAC320-8FP, MAC320A8FP 600
MAC320-10FP, MAC320A10FP 800
Peak Gate Voltage VGM 10 Volts
On-State RMS Current (TC = +75°C, Full Cycle Sine Wave 50 to 60 Hz)(2) IT(RMS) 20 Amps
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, T C = +75°C, ITSM 150 Amps
preceded and followed by rated current)
Peak Gate Power (T C = +75°C, Pulse Width = 2 µs) PGM 20 Watts
Average Gate Power (T C = +75°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current IGM 2 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.8 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all T C measurements is a point on the center lead of the package as close as possible to the
plastic body.

Motorola Thyristor Device Data 55

 MAC320FP Series MAC320AFP Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = +125°C — — 2 mA
Peak On-State Voltage (Either Direction) VTM — 1.4 1.7 Volts
(ITM = 28 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p 2%)
Peak Gate Trigger Current IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms
Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) — — 50
MT2(+), G(–) — — 50
MT2(–), G(–) — — 50
MT2(–), G(+) “A” SUFFIX ONLY — — 75
Peak Gate Trigger Voltage VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms
Minimum Gate Pulse Width = 2 µs)
MT2(+), G(+) — 0.9 2
MT2(+), G(–) — 0.9 2
MT2(–), G(–) — 1.1 2
MT2(–), G(+) “A” SUFFIX ONLY — 1.4 2.5
(Main Terminal Voltage = Rated VDRM, RL = 10 , TJ = +110°C)
MT2(+), G(+); MT2(+), G(–) 0.2 — —
MT2(–), G(–); MT2(–), G(+) “A” SUFFIX ONLY 0.2 — —
Holding Current (Either Direction) IH — 6 40 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 200 mA)
Turn-On Time t gt — 1.5 10 µs
(VD = Rated VDRM, ITM = 28 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2 µs)
Critical Rate of Rise of Commutation Voltage dv/dt(c) — 5 — V/µs
(VD = Rated VDRM, ITM = 28 A, Commutating di/dt = 10 A/ms,
Gate Unenergized, TC = +75°C)

TYPICAL CHARACTERISTICS
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)

130 40

120 α
PD(AV) , AVERAGE POWER (WATT)

35
α = 30° α dc
110 60° 30 180°
90° α = Conduction 90°
100 25 Angle
90 20

80 α 15
180° 60°
70 α dc 10 α = 30°
60 α = Conduction 5.0
Angle
50 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

Figure 9. RMS Current Derating Figure 10. On-State Power

Dissipation

56 Motorola Thyristor Device Data

 MAC320FP Series MAC320AFP Series
VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)
3 100
OFF-STATE VOLTAGE = 12 Vdc
ALL MODES 70
2
50
TJ = 25°C
125°C
30
1
20
0.7

i TM , INSTANTANEOUS FORWARD CURRENT (AMP)

0.5
10

0.3 7
–60 –40 –20 0 20 40 60 80 100 120 140
5
TJ, JUNCTION TEMPERATURE (°C)

Figure 11. Typical Gate Trigger Voltage 3

2
I GTM , GATE TRIGGER CURRENT (NORMALIZED)

3
OFF-STATE VOLTAGE = 12 Vdc
ALL MODES
2 1

0.7

0.5
1

0.3
0.7

0.2
0.5

0.3 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
TJ, JUNCTION TEMPERATURE (°C) vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

Figure 12. Typical Gate Trigger Current Figure 13. Maximum On-State
Characteristics

Motorola Thyristor Device Data 57

 MAC320FP Series MAC320AFP Series
3 300
GATE OPEN
I H , HOLDING CURRENT (NORMALIZED)

TSM , PEAK SURGE CURRENT (AMP)

APPLIES TO EITHER DIRECTION
2 200

1 100

0.7 70

0.5 50
TC = 80°C
f = 60 Hz
SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT
0.3 30
–60 –40 –20 0 20 40 60 80 100 120 140 1 2 3 5 7 10
TJ, JUNCTION TEMPERATURE (°C) NUMBER OF CYCLES
Figure 14. Typical Holding Figure 15. Maximum Nonrepetitive Surge Current
Current
1
r(t), TRANSIENT THERMAL RESISTANCE

0.5

0.2
(NORMALIZED)

ZθJC(t) = r(t) • RθJC

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

Figure 16. Thermal Response

58 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triacs MAC321
Silicon Bidirectional Thyristors Series
. . . designed for full-wave ac control applications primarily in industrial environments
needing noise immunity.
• Guaranteed High Commutation Voltage
dv/dt — 500 V/µs Min @ TC = 25°C TRIACs
• High Blocking Voltage — VDRM to 800 V 20 AMPERES RMS
• Photo Glass Passivated Junction for Improved Power Cycling Capability and 200 thru 800 VOLTS
Reliability

MT2 MT1
G

CASE 221A-04
(TO-220AB)
STYLE 4
MAXIMUM RATINGS (TC = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) (TJ = –40 to +125°C, VDRM Volts
1/2 Sine Wave 50 to 60 Hz, Open Gate)
MAC321-4 200
MAC321-6 400
MAC321-8 600
MAC321-10 800
Peak Gate Voltage VGM 10 Volts
On-State Current RMS (TC = +75°C IT(RMS) 20 Amp
Full Cycle Sine Wave 50 to 60 Hz)
Peak Surge Current (One Full Cycle, 60 Hz, T C = +75°C ITSM 150 Amp
preceded and followed by Rated Current)
Circuit Fusing Considerations (t = 8.3 ms) I2t 93 A2s
Peak Gate Power (T C = +75°C, Pulse Width = 2.0 µs) PGM 20 Watts
Average Gate Power (T C = +75°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current IGM 2.0 Amp
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.8 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 59

 MAC321 Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open)
TJ = 25°C — — 10 µA
TJ = +125°C — — 2.0 mA
Peak On-State Voltage (Either Direction) VTM — 1.4 1.7 Volts
(ITM = 28 A Peak; Pulse Width p 2.0 ms, Duty Cycle p 2.0%)
Gate Trigger Current (Continuous dc) IGT mA
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — — 100
MT2(+), G(–) — — 100
MT2(–), G(–) — — 100
Gate Trigger Voltage (Continuous dc) VGT Volts
(Main Terminal Voltage = 12 Vdc, RL = 100 Ohms)
MT2(+), G(+) — — 2.0
MT2(+), G(–) — — 2.0
MT2(–), G(–) — — 2.0
(Main Terminal Voltage = Rated VDRM, RL = 10 kΩ, TJ = +125°C)
MT2(+), G(+); MT2(–), G(–); MT2(+), G(–) 0.2 — —
Holding Current (Either Direction) IH — — 100 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 200 mA)
Turn-On Time tgt — 1.5 — µs
(VD = Rated VDRM, ITM = 28 A, IGT = 120 mA,
Rise Time = 0.1 µs, Pulse Width = 2.0 µs)
Critical Rate of Rise of Off-State Voltage dv/dt(s) V/µs
(VD = Rated VDRM, Exponential Voltage Rise, Gate Open)
TJ = 25°C 500 — —
TJ = +125°C 200 — —

TYPICAL CHARACTERISTICS
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)

130 40

120 α
PD(AV) , AVERAGE POWER (WATT)

35
α = 30° α dc
110 60° 30 180°
90° 90°
α = CONDUCTION
100 25 ANGLE
90 20

80 α 15
180° 60°
70 α dc 10 α = 30°
60 α = CONDUCTION 5
ANGLE
50 0
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

Figure 17. RMS Current Figure 18. On-State Power

Derating Dissipation

60 Motorola Thyristor Device Data

 MAC321 Series

VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)

3 100
OFF-STATE VOLTAGE = 12 Vdc
ALL MODES 70
2
50
TJ = 25°C
125°C
30
1
20
0.7

i TM , INSTANTANEOUS FORWARD CURRENT (AMP)

0.5
10

0.3 7
–60 –40 –20 0 20 40 60 80 100 120 140
5
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Typical Gate Trigger Voltage 3

2
I GTM , GATE TRIGGER CURRENT (NORMALIZED)

3
OFF-STATE VOLTAGE = 12 Vdc
ALL MODES
2 1

0.7

0.5
1

0.3
0.7

0.2
0.5

0.3 0.1
–60 –40 –20 0 20 40 60 80 100 120 140 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4
TJ, JUNCTION TEMPERATURE(°C) vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

Figure 20. Typical Gate Trigger Current Figure 21. Maximum On–State Characteristics

3 300
GATE OPEN
I H , HOLDING CURRENT (NORMALIZED)

TSM , PEAK SURGE CURRENT (AMP)

APPLIES TO EITHER DIRECTION

2 200

1 100

0.7 70

0.5 50
TC = 80°C
f = 60 Hz
SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT
0.3 30
–60 –40 –20 0 20 40 60 80 100 120 140 1 2 3 5 7 10
NUMBER OF CYCLES
TJ, JUNCTION TEMPERATURE (°C)

Figure 22. Typical Holding Figure 23. Maximum On-Repetitive Surge

Current Current

Motorola Thyristor Device Data 61

 MAC321 Series
1
r(t), TRANSIENT THERMAL RESISTANCE
0.5

0.2
(NORMALIZED)

ZθJC(t) = r(t) • RθJC

0.1

0.05

0.02

0.01
0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1k 2k 5k 10 k
t, TIME (ms)

Figure 24. Thermal

Response

62 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MBS4991
Silicon Bidirectional Switches MBS4992
Diode Thyristors MBS4993
. . . designed for full-wave triggering in Triac phase control circuits, half-wave SCR
triggering application and as voltage level detectors. Supplied in an inexpensive
plastic TO-226AA package for high-volume requirements, this low-cost plastic
SBS
package is readily adaptable for use in automatic insertion equipment.
(PLASTIC)
• Low Switching Voltage — 8 Volts Typical
• Uniform Characteristics in Each Direction
• Low On-State Voltage — 1.7 Volts Maximum
• Low Off-State Current — 0.1 µA Maximum
• Low Temperature Coefficient — 0.02 %/°C Typical
MT2 MT1

MT1
G
MT2
CASE 29-04
(TO-226AA)
STYLE 12
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Power Dissipation PD 500 mW
DC Forward Current IF 200 mA
DC Gate Current (Off-State Only) IG(off) 5 mA
Repetitive Peak Forward Current IFM(rep) 2 Amps
(1% Duty Cycle, 10 µs Pulse Width, TA = 100°C)
Non-repetitive Forward Current IFM(nonrep) 6 Amps
(10 µs Pulse Width, TA = 25°C)
Operating Junction Temperature Range TJ –55 to +125 °C
Storage Temperature Range Tstg –65 to +150 °C

REV 2

Motorola Thyristor Device Data 63

 MBS4991 MBS4992 MBS4993
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Switching Voltage MBS4991 VS 6 8 10 Vdc
MBS4992, MBS4993 7.5 8 9
Switching Current MBS4991 IS — 175 500 µAdc
MBS4992 — 90 120
MBS4993 175 250
Switching Voltage Differential (See Figure 10) MBS4991 ȧVS1–VS2ȧ — 0.3 0.5 Vdc
MBS4992, MBS4993 — 0.1 0.2
Gate Trigger Current MBS4992 IGF — — 100 µAdc
(VF = 5 Vdc, RL = 1 k ohm) MBS4993 — — 500
Holding Current MBS4991 IH — 0.7 1.5 mAdc
MBS4992 — 0.2 0.5
MBS4993 — 0.3 0.75
Off-State Blocking Current IB µAdc
(VF = 5 Vdc, TA = 25°C) MBS4991 — 0.08 1
(VF = 5 Vdc, TA = 85°C) MBS4991 — 2 10
(VF = 5 Vdc, TA = 25°C) MBS4992, MBS4993 — 0.08 0.1
(VF = 5 Vdc, TA = 100°C) MBS4992, MBS4993 — 6 10
Forward On-State Voltage VF Vdc
(IF = 175 mAdc) MBS4991 — 1.4 1.7
(IF = 200 mAdc) MBS4992, MBS4993 — 1.5 1.7
Peak Output Voltage (Cc = 0.1 µF, RL = 20 ohms, (Figure 7) Vo 3.5 4.8 — Vdc
Turn-On Time (Figure 8) t on — 1 — µs
Turn-Off Time (Figure 9) t off — 30 — µs
Temperature Coefficient of Switching Voltage (–50 to +125°C) TC — +0.02 — %/°C
Switching Current Differential (See Figure 10) IS1–IS2 — — 100 µA

TYPICAL ELECTRICAL CHARACTERISTICS

FIGURE 1 – SWITCHING VOLTAGE versus TEMPERATURE FIGURE 2 – SWITCHING CURRENT versus TEMPERATURE
1.04 8.0
VS , SWITCHING VOLTAGE (NORMALIZED)

I S , SWITCHING CURRENT (NORMALIZED)

1.03 7.0

1.02 6.0

1.01 5.0

1.00 4.0

0.99 3.0

0.98 2.0

0.97 1.0

0.96 0
–75 –50 –25 0 +25 +50 +75 +100 +125 –75 –50 –25 0 +25 +50 +75 +100 +125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

64 Motorola Thyristor Device Data

 MBS4991 MBS4992 MBS4993
FIGURE 3 – HOLDING CURRENT versus TEMPERATURE FIGURE 4 – OFF-STATE BLOCKING CURRENT
versus TEMPERATURE
8.0 10.0

I B , OFF-STATE BLOCKING CURRENT ( µA)

I H , HOLDING CURRENT (NORMALIZED)

7.0
Normalized VF = 5.0 V
6.0 to
25°C 1.0
5.0

4.0

3.0
0.1
2.0

1.0
0 0.01
–75 –50 –25 0 +25 +50 +75 +100 +125 –50 –25 0 +25 +50 +75 +100 +125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

FIGURE 5 – ON-STATE VOLTAGE versus FORWARD CURRENT FIGURE 6 – PEAK OUTPUT VOLTAGE (FUNCTION OF RL AND Cc)

10 7.0
I F, FORWARD ON-STATE CURRENT (AMP)

Vo, PEAK OUTPUT VOLTAGE (VOLTS)

6.0

1.0 5.0

4.0
RL = 500 Ω
3.0 RL = 100 Ω
0.1 RL = 50 Ω
2.0 RL = 20 Ω
RL = 5 Ω
1.0
TA = 25°C
0.01 0
0 1.0 2.0 3.0 4.0 5.0 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
VF, FORWARD ON-STATE VOLTAGE (VOLTS) Cc, CHARGING CAPACITANCE (µF)

FIGURE 7 – PEAK OUTPUT VOLTAGE TEST CIRCUIT

10 K Cc

15 V
Vin D.U.T. RL 0
10 ms V0
MIN

Motorola Thyristor Device Data 65

MBS4991 MBS4992 MBS4993
FIGURE 8 – TURN-ON TIME TEST CIRCUIT
Mercury Relay

1.0 kΩ
Anode
Voltage VS

+
12 V 1.0 kΩ D.U.T.
– 0.01 µF

+
ton VF
VF + 0.1 (VS–VF)

Turn-on time is measured from the time V S is achieved to the time when the anode voltage drops to within 90% of the difference between V S
and V F.

FIGURE 9 – TURN-OFF TIME TEST CIRCUIT

+I
VF1

100 Ω 500 Ω
+ IH1 VS1
C
5.0 V MT2 IS1
IS1
–
–V +V
Mercury IS2
Relay D.U.T. IB1
(N.O.) VS2
IH2
MT1

VF2
–I
CHARACTERISTICS

With the SBS in conduction and the relay contacts open, close the contacts to cause anode A2 to be driven negative. Decrease C until the SBS just
remains off when anode A2 becomes positive. The turn off time, toff, is the time from initial contact closure and until anode A2 voltage reaches
zero volts.

FIGURE 10 – DEVICE EQUIVALENT CIRCUIT, CHARACTERISTICS AND SYMBOLS

MT2 +I
VF1

MT2
IH1 VS1
IS1
IS1
G G –V +V
IS2
IB1
VS2
IH2
MT1
CIRCUIT SYMBOL
VF2
MT1 –I
EQUIVALENT CIRCUIT CHARACTERISTICS

66 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

SOTĆ223 SCR MCR08BT1

Silicon Controlled Rectifiers Series*
*Motorola preferred devices
Reverse Blocking Triode Thyristors
PNPN devices designed for line powered consumer applications such as relay and
lamp drivers, small motor controls, gate drivers for larger thyristors, and sensing and SCR
detection circuits. Supplied in surface mount package for use in automated 0.8 AMPERE RMS
manufacturing. 200 thru 600 Volts
• Sensitive Gate Trigger Current
• Blocking Voltage to 600 Volts
• Glass Passivated Surface for Reliability and Uniformity
• Surface Mount Package
• Devices Supplied on 1 K Reel

CASE 318E-04
(SOT-223)
STYLE 10

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM, VRRM Volts
(1/2 Sine Wave, RGK = 1000 Ω, TJ = 25 to 110°C)
MCR08BT1 200
MCR08DT1 400
MCR08MT1 600
On-State Current RMS (TC = 80°C) IT(RMS) 0.8 Amps
Peak Non-repetitive Surge
g Current ITSM 10 Amps
(One Full Cycle, 60 Hz, TC = 25°C)

Circuit Fusing Considerations (t = 8.3 ms) I2t 0.4 A2s

Peak Gate Power, Forward, TA = 25°C PGM 0.1 Watts
Average Gate Power (TC = 80°C, t = 8.3 ms) PG(AV) 0.01 Watts
Operating Junction Temperature Range TJ –40 to +110 °C
Storage Temperature Range Tstg –40 to +150 °C
Maximum Device Temperature for Soldering Purposes (for 10 Seconds Maximum) TL 260 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Ambient RθJA 156 °C/W
PCB Mounted per Figure 1
Thermal Resistance, Junction to Tab RθJT 25 °C/W
Measured on Anode Tab Adjacent to Epoxy
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant source such
that the voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola Thyristor Device Data 67

MCR08BT1 Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted, RGK = 1 KΩ)
Characteristic Symbol Min Typ Max Unit
Peak Repetitive Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, RGK = 1000 Ω) TJ = 25°C — — 10 µA
TJ = 110°C — — 200 µA
Maximum On-State Voltageg (Either
( Direction)*
) VTM — — 1.7 Volts
(IT = 1.0 A Peak, TA = 25°C)

Gate Trigger
gg Current ((Continuous dc)) IGT — — 200 µA
µ
(Anode Voltage = 7.0 Vdc, RL = 100 Ω)

Holding Current IH — — 5.0 mA

(VD = 7.0 Vdc,
Initializing Current = 20 mA, RGK = 1000 Ω)
Gate Trigger
gg Voltage
g ((Continuous dc)) VGT — — 0.8 Volts
(Anode Voltage = 7.0 Vdc, RL = 100 Ω)

Critical Rate-of-Rise of Off State Voltage

g dv/dt 10 — — µ
V/µs
(Vpk = Rated VDRM, TC = 110°C, RGK = 1000 Ω, Exponential Method)

* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

0.15
3.8
0.079
2.0

0.244
0.091 0.091
6.2
2.3 2.3
0.079
2.0

0.059 0.059 0.059 ǒinchesǓ BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.
mm
0.984 1.5 1.5 1.5 BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.
25.0 MATERIAL: G10 FIBERGLASS BASE EPOXY

0.096 0.096 0.096

2.44 2.44 2.44

0.059 0.059
1.5 1.5

0.472
12.0

Figure 25. PCB for Thermal Impedance and

Power Testing of SOT-223

68 Motorola Thyristor Device Data

 MCR08BT1 Series

IT, INSTANTANEOUS ON-STATE CURRENT (AMPS)

10 160
150 TYPICAL L
140

THERMAL RESISTANCE, ( °C/W)

MAXIMUM

R θJA , JUNCTION TO AMBIENT

130
120 DEVICE MOUNTED ON L
1.0 FIGURE 1 AREA = L2 4
110 PCB WITH TAB AREA
100 AS SHOWN
90 1 2 3
80
0.1 70
TYPICAL AT TJ = 110°C 60
50 MINIMUM
MAX AT TJ = 110°C
40 FOOTPRINT = 0.076 cm2
MAX AT TJ = 25°C
0.01 30
0 1.0 2.0 3.0 4.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) FOIL AREA (cm2)

Figure 26. On-State Characteristics Figure 27. Junction to Ambient Thermal

Resistance versus Copper Tab Area

110 110
1.0 cm2 FOIL, 50 OR
100 100 60 Hz HALFWAVE
50 OR 60 Hz HALFWAVE α dc
AMBIENT TEMPERATURE ( °C)

AMBIENT TEMPERATURE ( °C)

α = CONDUCTION
T A , MAXIMUM ALLOWABLE

T A , MAXIMUM ALLOWABLE
90 90
ANGLE 180°
80 80
dc 120°
70 70
180°
60 60 α = 30°
120° 60°
50 50
α = 30°
40 40 90°
60° α
90°
30 30 α = CONDUCTION
ANGLE
20 20
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
IT(AV), AVERAGE ON-STATE CURRENT (AMPS) IT(AV), AVERAGE ON-STATE CURRENT (AMPS)

Figure 28. Current Derating, Minimum Pad Figure 29. Current Derating, 1.0 cm Square
Size Pad
Reference: Ambient Temperature Reference: Ambient Temperature
110 110
PAD AREA = 4.0 cm2, 50 50 OR 60 Hz HALFWAVE
dc
OR 60 Hz HALFWAVE
100 dc
AMBIENT TEMPERATURE ( °C)

T(tab) , MAXIMUM ALLOWABLE

T A , MAXIMUM ALLOWABLE

180°
TAB TEMPERATURE ( ° C)

180°
90 120°
α = 30°
120°
80 α = 30°
60° 60°
70
90° 90°
60 α α
α = CONDUCTION α = CONDUCTION
ANGLE ANGLE
50 85
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
IT(AV), AVERAGE ON-STATE CURRENT (AMPS) IT(AV), AVERAGE ON-STATE CURRENT (AMPS)

Figure 30. Current Derating, 2.0 cm Square Figure 31. Current Derating
Pad Reference: Anode Tab
Reference: Ambient Temperature

Motorola Thyristor Device Data 69

 MCR08BT1 Series
1.0 1.0

r T , TRANSIENT THERMAL RESISTANCE

0.9
MAXIMUM AVERAGE POWER α α = 30°
P(AV),DISSIPATION (WATTS) 0.8 α = CONDUCTION
ANGLE 60°
0.7

NORMALIZED
0.6
90°
0.5 0.1
0.4
dc
0.3 180°
0.2 120°
0.1
0 0.01
0 0.1 0.2 0.3 0.4 0.5 0.0001 0.001 0.01 0.1 1.0 10 100
IT(AV), AVERAGE ON-STATE CURRENT (AMPS) t, TIME (SECONDS)

Figure 32. Power Dissipation Figure 33. Thermal Response Device

Mounted on Figure 1 Printed Circuit Board
VGT , GATE TRIGGER VOLTAGE (VOLTS)

0.7 2.0

VAK = 7.0 V VAK = 7.0 V

0.6 RL = 140 Ω RL = 3.0 k

I H , HOLDING CURRENT
RGK = 1.0 kΩ RGK = 1.0 k

(NORMALIZED)
0.5 1.0

0.4

0.3 0
–40 –20 0 20 40 60 80 110 –40 –20 0 20 40 60 80 110
TJ, JUNCTION TEMPERATURE, (°C) TJ, JUNCTION TEMPERATURE, (°C)

Figure 34. Typical Gate Trigger Voltage Figure 35. Typical Normalized Holding Current
versus Junction Temperature versus Junction Temperature

0.7 1000
V GT , GATE TRIGGER VOLTAGE (VOLTS)

I GT , GATE TRIGGER CURRENT ( µA)

0.65
RGK = 1000 Ω, RESISTOR
0.6 CURRENT INCLUDED
100
0.55

0.5 VAK = 7.0 V

RL = 140 Ω
0.45 VAK = 7.0 V WITHOUT GATE RESISTOR
RL = 140 Ω 10
0.4 TJ = 25°C

0.35

0.3 1.0
0.1 1.0 10 100 1000 –40 –20 0 20 40 60 80 110
IGT, GATE TRIGGER CURRENT (µA) TJ, JUNCTION TEMPERATURE (°C)

Figure 36. Typical Range of VGT Figure 37. Typical Gate Trigger Current
versus Measured IGT versus Junction Temperature

70 Motorola Thyristor Device Data

 MCR08BT1 Series
100 10000
5000
TJ = 25°C Vpk = 400 V
IH , HOLDING CURRENT (mA)
1000
500
10 IGT = 48 µA

STATIC dv/dt (V/ µS)

100 TJ = 25°
50
IGT = 7 µA 10
1.0 125° 50°
5.0
1.0 110°
75°
0.5
0.1 0.1
1.0 10 100 1000 10,000 100,000 10 100 1000 10,000 100,000
RGK, GATE-CATHODE RESISTANCE (OHMS) RGK, GATE-CATHODE RESISTANCE (OHMS)

Figure 38. Holding Current Range versus Figure 39. Exponential Static dv/dt versus Junction
Gate-Cathode Resistance Temperature and Gate-Cathode Termination Resistance

10000 10000
300 V
TJ = 110°C TJ = 110°C
1000 1000 400 V (PEAK)
200 V
100 V
500 500
400 V
STATIC dv/dt (V/ µS)

STATIC dv/dt (V/ µS)

100 50 V 100 RGK = 100

50 50
500 V
10 10 RGK = 1.0 k

5.0 5.0
RGK = 10 k
1.0 1.0
10 100 1000 10,000 0.01 0.1 1.0 10 100
RGK, GATE-CATHODE RESISTANCE (OHMS) CGK, GATE-CATHODE CAPACITANCE (nF)

Figure 40. Exponential Static dv/dt versus Peak Figure 41. Exponential Static dv/dt versus
Voltage and Gate-Cathode Termination Resistance Gate-Cathode Capacitance and Resistance

10000

1000

500
STATIC dv/dt (V/ µS)

100

50
IGT = 70 µA
10 IGT = 5 µA
IGT = 35 µA
5.0
IGT = 15 µA
1.0
10 100 1000 10,000 100,000
GATE-CATHODE RESISTANCE (OHMS)

Figure 42. Exponential Static dv/dt versus

Gate-Cathode Termination Resistance and
Product Trigger Current Sensitivity

Motorola Thyristor Device Data 71

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR8
Silicon Controlled Rectifiers SERIES*
Reverse Blocking Thyristors *Motorola preferred devices

Designed primarily for half–wave ac control applications, such as motor SCRs

controls, heating controls, and power supplies; or wherever half–wave, silicon 8 AMPERES RMS
gate–controlled devices are needed. 400 thru 800
VOLTS
• Blocking Voltage to 800 Volts
• On–State Current Rating of 8 Amperes RMS
A
• High Surge Current Capability — 80 Amperes
• Industry Standard TO220 AB Package for Ease of Design
• Glass Passivated Junctions for Reliability and Uniformity

K
A
G

CASE 221A-06
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit
Peak Repetitive Off–State Voltage(1) VDRM Volts
Peak Repetitive Reverse Voltage VRRM
(TJ = –40 to 125°C) MCR8D 400
MCR8M 600
MCR8N 800

On–State RMS Current IT(RMS) 8 A

(All Conduction Angles)
Peak Non–repetitive Surge Current ITSM 80 A
(One Half Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 26.5 A2sec
Peak Gate Power (Pulse Width v1.0 µs, TC = 80°C) PGM 5.0 Watts

Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.5 Watts

Peak Gate Current (Pulse Width v1.0 µs, TC = 80°C) IGM 2.0 A

Operating Junction Temperature Range TJ –40 to +125 °C

Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case RθJC 2.0 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

72 Motorola Thyristor Device Data

 MCR8 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Forward Blocking Current TJ = 25°C IDRM — — 0.01 mA
Peak Reverse Blocking Current TJ = 125°C IRRM — — 2.0
(VAK = Rated VDRM or VRRM, Gate Open)
ON CHARACTERISTICS
Peak On–State Voltage* (ITM = 16 A) VTM — — 1.8 Volts
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) IGT 2.0 7.0 15 mA
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ω) VGT 0.5 0.65 1.0 Volts
Hold Current (Anode Voltage = 12 V) IH 4.0 22 30 mA
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off–State Voltage dv/dt 50 200 — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width v2.0 ms, Duty Cycle v2 %.
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

125 10
dc
180°

P(AV) AVERAGE POWER (WATTS)

120 8
a a 120°
90°
a = Conduction a = Conduction
115 6
Angle Angle 60°
a = 30°
110 4

a = 30° 60° 90° 120° 180° dc

105 2

100 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(AV), AVERAGE ON–STATE CURRENT (AMP) IT(AV), AVERAGE ON–STATE CURRENT (AMP)

Figure 1. Average Current Derating Figure 2. Maximum On–state Power

Dissipation
IT , INSTANTANEOUS ON–STATE CURRENT (AMPS)

100 1
R(t) TRANSIENT THERMAL R (NORMALIZED)

Maximum @ TJ = 125°C

10
Typical @ TJ = 25°C
0.1

1 ZqJC(t) = RqJC ⋅ R(t)

Maximum @ TJ = 25°C

0.1 0.01
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.1 1 10 100 1000 1⋅104
VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS) t, TIME (ms)

Figure 3. On–State Characteristics Figure 4. Transient Thermal Response

Motorola Thyristor Device Data 73

MCR8 SERIES
100 100

I L , LATCHING CURRENT (mA)

IH , HOLDING CURRENT (mA)

10 10
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Typical Holding Current Versus Figure 6. Typical Latching Current Versus
Junction Temperature Junction Temperature

100 0.80

V GT, GATE TRIGGER VOLTAGE (VOLTS)

0.75
I GT , GATE TRIGGER CURRENT (mA)

0.70

0.65
0.60
10
0.55
0.50
0.45
0.40
1 0.35
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 7. Typical Gate Trigger Current Versus Figure 8. Typical Gate Trigger Voltage Versus
Junction Temperature Junction Temperature

1000 80
I TSM , PEAK SURGE CURRENT (AMP)

Tj = 125°C VPK = 800 V

70
STATIC dv/dt (V/uS)

60

50

100 40
10 100 1000 1⋅104 1 2 3 4 5 6 7 8 9 10
RGK, GATE CATHODE RESISTANCE (OHMS) NUMBER OF CYCLES

Figure 9. Typical Exponential Static dv/dt Versus Figure 10. Maximum Non–Repetitive
Gate Cathode Resistance Surge Current

74 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR8S
SERIES*
Advance Information *Motorola preferred devices

Silicon Controlled Rectifiers

Reverse Blocking Thyristors SCRs
8 AMPERES RMS
400 thru 800
Designed primarily for half–wave ac control applications, such as motor VOLTS
controls, heating controls, and power supplies; or wherever half–wave, silicon
gate–controlled devices are needed.
• Blocking Voltage to 800 Volts A
• On–State Current Rating of 8 Amperes RMS
• High Surge Current Capability — 90 Amperes
• Industry Standard TO–220AB Package for Ease of Design
• Glass Passivated Junctions for Reliability and Uniformity
• Low Trigger Currents, 200µA Maximum for Direct Driving from Integrated Circuits K
A
G

CASE 221A-06
(TO-220AB)
Style 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit
Peak Repetitive Off–State Voltage (1) VDRM Volts
Peak Repetitive Reverse Voltage VRRM
(TJ = –40 to 110°C; RGK = 1.0 KΩ) MCR8SD 400
MCR8SM 600
MCR8SN 800

On–State RMS Current IT(RMS) 8 A

(All Conduction Angles)
Peak Non–repetitive Surge Current ITSM 90 A
(One Half Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 34 A2sec
Peak Gate Power (Pulse Width v1.0 µs, TC = 80°C) PGM 5.0 Watts

Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.5 Watts

Peak Gate Current (Pulse Width v1.0 µs, TC = 80°C) IGM 2.0 A

Operating Junction Temperature Range TJ –40 to +110 °C

Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case RθJC 2.2 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 75

MCR8S SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C; RGK = 1.0 KΩ unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Forward Blocking Current TJ = 25°C IDRM — — 10 µA
Peak Reverse Blocking Current TJ = 110°C IRRM — — 500
(VAK = Rated VDRM or VRRM, Gate Open) (1)
ON CHARACTERISTICS
Peak On–State Voltage (ITM = 16 A) (2) VTM — 1.4 1.8 Volts
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) (3) IGT 5.0 20 200 µA
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ω) VGT 0.5 0.65 1.0 Volts
Hold Current (Anode Voltage = 12 V) IH 0.5 1.0 6.0 mA
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off–State Voltage (dv/dt) 2.0 10 — V/µs
(VD = 67% of Rated VDRM, Exponential Waveform, TJ = 110°C)
(1) Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant
current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage.
(2) Pulse test: P.W. v 2ms, Duty Cycle v 2%.
(3) Does not include RGK current.

76 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR12
SERIES*
Advance Information *Motorola preferred devices

Silicon Controlled Rectifiers

Reverse Blocking Thyristors SCRs
12 AMPERES RMS
400 thru 800
Designed primarily for half–wave ac control applications, such as motor VOLTS
controls, heating controls, and power supplies; or wherever half–wave, silicon
gate–controlled devices are needed.
• Blocking Voltage to 800 Volts A
• On–State Current Rating of 12 Amperes RMS
• High Surge Current Capability — 100 Amperes
• Industry Standard TO–220AB Package for Ease of Design
• Glass Passivated Junctions for Reliability and Uniformity
K
A
G

CASE 221A-06
(TO-220AB)
Style 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit
Peak Repetitive Off–State Voltage (1) VDRM Volts
Peak Repetitive Reverse Voltage VRRM
(TJ = –40 to 125°C) MCR12D 400
MCR12M 600
MCR12N 800

On–State RMS Current IT(RMS) 12 A

(All Conduction Angles)
Peak Non–repetitive Surge Current ITSM 100 A
(One Half Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 41 A2sec
Peak Gate Power (Pulse Width v1.0 µs, TC = 80°C) PGM 5.0 Watts

Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.5 Watts

Peak Gate Current (Pulse Width v1.0 µs, TC = 80°C) IGM 2.0 A

Operating Junction Temperature Range TJ –40 to +125 °C

Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case RθJC 2.0 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 77

MCR12 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Forward Blocking Current TJ = 25°C IDRM — — 0.01 mA
Peak Reverse Blocking Current TJ = 125°C IRRM — — 2.0
(VAK = Rated VDRM or VRRM, Gate Open)
ON CHARACTERISTICS
Peak On–State Voltage* (ITM = 24 A) VTM — — 2.2 Volts
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) IGT 2.0 7.0 20 mA
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ω) VGT 0.5 0.65 1.0 Volts
Hold Current (Anode Voltage = 12 V) IH 4.0 25 40 mA
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off–State Voltage (dv/dt) 50 200 — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 25°C)
*Indicates Pulse Test: Pulse Width v 2.0 ms, Duty Cycle v 2%.

78 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR16
Silicon Controlled Rectifiers SERIES*
*Motorola preferred devices
Reverse Blocking Thyristors
Designed primarily for half–wave ac control applications, such as motor SCRs
controls, heating controls, and power supplies; or wherever half–wave, silicon 16 AMPERES RMS
gate–controlled devices are needed. 400 thru 800
VOLTS
• Blocking Voltage to 800 Volts
• On–State Current Rating of 16 Amperes RMS
• High Surge Current Capability — 160 Amperes A
• Industry Standard TO–220AB Package for Ease of Design
• Glass Passivated Junctions for Reliability and Uniformity

K
A
G

CASE 221A-06
(TO-220AB)
Style 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit
Peak Repetitive Off–State Voltage (1) VDRM Volts
Peak Repetitive Reverse Voltage VRRM
(TJ = –40 to 125°C) MCR16D 400
MCR16M 600
MCR16N 800

On–State RMS Current IT(RMS) 16 A

(All Conduction Angles)
Peak Non–repetitive Surge Current ITSM 160 A
(One Half Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 106 A2sec
Peak Gate Power (Pulse Width v1.0 µs, TC = 80°C) PGM 5.0 Watts

Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.5 Watts

Peak Gate Current (Pulse Width v1.0 µs, TC = 80°C) IGM 2.0 A

Operating Junction Temperature Range TJ –40 to +125 °C

Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case RθJC 1.5 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds TL 260 °C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Motorola Thyristor Device Data 79

 MCR16 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Forward Blocking Current TJ = 25°C IDRM — — 0.01 mA
Peak Reverse Blocking Current TJ = 125°C IRRM — — 2.0
(VAK = Rated VDRM or VRRM, Gate Open)
ON CHARACTERISTICS
Peak On–State Voltage* (ITM = 32 A) VTM — — 1.7 Volts
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) IGT 2.0 8.0 20 mA
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ω) VGT 0.5 0.65 1.0 Volts
Hold Current (Anode Voltage = 12 V) IH 4.0 25 40 mA
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off–State Voltage dv/dt 50 200 — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 25°C)
*Indicates Pulse Test: Pulse Width v 2.0 ms, Duty Cycle v 2%.
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

MAXIMUM AVERAGE POWER P (AV) DISSIPATION (WATTS)

125 22
20
120 dc
18
180°
115
a 16 a
120°
a = Conduction 14 a = Conduction 90°
110 Angle 12 Angle
60°
105
10 a = 30°
8
100 6
a = 30° 60° 90° 120° 180° dc
4
95
2
90 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
IT(AV), AVERAGE ON–STATE CURRENT (AMP) IT(AV), AVERAGE ON–STATE CURRENT (AMP)

Figure 1. Average Current Derating Figure 2. Maximum On–State Power Dissipation

IT , INSTANTANEOUS ON–STATE CURRENT (AMPS)

100 1
R(t) TRANSIENT THERMAL R (NORMALIZED)

Typical @ TJ = 25°C

Maximum @ TJ = 125°C

10
ZqJC(t) = RqJC(t) ⋅ r(t)
0.1

Maximum @ TJ = 25°C
1

0.1 0.01
0.5 1 1.5 2 2.5 3 3.5 0.1 1 10 100 1000 1⋅104
VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS) t, TIME (ms)

Figure 3. On–State Characteristics Figure 4. Transient Thermal Response

80 Motorola Thyristor Device Data

 MCR16 SERIES
100 100

I L , LATCHING CURRENT (mA)

IH , HOLDING CURRENT (mA)

10 10
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Typical Holding Current Versus Figure 6. Typical Latching Current Versus
Junction Temperature Junction Temperature

100 0.85

V GT, GATE TRIGGER VOLTAGE (VOLTS)

0.80
I GT , GATE TRIGGER CURRENT (mA)

0.75
0.70

0.65
10
0.60

0.55
0.50
0.45
1 0.40
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 7. Typical Gate Trigger Current Versus Figure 8. Typical Gate Trigger Voltage Versus
Junction Temperature Junction Temperature

1400 160
1 Cycle
I TSM , PEAK SURGE CURRENT (AMP)

150
1200
TJ = 125°C VPK = 800 V 140
STATIC dv/dt (V/uS)

1000
130

120
800

110
600 TJ = 125°C f = 60 Hz
100

400 90
10 100 1000 1⋅104 1 2 3 4 5 6 7 8 9 10
RGK, GATE CATHODE RESISTANCE (OHMS) NUMBER OF CYCLES

Figure 9. Typical Exponential Static dv/dt Versus Figure 10. Maximum Non–Repetitive
Gate Cathode Resistance Surge Current

Motorola Thyristor Device Data 81

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifiers MCR22Ć2

thru
. . . designed and tested for repetitive peak operation required for CD ignition, fuel
ignitors, flash circuits, motor controls and low-power switching applications.
MCR22Ć8
• 150 Amperes for 2 µs Safe Area
• High dv/dt
• Very Low Forward “On” Voltage at High Current SCRs
• Low-Cost TO-226AA (TO-92) 1.5 AMPERES RMS
50 thru 600 VOLTS

G
A K

K
G CASE 29-04
A (TO-226AA)
STYLE 10

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage VDRM, Volts
(RGK = IK, TJ = 25 to 125°C) VRRM
MCR22-2 50
MCR22-3 100
MCR22-4 200
MCR22-6 400
MCR22-8 600
On-State Current RMS IT(RMS) 1.5 Amps
(All Conduction Angles)
Peak Non-repetitive Surge Current, TA = 25°C ITSM 15 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations (t = 8.3 ms) I2t 0.9 A2s
Peak Gate Power, TA = 25°C PGM 0.5 Watt
Average Gate Power, TA = 25°C PG(AV) 0.1 Watt
Peak Forward Gate Current, TA = 25°C IFGM 0.2 Amp
(300 µs, 120 PPS)
Peak Reverse Gate Voltage VRGM 5 Volts
Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
Lead Solder Temperature — +230 °C
(Lead Length q1/16I from case, 10 s Max)
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

82 Motorola Thyristor Device Data

 MCR22Ć2 thru MCR22Ć8
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 50 °C/W
Thermal Resistance, Junction to Ambient RθJA 160 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted. RGK = 1000 Ohms.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM) TC = 25°C — — 10 µA
TC = 125°C — — 200 µA
Forward “On” Voltage VTM — 1.2 1.7 Volts
(ITM = 1 A Peak)
Gate Trigger Current (Continuous dc)(1) TC = 25°C IGT — 30 200 µA
(Anode Voltage = 6 Vdc, RL = 100 Ohms) TC = –40°C — — 500
Gate Trigger Voltage (Continuous dc) TC = 25°C VGT — — 0.8 Volts
(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –40°C — — 1.2
(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C VGD 0.1 — —
Holding Current TC = 25°C IH — 2 5 mA
(Anode Voltage = 12 Vdc) TC = –40°C — — 10
Forward Voltage Application Rate dv/dt — 25 — V/µs
(TC = 125°C)
1. RGK Current Not Included in Measurement.

CURRENT DERATING
TA , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (° C)

FIGURE 1 — MAXIMUM CASE TEMPERATURE FIGURE 2 — MAXIMUM AMBIENT TEMPERATURE

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

140 140
120
100 100
80
α = 180° dc
60 60
α = CONDUCTION
ANGLE 40
α = 180° dc
20 20
α = CONDUCTION ANGLE
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0
IT(AV), AVERAGE ON-STATE CURRENT (AMPS) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 83

 MCR22Ć2 thru MCR22Ć8
FIGURE 3 — TYPICAL FORWARD VOLTAGE
5.0

3.0

2.0 TJ = 125°C
25°C

1.0

I T , INSTANTANEOUS ON-STATE CURRENT (AMP)

0.7

0.5

0.3

0.2

0.1

0.07

0.05

0.03

0.02

0.01
0 0.5 1.0 1.5 2.0 2.5
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

FIGURE 4 — THERMAL RESPONSE

1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.7
0.5
0.3
(NORMALIZED)

0.2

0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10000
t, TIME (ms)

84 Motorola Thyristor Device Data

 MCR22Ć2 thru MCR22Ć8
TYPICAL CHARACTERISTICS

FIGURE 5 — GATE TRIGGER VOLTAGE FIGURE 6 — TYPICAL GATE TRIGGER CURRENT

0.8 100
VG , GATE TRIGGER VOLTAGE (VOLTS)

VAK = 7.0 V

I GT GATE TRIGGER CURRENT ( µA)

50
0.7 RL = 100
30
20
0.6
10
0.5
5.0

0.4 3.0
2.0

0.3 1.0
–75 –50 –25 0 25 50 75 100 125 –40 –20 0 20 40 60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C) TJ JUNCTION TEMPERATURE (°C)

P(AV) MAXIMUM AVERAGE POWER DISSIPATION (WATTS)

FIGURE 7 — HOLDING CURRENT FIGURE 8 — POWER DISSIPATION

10 2.0
1.8
120° 180°
90°
I H , HOLDING CURRENT (mA)

1.6 60°
VAK = 12 V 30°
1.4
RL = 100 Ω
5.0 1.2
1.0
dc
0.8
2.0 0.6
0.4
0.2
1.0 0
–40 –20 0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
TJ, JUNCTION TEMPERATURE (°C) IT(AV), AVERAGE ON-STATE CURRENT (AMPS)

Motorola Thyristor Device Data 85

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR25
Silicon Controlled Rectifiers SERIES*
Reverse Blocking Thyristors *Motorola preferred devices

Designed primarily for half–wave ac control applications, such as motor SCRs

controls, heating controls, and power supplies; or wherever half–wave, silicon 25 AMPERES RMS
gate–controlled devices are needed. 400 thru 800
• Blocking Voltage to 800 Volts VOLTS
• On-State Current Rating of 25 Amperes RMS
• High Surge Current Capability — 300 Amperes
• Industry Standard TO–220AB Package for Ease of Design A

• Glass Passivated Junctions for Reliability and Uniformity

K
A
G
CASE 221A–06
(TO-220AB)
Style 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit
Peak Repetitive Off-State Voltage (1) VDRM Volts
Peak Repetitive Reverse Voltage VRRM
(TJ = –40 to 125°C) MCR25D 400
MCR25M 600
MCR25N 800
On-State RMS Current IT(RMS) 25 A
(All Conduction Angles)
Peak Non-repetitive Surge Current ITSM 300 A
(One Half Cycle, 60 Hz, TJ = 125°C)
Circuit Fusing Consideration (t = 8.3 ms) I2t 373 A2sec
Peak Gate Power (Pulse Width ≤ 1.0 µs, TC = 80°C) PGM 20.0 Watts
Average Gate Power (t = 8.3 ms, TC = 80°C) PG(AV) 0.5 Watts
Peak Gate Current (Pulse Width ≤ 1.0 µs, TC = 80°C) IGM 2.0 A
Operating Junction Temperature Range TJ – 40 to +125 °C
Storage Temperature Range Tstg – 40 to +150 °C

THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case RθJC 1.5 °C/W
— Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 5 Seconds TL 260 °C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2

86 Motorola Thyristor Device Data

 MCR25 SERIES
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
Peak Forward Blocking Current IDRM mA
Peak Reverse Blocking Current IRRM
(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C — — 0.01
TJ = 125°C — — 2.0
ON CHARACTERISTICS
Peak On-State Voltage* (ITM = 50 A) VTM — — 1.8 Volts
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ω) IGT 4.0 10 30 mA
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ω) VGT 0.5 0.65 1.0 Volts
Hold Current (Anode Voltage =12 V) IH 5.0 25 40 mA

DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Off–State Voltage dv/dt 50 200 — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
*Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.

125
T C , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)

35
°
120 5

P(AV) , AVERAGE POWER DISSIPATION (WATTS)

0
30
115 dc
a
180°
110 a 25
120°
a = Conduction 90°
105 Angle 20 60 °
100 a = 30°
15
95

90 10
85
a = 30° 60 ° 90° 120° 180° dc 5
80

75 0
0 5 10 15 20 25 0 5 10 15 20 25
IT(AV), AVERAGE ON–STATE CURRENT (AMPS) IT(AV), AVERAGE ON–STATE CURRENT (AMPS)
Figure 1. Average Current Derating Figure 2. Maximum On–State Power Dissipation

Motorola Thyristor Device Data 87

 MCR25 SERIES

I T , INSTANTANOUS ON-STATE CURRENT (AMPS)

1
100

R(t) TRANSIENT THERMAL R (NORMALIZED)

Maximum @ TJ = 125°C

Typical @ TJ = 25°C
10
Z qJC(t) + RqJC @ R(t)
Maximum @ TJ = 25°C 0.1

0.1 0.01
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 0.1 1 10 100 1000 @
1 10 4
VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS) t, TIME (ms)
Figure 3. On–State Characteristics Figure 4. Transient Thermal Response

100
100
I H , HOLDING CURRENT (mA)

I L , LATCHING CURRENT (mA)

10

1 10
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Typical Holding Current Versus Figure 6. Typical Latching Current Versus
Junction Temperature Junction Temperature

100
0.85

0.8
VGT, GATE TRIGGER VOLTAGE (VOLTS)
I GT, TRIGGER CURRENT (mA)

0.75

0.7

0.65
10
0.6

0.55

0.5

0.45

1 0.4
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Typical Gate Trigger Current Versus Figure 8. Typical Gate Trigger Voltage Versus
Junction Temperature Junction Temperature

88 Motorola Thyristor Device Data

 MCR25 SERIES

1200 2500
Gate Cathode Open,
Gate–Cathode Open, (dv/dt does not depend on RGK )
1000 (dv/dt does not depend on RGK) 2000

STATIC dv/dt (V/us)

800
STATIC dv/dt (V/us)

1500
85°C VPK = 275
600
100°C
110°C 1000
400 VPK = 400
TJ = 125°C VPK = 600
500
200 VPK = 800

0 0
200 300 400 500 600 700 800 80 85 90 95 100 105 110 115 120 125
VPK , Peak Voltage (Volts) TJ, Junction Temperature (°C )

Figure 9. Typical Exponential Static dv/dt Figure 10. Typical Exponential Static dv/dt
Versus Peak Voltage. Versus Junction Temperature.

300

1 CYCLE
280
I TSM, SURGE CURRENT (AMPS)

260

240

220

200
TJ=125° C f=60 Hz
180

160
1 2 3 4 5 6 7 8 9 10
NUMBER OF CYCLES
Figure 11. Maximum Non–Repetitive
Surge Current

Motorola Thyristor Device Data 89

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifiers MCR72

Reverse Blocking Triode Thyristors
Series
. . . designed for industrial and consumer applications such as temperature, light and
speed control; process and remote controls; warning systems; capacitive discharge
circuits and MPU interface. SCRs
• Center Gate Geometry for Uniform Current Density 8 AMPERES RMS
• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and 50 thru 800 VOLTS
Stability
• Small, Rugged Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Low Trigger Currents, 200 µA Maximum for Direct Driving from Integrated Circuits
G
A C

CASE 221A-04
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = – 40 to 110°C, or
1/2 Sine Wave, RGK = 1kΩ) VRRM
MCR72-2 50
MCR72-3 100
MCR72-4 200
MCR72-6 400
MCR72-8 600
MCR72-10 800
On-State RMS Current (TC = 83°C) IT(RMS) 8 Amps
Peak Non-repetitive Surge Current ITSM 100 Amps
(1/2 Cycle, 60 Hz, TJ = –40 to 110°C)
Circuit Fusing (t = 8.3 ms) I2t 40 A2s
Peak Gate Voltage (t p 10 µs) VGM ±5 Volts
Peak Gate Current (t p 10 µs) IGM 1 Amp
Peak Gate Power (t p 10 µs) PGM 5 Watts
Average Gate Power PG(AV) 0.75 Watts
Operating Junction Temperature Range TJ –40 to +110 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; (cont.)
however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages
shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.

90 Motorola Thyristor Device Data

 MCR72 Series
MAXIMUM RATINGS — continued
Rating Symbol Value Unit
Storage Temperature Range Tstg –40 to + 150 °C
Mounting Torque — 8 in. lb.
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current(1) I DRM , I RRM
(VAK = Rated VDRM or VRRM) TJ = 25°C — — 10 µA
TJ = 110°C — — 500 µA
On-State Voltage VTM — 1.7 2 Volts
(ITM = 16 A Peak, Pulse Width p 1 ms, Duty Cycle p 2%)
Gate Trigger Current (Continuous dc)(2) IGT — 30 200 µA
(VD = 12 V, RL = 100 Ω)
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ω) — 0.5 1.5
(VD = Rated VDRM, RL = 10 kΩ, TJ = 110°C) 0.1 — —
Holding Current IH — — 6 mA
(VD = 12 V, ITM = 100 mA)
Critical Rate-of-Rise of Forward Blocking Voltage dv/dt — 10 — V/µs
(VD = Rated VDRM, TJ = 110°C, Exponential Waveform)
Gate Controlled Turn-On Time tgt — 1 — µs
(VD = Rated VDRM, ITM = 16 A, IG = 2 mA)
1. Ratings apply for negative gate voltage or RGK = 1 kΩ. Devices shall not have a positive gate voltage concurrently with a negative voltage
on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage
applied exceeds the rated blocking voltage.
2. Does not include RGK current.

FIGURE 1 — AVERAGE CURRENT DERATING FIGURE 2 — ON-STATE POWER DISSIPATION

PAV , AVERAGE POWER DISSIPATION (WATTS)

110 16
T C , MAXIMUM CASE TEMPERATURE ( °C)

dc
100 12
α α 180°

α = 30° α = Conduction Angle α = Conduction Angle 90°

90 8.0
60°
90° α = 30° 60°

180°
80 4.0
dc

70 0
0 2.0 4.0 6.0 8.0 0 2.0 4.0 6.0 8.0
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 91

 MCR72 Series
FIGURE 3 — NORMALIZED GATE CURRENT FIGURE 4 — GATE VOLTAGE
3.0

VGT , GATE TRIGGER VOLTAGE (VOLTS)

0.7
2.0
NORMALIZED GATE CURRENT

VD = 12 Vdc 0.6
VD = 12 Vdc
0.5
1.0
0.4

0.3

0.5 0.2

0.1
0.3
–40 –20 0 20 40 60 80 90 100 120 140 –60 –40 –20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

92 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR100
Silicon Controlled Rectifiers Series*
Reverse Blocking Triode Thyristors
*Motorola preferred devices
PNPN devices designed for high volume, line-powered consumer applications such
as relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and
sensing and detection circuits. Supplied in an inexpensive plastic TO-226AA package
which is readily adaptable for use in automatic insertion equipment. SCRs
• Sensitive Gate Trigger Current — 200 µA Maximum 0.8 AMPERE RMS
• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 125°C 100 thru 600 VOLTS
• Low Holding Current — 5 mA Maximum
• Glass-Passivated Surface for Reliability and Uniformity

G
A K

K
G CASE 29-04
A (TO-226AA)
STYLE 10

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = 25 to 125°C, RGK = 1 kΩ MCR100–3 and 100
MCR100–4 VRRM 200
MCR100–6 400
MCR100–8 600
Forward Current RMS (See Figures 1 & 2) IT(RMS) 0.8 Amps
(All Conduction Angles)
Peak Forward Surge Current, TA = 25°C ITSM 10 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations I2t 0.415 A2s
(t = 8.3 ms)
Peak Gate Power — Forward, TA = 25°C PGM 0.1 Watts
Average Gate Power — Forward, TA = 25°C PGF(AV) 0.01 Watt
Peak Gate Current — Forward, TA = 25°C IGFM 1 Amp
(300 µs, 120 PPS)
Peak Gate Voltage — Reverse VGRM 5 Volts
Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
Lead Solder Temperature — +230 °C
(< 1/16I from case, 10 s max)

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 93

 MCR100 Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted.)
Characteristic Symbol Min Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM) TC = 25°C — 10 µA
TC = 125°C — 100 µA
Forward “On” Voltage(1) VTM — 1.7 Volts
(ITM = 1 A Peak @ TA = 25°C)
Gate Trigger Current (Continuous dc)(2) TC = 25°C IGT — 200 µA
(Anode Voltage = 7 Vdc, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) TC = 25°C VGT — 0.8 Volts
(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –40°C — 1.2
(Anode Voltage = Rated VDRM, RL = 100 Ohms) TC = 125°C 0.1 —
Holding Current TC = 25°C IH — 5 mA
(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –40°C — 10
1. Forward current applied for 1 ms maximum duration, duty cycle p 1%.
2. RGK current is not included in measurement.

FIGURE 1 – MCR100-7, MCR100-8 CURRENT DERATING FIGURE 2 – MCR100-7, MCR100-8 CURRENT DERATING
(REFERENCE: CASE TEMPERATURE) (REFERENCE: AMBIENT TEMPERATURE)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

120 α 120
α = CONDUCTION ANGLE α
α = CONDUCTION ANGLE
T A , MAXIMUM ALLOWABLE AMBIENT

110
CASE MEASUREMENT
POINT — CENTER OF 100
100
FLAT PORTION TYPICAL PRINTED
TEMPERATURE ( °C)

90 CIRCUIT BOARD
dc 80 MOUNTING
80

70 60 dc
α = 30° 120° 180°
60° 90°
60
40
50
α = 30° 60° 90° 120° 180°
40 20
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4
IT(AV), AVERAGE ON-STATE CURRENT (AMP) IT(AV), AVERAGE ON-STATE CURRENT (AMP)

94 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifiers MCR102

Reverse Blocking Triode Thyristors MCR103
Annular PNPN devices designed for low cost, high volume consumer applications
such as relay and lamp drivers, small motor controls, gate drivers for larger thyristors,
and sensing and detection circuits. Supplied in an inexpensive plastic TO-226AA SCRs
package which is readily adaptable for use in automatic insertion equipment. 0.8 AMPERES RMS
• Sensitive Gate Trigger Current — 200 µA Maximum 30 and 60 VOLTS
• Low Reverse and Forward Blocking Current — 100 µA Maximum, TC = 85°C
• Low Holding Current — 5 mA Maximum
• Passivated Surface for Reliability and Uniformity

G
A K

K CASE 29-04
G
A (TO-226AA)
STYLE 10

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(2) VDRM Volts
(TC = + 85°C, RGK = 1 kΩ) MCR102 VRRM 30
MCR103 60
Forward Current RMS (See Figures 1 & 2) IT(RMS) 0.8 Amps
(All Conduction Angles)
Peak Forward Surge Current, TA = 25°C ITSM 10 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations I2t 0.415 A2s
(t = 8.3 ms)
Peak Gate Power — Forward, TA = 25°C PGM 0.1 Watt
Average Gate Power — Forward, TA = 25°C PGF(AV) 0.01 Watt
Peak Gate Current — Forward, TA = 25°C IGFM 1 Amp
(300 µs, 120 PPS)
Peak Gate Voltage — Reverse VGRM 4 Volts
Operating Junction Temperature Range @ Rated VRRM and VDRM TJ –40 to +85 °C
Storage Temperature Range Tstg –40 to +150 °C
Lead Solder Temperature — + 230 °C
t
( 1/16″ from case, 10 s max)
1. Temperature reference point for all case temperature is center of flat portion of package. (TC = +85°C unless otherwise noted.)
2. VDRM and VRRM for all types can be applied on a continuous dc basis without incurring damage. Ratings apply for zero or negative gate
voltage but positive gate voltage shall not be applied concurrently with a negative potential on the anode. When checking forward or reverse
blocking capability, thyristor devices should not be tested with a constant current source in a manner that the voltage applied exceeds the
rated blocking voltage.

Motorola Thyristor Device Data 95

 MCR102 MCR103
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 75 °C/W
Thermal Resistance, Junction to Ambient RθJA 200 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ω unless otherwise specified.)
Characteristic Symbol Min Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM) TC = 25°C — 10 µA
TC = 85°C — 100 µA
Forward “On” Voltage(1) VTM — 1.7 Volts
(ITM = 1 A Peak @ TA = 25°C)
Gate Trigger Current (Continuous dc)(2) TC = 25°C IGT — 200 µA
(Anode Voltage = 7 Vdc, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) TC = 25°C VGT — 0.8 Volts
(Anode Voltage = 7 Vdc, RL = 100 Ohms) TC = –65°C VGD — 1.2
TC = 85°C 0.1 —
Holding Current TC = 25°C IH — 5 mA
(Anode Voltage = 7 Vdc, initiating current = 20 mA) TC = –65°C — 10
1. Forward current applied for 1 ms maximum duration, duty cycle p 1%.
2. RGK current is not included in measurement.

FIGURE 1 – CURRENT DERATING FIGURE 2 – CURRENT DERATING

(REFERENCE: CASE TEMPERATURE) (REFERENCE: AMBIENT TEMPERATURE)
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

90 α
90
α = CONDUCTION
ANGLE
T A , MAXIMUM ALLOWABLE AMBIENT

α = CONDUCTION ANGLE
CASE MEASUREMENT
POINT — CENTER OF TYPICAL PRINTED α
70 70
FLAT PORTION CIRCUIT BOARD
TEMPERATURE ( °C)

MOUNTING
dc
50 50
120°
180°
α = 30° α = 30°
60° 90°
30 30 60° dc
120° 180° 90°

10 10
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4
IF(AV), AVERAGE FORWARD CURRENT (AMP) IF(AV), AVERAGE FORWARD CURRENT (AMP)

96 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR106
Silicon Controlled Rectifiers Series*
Reverse Blocking Triode Thyristors
*Motorola preferred devices
PNPN devices designed for high volume consumer applications such as except MCR106–3
temperature, light and speed control; process and remote control, and warning
systems where reliability of operation is important.
• Glass-Passivated Surface for Reliability and Uniformity SCRs
• Power Rated at Economical Prices 4 AMPERES RMS
• Practical Level Triggering and Holding Characteristics 60 thru 600 VOLTS
• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat
Dissipation and Durability

G
A K

G CASE 77-08
A
K (TO-225AA)
STYLE 2

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = 110°C, RGK = 1 kΩ) and
MCR106-2 VRRM 60
MCR106-3 100
MCR106-4 200
MCR106-6 400
MCR106-8 600
RMS Forward Current IT(RMS) 4 Amps
(All Conduction Angles)
Average Forward Current IT(AV) 2.55 Amps
TC = 93°C or
TA = 30°C
Peak Non-repetitive Surge Current ITSM 25 Amps
(1/2 Cycle, 60 Hz, TJ = –40 to +110°C)
Circuit Fusing Considerations I2t 2.6 A2s
(t = 8.3 ms)
Peak Gate Power PGM 0.5 Watt
Average Gate Power PG(AV) 0.1 Watt
Peak Forward Gate Current IGM 0.2 Amp
Peak Reverse Gate Voltage VRGM 6 Volts
Operating Junction Temperature Range TJ –40 to +110 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; (cont.)
however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages
shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.

Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 97

MCR106 Series
MAXIMUM RATINGS — continued
Rating Symbol Value Unit
Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque(1) — 6 in. lb.
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 3 °C/W
Thermal Resistance, Junction to Ambient RθJA 75 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C and RGK = 1000 Ohms unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM) TJ = 25°C — — 10 µA
TJ = 110°C — — 200 µA
Forward “On” Voltage VTM — — 2 Volts
(ITM = 4 A Peak)
Gate Trigger Current (Continuous dc)(2) IGT µA
(VAK = 7 Vdc, RL = 100 Ohms) — — 200
(VAK = 7 Vdc, RL = 100 Ohms, TC = –40°C) — — 500
Gate Trigger Voltage (Continuous dc) VGT — — 1 Volts
(VAK = 7 Vdc, RL = 100 Ohms, TC = 25°C)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(VAK = Rated VDRM, RL = 100 Ohms, TJ = 110°C)
Holding Current IH — — 5 mA
(VAK = 7 Vdc, TC = 25°C)
Forward Voltage Application Rate dv/dt — 10 — V/µs
(TJ = 110°C)
1. Torque rating applies with use of compression washer (B52200-F006 or equivalent). Mounting torque in excess of 6 in. lb. does not
appreciably lower case-to-sink thermal resistance. Anode lead and heatsink contact pad are common. (See AN209B).
For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C. For optimum
results, an activated flux (oxide removing) is recommended.
2. RGK current is not included in measurement.

98 Motorola Thyristor Device Data

 MCR106 Series
CURRENT DERATING

FIGURE 1 – MAXIMUM CASE TEMPERATURE FIGURE 2 – MAXIMUM AMBIENT TEMPERATURE

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

110 110

TA , MAXIMUM ALLOWABLE AMBIENT

106
90
102
π

TEMPERATURE ( °C)
0 α
98 f = 60 Hz 0 α π
70
f = 60 Hz
94

90 50
α = 30° 60° 90° 120° 180° dc
86
α = 30° 60° 90° 180° dc
82 30
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
IT(AV), AVERAGE FORWARD CURRENT (AMP) IT(AV), AVERAGE FORWARD CURRENT (AMP)

Motorola Thyristor Device Data 99

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Thyristors MCR218
Silicon-Controlled Rectifiers Series
. . . designed primarily for half-wave ac control applications, such as motor controls,
heating controls and power supplies; or wherever half-wave silicon gate-controlled,
solid-state devices are needed. SCRs
• Glass-Passivated Junctions 8 AMPERES RMS
• Blocking Voltage to 800 Volts 50 thru 800 VOLTS
• TO-220 Construction — Low Thermal Resistance, High Heat Dissipation and
Durability

G
A K

CASE 221A-04
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Voltage(1) VDRM Volts
(TJ = 25 to 125°C, Gate Open) MCR218–2 VRRM 50
MCR218–3 100
MCR218–4 200
MCR218–6 400
MCR218–8 600
MCR218–10 800
Forward Current RMS IT(RMS) 8 Amps
(All Conduction Angles)
Peak Forward Surge Current ITSM 80 Amps
(1/2 Cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations I2t 26 A2s
(t = 8.3 ms)
Forward Peak Gate Power PGM 5 Watts
Forward Average Gate Power PG(AV) 0.5 Watt
Forward Peak Gate Current IGM 2 Amps
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

100 Motorola Thyristor Device Data

 MCR218 Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2 °C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak On-State Voltage(1) VTM — 1.5 1.8 Volts
(ITM = 16 A Peak)
Gate Trigger Current (Continuous dc) IGT — 10 25 mA
(VD = 12 V, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 V, RL = 100 Ohms) — — 1.5
(Rated VDRM, RL = 1000 Ohms, TJ = 125°C) 0.2 — —
Holding Current IH — 16 30 mA
(Anode Voltage = 24 Vdc, Peak Initiating On-State Current = 0.5 A,
0.1 to 10 ms Pulse, Gate Trigger Source = 7 V, 20 Ohms)
Critical Rate-of-Rise of Off-State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125°C)
1. Pulse Test: Pulse Width = 1 ms, Duty Cycle p2%.
FIGURE 1 – CURRENT DERATING
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

125

115
α

α = CONDUCTION ANGLE
105

95

dc
85

α = 30° 60° 90° 120° 180°

75
0 1 2 3 4 5 6 7 8
IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)

FIGURE 2 — ON-STATE POWER DISSIPATION FIGURE 3 — NORMALIZED GATE TRIGGER CURRENT

I GT , NORMALIZED GATE TRIGGER CURRENT (mA)
P(AV), AVERAGE ON-STATE POWER DISSIPATION

15 3.0

2.0
12 VD = 12 Vdc
α
1.5
α = Conduction Angle dc
9.0
180°
(WATTS)

120° 1.0
90° 0.9
60°
6.0
α = 30° 0.7

3.0 0.5
0.4
0 0.3
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 –60 –40 –20 0 20 40 60 80 100 120 140
IT(AV), AVG. ON-STATE CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C)

Motorola Thyristor Device Data 101

 MCR218 Series
FIGURE 4 — NORMALIZED GATE TRIGGER VOLTAGE FIGURE 5 — NORMALIZED HOLDING CURRENT
1.3 4.0

I H , NORMALIZED HOLDING CURRENT (mA)

V GT , NORMALIZED GATE TRIGGER VOLTAGE

3.0
1.2

2.0
VD = 12 Vdc VD = 12 Vdc
1.5
1.0
0.9
1.0
0.7 0.9
0.7
0.5
0.4 0.5
0.3 0.4
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

102 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR218FP
Series
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
. . . designed primarily for half-wave ac control applications, such as motor controls,
heating controls and power supply crowbar circuits. ISOLATED SCRs
• Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformity 8 AMPERES RMS
and Stability 50 thru 800
• Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High Heat VOLTS
Dissipation and Durability
• Blocking Voltage to 800 Volts
• 80 A Surge Current Capability
• Insulated Package Simplifies Mounting

G
A K CASE 221C-02
STYLE 2

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = –40 to +125°C, Gate Open) VRRM
MCR218-2FP 50
MCR218-4FP 200
MCR218-6FP 400
MCR218-8FP 600
MCR218-10FP 800
On-State RMS Current (TC = +70°C) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 8 Amps
Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +70°C) ITSM 80 Amps
Preceded and followed by rated current
Circuit Fusing (t = 8.3 ms) I2t 26 A2s
Peak Gate Power (TC = +70°C, Pulse Width = 10 µs) PGM 5 Watts
Average Gate Power (TC = +70°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current (TC = +70°C, Pulse Width = 10 µs) IGM 2 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +125 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic body.

Motorola Thyristor Device Data 103

 MCR218FP Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit
Peak Forward Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak Reverse Blocking Current IRRM — — 2 mA
(VR = Rated VRRM, TJ = 125°C)
Forward “On” Voltage(1) VTM — 1 1.8 Volts
(ITM = 16 A Peak)
Gate Trigger Current (Continuous dc) IGT — 10 25 mA
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) VGT — — 1.5 Volts
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(Anode Voltage = Rated VDRM, RL = 100 Ohms, TJ = 125°C)
Holding Current IH — 16 30 mA
(Anode Voltage = 12 Vdc)
Turn-On Time tgt — 1.5 — µs
(ITM = 8 A, IGT = 40 mAdc)
Turn-Off Time (VD = Rated VDRM, tq µs
ITM = 8 A, IR = 8 A) TJ = 25°C — 15 —
TJ = 125°C — 35 —
Critical Rate-of-Rise of Off-State Voltage dv/dt — 100 — V/µs
(Gate Open, VD = Rated VDRM, Exponential Waveform)
1. Pulse Test: Pulse Width = 1 ms, Duty Cycle p 2%.
TYPICAL CHARACTERISTICS
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

P(AV) , AVERAGE ON-STATE POWER DISSIPATION

125 15

115 12 α
α
α = CONDUCTION ANGLE α = CONDUCTION ANGLE dc
105 9
(WATTS)

120° 180°

60° 90
95 6 °
α = 30°
dc
85 3

α = 30° 60° 90° 120° 180°

75 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS) IT(AV), AVG. ON-STATE CURRENT (AMPS)

Figure 1. Current Derating Figure 2. On-State Power Dissipation

104 Motorola Thyristor Device Data

 MCR218FP Series
100 80
1 CYCLE

I TSM , PEAK SURGE CURRENT (AMP)

70
TJ = 25°C 75
50
125°C
70
30

20
i F , INSTANTANEOUS ON-STATE FORWARD CURRENT (AMP)

65
TC = 85°C
f = 60 Hz
10 60
SURGE IS PRECEDED AND
7 FOLLOWED BY RATED CURRENT
55
5 1 2 3 4 6 8 10
NUMBER OF CYCLES
3 Figure 4. Maximum Non-Repetitive Surge Current
2

+I
1

0.7
IT FORWARD
0.5 REVERSE BREAKOVER
BLOCKING VT POINT
0.3 REGION IH
IDRM
–V +V
0.2 IRRM VDRM
VRRM
FORWARD
REVERSE BLOCKING
0.1 AVALANCHE –I REGION
0.4 1.2 2 2.8 3.6 4.4 5.2 6 REGION
v F, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

Figure 3. Maximum On-State Characteristics Figure 5. Characteristics and Symbols

1
r(t), TRANSIENT THERMAL RESISTANCE

0.7
0.5
0.3
(NORMALIZED)

0.2 ZθJC(t) = RθJC • r(t)

0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1.0 k 2.0 k 3.0 k 5.0 k
t, TIME (ms)

Figure 6. Thermal Response

Motorola Thyristor Device Data 105

 MCR218FP Series

I GT, GATE TRIGGER CURRENT (NORMALIZED)

VGT , GATE TRIGGER VOLTAGE (NORMALIZED)

2 2
VD = 12 V VD = 12 V
1.6 1.6

1.2 1.2

0.8 0.8

0.4 0.4

0 0
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 7. Gate Trigger Current versus Temperature Figure 8. Gate Trigger Voltage versus Temperature

2
IH , HOLDING CURRENT (NORMALIZED)

VD = 12 V
1.6

1.2

0.8

0.4

0
–60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)

Figure 9. Holding Current versus Temperature

106 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR225FP
Series
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
. . . designed primarily for half-wave ac control applications, such as motor controls,
ISOLATED SCRs
heating controls and power supply crowbar circuits.
25 AMPERES RMS
• Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformity 50 thru 800 VOLTS
and Stability
• Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High Heat
Dissipation and Durability
• Blocking Voltage to 800 Volts
• 300 A Surge Current Capability
• Insulated Package Simplifies Mounting

G
CASE 221C-02
A K
STYLE 2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = –40 to +125°C, Gate Open) VRRM
MCR225-2FP 50
MCR225-4FP 200
MCR225-6FP 400
MCR225-8FP 600
MCR225-10FP 800
On-State RMS Current (TC = +70°C) Full Cycle Sine Wave 50 to 60 Hz(2) IT(RMS) 25 Amps
Peak Non-repetitive Surge Current (One Full Cycle, 60 Hz, TC = +70°C) ITSM 300 Amps
Preceded and followed by rated current
Circuit Fusing (t = 8.3 ms) I2t 375 A2s
Peak Gate Power (TC = +70°C, Pulse Width = 10 µs) PGM 20 Watts
Average Gate Power (TC = +70°C, t = 8.3 ms) PG(AV) 0.5 Watt
Peak Gate Current (TC = +70°C, Pulse Width = 10 µs) IGM 2 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) V(ISO) 1500 Volts
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +125 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

Motorola Thyristor Device Data 107

 MCR225FP Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1.5 °C/W
Thermal Resistance, Case to Sink RθCS 2.2 (typ) °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit
Peak Forward Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Peak Reverse Blocking Current IRRM — — 2 mA
(VR = Rated VRRM) TJ = 125°C
Forward “On” Voltage(1) VTM — — 1.8 Volts
(ITM = 50 A)
Gate Trigger Current (Continuous dc) IGT — — 40 mA
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
Gate Trigger Voltage (Continuous dc) VGT — 0.8 1.5 Volts
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(Anode Voltage = Rated VDRM, RL = 100 Ohms, TJ = 125°C)
Holding Current IH — 20 40 mA
(Anode Voltage = 12 Vdc)
Turn-On Time tgt — 1.5 — µs
(ITM = 25 A, IGT = 40 mAdc)
Turn-Off Time (VDRM = Rated Voltage) tq µs
(ITM = 25 A, IR = 25 A) — 15 —
(ITM = 25 A, IR = 25 A, TJ = 125°C) — 35 —
Critical Rate-of-Rise of Off-State Voltage dv/dt — 100 — V/µs
(Gate Open, VD = Rated VDRM, Exponential Waveform)
1. Pulse Test: Pulse Width = 1 ms, Duty Cycle p 2%.

TYPICAL CHARACTERISTICS

130 32
TC, MAXIMUM CASE TEMPERATURE (° C)

P(AV) , AVERAGE POWER (WATTS)

180° dc
120 α
α 24
α = CONDUCTION ANGLE α = CONDUCTION ANGLE 60°
90°
110
α = 30°
16
100
TJ = 125°C
α = 30° 60° 90° 180° dc 8
90

80 0
0 4 8 12 16 20 0 4 8 12 16 20
IT(AV), ON-STATE FORWARD CURRENT (AMPS) IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)

Figure 10. Average Current Derating Figure 11. Maximum On–State Power Dissipation

108 Motorola Thyristor Device Data

 MCR225FP Series
100 300
1 CYCLE

I TSM , PEAK SURGE CURRENT (AMP)

70
275
50

30 250
125°C
20 225
TC = 85°C
i F , INSTANTANEOUS FORWARD CURRENT (AMPS)

f = 60 Hz
25°C
10 200
SURGE IS PRECEDED AND
7 FOLLOWED BY RATED CURRENT
175
5 1 2 3 4 6 8 10
NUMBER OF CYCLES

3 Figure 13. Maximum Non-Repetitive Surge

Current
2

+I
1

0.7
IT FORWARD
0.5 REVERSE BREAKOVER
BLOCKING VT POINT
REGION IH
0.3 IDRM
–V +V
0.2 IRRM VDRM
VRRM
FORWARD
REVERSE BLOCKING
0.1 AVALANCHE –I REGION
0 0.4 0.8 1.2 1.6 2 2.4 2.8 REGION
vF, INSTANTANEOUS VOLTAGE (VOLTS)

Figure 12. Maximum Forward Voltage Figure 14. Characteristics and Symbols

1
r(t), TRANSIENT THERMAL RESISTANCE

0.7
0.5
0.3
(NORMALIZED)

0.2
ZθJC(t) = RθJC • r(t)

0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1.0 k 2.0 k 3.0 k 5.0 k 10 k
t, TIME (ms)

Figure 15. Thermal

Response

Motorola Thyristor Device Data 109

 MCR225FP Series

I GT, GATE TRIGGER CURRENT (NORMALIZED)

VGT , GATE TRIGGER VOLTAGE (NORMALIZED)

2 2
VD = 12 V VD = 12 V
1.6 1.6

1.2 1.2

0.8 0.8

0.4 0.4

0 0
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Gate Trigger Current versus Figure 17. Gate Trigger Voltage versus
Temperature Temperature
2
IH , HOLDING CURRENT (NORMALIZED)

VD = 12 V
1.6

1.2

0.8

0.4

0
–60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Holding Current versus Temperature

110 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR264Ć4
thru
MCR264Ć10
Thyristors
Silicon Controlled Rectifiers
SCRs
. . . designed for back-to-back SCR output devices for solid state relays or applications 40 AMPERES RMS
requiring high surge operation. 200 thru 800 VOLTS
• Photo Glass Passivated Blocking Junctions for High Temperature Stability,
Center Gate for Uniform Parameters
• 400 Amperes Surge Capability
• Blocking Voltage to 800 Volts
G
A K

CASE 221A-04
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = 25 to 125°C, Gate Open) VRRM
MCR264-4 200
MCR264-6 400
MCR264-8 600
MCR264-10 800
Forward Current (TC = 80°C) IT(RMS) 40 Amps
(All Conduction Angles) IT(AV) 25
Peak Non-repetitive Surge Current – 8.3 ms ITSM 400 Amps
(1/2 Cycle, Sine Wave) 1.5 ms 450
Forward Peak Gate Power PGM 20 Watts
Forward Average Gate Power PG(AV) 0.5 Watt
Forward Peak Gate Current IGM 2 Amps
(300 µs, 120 PPS)
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
These devices are rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when
the device is to be used at high sustained currents.

REV 1

Motorola Thyristor Device Data 111

 MCR264Ć4 thru MCR264Ć10
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 1 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current I DRM , I RRM
(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Forward “On” Voltage(1) VTM — 1.4 2 Volts
(ITM = 80 A)
Gate Trigger Current (Continuous dc) IGT — 15 50 mA
(Anode Voltage = 12 Vdc, RL = 100 Ohms, TC = – 40°C) — 30 90
Gate Trigger Voltage (Continuous dc) VGT — 1 1.5 Volts
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(Anode Voltage = Rated VDRM, RL = 100 Ohms, TJ = 125°C)
Holding Current IH — 30 60 mA
(Anode Voltage = 12 Vdc)
Turn-On Time tgt — 1.5 — µs
(ITM = 40 A, IGT = 60 mAdc)
Critical Rate-of-Rise of Off-State Voltage dv/dt — 50 — V/µs
(Gate Open, VD = Rated VDRM, Exponential Waveform)
1. Pulse Test: Pulse Width p 300 µs, Duty Cycle p 2%.

FIGURE 1 — AVERAGE CURRENT DERATING FIGURE 2 — MAXIMUM ON-STATE POWER DISSIPATION

125 50
TC, MAXIMUM CASE TEMPERATURE ( ° C)

180°
45
P(AV) , AVERAGE POWER (WATTS)

115 α 40
α = CONDUCTION ANGLE 90°
35 60°
dc
105 30 α = 30°
25
dc
95 20
15
85 α = 30° 10 α
60° α = CONDUCTIVE ANGLE
5.0
90° 180°
75 0
0 5.0 10 15 20 25 0 5.0 10 15 20 25
IT(AV), ON-STATE FORWARD CURRENT (AMPS) IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)

112 Motorola Thyristor Device Data

 MCR264Ć4 thru MCR264Ć10
FIGURE 3 — GATE TRIGGER CURRENT FIGURE 4 — NEW GATE TRIGGER VOLTAGE
40 1.1

VGT , GATE TRIGGER VOLTAGE (VOLTS)

I GT , GATE TRIGGER CURRENT (mA)

1.0 OFF-STATE VOLTAGE = 12 V

OFF-STATE VOLTAGE = 12 V
20 0.9

0.8

0.7
10
0.6
7.0
0.5
5.0
4.0 0.4
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 — HOLDING CURRENT FIGURE 6 — TYPICAL FORWARD VOLTAGE

IF , INSTANTANEOUS FORWARD CURRENT (AMPS)

70
100
50 OFF-STATE VOLTAGE = 12 V
IH , HOLDING CURRENT (mA)

30 TJ = 25°C

20 10

10

7.0
–60 –40 –20 0 20 40 60 80 100 120 140 1.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TJ, JUNCTION TEMPERATURE (°C)
vF, INSTANTANEOUS VOLTAGE (VOLTS)

FIGURE 7 — THERMAL RESPONSE

1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.7
0.5
0.3
(NORMALIZED)

0.2
ZθJC(t) = RθJC • r(t)
0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1k 2k 3k 5k 10 k
t, TIME (ms)

Motorola Thyristor Device Data 113

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR265-2
Thyristors thru
Silicon Controlled Rectifiers
MCR265-10
. . . designed for inverse parallel SCR output devices for solid state relays, welders,
battery chargers, motor controls or applications requiring high surge operation.
• Photo Glass Passivated Blocking Junctions for High Temperature Stability,
Center Gate for Uniform Parameters SCRs
• 550 Amperes Surge Capability 55 AMPERES RMS
• Blocking Voltage to 800 Volts 50 thru 800 VOLTS

G
A K

CASE 221A-04
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = 25 to 125°C, Gate Open) VRRM
MCR265-2 50
MCR265-4 200
MCR265-6 400
MCR265-8 600
MCR265-10 800
Forward Current (TC = 70°C) IT(RMS) 55 Amps
(All Conduction Angles) IT(AV) 35
Peak Non-repetitive Surge Current — 8.3 ms ITSM 550 Amps
(1/2 Cycle, Sine Wave)
Forward Peak Gate Power PGM 20 Watts
Forward Average Gate Power PG(AV) 0.5 Watt
Forward Peak Gate Current IGM 2 Amps
(300 µs, 120 PPS)
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
These devices are rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when
the device is to be used at high sustained currents.

114 Motorola Thyristor Device Data

 MCR265-2 thru MCR265-10
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 0.9 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 125°C — — 2 mA
Forward “On” Voltage(1) VTM — 1.5 1.9 Volts
(ITM = 110 A)
Gate Trigger Current (Continuous dc) IGT mA
(Anode Voltage = 12 Vdc, RL = 100 Ohms) — 20 50
(TC = –40°C) — 40 90
Gate Trigger Voltage (Continuous dc) VGT — 1 1.5 Volts
(Anode Voltage = 12 Vdc, RL = 100 Ohms)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(Anode Voltage = Rated VDRM, RL = 100 Ohms, TJ = 125°C)
Holding Current IH — 30 75 mA
(Anode Voltage = 12 Vdc, Gate Open)
Turn-On Time tgt — 1.5 — µs
(ITM = 55 A, IGT = 200 mAdc)
Critical Rate-of-Rise of Off-State Voltage dv/dt — 50 — V/µs
(Gate Open, VD = Rated VDRM, Exponential Waveform)
1. Pulse Width p 300 µs, Duty Cycle p 2%.

FIGURE 1 — AVERAGE CURRENT DERATING FIGURE 2 — MAXIMUM ON-STATE POWER DISSIPATION

125 60
TC, MAXIMUM CASE TEMPERATURE ( ° C)

121 180°
54
P(AV) , AVERAGE POWER (WATTS)

117 90°
113 α 48 60°
109 α = CONDUCTION ANGLE 42
105 dc
36
101 α = 30°
97 30
93 24 α = 30°
89 dc
85 18
81 12 α
77 60° 90° α = CONDUCTION ANGLE
180° 6.0
73
69 0
0 4.0 8.0 12 16 20 24 28 32 36 40 0 5.0 10 15 20 25 30 35 40
IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS) IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)*

Motorola Thyristor Device Data 115

 MCR265-2 thru MCR265-10
FIGURE 3 — GATE TRIGGER CURRENT FIGURE 4 — GATE TRIGGER VOLTAGE
2.5 3.0
2.0
VD = 12 Vdc 2.0
NORMALIZED GATE CURRENT

NORMALIZED GATE VOLTAGE

1.5 VD = 12 Vdc
1.5
1.0
1.0
0.7 0.8

0.5
0.4 0.5

0.3
0.25 0.3
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

FIGURE 5 — HOLDING CURRENT FIGURE 6 — TYPICAL ON-STATE CHARACTERISTICS

I TM , INSTANTANEOUS ON-STATE CURRENT (AMPS)

3.0 1000
NORMALIZED HOLDING CURRENT

2.0
VD = 12 Vdc
100

1.0
TJ = 25°C
0.7
10
0.5

0.3 1.0
– 60 – 40 – 20 0 20 40 60 80 100 120 140 0 1.0 2.0 3.0
TJ, JUNCTION TEMPERATURE (°C) VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

FIGURE 7 — THERMAL RESPONSE

1.0
r(t), TRANSIENT THERMAL RESISTANCE

0.7
0.5
0.3
(NORMALIZED)

0.2
ZθJC(t) = RθJC • r(t)
0.1
0.07
0.05
0.03
0.02

0.01
0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1k 2k 3k 5k 10k
t, TIME (ms)

116 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifiers MCR310

Reverse Blocking Triode Thyristors
Series
. . . designed for industrial and consumer applications such as temperature, light and
speed control; process and remote controls; warning systems; capacitive discharge
circuits and MPU interface.
• Center Gate Geometry for Uniform Current Density
• All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability SCRs
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat 10 AMPERES RMS
Dissipation and Durability 50 thru 800 VOLTS
• Low Trigger Currents, 200 µA Maximum for Direct Driving from Integrated Circuits

G
A C
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking VDRM Volts
Voltage(1) or
(TJ = –40 to 110°C) VRRM
(1/2 Sine Wave, RGK = 1 kΩ)
MCR310-2 50
MCR310-3 100
MCR310-4 200 K
MCR310-6 400 A CASE 221A-04
MCR310-8 600 G (TO-220AB)
MCR310-10 800 STYLE 3

On-State RMS Current (TC = 75°C) IT(RMS) 10 Amps

Peak Non-repetitive Surge Current ITSM 100 Amps
(1/2 Cycle, 60 Hz, TJ = –40 to 110°C)
Circuit Fusing (t = 8.3 ms) I2t 40 A2s
Peak Gate Voltage (t p 10 µs) VGM ±5 Volts
Peak Gate Current (t p 10 µs) IGM 1 Amp
Peak Gate Power (t p 10 µs) PGM 5 Watts
Average Gate Power PG(AV) 0.75 Watt
Operating Junction Temperature Range TJ –40 to +110 °C
Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque – 8 in.-lb.
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or
negative gate voltage; however, positive gate voltage shall not be applied concurrent with
negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

Motorola Thyristor Device Data 117

 MCR310 Series
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1 kΩ unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Peak Forward Blocking Current(1) TC = 110°C IDRM — — 500 µA
(TJ = 110°C, VD = Rated VDRM) TC = 25°C — — 10 µA
Peak Reverse Blocking Current(1) TC = 110°C IRRM — — 500 µA
(TJ = 110°C, VR = Rated VRRM) TC = 25°C — — 10 µA
On-State Voltage VTM — 1.7 2.2 Volts
(ITM = 20 A Peak, Pulse Width p 1 ms, Duty Cycle p 2%)
Gate Trigger Current, Continuous dc(2) IGT — 30 200 µA
(VD = 12 V, RL = 100 Ω)
Gate Trigger Voltage, Continuous dc VGT Volts
(VD = 12 V, RL = 100 Ω) — 0.5 1.5
(VD = Rated VDRM, RL = 10 kΩ, TJ = 110°C) 0.1 — —
Holding Current IH — — 6 mA
(VD = 12 V, ITM = 100 mA)
Critical Rate of Rise of Forward Blocking Voltage dv/dt — 10 — V/µs
(VD = Rated VDRM, TJ = 110°C, Exponential Waveform)
Gate Controlled Turn-On Time tgt — 1 — µs
(VD = Rated VDRM, ITM = 20 A, IG = 2 mA)
1. Ratings apply for negative gate voltage or RGK = 1 kΩ. Devices shall not have a positive gate voltage concurrently with a negative voltage
on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage
applied exceeds the rated blocking voltage.
2. Does not include RGK current. PAV , AVERAGE POWER DISSIPATION (WATTS)

120 20
TC , MAXIMUM CASE TEMPERATURE (°C)

dc
110 16
α α
α = CONDUCTION ANGLE α = CONDUCTION ANGLE
12 180°
100
90°
α = 30°
90 8 α = 30° 60°
60°
90°
180°
80 4
dc
70 0
0 2 4 6 8 10 0 2 4 6 8 10
IT(AV), AVERAGE ON-STATE CURRENT (AMPS) IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
Figure 19. Average Current Figure 20. On-State Power Dissipation
Derating
3
VGT , GATE TRIGGER VOLTAGE (VOLTS)

0.7
2 VD = 12 Vdc
NORMALIZED GATE CURRENT

VD = 12 Vdc
0.6
0.5
1
0.4

0.3

0.5 0.2

0.1
0.3
–40 –20 0 20 40 60 80 90 100 120 140 –60 –40 –20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Normalized Gate Current Figure 22. Gate Voltage

118 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifiers MCR506

. . . PNPN devices designed for high volume consumer applications such as
Series
temperature, light, and speed control; process and remote control, and warning
systems where reliability of operation is important.
• Passivated Surface for Reliability and Uniformity
• Power Rated at Economical Prices SCRs
• Practical Level Triggering and Holding Characteristics 6 AMPERES RMS
• Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat 50 thru 600 VOLTS
Dissipation and Durability.

G
A K

G CASE 77-08
A
K (TO-225AA)
STYLE 2

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VDRM Volts
(TJ = 25 to 110°C, RGK = 1 kΩ) VRRM
MCR506-2 50
MCR506-3 100
MCR506-4 200
MCR506-6 400
MCR506-8 600
RMS Forward Current (All Conduction Angles) IT(RMS) 6 Amp
Average Forward Current (TC = 93°C) IT(AV) 3.82 Amp
Peak Non-repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = –40 to 110°C) ITSM 40 Amp
Circuit Fusing Considerations (t = 8.3 ms) I2t 2.6 A2s
Peak Gate Power PGM 0.5 Watt
Average Gate Power PG(AV) 0.1 Watt
Peak Forward Gate Current IGM 0.2 Amp
Peak Reverse Gate Voltage VRGM 6 Volts
Operating Junction Temperature Range TJ –40 to 110 °C
Storage Temperature Range Tstg –40 to 150 °C
Mounting Torque(2) — 6 in. lb.
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.
2. Torque rating applies with use of torque washer (Shakeproof WD19523 or equivalent). Mounting torque in excess of 6 in. lb. does not
appreciably lower case-to-sink thermal resistance. Anode lead and heat sink contact pad are common. (See AN290 B)
For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +225°C. For optimum
results, an activated flux (oxide removing) is recommended.

Motorola Thyristor Device Data 119

 MCR506 Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 3 °C/W
Thermal Resistance, Junction to Ambient RθJA 75 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C, RGK = 1000 Ohms unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward Blocking Current IDRM — — 200 µA
(VD = Rated VDRM, TJ = 110°C)
Peak Reverse Blocking Current IRRM — — 200 µA
(VR = Rated VRRM, TJ = 110°C)
Forward “On” Voltage VTM — — 1.9 Volts
(ITM = 12 A Peak)
Gate Trigger Current (Continuous dc) IGT µA
(VAK = 7 Vdc, RL = 100 Ohms) — — 200
(VAK = 7 Vdc, RL = 100 Ohms, TC = –40°C) — — 500
Gate Trigger Voltage (Continuous dc) VGT — — 1 Volts
(VAK = 7 Vdc, RL = 100 Ohms, TC = 25°C)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(VAK = Rated VDRM, RL = 100 Ohms, TJ = 110°C)
Holding Current IH — — 5 mA
(VAK = 7 Vdc, TC = 25°C)
Forward Voltage Application Rate dv/dt — 10 — V/µs
(VD = Rated VDRM, Exponential Waveform, TJ = 110°C)

FIGURE 1 — CURRENT DERATING FIGURE 2 — POWER DISSIPATION

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

P(AV) , AVERAGE POWER DISSIPATION (WATTS)

110 10.0
105
8.0
100

95
6.0
90

85 4.0

80
2.0
75
70 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
IT(RMS), RMS ON-STATE CURRENT (AMPS) IT(RMS), RMS ON-STATE CURRENT (AMPS)

120 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MCR703A
Silicon Controlled Rectifiers thru
Reverse Blocking Triode Thyristors MCR708A*
. . . PNPN devices designed for high volume, low cost consumer applications such as *Motorola preferred devices
temperature, light and speed control; process and remote control; and warning
systems where reliability of operation is critical.
• Small Size SCRs
• Passivated Die Surface for Reliability and Uniformity 4.0 AMPERES RMS
• Low Level Triggering and Holding Characteristics 100 thru 600 VOLTS
• Recommend Electrical Replacement for C106
• Available in Two Package Styles:
Surface Mount Leadforms — Case 369A
Miniature Plastic Package — Straight Leads — Case 369
ORDERING INFORMATION G
A
• To Obtain “DPAK” in Surface Mount Leadform (Case 369A):
Shipped in Sleeves — No Suffix, i.e., MCR706A K
Shipped in 16 mm Tape and Reel — Add “RL” Suffix to Device Number, i.e.,
MCR706ARL
• To Obtain “DPAK” in Straight Lead Version:
Shipped in Sleeves — Add ‘1’ Suffix to Device Number, i.e., MCR706A1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)
A
Characteristic Symbol Value Unit
G
Peak Repetitive Forward and Reverse Blocking Voltage VDRM Volts A
(1) or K
(1/2 Sine Wave) VRRM
(RGK = 1000 Ohms, MCR703A1, MCR703A 100 CASE 369A
TC = –40 to +110°C) MCR704A1, MCR704A 200 STYLE 5
MCR706A1, MCR706A 400
A
MCR708A1, MCR708A 600
Peak Non-repetitive Reverse Blocking Voltage VRSM Volts
(1/2 Sine Wave, RGK = 1000 Ohms, G
TC = –40 to +110°C) MCR703A1, MCR703A 150 A
MCR704A1, MCR704A 250 K
MCR706A1, MCR706A 450 CASE 369
MCR708A1, MCR708A 650 STYLE 5
Average On-State Current (TC = –40 to +90°C) IT(AV) 2.6 Amps
(TC = +100°C) 1.6
0.190
Surge On-State Current (1/2 Sine Wave, 60 Hz, TC = ITSM 25 Amps 4.826
+90°C) 35
(1/2 Sine Wave, 1.5 ms TC =
+90°C)
4.191
0.165

Circuit Fusing (t = 8.3 ms) I2t 2.6 A2s

Peak Gate Power (Pulse Width = 10 µs, TC = 90°C) PGM 0.5 Watt
Average Gate Power (t = 8.3 ms, TC = 90°C) PG(AV) 0.1 Watt
0.100
2.54

Peak Forward Gate Current IGM 0.2 Amp

Peak Reverse Gate Voltage VRGM 6 Volts
0.118
3.0

Operating Junction Temperature Range TJ –40 to +110 °C

Storage Temperature Range Tstg –40 to +150 °C
0.063
1.6

1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or 0.243 ǒinchesǓ
negative gate voltage; however, positive gate voltage shall not be applied concurrent with 6.172 mm
negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded. Figure 23. Figure 1.
Preferred devices are Motorola recommended choices for future use and best overall value. Minimum Pad
Sizes for
REV 1 Surface Mounting
Motorola Thyristor Device Data 121
 MCR703A thru MCR708A
THERMAL CHARACTERISTICS
Characteristic Symbol Min Max Unit
Thermal Resistance, Junction to Case RθJC — 8.33 °C/W
Thermal Resistance, Junction to Ambient (Case 369A-04)(1) RθJA — 80 °C/W
Thermal Resistance, Junction to Ambient (Case 369-03)(2) RθJA — 85 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C and RGK = 1000 ohms unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM µA
(VAK = Rated VDRM or VRRM) TC = 25°C — 10
TC = 110°C — — 200
Peak Forward “On” Voltage VTM — — 2.2 Volts
(ITM = 8.2 A Peak, Pulse Width = 1 to 2 ms, 2% Duty Cycle)
Gate Trigger Current (Continuous dc)(3) IGT µA
(VAK = 12 Vdc, RL = 24 Ohms) — 25 75
(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C) — — 300
Gate Trigger Voltage (Continuous dc) VGT — — 1 Volts
(Source Voltage = 12 V, RS = 50 Ohms)
(VAK = 12 Vdc, RL = 24 Ohms, TC = –40°C)
Gate Non-Trigger Voltage VGD 0.2 — — Volts
(VAK = Rated VDRM, RL = 100 Ohms, TC = 110°C)
Holding Current IH mA
(VAK = 12 Vdc, IGT = 2 mA) TC = 25°C — — 5
(Initiating On-State Current = 200 mA) TC = –40°C — — 10
Total Turn-On Time tgt — 2 — µs
(Source Voltage = 12 V, RS = 6 k Ohms)
(ITM = 8.2 A, IGT = 2 mA, Rated VDRM)
(Rise Time = 20 ns, Pulse Width = 10 µs)
Forward Voltage Application Rate dv/dt — 10 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 110°C)
1. Case 369A-04 when surface mounted on minimum pad sizes recommended.
2. Case 369-03 standing in free air.
3. RGK current not included in measurement.
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( °C)

110 110
TA , MAXIMUM ALLOWABLE AMBIENT

106
90
102
TEMPERATURE ( °C)

0 α π
98 f = 60 Hz 0 α π
70
f = 60 Hz
94

90 50
α = 30° 60° 90° 120° 180° dc
86
α = 30° 60° 90° 180° dc
82 30
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
IT(AV), AVERAGE FORWARD CURRENT (AMP) IT(AV), AVERAGE FORWARD CURRENT (AMP)

Figure 24. Maximum Case Figure 25. Maximum Ambient Temperature

Temperature

122 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Sidac High Voltage MKP1V120

Bilateral Triggers MKP1V130
. . . designed for direct interface with the ac power line. Upon reaching the breakover
voltage in each direction, the device switches from a blocking state to a low voltage
on–state. Conduction will continue like an SCR until the main terminal current drops SIDACs
below the holding current. The plastic axial lead package provides high pulse current O.9 AMPERES RMS
capability at low cost. Glass passivation insures reliable operation. Applications are: 110 thru 280 VOLTS
• High Pressure Sodium Vapor Lighting
• Strobes and Flashers
• Ignitors
• High Voltage Regulators
• Pulse Generators MT1 MT2

CASE 59-04
(DO–41)

Polarity denoted by cathode band

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

MKP1V120
Rating Symbol Unit
MKP1V130
Off–State Repetitive Voltage VDRM "90 Volts
On–State Current RMS (TL = 80°C, Lead Length = 3/8″, IT(RMS) 0.9 Amp
conduction angle = 180°, 60 Hz Sine Wave)
On–State Surge Current (Non–repetitive) ITSM 4 Amps
(60 Hz One Cycle Sine Wave, Peak Value)
Operating Junction Temperature Range TJ –40 to +125 °C
Storage Temperature Range Tstg –40 to +150 °C
Lead Solder Temperature TL 230 °C
(Lead Length w 1/16″ from Case, 10 s Max)
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Lead RθJL 40 °C/W
Lead Length = 3/8″

REV 1

Motorola Thyristor Device Data 123

 MKP1V120 MKP1V130
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; both directions)
Characteristic Symbol Min Typ Max Unit
Breakover Voltage VBO Volts
MKP1V120 110 — 130
MKP1V130 120 — 140
Repetitive Peak Off–State Current IDRM — — 5 µA
(60 Hz Sine Wave, VD = Rated VDRM) TJ = 125°C — — 50
Forward “On’’ Voltage VTM — 1.3 1.5 Volts
(ITM = 1 A)
Dynamic Holding Current IH — — 100 mA
Switching Resistance RS 0.1 — — kΩ
Breakover Current IBO — — 200 µA
Maximum Rate–of–Change of On–State Current MKP1V120, 130 di/dt — 90 — A/µs

140 1.0
TL , MAXIMUM ALLOWABLE LEAD TEMPERATURE (° C)

TL TJ = 125°C
130

IT(RMS) , ON–STATE CURRENT (AMPS)

Sine Wave
120 3/8″ 3/8″ 0.8 Conduction Angle = 180°C
110 Assembled in PCB
100 TJ = 125°C 0.6 Lead Length = 3/8″
Sine Wave
90 Conduction Angle = 180°C
80 0.4
70
60 0.2
50
40
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 20 40 60 80 100 120 140
IT(RMS), ON–STATE CURRENT (AMPS) TA, MAXIMUM AMBIENT TEMPERATURE (°C)

124 Motorola Thyristor Device Data

 MKP1V120 MKP1V130
THERMAL CHARACTERISTICS
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED
1.0
0.7
0.5
The temperature of the lead should be
0.3 measured using a thermocouple placed on the
0.2 lead as close as possible to the tie point. The
thermal mass connected to the tie point is
ZqJL(t) = RqJL • r(t) normally large enough so that it will not
0.1 DTJL = Ppk RqJL[r(t)] significantly respond to heat surges generated
0.07 where: tp TIME
in the diode as a result of pulsed operation
0.05 DTJL = the increase in junction temperature above the once steady–state conditions are achieved.
lead temperature Using the measured value of TL, the junction
0.03
r(t) = normalized value of transient thermal resistance at temperature may be determined by:
0.02 time, t from this figure. For example,
r(tp) = normalized value of transient resistance at time tp. TJ = TL + DTJL
0.01
0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
t, TIME (ms)

TYPICAL CHARACTERISTICS

1.4
VBO , BREAKOVER VOLTAGE (NORMALIZED)

1.0 IH , HOLDING CURRENT (NORMALIZED) 1.2

1.0

0.9 0.8

0.6

0.8 0.4
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Motorola Thyristor Device Data 125

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MKP3V110*
Sidac High Voltage MKP3V120*
Bilateral Triggers MKP3V130*
. . . designed for direct interface with the ac power line. Upon reaching the breakover *Motorola preferred devices
voltage in each direction, the device switches from a blocking state to a low voltage
on–state. Conduction will continue like an SCR until the main terminal current drops
below the holding current. The plastic axial lead package provides high pulse current
SIDACs
capability at low cost. Glass passivation insures reliable operation. Applications are:
1 AMPERE RMS
• High Pressure Sodium Vapor Lighting 100 thru 135 VOLTS
• Strobes and Flashers
• Ignitors
• High Voltage Regulators
• Pulse Generators
MT1 MT2

CASE 267–03
SURMETIC 50
PLASTIC AXIAL

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Min Max Unit
Repetitive Breakover Voltage V(BO) Volts
MKP3V110 100 120
MKP3V120 110 130
MKP3V130 120 140
Off–State Repetitive Voltage VDRM — "90 Volts
On–State RMS Current IT(RMS) — 1 Amp
On–State Surge Current (Non–repetitive) ITSM — 20 Amps
(60 Hz One Cycle Sine Wave, Peak Value)
Operating Junction Temperature Range TJ –40 +125 °C
Storage Temperature Range Tstg –40 +150 °C
Lead Solder Temperature — — +230 °C
(Lead Length w1/16″ from Case, 10 s Max)
THERMAL CHARACTERISTICS
Characteristic Symbol Min Max Unit
Thermal Resistance, Junction to Lead RθJL — 15 °C/W
(Lead Length = 3/8″)

Preferred devices are Motorola recommended choices for future use and best overall value.

126 Motorola Thyristor Device Data

 MKP3V110 MKP3V120 MKP3V130
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; both directions)
Characteristic Symbol Min Typ Max Unit
Breakover Current I(BO) — — 200 µA
Repetitive Peak Off–State Current IDRM — — 10 µA
(60 Hz Sine Wave, VD = 90 V)
Forward “On’’ Voltage VTM — 1.1 1.5 Volts
(ITM = 1 A Peak)
Dynamic Holding Current IH — — 100 mA
Switching Resistance RS 0.1 — — kΩ
Maximum Rate of Change of On–State Current di/dt — 50 — A/µs

CURRENT DERATING

130
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)

TA , MAXIMUM ALLOWABLE AMBIENT

120
α
α
140

TEMPERATURE ( °C)
α = Conduction Angle
110 α = Conduction Angle 120 TJ Rated = 125°C
TJ Rated = 125°C
100
100 80
a = 180°
60
90 40
20
a = 180°
80 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
IT(AV), AVERAGE ON–STATE CURRENT (AMPS) IT(AV), AVERAGE ON–STATE CURRENT (AMPS)

Motorola Thyristor Device Data 127

 MKP3V110 MKP3V120 MKP3V130
THERMAL CHARACTERISTICS
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED
1.0
ZqJL(t) = RqJL • r(t) LEAD LENGTH = 1/4″
0.5 DTJL = Ppk RqJL[r(t)]
where: tp TIME The temperature of the lead should be
0.3 DTJL = the increase in junction temperature above the measured using a thermocouple placed on the
0.2 lead temperature lead as close as possible to the tie point. The
r(t) = normalized value of transient thermal resistance at thermal mass connected to the tie point is
0.1 time, t from this figure. For example, normally large enough so that it will not
r(tp) = normalized value of significantly respond to heat surges generated
0.05 transient resistance at time tp. in the diode as a result of pulsed operation
once steady–state conditions are achieved.
0.03 Using the measured value of TL, the junction
0.02 temperature may be determined by:
TJ = TL + DTJL
0.01
0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k 20 k
t, TIME (ms)

TYPICAL CHARACTERISTICS

100 250
90 225
I(BO) , BREAKOVER CURRENT ( mA)

80 IH , HOLDING CURRENT (mA) 200

70 175
60 150
50 125
40 100
30 75
20 50
10 25
0 0
–60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

128 Motorola Thyristor Device Data

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MMT10V275*
Advance Information MMT10V400*
Thyristor Surge Suppressors
*Motorola preferred devices

High Voltage Bidirectional TVS Devices

BIDIRECTIONAL
These transient voltage suppression (TVS) devices prevent overvoltage THYRISTOR SURGE
damage to sensitive circuits by lightning, induction and power line crossings. SUPPRESSORS
They are breakover–triggered crowbar protectors. Turn–off occurs when the 25 WATTS STEADY STATE
surge current falls below the holding current value.
Applications include current loop lines in telephony and control systems,
central office stations, repeaters, building and residence entrance terminals and
electronic telecom equipment.
• High Surge Current Capability
• Bidirectional Protection in a Single Device
• Little Change of Voltage Limit with Transient Amplitude or Rate
• Freedom from Wearout Mechanisms Present in Non–Semiconductor De-
vices
• Fail–Safe. Shorts When Overstressed, Preventing Continued Unprotected
Operation. CASE 416A–01

DEVICE RATINGS:
– 40°C to 50°C for MMT10V275
– 40°C to 65°C for MMT10V400 (except surge)
Parameter Symbol Value Unit
Peak Repetitive Off–State Voltage — Maximum VDM Volts
MMT10V275 ± 200
MMT10V400 ± 265
On–State Surge Current — Maximum Nonrepetitive (MMT10V400 – 20°C to 65°C)
10 x 1000 µs exponential wave, Notes 1, 2, 3 ITSM1 ± 100 A(pk)
60 Hz ac, 1000 V(rms), RS = 1.0 kΩ, 1 second ISTM2 ± 10 A(rms)
60 Hz ac, 480 V(rms), RS = 48 Ω, 2 seconds ISTM3 ± 1.0 A(rms)
Rate of Change of On–State Current — Maximum Nonrepetitive di/dt 50 A/µs
Critical Damped Wave, C = 1.2 µF, L = 16 µH, R = 7.4,
VCI = 1000 V, I(pk) = 100 A (short circuit), 0 to 50% I (pk)

DEVICE THERMAL RATINGS

Operating Temperature Range TJ1 – 40 to + 125 °C
Blocking or Conducting State
Overload Junction Temperature — Maximum TJ2 + 175 °C
Conducting State Only
Thermal Resistance, Junction to Case — Maximum RθJC 1.5 °C/W
Thermal Resistance, Case to Ambient, Without Heatsink — + 200 °C/W

This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.

Motorola Thyristor Device Data 129

MMT10V275 MMT10V400
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristics Symbol Min Typ Max Unit
Breakover Voltage V(BO)1 Volts
(dv/dt = 100 V/µs, ISC = 10 A, Vdc = 1000 V) MMT10V275 — — 275
MMT10V400 — — 400
Breakover Voltage V(BO)2 Volts
(f = 60 Hz, ISC = 1.0 A(rms), VOC = 1000 V(rms), MMT10V275 — — 275
RI = 1.0 kΩ, t = 0.5 cycle, Note 2) MMT10V400 — — 400
Breakover Voltage Temperature Coefficient dV(BO)/dTJ — 0.05 — %/°C
Breakdown Voltage V(BR) Volts
(I(BR) = 1.0 mA) MMT10V275 200 — —
MMT10V400 265 — —
Breakdown Voltage Temperature Coefficient dV(BO)/dTJ — 0.11 — %/°C
Off State Current (VD = 160 V) ID — — 3.0 µA
On–State Voltage (IT = 10 A) VT — 3.0 4.0 Volts
(PW ≤ 300 µs, Duty Cycle ≤ 2%, Note 2)
Breakover Current (f = 60 Hz, VDM = 1000 V(rms), RS = 1.0 kΩ) IBO — 500 — mA
Holding Current Note 2 IH — 400 — mA
(10 x 100 Ms exponential wave, IT = 10 A, V = 52 V, RS = 200 Ω)
Critical Rate of Rise of Off–State Voltage dv/dt 2000 — — V/µs
(Linear waveform, VD = 0.8 x Rated VDRM, TJ = 125°C)
Capacitance (f = 1.0 MHz, 50 V, 15 mV) CO — 55 — pF
1. Allow cooling before testing second polarity.
2. Measured under pulse conditions to reduce heating.
3. Requires θCS ≤ 6°C/W each side, infinite heatsink.

RθS(A1) RθC(S1) RθJ(C1) RθJ(C2) RθC(S2) RθS(A2)

TA TS1 TC1 TJ TC2 TS2 TA
PD

Terms in the model signify:

TA = Ambient Temp. RθSA = Thermal Resistance, Heatsink to Ambient
TS = Heatsink Temp. RθCS = Thermal Resistance, Case to Heatsink
TC = Case Temp. RθJC = Thermal Resistance, Junction to Case
TJ = Junction Temp. PD = Power Dissipation

Subscripts 1 and 2 denote the device terminals, MT1 and MT2, respectively.
Thermal resistance values are: RθCS = 6°C/W maximum (each side)
RθJC = 3°C/W maximum (each side)
The RθCS values are estimates for dry mounting with heatsinks contacting the
raised pedestal on the package. For minimum thermal resistance, the device
should be sandwiched between clean, flat, smooth conducting electrodes and
securely held in place with a compressive force of 2 pounds maximum. The
electrodes should contact the entire pedestal area. When the device is
mounted symmetrically, the thermal resistances are identical. The values for
RθSA and RθCS are controlled by the user and depend on heatsink design and
mounting conditions.

Figure 9. Thermal Circuit, Device Mounted Between Heatsinks

130 Motorola Thyristor Device Data

 MMT10V275 MMT10V400
600 0

TEMPERATURE COEFFICIENT (mA/ °C)

I H, HOLDING CURRENT (mA) 550

∆ I H , HOLDING CURRENT
500 –1

450
TYPICAL
400 –2

350

300 –3 TYPICAL LOW

250

200 –4
0 10 20 30 40 50 60 70 80 200 250 300 350 400 450 500 550 600
TJ, JUNCTION TEMPERATURE (°C) IH, HOLDING CURRENT AT 0°C (mA)

Figure 10. Typical Holding Current Figure 11. Holding Current Temperature
Coefficient

1.2 10

I BO, NORMALIZED BREAKOVER CURRENT

The thermal coefficient of VF(BR) is similar to that of a zener Note: The behavior of the breakover current during AC operation
NORMALIZED BREAKOVER VOLTAGE

diode. IBO falls with temperature, reducing the zener is complex, due to junction heating, case heating and thermal
1.15 impedance contribution to VBO. This causes the VBO interaction between the device halves. Microplasma conduction
temperature coefficient perature to be less than or equal to the at the beginning of breakdown sometimes results in higher local
VF(BR) coefficient. The graph allows the estimation of the current densities and earlier than predicted switching. This
1.1 maximum voltage rise of either parameter. reduces power dissipation and stress on the device.

1.05 1 MAXIMUM IBO = 1.0 A

at 25°C
1
FIRST HALF–CYCLE
NORMALIZED MINIMUM IBO UNIT
0.95 f = 60 Hz
TO 25°C VOC = 1000 V (rms)
IOC = 1.0 A (rms)
0.9 0.1
– 20 0 20 40 60 80 100 120 140 – 40 – 20 0 20 40 60 80 100 120 140 160
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE PRIOR TO TEST (°C)

Figure 12. Normalized Maximum 60 Hz VBO Figure 13. Temperature Dependence of 60 Hz

versus Junction Temperature Breakover Current

Motorola Thyristor Device Data 131

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Controlled Rectifiers S2800

Reverse Blocking Triode Thyristors Series
. . . designed primarily for half-wave ac control applications, such as motor controls,
heating controls and power supplies; or wherever half–wave silicon gate–controlled,
solid–state devices are needed. SCRs
• Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformity 10 AMPERES RMS
and Stability 50 thru 800 VOLTS
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• Blocking Voltage to 800 Volts
G
A K

CASE 221A-04
(TO-220AB)
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Forward and Reverse Blocking Voltage(1) VRRM Volts
(TJ = 25 to 100°C, Gate Open) VDRM
F 50
A 100
B 200
S2800 D 400
M 600
N 800
Peak Non–repetitive Reverse Voltage and VRSM Volts
Non–Repetitive Off–State Voltage(1) VDSM
F 75
A 125
B 250
S2800 D 500
M 700
N 900
RMS Forward Current IT(RMS) 10 Amps
(All Conduction Angles) TC = 75°C
Peak Forward Surge Current (1 Cycle, Sine Wave, 60 Hz, TC = 80°C) ITSM 100 Amps
Circuit Fusing Considerations (t = 8.3 ms) I2t 40 A2s
Forward Peak Gate Power (t v 10 µs) PGM 16 Watts
Forward Average Gate Power PG(AV) 0.5 Watt
Operating Junction Temperature Range TJ –40 to +100 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate
voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current
source such that the voltage ratings of the devices are exceeded.

132 Motorola Thyristor Device Data

 S2800 Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Forward or Reverse Blocking Current IDRM, IRRM
(VAK = Rated VDRM or VRRM, Gate Open) TC = 25°C — — 10 µA
TC = 100°C — — 2 mA
Instantaneous On–State Voltage, VT — 1.7 2 Volts
(ITM = 30 A Peak, Pulse Width v1 ms, Duty Cycle v 2%)
Gate Trigger Current (Continuous dc) IGT — 8 15 mA
(VD = 12 Vdc, RL = 30 Ohms)
Gate Trigger Voltage (Continuous dc) VGT — 0.9 1.5 Volts
(VD = 12 Vdc, RL = 30 Ohms)
Holding Current IH — 10 20 mA
(Gate Open, VD = 12 Vdc, IT = 150 mA)
Gate Controlled Turn–On Time tqt — 1.6 — µs
(VD = Rated VDRM, ITM = 2 A, IGR = 80 mA)
Circuit Commutated Turn–Off Time tq — 25 — µs
(VD = VDRM, ITM = 2 A, Pulse Width = 50 µs,
dv/dt = 200 V/µs, di/dt = 10 A/µs, TC = 75°C)
Critical Rate–of–Rise of Off–State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Rise, TC = 100°C)

FIGURE 1 – CURRENT DERATING FIGURE 2 – POWER DISSIPATION

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (° C)

12
P(AV) , AVERAGE POWER DISSIPATION (WATTS)

HALF–WAVE
CURRENT WAVEFORM: A SINUSOIDAL
MAXIMUM
100 10
LOAD: RESISTIVE OR INDUCTIVE
MAXIMUM
8
90 IT(RMS)
6

IT(AV) 4 HALF–WAVE
80 CURRENT WAVEFORM: A SINUSOIDAL
LOAD: RESISTIVE OR INDUCTIVE
2
RMS CURRENT
10 AV CURRENT
70 0
0 2 4 6 8 0 2 4 6 8 10
IT(AV), IT(RMS), ON–STATE CURRENT (AMPS) IT(AV), IT(RMS), MAXIMUM ON–STATE CURRENT (AMP)

Motorola Thyristor Device Data 133

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Sensitive Gate Triacs T2322

Silicon Bidirectional Triode Thyristors T2323
. . . designed primarily for ac power switching. The gate sensitivity of these triacs
Series*
*Motorola preferred devices
permits the use of economical transistorized or integrated circuit control circuits, and
it enhances their use in low-power phase control and load-switching applications.
• Very High Gate Sensitivity
SENSITIVE GATE TRIACs
• Low On-State Voltage at High Current Levels
2.5 AMPERES RMS
• Glass-Passivated Chip for Stability
200 thru 600 VOLTS
• Small, Rugged Thermopad Construction for Low Thermal Resistance, High Heat
Dissipation and Durability

MT2

G
MT2
MT1
MT2 MT1 CASE 77-08
G
(TO-225AA)
STYLE 5

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Suffix Symbol Value Unit
Peak Repetitive Off-State Voltage(1) B VDRM 200 Volts
(TJ = 25 to 100°C, Gate Open) D 400
T2322, T2323 M 600
RMS On-State Current (TC = 70°C) IT(RMS) 2.5 Amps
(Full-Cycle Sine Wave 50 to 60 Hz)
Peak Non-repetitive Surge Current ITSM 25 Amps
(One Full Cycle, 60 Hz)
Circuit Fusing I2t 2.6 A2s
(t = 8.3 ms)
Peak Gate Power (1 µs) PGM 10 Watts
Average Gate Power (TC = 60°C + 38.3 ms) PG(AV) 0.15 Watt
Peak Gate Current (1 µs) IGM 0.5 Amp
Operating Junction Temperature Range TJ –40 to +110 °C
Storage Temperature Range Tstg –40 to +150 °C
Mounting Torque (6-32 Screw)(2) — 8 in. lb.
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. Torque rating applies with use of torque washer (Shakeproof WD19523 or equivalent). Mounting Torque in excess of 6 in. lb. does not
appreciably lower case-to-sink thermal resistance. Main terminal 2 and heat-sink contact pad are common.
For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200°C, for 10 seconds.
Consult factory for lead bending options.

Preferred devices are Motorola recommended choices for future use and best overall value.

134 Motorola Thyristor Device Data

 T2322 T2323 Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 3.5 °C/W
Thermal Resistance, Junction to Ambient RθJA 60 °C/W
ELECTRICAL CHARACTERISTICS (TC = 25°C and either polarity of MT2 to MT1 voltage unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 10 µA
TJ = 100°C — 0.2 0.75 mA
Peak On-State Voltage* VTM Volts
(ITM = 10 A) T2323 Series — 1.7 2.6
T2322 Series — 1.7 2.2
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 V, RL = 30 Ω)
All Modes T2322 Series — — 10
MT2(+), G(+); MT2(–), G(–) T2323 Series — — 25
MT2(+), G(–); MT2(–),I G(+) T2323 Series — — 40
Gate Trigger Voltage (Continuous dc) VGT Volts
(VD = 12 Vdc, RL = 30 Ω, TC = 25°C) — 1 2.2
(VD = VDRM, RL = 125 Ω, TC = 100°C) 0.15 — —
Holding Current IH — 15 30 mA
(VD = 12 V, ITM = 150 mA, Gate Open)
Gate Controlled Turn-On Time tgt — 1.8 2.5 µs
(VD = Rated VDRM, ITM = 10 A pk, IG = 60 mA)
Critical Rate-of-Rise of Off-State Voltage dv/dt 10 100 — V/µs
(VD = Rated VDRM, Exponential Waveform, TC = 100°C)
Critical Rate-of-Rise of Commutation Voltage dv/dt(c) 1 4 — V/µs
(VD = Rated VDRM, ITM = 3.5 A pk, Commutating
di/dt = 1.26 A/ms, Gate Unenergized, TC = 90°C)
*Pulse Test: Pulse Width p 300 µs, Duty Cycle p 2%.

Motorola Thyristor Device Data 135

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triacs T2500
Silicon Bidirectional Thyristors Series
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies.
• Blocking Voltage to 800 Volts TRIACs
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity 6 AMPERES RMS
and Stability 200 thru 800 VOLTS
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability

MT2 MT1
G

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) VDRM Volts
(TJ = –40 to +100°C, Gate Open)
T2500 B 200
D 400
M 600
N 800
On-State Current RMS (TC = +80°C) IT(RMS) 6 Amps
(Full Cycle Sine Wave 50 to 60 Hz)
Peak Non-repetitive Surge Current ITSM 60 Amps
(One Full Cycle, 60 Hz, TC = +80°C)
Circuit Fusing Considerations I2t 15 A2s
(t = 8.3 ms)
Peak Gate Power PGM 16 Watts
(TC = +80°C, Pulse Width = 1 µs)
Average Gate Power PG(AV) 0.2 Watt
(TC = +80°C, t = 8.3 ms)
Peak Gate Trigger Current (Pulse Width = 10 µs) IGTM 4 Amps
Operating Junction Temperature Range TJ –40 to +100 °C
Storage Temperature Range Tstg –40 to +150 °C
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

136 Motorola Thyristor Device Data

 T2500 Series
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.7 °C/W

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM — — 2 mA
(Rated VDRM, Gate Open,TJ = 100°C)
Maximum On-State Voltage (Either Direction)* VTM — — 2 Volts
(IT = 30 A Peak)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 12 Ohms)
MT2(+), G(+) — 10 25
MT2(+), G(–) — 20 60
MT2(–), G(–) — 15 25
MT2(–), G(+) — 30 60
Gate Trigger Voltage (Continuous dc) (All Quadrants) VGT Volts
(VD = 12 Vdc, RL = 12 Ohms) — 1.25 2.5
(VD = VDROM, RL = 125 Ohms, TC = 100°C) 0.2 — —
Holding Current (Either Direction) IH — 15 30 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 150 mA)
Gate Controlled Turn-On Time tgt — 1.6 — µs
(Rated VDRM, IT = 10 A , IGT = 160 mA, Rise Time = 0.1 µs)
Critical Rate-of-Rise of Commutation Voltage dv/dt(c) — 10 — V/µs
(Rated VDRM, IT(RMS) = 6 A, Commutating di/dt = 3.2 A/ms,
Gate Unenergized, TC = 80°C)
Critical Rate-of-Rise of Off-State Voltage dv/dt V/µs
(Rated VDRM, Exponential Voltage Rise,
Gate Open, TC = 100°C) T2500B — 100 —
T2500D,M,N — 75 —
*Pulse Test: Pulse Width p 300 µs, Duty Cycle p 2%.

QUADRANT DEFINITIONS
MT2(+)
QUADRANT II QUADRANT I

MT2(+), G(–) MT2(+), G(+)

ELECTRICAL CHARACTERISTICS of RECOMMENDED

BIDIRECTIONAL SWITCHES

G(–) G(+) USAGE General

QUADRANT III QUADRANT IV PART NUMBER MBS4991 MBS4992

VS 6.0 – 10 V 7.5 – 9.0 V

IS 350 µA Max 120 µA Max

MT2(–), G(–) MT2(–), G(+) VS1 – VS2 0.5 V Max 0.2 V Max

Temperature
0.02%/°C Typ
MT2(–) Coefficient

See AN-526 for Theory and Characteristics of Silicon Bidirectional Switches.

Motorola Thyristor Device Data 137

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Silicon Bidirectional T2500FP

Triode Thyristors Series
. . . designed primarily for full-wave ac control applications, such as solid-state relays,
motor controls, heating controls and power supplies; or wherever full-wave silicon ISOLATED TRIACs
gate controlled solid-state devices are needed. Triac type thyristors switch from a THYRISTORS
blocking to a conducting state for either polarity of applied anode voltage with positive 6 AMPERES RMS
or negative gate triggering. 200 thru 800 VOLTS
• Blocking Voltage to 800 Volts
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and
Stability
• Small, Rugged, Isolated Construction for Low Thermal Resistance, High Heat
Dissipation and Durability

MT2 MT1 CASE 221C-02

G
STYLE 3

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Repetitive Peak Off-State Voltage(1) VDRM Volts
(TJ = –40 to +100°C, Gate Open)
T2500BFP 200
T2500DFP 400
T2500MFP 600
T2500NFP 800
On-State RMS Current (TC = +80°C )(2) IT(RMS) 6 Amps
(Full Cycle Sine Wave 50 to 60 Hz)
Peak Non–repetitive Surge Current ITSM 60 Amps
(One Full Cycle, 60 Hz, T C = +80°C)
Circuit Fusing Considerations I2t 40 A2s
(t = 8.3 ms)
Peak Gate Power PGM 1 Watt
(T C = +80°C, Pulse Width = 1 µs)
Average Gate Power PG(AV) 0.2 Watt
(T C = +80°C, t = 8.3 ms)
Peak Gate Trigger Current (Pulse Width = 10 µs) IGTM 4 Amps
RMS Isolation Voltage (TA = 25°C, Relative Humidity p 20%) VISO 1500 Volts
Operating Junction Temperature Range TJ –40 to +100 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case(2) RθJC 2.7 °C/W
Case to Sink RθCS 2.2(typ)
Junction to Ambient RθJA 60
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
2. The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic
body.

138 Motorola Thyristor Device Data

 T2500FP Series
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Off–State Current (Either Direction) IDRM — — 2 mA
(VD = Rated VDRM, TJ = 100°C, Gate Open)
Maximum On-State Voltage (Either Direction)* VTM — — 2 Volts
(IT = 30 A Peak)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 12 Ohms)
MT2(+), G(+) — 10 25
MT2(+), G(–) — 20 60
MT2(–), G(–) — 15 25
MT2(–), G(+) — 30 60
Gate Trigger Voltage (Continuous dc) (All Quadrants) VGT Volts
(VD = 12 Vdc, RL = 12 Ohms) — 1.25 2.5
(VD = VDROM, RL = 125 Ohms, TC = 100°C, All Trigger Models) 0.2 — —
Holding Current (Either Direction) IH — 15 30 mA
(Main Terminal Voltage = 12 Vdc, Gate Open,
Initiating Current = 150 mA, TC = 25°C)
Gate Controlled Turn-On Time t gt — 1.6 — µs
(VD = Rated VDRM, IT = 10 A,
IGT = 160 mA, Rise Time 0.1 µs)p
Critical Rate–of–Rise of Commutation Voltage dv/dt(c) — 10 — V/µs
(VD = Rated VDRM, IT(RMS) = 6 A,
Commutating di/dt = 3.2 A/ms,
Gate Unenergized, TC = 80°C)
Critical Rate–of–Rise of Off–State Voltage dv/dt — 100 — V/µs
(VD = Rated VDRM, Exponential Voltage Rise,
Gate Open, TC = 100°C)
*Pulse Test: Pulse Width p 300 µs, Duty Cycle p 2%.
Quadrant Definitions Electrical Characteristics of Recommended
Bidirectional Switches
MT2(+)
Usage General
Quadrant II Quadrant I
Part Number MBS4991 MBS4992
MT2(+), G(–) MT2(+), G(+) VS 6–10 V 7.5–9 V
Trigger devices are recommended IS 350 µA Max 120 µA Max
for gating on Triacs. They provide:
G(–) G(+) 1. Consistent predictable turn–on VS1–VS2 0.5 V Max 0.2 V Max
points.
Quadrant III Quadrant IV 2. Simplified circuitry. Temperature
3. Fast turn–on time for cooler, 0.02%/°C Typ
Coefficient
more efficient and reliable
MT2(–), G(–) MT2(–), G(+) operation.
MT2(–)

Motorola Thyristor Device Data 139

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

Triacs T2800
Bidirectional Triode Thyristors SERIES
. . . designed primarily for full-wave ac control applications, such as light dimmers,
motor controls, heating controls and power supplies.
• Blocking Voltage to 600 Volts TRIACs
• All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and 8 AMPERES RMS
Stability 200 thru 600 VOLTS
• Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat
Dissipation and Durability
• T2800 — Four Quadrant Gating

MT2 MT1
G

CASE 221A-04
(TO-220AB)
STYLE 4

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted.)

Rating Symbol Value Unit
Peak Repetitive Off-State Voltage(1) VDRM Volts
(TJ = –40 to +100°C, Gate Open)
T2800 B 200
D 400
M 600
RMS On-State Current (TC = +80°C) IT(RMS) 8 Amps
(Conduction Angle = 360°)
Peak Non-repetitive Surge Current ITSM 100 Amps
(One Full Cycle, 60 Hz, TJ = +80°C)
Circuit Fusing I2t 40 A2s
(t = 8.3 ms)
Peak Gate Power (Pulse Width = 1 µs) PGM 16 Watts
Average Gate Power PG(AV) 0.35 Watt
Peak Gate Trigger Current (Pulse Width = 1 µs) IGTM 4 Amps
Operating Junction Temperature Range TJ –40 to +100 °C
Storage Temperature Range Tstg –40 to +150 °C
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 2.2 °C/W
1. VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

REV 1

140 Motorola Thyristor Device Data

 T2800 SERIES
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Peak Blocking Current IDRM
(VD = Rated VDRM, Gate Open) TC = 25°C — — 10 µA
TC = 100°C — — 2 mA
Peak On-State Voltage (Either Direction)* VTM — 1.7 2 Volts
(IT = 30 A Peak)
Gate Trigger Current (Continuous dc) IGT mA
(VD = 12 Vdc, RL = 12 Ohms)
MT2(+), G(+) T2800 — 10 25
MT2(+), G(–) T2800 — 20 60
MT2(–), G(–) T2800 — 15 25
MT2(–), G(+) T2800 — 30 60

Gate Trigger Voltage (Continuous dc) (All Polarities) VGT Volts

(VD = 12 Vdc, RL = 100 Ohms) — 1.25 2.5
(RL = 125 Ohms, VD = VDRM, TC = 100°C) 0.2 — —
Holding Current (Either Direction) IH mA
(VD = 12 Vdc, Gate Open) T2800 — 15 30

Gate Controlled Turn-On Time tgt — 1.6 — µs

(VD = Rated VDRM, IT = 10 A, IGT = 80 mA, Rise Time = 0.1 µs)
Critical Rate-of-Rise of Commutation Voltage dv/dt(c) — 10 — V/µs
(VD = Rated VDRM, IT(RMS) = 8 A, Commutating di/dt = 4.1 A/ms,
Gate Unenergized, TC = 80°C)
Critical Rate-of-Rise of Off-State Voltage dv/dt V/µs
(VD = Rated VDRM, Exponential Voltage Rise,
Gate Open, TC = 100°C)
T2800 B 100 — —
D — — —
M 60 — —
*Pulse Test: Pulse Width p 300 µs, Duty Cycle p 2%.

FIGURE 1 – CURRENT DERATING FIGURE 2 – POWER DISSIPATION

TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)

P(AV) , AVERAGE POWER DISSIPATION (WATTS)

100 12

10
95 FULL CYCLE
FULL CYCLE SINUSOIDAL MAXIMUM
8
SINUSOIDAL WAVEFORM
WAVEFORM TYPICAL
90 6

4
85
2

80 0
0 2 4 6 8 0 2 4 6 8 10 12
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), RMS ON-STATE CURRENT (AMP)

Motorola Thyristor Device Data 141

 Surface Mount
Package Information and
Tape and Reel Specifications

4–1
 INFORMATION FOR USING SURFACE MOUNT THYRISTORS

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total interface between the board and the package. With the
design. The footprint for the semiconductor packages must correct pad geometry, the packages will self align when
be the correct size to insure proper solder connection subjected to a solder reflow process.

0.15
3.8

0.079
2.0
0.165 0.118
4.191 3.0
0.100
0.248
2.54
6.3
0.091 0.091 0.063
2.3 2.3 1.6
0.190 0.243
0.079 4.826 6.172
2.0

0.059 0.059 0.059 inches

1.5 1.5 1.5 mm inches
mm

SOT-223 DPAK

POWER DISSIPATION
The power dissipation of a surface mount thyristor is a board which can defeat the purpose of using surface mount
function of the MT2 or anode pad size. This can vary from technology. A graph of RθJA versus MT2 or anode pad area
the minimum pad size for soldering to a pad size given for for a SOT-223 package is shown in Figure 1.
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance 160
from the device junction to ambient, and the operating
Rθ JA , JUNCTION TO AMBIENT THERMAL

150 TYPICAL L
temperature, TA. Using the values provided on the data 140 MAXIMUM
sheets for various packages, PD can be calculated as 130
follows: 120 L
RESISTANCE, ° C/W

DEVICE MOUNTED ON 4
TJ(max) – TA 110 FIGURE 1 AREA = L2
PD = 100 PCB WITH TAB AREA
RθJA AS SHOWN
90 1 2 3
The values for the equation are found in the maximum 80
ratings table on the data sheets. For example, substituting 70
these values into the equation for a SOT-223 at an ambient 60
temperature TA of 25°C, one can calculate the power 50 MINIMUM
dissipation of the device to be 550 milliwatts. 40 FOOTPRINT = 0.076 cm2
30
110°C – 25°C 0 2.0 4.0 6.0 8.0 10
PD = = 550 milliwatts
156°C/W FOIL AREA (cm2)

Figure 1. Junction to Ambient

The 156°C/W for the SOT-223 package assumes the use
Thermal Resistance versus Copper
of the recommended footprint on a glass epoxy printed circuit
Tab Area
board to achieve a power dissipation of 550 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT-223 package. One is to increase the area of Another alternative would be to use a ceramic substrate or
the MT2 or anode pad. By increasing the area of the MT2 or an aluminum core board such as Thermal Clad. Using a
anode pad, the power dissipation can be increased. Al- board material such as Thermal Clad, an aluminum core
though one can almost double the power dissipation with this board, the power dissipation can be doubled using the same
method, one will be giving up area on the printed circuit footprint.

Surface Mount Package Information and Tape and Reel Specifications Motorola Thyristor Device Data
4–2
 SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed or stainless steel with a typical thickness of 0.008 inches.
circuit board, solder paste must be applied to the pads. A The stencil opening size should be the same as the pad size
solder stencil is required to screen the optimum amount of on the printed circuit board, i.e., a 1:1 registration.
solder paste onto the footprint. The stencil is made of brass
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated • The soldering temperature and time shall not exceed
temperature of the device. When the entire device is heated 260°C for more than 10 seconds.
to a high temperature, failure to complete soldering within a
• When shifting from preheating to soldering, the maximum
short time could result in device failure. Therefore, the
temperature gradient shall be 5°C or less.
following items should always be observed in order to
minimize the thermal stress to which the devices are • After soldering has been completed, the device should be
subjected. allowed to cool naturally for at least three minutes. Gradual
• Always preheat the device. cooling should be used as the use of forced cooling will in-
crease the temperature gradient and result in latent failure
• The delta temperature between the preheat and soldering due to mechanical stress.
should be 100°C or less.*
• Mechanical stress or shock should not be applied during
• When preheating and soldering, the temperature of the cooling.
leads and the case must not exceed the maximum temper-
ature ratings as shown on the data sheet. When using in- *Soldering a device without preheating can cause excessive
frared heating with the reflow soldering method, the differ- thermal shock and stress which can result in damage to the
ence shall be a maximum of 10°C. device.
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control of a test board at or near a central solder joint. The two
settings that will give the desired heat pattern. The operator profiles are based on a high density and a low density board.
must set temperatures for several heating zones, and a The Vitronics SMD310 convection/infrared reflow soldering
figure for belt speed. Taken together, these control settings system was used to generate this profile. The type of solder
make up a heating “profile” for that particular circuit board. On used was 62/36/2 Tin Lead Silver with a melting point
machines controlled by a computer, the computer remem- between 177 –189°C. When this type of furnace is used for
bers these profiles from one operating session to the next. solder reflow work, the circuit boards and solder joints tend to
Figure 2 shows a typical heating profile for use when heat first. The components on the board are then heated by
soldering a surface mount device to a printed circuit board. conduction. The circuit board, because it has a large surface
This profile will vary among soldering systems but it is a good area, absorbs the thermal energy more efficiently, then
starting point. Factors that can affect the profile include the distributes this energy to the components. Because of this
type of soldering system in use, density and types of effect, the main body of a component may be up to 30
components on the board, type of solder used, and the type degrees cooler than the adjacent solder joints.
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7
PREHEAT VENT HEATING HEATING HEATING VENT COOLING
ZONE 1 “SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7
“RAMP” “RAMP” “SOAK” “SPIKE” 205° TO
219°C
200°C 170°C
DESIRED CURVE FOR HIGH PEAK AT
MASS ASSEMBLIES 160°C SOLDER
JOINT
150°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
100°C 140°C (DEPENDING ON
100°C MASS OF ASSEMBLY)

DESIRED CURVE FOR LOW

MASS ASSEMBLIES
50°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

Figure 2. Typical Solder Heating Profile

Motorola Thyristor Device Data Surface Mount Package Information and Tape and Reel Specifications
4–3
Tape and Reel Specifications

Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as the
shipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a secure
cavity for the product when sealed with the “peel-back” cover tape.

• One Reel Size — 7″, 1000 Units SOT-223

• Used for Automatic Pick and Place Feed Systems 12 mm

• Minimizes Product Handling

• EIA 481A DIRECTION
• SOT-223 in 12 mm Tape OF FEED

Use the standard device title to order the SOT-223 package in 12 mm

Tape and Reel. Note that each individual reel has 1000 devices contained
in the tape. Also note the minimum lot size is one full reel for each line item,
and orders are required to be in increments of the single reel quantity.

• One Reel Size — 13″, 2500 Units

• Used for Automatic Handling DPAK
16 mm
• Minimizes Product Handling
• EIA 481A DIRECTION
• DPAK in 16 mm Tape OF FEED
• Add a T4 suffix to the device title to order devices in
16 mm Tape and Reel

Note that each individual reel has 2500 devices contained in the tape. Also note the minimum lot size is one full reel for each
line item, and orders are required to be in increments of the single reel quantity.

Surface Mount Package Information and Tape and Reel Specifications Motorola Thyristor Device Data
4–4
TO–92 EIA, IEC, EIAJ
TO–92
Radial Tape in Fan Fold
RADIAL
Box or On Reel TAPE IN
Radial tape in fan fold box or on reel of the reliable TO–92 package are FAN FOLD
the best methods of capturing devices for automatic insertion in printed
circuit boards. These methods of taping are compatible with various BOX OR
equipment for active and passive component insertion.
• Available in Fan Fold Box
ON REEL
• Available on 365 mm Reels
• Accommodates All Standard Inserters
• Allows Flexible Circuit Board Layout
• 2.5 mm Pin Spacing for Soldering
• EIA–468, IEC 286–2, EIAJ RC1008B

Ordering Notes:
When ordering radial tape in fan fold box or on reel, specify the style per
Figures 3 through 8. Add the suffix “RLR” and “Style” to the device title, i.e.
MPS3904RLRA. This will be a standard MPS3904 radial taped and
supplied on a reel per Figure 9.
Fan Fold Box Information — Minimum order quantity 1 Box/$200LL.
Order in increments of 2000.
Reel Information — Minimum order quantity 1 Reel/$200LL.
Reel Information — Order in increments of 2000.

US/European Suffix Conversions

US EUROPE

RLRA RL

RLRE RL1

RLRM ZL1

Motorola Thyristor Device Data Surface Mount Package Information and Tape and Reel Specifications
4–5
 TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A
H2B H2B

W2
H4 H5
T1
L1
H1
W1 W
L T

F1 T2
F2
P2 P2 D

P1
P

Figure 1. Device Positioning on Tape

Specification
Inches Millimeter
Symbol Item Min Max Min Max
D Tape Feedhole Diameter 0.1496 0.1653 3.8 4.2
D2 Component Lead Thickness Dimension 0.015 0.020 0.38 0.51
F1, F2 Component Lead Pitch 0.0945 0.110 2.4 2.8
H Bottom of Component to Seating Plane .059 .156 1.5 4.0
H1 Feedhole Location 0.3346 0.3741 8.5 9.5
H2A Deflection Left or Right 0 0.039 0 1.0
H2B Deflection Front or Rear 0 0.051 0 1.0
H4 Feedhole to Bottom of Component 0.7086 0.768 18 19.5
H5 Feedhole to Seating Plane 0.610 0.649 15.5 16.5
L Defective Unit Clipped Dimension 0.3346 0.433 8.5 11
L1 Lead Wire Enclosure 0.09842 — 2.5 —
P Feedhole Pitch 0.4921 0.5079 12.5 12.9
P1 Feedhole Center to Center Lead 0.2342 0.2658 5.95 6.75
P2 First Lead Spacing Dimension 0.1397 0.1556 3.55 3.95
T Adhesive Tape Thickness 0.06 0.08 0.15 0.20
T1 Overall Taped Package Thickness — 0.0567 — 1.44
T2 Carrier Strip Thickness 0.014 0.027 0.35 0.65
W Carrier Strip Width 0.6889 0.7481 17.5 19
W1 Adhesive Tape Width 0.2165 0.2841 5.5 6.3
W2 Adhesive Tape Position .0059 0.01968 .15 0.5
NOTES:
1. Maximum alignment deviation between leads not to be greater than 0.2 mm.
2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm.
3. Component lead to tape adhesion must meet the pull test requirements established in Figures 5, 6 and 7.
4. Maximum non–cumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches.
5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive.
6. No more than 1 consecutive missing component is permitted.
7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component.
8. Splices will not interfere with the sprocket feed holes.

Surface Mount Package Information and Tape and Reel Specifications Motorola Thyristor Device Data
4–6
 TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL

FAN FOLD BOX STYLES

ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ADHESIVE TAPE ON ADHESIVE TAPE ON
TOP SIDE TOP SIDE 330 mm

ÇÇÇÇÇÇÇ
FLAT SIDE
13”
ROUNDED SIDE

ÇÇÇÇÇÇÇ
CARRIER MAX
CARRIER STRIP

ÇÇÇÇÇÇÇ
STRIP 252 mm
MAX
9.92”

FLAT SIDE OF TRANSISTOR ROUNDED SIDE OF TRANSISTOR AND

AND ADHESIVE TAPE VISIBLE. ADHESIVE TAPE VISIBLE. 58 mm
2.28”
Style M fan fold box is equivalent to styles E and Style P fan fold box is equivalent to styles A and
MAX
F of reel pack dependent on feed orientation from B of reel pack dependent on feed orientation from
box. box.
Figure 2. Style M Figure 3. Style P Figure 4. Fan Fold Box Dimensions

ADHESION PULL TESTS

500 GRAM PULL FORCE

70 GRAM
100 GRAM
PULL FORCE
PULL FORCE
16 mm
16 mm

HOLDING
HOLDING
FIXTURE
FIXTURE HOLDING
FIXTURE

There shall be no deviation in the leads and

no component leads shall be pulled free of
The component shall not pull free with a 300 gram The component shall not pull free with a 70 gram the tape with a 500 gram load applied to the
load applied to the leads for 3 ± 1 second. load applied to the leads for 3 ± 1 second. component body for 3 ± 1 second.

Figure 5. Test #1 Figure 6. Test #2 Figure 7. Test #3

Motorola Thyristor Device Data Surface Mount Package Information and Tape and Reel Specifications
4–7
 TO–92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
REEL STYLES

CORE DIA.
ARBOR HOLE DIA. 82mm ± 1mm
30.5mm ± 0.25mm

MARKING NOTE

HUB RECESS
76.2mm ± 1mm

RECESS DEPTH
365mm + 3, – 0mm
9.5mm MIN

38.1mm ± 1mm
48 mm
MAX

Material used must not cause deterioration of components or degrade lead solderability

Figure 8. Reel Specifications

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP CARRIER STRIP

ROUNDED
SIDE FLAT SIDE
ADHESIVE TAPE

FEED FEED

Rounded side of transistor and adhesive tape visible. Flat side of transistor and carrier strip visible
(adhesive tape on reverse side).

Figure 9. Style A Figure 10. Style B

ADHESIVE TAPE ON REVERSE SIDE

CARRIER STRIP ROUNDED

CARRIER STRIP
FLAT SIDE SIDE
ADHESIVE TAPE

FEED FEED

Flat side of transistor and adhesive tape visible. Rounded side of transistor and carrier strip visible
(adhesive tape on reverse side).

Figure 11. Style E Figure 12. Style F

Surface Mount Package Information and Tape and Reel Specifications Motorola Thyristor Device Data
4–8
 Outline Dimensions
and Leadform Options

5–1
Outline Dimensions

CASE 29–04
A TO–226AA (TO-92)
B
STYLES 3, 9, 10, 12, 16 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
R 2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
P IS UNCONTROLLED.
L 4. DIMENSION F APPLIES BETWEEN P AND L.
SEATING F DIMENSION D AND J APPLY BETWEEN L AND K
PLANE K MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.
STYLE 3: STYLE 9:
PIN 1. ANODE PIN 1. BASE 1 INCHES MILLIMETERS
2. ANODE 2. EMITTER DIM MIN MAX MIN MAX
3. CATHODE 3. BASE 2 A 0.175 0.205 4.45 5.20
X X D B 0.170 0.210 4.32 5.33
G C 0.125 0.165 3.18 4.19
D 0.016 0.022 0.41 0.55
H J STYLE 10: STYLE 12:
F 0.016 0.019 0.41 0.48
PIN 1. CATHODE PIN 1. MAIN TERMINAL 1
G 0.045 0.055 1.15 1.39
V C 2. GATE 2. GATE
3. ANODE 3. MAIN TERMINAL 2 H 0.095 0.105 2.42 2.66
SECTION X–X J 0.015 0.020 0.39 0.50
1 K 0.500 ––– 12.70 –––
N L 0.250 ––– 6.35 –––
STYLE 16: N 0.080 0.105 2.04 2.66
N P ––– 0.100 ––– 2.54
PIN 1. ANODE
2. GATE R 0.115 ––– 2.93 –––
3. CATHODE V 0.135 ––– 3.43 –––

CASE 59–04
B DO–41

NOTES:
1. POLARITY DENOTED BY CATHODE BAND.
2. LEAD DIAMETER NOT CONTROLLED WITHIN F
D DIMENSION.
K
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A A 5.97 6.60 0.235 0.260
B 2.79 3.05 0.110 0.120
D 0.76 0.86 0.030 0.034
K 27.94 ––– 1.100 –––

CASE 77–08
–B– TO–225AA
U F C (Formerly TO-126) NOTES:
Q STYLES 2, 5 1. DIMENSIONING AND TOLERANCING PER ANSI
M Y14.5M, 1982.
–A– 2. CONTROLLING DIMENSION: INCH.
INCHES MILLIMETERS
1 2 3
DIM MIN MAX MIN MAX
STYLE 2: STYLE 5: A 0.425 0.435 10.80 11.04
PIN 1. CATHODE PIN 1. MT 1 B 0.295 0.305 7.50 7.74
H 2. ANODE 2. MT 2 C 0.095 0.105 2.42 2.66
K 3. GATE 3. GATE D 0.020 0.026 0.51 0.66
F 0.115 0.130 2.93 3.30
G 0.094 BSC 2.39 BSC
H 0.050 0.095 1.27 2.41
J 0.015 0.025 0.39 0.63
V J K 0.575 0.655 14.61 16.63
G M 5 _ TYP 5 _ TYP
R
Q 0.148 0.158 3.76 4.01
S 0.25 (0.010) M A M B M R 0.045 0.055 1.15 1.39
S 0.025 0.035 0.64 0.88
D 2 PL U 0.145 0.155 3.69 3.93
V 0.040 ––– 1.02 –––
0.25 (0.010) M A M B M

Outline Dimensions and Leadform Options Motorola Thyristor Device Data

5–2
 OUTLINE DIMENSIONS—continued

NOTES:
SEATING
CASE 221A–04 1. DIMENSIONING AND TOLERANCING PER ANSI
–T– PLANE TO–220AB Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
STYLES 3, 4 3. DIMENSION Z DEFINES A ZONE WHERE ALL
B C BODY AND LEAD IRREGULARITIES ARE
T ALLOWED.
F S
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
4 STYLE 3: A 0.570 0.620 14.48 15.75
Q A PIN 1. CATHODE B 0.380 0.405 9.66 10.28
2. ANODE C 0.160 0.190 4.07 4.82
1 2 3 U 3. GATE D 0.025 0.035 0.64 0.88
4. ANODE F 0.142 0.147 3.61 3.73
H G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
K J 0.014 0.022 0.36 0.55
Z STYLE 4: K 0.500 0.562 12.70 14.27
PIN 1. MAIN TERMINAL 1 L 0.045 0.055 1.15 1.39
2. MAIN TERMINAL 2 N 0.190 0.210 4.83 5.33
L R 3. GATE Q 0.100 0.120 2.54 3.04
4. MAIN TERMINAL 2 R 0.080 0.110 2.04 2.79
V J S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
G U 0.000 0.050 0.00 1.27
D V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04
N

NOTES:
CASE 221A–06 1. DIMENSIONING AND TOLERANCING PER ANSI
SEATING TO–220AB Y14.5M, 1982.
–T– PLANE 2. CONTROLLING DIMENSION: INCH.
STYLES 3, 4 3. DIMENSION Z DEFINES A ZONE WHERE ALL
B F C BODY AND LEAD IRREGULARITIES ARE
T S ALLOWED.

4 INCHES MILLIMETERS
STYLE 3: DIM MIN MAX MIN MAX
PIN 1. CATHODE A 0.570 0.620 14.48 15.75
Q A B 0.380 0.405 9.66 10.28
2. ANODE
3. GATE C 0.160 0.190 4.07 4.82
1 2 3 U 4. ANODE D 0.025 0.035 0.64 0.88
H F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
K H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
Z STYLE 4:
K 0.500 0.562 12.70 14.27
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2 L 0.045 0.060 1.15 1.52
3. GATE N 0.190 0.210 4.83 5.33
L R Q 0.100 0.120 2.54 3.04
4. MAIN TERMINAL 2
R 0.080 0.110 2.04 2.79
V J S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
G U 0.000 0.050 0.00 1.27
D V 0.045 ––– 1.15 –––
Z ––– 0.080 ––– 2.04
N

–T– SEATING CASE 221C–02 NOTES:

PLANE 1. DIMENSIONING AND TOLERANCING PER ANSI
–B– STYLES 2, 3
F C Y14.5M, 1982.
P S 2. CONTROLLING DIMENSION: INCH.
N 3. LEAD DIMENSIONS UNCONTROLLED WITHIN
DIMENSION Z.
INCHES MILLIMETERS
E STYLE 2: DIM MIN MAX MIN MAX
PIN 1. CATHODE A 0.680 0.700 17.28 17.78
A 2. ANODE B 0.388 0.408 9.86 10.36
Q 3. GATE
H C 0.175 0.195 4.45 4.95
1 2 3 D 0.025 0.040 0.64 1.01
E 0.340 0.355 8.64 9.01
–Y– STYLE 3: F 0.140 0.150 3.56 3.81
PIN 1. MT 1 G 0.100 BSC 2.54 BSC
K 2. MT 2 H 0.110 0.155 2.80 3.93
3. GATE J 0.018 0.028 0.46 0.71
Z
K 0.500 0.550 12.70 13.97
L 0.045 0.070 1.15 1.77
L J N 0.049 ––– 1.25 –––
P 0.270 0.290 6.86 7.36
G R Q 0.480 0.500 12.20 12.70
D 3 PL R 0.090 0.120 2.29 3.04
S 0.105 0.115 2.67 2.92
0.25 (0.010) M B M Y Z 0.070 0.090 1.78 2.28

Motorola Thyristor Device Data Outline Dimensions and Leadform Options

5–3
OUTLINE DIMENSIONS—continued

CASE 267–03
B

NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 2. CONTROLLING DIMENSION: INCH.

INCHES MILLIMETERS
K DIM MIN MAX MIN MAX
A 0.370 0.380 9.40 9.65
B 0.190 0.210 4.83 5.33
D 0.048 0.052 1.22 1.32
K 1.000 ––– 25.40 –––

CASE 318E–04
A SOT–223
F STYLES 10. 11
NOTES:
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. CONTROLLING DIMENSION: INCH.
4
INCHES MILLIMETERS
S B STYLE 10: STYLE 11: DIM MIN MAX MIN MAX
1 2 3 PIN 1. CATHODE PIN 1. MT 1
A 0.249 0.263 6.30 6.70
2. ANODE 2. MT 2
B 0.130 0.145 3.30 3.70
3. GATE 3. GATE
C 0.060 0.068 1.50 1.75
4. ANODE 4. MT 2
D 0.024 0.035 0.60 0.89
D F 0.115 0.126 2.90 3.20
G 0.087 0.094 2.20 2.40
L
G H 0.0008 0.0040 0.020 0.100
J 0.009 0.014 0.24 0.35
J K 0.060 0.078 1.50 2.00
C L 0.033 0.041 0.85 1.05
M 0_ 10 _ 0_ 10 _
0.08 (0003) M S 0.264 0.287 6.70 7.30
H
K

CASE 369–07
B C STYLE 5
V R E NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.235 0.250 5.97 6.35
1 2 3
B 0.250 0.265 6.35 6.73
STYLE 5:
C 0.086 0.094 2.19 2.38
S PIN 1. GATE
D 0.027 0.035 0.69 0.88
2. ANODE
–T– 3. CATHODE E 0.033 0.040 0.84 1.01
SEATING K 4. ANODE F 0.037 0.047 0.94 1.19
PLANE G 0.090 BSC 2.29 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
J K 0.350 0.380 8.89 9.65
F R 0.175 0.215 4.45 5.46
H S 0.050 0.090 1.27 2.28
D 3 PL V 0.030 0.050 0.77 1.27

G 0.13 (0.005) M T

Outline Dimensions and Leadform Options Motorola Thyristor Device Data

5–4
OUTLINE DIMENSIONS—continued

CASE 369A–13
STYLE 5
–T– SEATING
PLANE NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
B C Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V R E
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
4 A 0.235 0.250 5.97 6.35
Z B 0.250 0.265 6.35 6.73
A STYLE 5: C 0.086 0.094 2.19 2.38
S PIN 1. GATE D 0.027 0.035 0.69 0.88
1 2 3 2. ANODE E 0.033 0.040 0.84 1.01
U 3. CATHODE F 0.037 0.047 0.94 1.19
K 4. ANODE G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
F J K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
L H R 0.175 0.215 4.45 5.46
S 0.020 0.050 0.51 1.27
D 2 PL U 0.020 ––– 0.51 –––
V 0.030 0.050 0.77 1.27
G 0.13 (0.005) M T Z 0.138 ––– 3.51 –––

CASE 416A–01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
0.0127 (0.0005) T Y14.5M, 1982.
–T– 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION M AND P MAXIMUM MISALIGNMENT
C M OF HALFS.
NOTE 3
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.110 0.120 2.79 3.05
B 0.110 0.120 2.79 3.05
P C 0.072 0.080 1.83 2.03
A B N R NOTE 3 E 0.006 0.010 0.15 0.25
M ––– 4_ ––– 4_
N 0.073 0.077 1.85 1.96
P ––– 0.130 ––– 3.30
R 0.065 0.070 1.65 1.78

R
E
N

Motorola Thyristor Device Data Outline Dimensions and Leadform Options

5–5
Leadform Options — TO-92 (Case 29) & TO-225AA (Case 77)
Plastic packaged semiconductors may be leadformed to a applicable leadform number, then contact your local Motorola
variety of configurations for insertion into sockets or circuit representative for the special part number and pricing.
boards. Leadform options require assignment of a special Leadform orders require a minimum order quantity and are
part number before ordering. To order leadformed product, non-cancellable after processing.
determine the desired leadform, the case number and

CASE 29 CASE 29
LEADFORM 5* LEADFORM 18*
(TO-92 to fit TO-5) (TO-92 to fit TO-18)

0.280
0.250 0.019 0.250
0.018 DIA. 0.01
0.140
0.140
REF.

0.587 0.587
0.593 0.180 0.593 0.180

0.200 DIA. 0.013 RAD.

0.030 0.003
PIN CIRCLE 0.090 RAD. 0.095
0.010
0.085
RAD.

1 2 3
12 3

0.100 0.150

0.100
5° Typ.
DIA.
0.055
0.045

CASE 77 CASE 77
LEADFORM VA LEADFORM VB

0.927
0.867
0.880
0.828

0.093 0.255
Typ. 0.500 0.285
30° REF.

0.100
MOUNTING SURFACE

Outline Dimensions and Leadform Options Motorola Thyristor Device Data

5–6
TO-92 & TO-225AA Leadform Options (continued)

CASE 77 CASE 77
LEADFORM VD LEADFORM VE

0.608 ± .010

UNDERSIDE 0.094 TYP.

UNDERSIDE
OF LEAD 0.387 ± .01 OF LEAD 0.680 ± .015
.050 REF. 0.050 REF.
CL
0.575 ± .015
CL

0.100 ± .01 0.02R ± .005 TYP.

BOTTOM OF BOTTOM OF 0.190 MIN
HEATSINK HEATSINK
0.350 MAX.

CASE 77 CASE 77
LEADFORM VK LEADFORM VL

0.497 ± .005
0.472 ± .015

0.140
± .010

UNDERSIDE UNDERSIDE
OF LEAD OF LEAD
.050 REF. .050 REF.

BOTTOM OF BOTTOM OF
HEATSINK HEATSINK

Motorola Thyristor Device Data Outline Dimensions and Leadform Options

5–7
TO-92 & TO-225AA Leadform Options (continued)

CASE 77 CASE 77
LEADFORM VP LEADFORM VS

0.278
REF.
0.340 0.740
± .005 0.510 MIN. 0.840 MIN.
± .005

UNDERSIDE
0.500 ± .005 OF LEAD
CL
0.330 ± .005 0.050 REF. 0.018 RAW LEAD (REF.)
CL

0.220
± .005 0.025 R 0.050 MAX.
MOUNTING SURFACE
MAX. TYP.
BOTTOM OF 0.200 ± .01 0.180 ± .03
(Metal) HEATSINK 30°
REF.

Outline Dimensions and Leadform Options Motorola Thyristor Device Data

5–8
Leadform Options — TO-220 (Case 221A)
• Leadform options require assignment of a special part number before ordering.
• Contact your local Motorola representative for special part number and pricing.
• 10,000 piece minimum quantity orders are required.
• Leadform orders are non-cancellable after processing.
• Leadforms apply to both Motorola Case 221A-04 and 221A-06 except as noted.

LEADFORM AS LEADFORM BC

.950 MIN. 1.00 MIN.

.100 REF.
.20 REF.
.736 ± .010
0.100 TYP.
.620 ± .015
0.750 MAX.

0.100 TYP.

.125 ± .010 MOUNTING

SURFACE

LEADFORM AN

0.040 RAD
± 0.015

" 0.020 " .02

.380
" .03
.285 .186

MOUNTING
SURFACE .580
" 0.015
.240
± .010

Motorola Thyristor Device Data Outline Dimensions and Leadform Options

5–9
TO-220 Leadform Options (continued)

LEADFORM AF LEADFORM BA

CASE A B
221A-04 0.220 Min. 0.325 Min.
MOUNTING
SURFACE 221A-06 0.190 Min. 0.290 Min.

.660
± .02 .557
.040 MIN.
(REF.)

CL LEAD
.050 REF.
"
0.018
.100 REF. .005
.200 REF.
B A 0.020 RAD.
TYP. MOUNTING
SURFACE
0.100 TYP. 0.100 0.586
±0.020 TYP. 0.616

LEADFORM BL LEADFORM AK

" .010
.140
CASE A
221A-04 0.325 Min.
.500
.600
± .02 221A-06 0.290 Min.
± 0.015
" .010
.590
.150 MIN
" 0.015
.775

UNDERSIDE
OF LEAD
.095 + .010

.06 R .017
.100 REF
REF
A .025 R .200 REF
.050 REF
MAX
MOUNTING
SURFACE .015
.015

.032 REF

Outline Dimensions and Leadform Options Motorola Thyristor Device Data

5–10
 TO-220 Leadform Options (continued)

LEADFORM BG LEADFORM BS

0.607
0.080 ± 0.015
± 0.015
0.620 REF.
0.780 ± 0.015

0.325
± 0.020

" 0.020
0.296

LEADFORM AJ LEADFORM AU

CASE A CASE A
221A-04 0.360 ± 0.010 221A-04 0.920 Min.
221A-06 Lead Not Trimmed 221A-06 0.885 Min.
0.300 Min.

" .01
.100 REF. .765

" .01
.200 REF. .574

" .004 " .010

.017 .580
.050 REF. A
.032 REF.
.06 R
A

LEADFORM 3 LEADS .095 REF.

.190 ± .020

Motorola Thyristor Device Data Outline Dimensions and Leadform Options

5–11
TO-220 Leadform Options (continued)

LEADFORM BU LEADFORM BV

.680 ± .005 0.005

± 0.005

UNDERSIDE 0.102 ± 0.005

OF LEAD
.094 ± .01 0.680 ± 0.005
.005 ± .005

.102 ± .003
MOUNTING
SURFACE

LEADFORM BD LEADFORM DW

.100 REF.
" .010
.735
.800 ± .050
.20 REF. 3 LEADS

" .010
.610

.223
± .010

Outline Dimensions and Leadform Options Motorola Thyristor Device Data

5–12
 Index and
Cross Reference

6–1
Index and Cross Reference
The following table represents a cross-reference guide for all Thyristor devices which are manufactured by Motorola. Where
the Motorola part number differs from the Industry part number, the Motorola device is a “form, fit and function” replacement for
the Industry part number; however, some differences in characteristics and/or specifications may exist.

Motorola Motorola Motorola Motorola

Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

2N1601 MCR12D 3–141 2N3937 MCR12D 3–141

2N1602 MCR12D 3–141 2N3938 MCR12D 3–141
2N1603 MCR12D 3–141 2N3939 MCR12D 3–141
2N1604 MCR12D 3–141 2N3940 MCR12M 3–141
2N1770 MCR12D 3–141 2N4096 MCR103 3–156
2N1771 MCR12D 3–141 2N4097 MCR100–3 3–154
2N1771A MCR12D 3–141 2N4098 MCR100–4 3–154
2N1772 MCR12D 3–141 2N4101 S2800M 3–193
2N1772A MCR12D 3–141 2N4102 S2800M 3–193
2N1773 MCR12D 3–141 2N4103 2N6508 3–26
2N1773A MCR12D 3–141 2N4108 MCR103 3–156
2N1774 MCR12D 3–141 2N4109 MCR100–3 3–154
2N1774A MCR12D 3–141 2N4110 MCR100–4 3–154
2N1775 MCR12D 3–141 2N4144 MCR102 3–156
2N1775A MCR12D 3–141 2N4145 MCR102 3–156
2N1776 MCR12D 3–141 2N4147 MCR103 3–156
2N1776A MCR12D 3–141 2N4148 MCR100–3 3–154
2N1777 MCR12D 3–141 2N4149 MCR100–4 3–154
2N1777A MCR12D 3–141 2N4167 MCR12D 3–141
2N1778 MCR12M 3–141 2N4168 MCR12D 3–141
2N1778A MCR12M 3–141 2N4169 MCR12D 3–141
2N2575 2N6505 3–26 2N4170 MCR12D 3–141
2N2576 2N6507 3–26 2N4171 MCR12D 3–141
2N2679 MCR102 3–156 2N4172 MCR12D 3–141
2N2680 MCR103 3–156 2N4173 MCR12M 3–141
2N2682 MCR100–4 3–154 2N4174 MCR12M 3–141
2N2683 MCR102 3–156 2N4183 MCR12D 3–141
2N2684 MCR103 3–156 2N4184 MCR12D 3–141
2N2685 MCR100–3 3–154 2N4185 MCR12D 3–141
2N2686 MCR100–4 3–154 2N4186 MCR12D 3–141
2N2687 MCR102 3–156 2N4187 MCR12D 3–141
2N2688 MCR103 3–156 2N4188 MCR12D 3–141
2N2689 MCR100–3 3–154 2N4189 MCR12M 3–141
2N2690 MCR100–4 3–154 2N4190 MCR12M 3–141
2N2919 MCR12M 3–141 2N4332 MCR102 3–156
2N3001 MCR102 3–156 2N4333 MCR103 3–156
2N3002 MCR103 3–156 2N4334 MCR100–3 3–154
2N3003 MCR100–3 3–154 2N4335 MCR100–4 3–154
2N3004 MCR100–4 3–154 2N4336 MCR100–4 3–154
2N3005 MCR102 3–156 2N4441 MCR218–2 3–161
2N3006 MCR103 3–156 2N4442 MCR218–4 3–161
2N3007 MCR100–3 3–154 2N4443 MCR218–6 3–161
2N3008 MCR100–4 3–154 2N4444 MCR218–8 3–161
2N3027 MCR102 3–156 2N5060 2N5060 3–2
2N3028 MCR103 3–156 2N5061 2N5061 3–2
2N3029 MCR100–3 3–154 2N5062 2N5062 3–2
2N3030 MCR102 3–156 2N5064 2N5064 3–2
2N3031 MCR103 3–156 2N5722 MCR100–6 3–154
2N3032 MCR100–3 3–154 2N5724 MCR103 3–156
2N3228 S2800B 3–193 2N5725 MCR100–3 3–154
2N3254 MCR102 3–156 2N5726 MCR100–4 3–154
2N3255 MCR102 3–156 2N5754 2N6071 3–10
2N3256 MCR103 3–156 2N5755 2N6071 3–10
2N3257 MCR102 3–156 2N5756 2N6073 3–10
2N3258 MCR102 3–156 2N5757 2N6073 3–10
2N3259 MCR103 3–156 2N6027 2N6027 3–6
2N3269 MCR12D 3–141 2N6028 2N6028 3–6
2N3270 MCR12D 3–141 2N6068 2N6071 3–10
2N3271 MCR12D 3–141 2N6068A 2N6071A 3–10
2N3272 MCR12D 3–141 2N6069 2N6071 3–10
2N3668 2N6506 3–26 2N6069A 2N6071A 3–10
2N3669 2N6506 3–26 2N6070 2N6071 3–10
2N3936 MCR12D 3–141 2N6070A 2N6071A 3–10

Index and Cross Reference Motorola Thyristor Device Data

6–2
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

2N6071 2N6071 3–10 2N881 MCR100–4 3–154

2N6071A 2N6071A 3–10 2N884 MCR102 3–156
2N6072 2N6073 3–10 2N885 MCR102 3–156
2N6072A 2N6073A 3–10 2N886 MCR103 3–156
2N6073 2N6073 3–10 2N887 MCR100–3 3–154
2N6073A 2N6073A 3–10 2N888 MCR100–4 3–154
2N6074B 2N6075B 3–10 2N889 MCR100–4 3–154
2N6075 2N6075 3–10 2N948 MCR102 3–156
2N6075B 2N6075B 3–10 2N949 MCR103 3–156
2N6151 MAC210A4 3–75 2N950 MCR100–3 3–154
2N6152 MAC210A6 3–75 BRB10–400B MAC12D 3–53
2N6153 MAC210A8 3–75 BRX44 BRX44 3–30
2N6154 MAC210A4 3–75 BRX45 BRX45 3–30
2N6155 MAC210A6 3–75 BRX46 BRX46 3–30
2N6156 MAC210A8 3–75 BRX47 BRX47 3–30
2N6234 2N6238 3–15 BRX49 BRX49 3–30
2N6235 2N6238 3–15 BRY55M–300 BRY55–400 3–32
2N6236 2N6237 3–15 BRY55M–400 BRY55–400 3–32
2N6237 2N6237 3–15 BRY55M–600 BRY55–600 3–32
2N6238 2N6238 3–15 BRY55–100 BRY55–100 3–32
2N6239 2N6239 3–15 BRY55–200 BRY55–200 3–32
2N6240 2N6240 3–15 BRY55–30 BRY55–30 3–32
2N6241 2N6241 3–15 BRY55–400 BRY55–400 3–32
2N6342 2N6342 3–18 BRY55–500 BRY55–500 3–32
2N6342A 2N6344 3–22 BRY55–60 BRY55–60 3–32
2N6343 2N6343 3–18 BRY55–600 BRY55–600 3–32
2N6343 MAC9D 3–49 BT137G–600 MAC9M 3–49
2N6343A MAC12D 3–53 BT137G–800 MAC9N 3–49
2N6344 2N6344 3–18 BT137G400 MAC9D 3–49
2N6344 MAC9M 3–49 BT137–500E MAC228A8 3–106
2N6344A MAC12D 3–53 BT137–500F T2800M 3–201
2N6345 2N6345 3–18 BT137–500G MAC228A8 3–106
2N6345 MAC9N 3–49 BT137–600E MAC228A8 3–106
2N6345A 2N6345A MAC12M 3–53 BT137–600F T2800M 3–201
2N6346 2N6346 3–18 BT137–600G MAC228A8 3–106
2N6346A 2N6346A 3–22 BT137–800E MAC228A10 3–106
2N6347 2N6347 3–18 BT137–800G MAC228A10 3–106
2N6347A 2N6347A 3–22 BT138–500G 2N6348A 3–22
2N6348 2N6348 3–18 BT138–600G 2N6348A 3–22
2N6348A 2N6348A 3–22 BT139G–400 MAC16D 3–67
2N6349 2N6349 3–18 BT139G–600 MAC16M 3–67
2N6349A 2N6349A 3–22 BT139G–800 MAC16N 3–67
2N6394 MCR12D 3–141 BT149A 2N5062 3–2
2N6395 MCR12D 3–141 BT149B 2N5064 3–2
2N6396 MCR12D 3–141 BT149D MCR100–6 3–154
2N6397 MCR12D 3–141 BT149E MCR100–8 3–154
2N6397 MCR12D 3–141 BT149F 2N5061 3–2
2N6398 MCR12M 3–141 BT149M MCR100–8 3–154
2N6398 MCR12M 3–141 BT151–500R MCR12M 3–141
2N6399 MCR12N 3–141 BT151–650R MCR12N 3–141
2N6399 MCR12N 3–141 BT151–800A MCR12N 3–141
2N6400 MCR16D 3–143 BT152–400R 2N6507 3–26
2N6401 MCR16D 3–143 BT152–600R 2N6508 3–26
2N6402 MCR16D 3–143 BT152–800R 2N6509 3–26
2N6403 MCR16D 3–143 BT153 MCR218–8 3–161
2N6403 MCR16D 3–143 BTA04–200A T2500BFP 3–199
2N6404 MCR16M 3–143 BTA04–400A T2500DFP 3–199
2N6404 MCR16M 3–143 BTA04–600A T2500MFP 3–199
2N6405 MCR16N 3–143 BTA04–800A T2500NFP 3–199
2N6405 MCR16N 3–143 BTA06–200A T2500BFP 3–199
2N6504 2N6504 3–26 BTA06–200C T2500BFP 3–199
2N6505 2N6505 3–26 BTA06–400A T2500DFP 3–199
2N6506 2N6506 3–26 BTA06–400C T2500DFP 3–199
2N6507 2N6507 3–26 BTA06–600A T2500MFP 3–199
2N6508 2N6508 3–26 BTA06–600C T2500MFP 3–199
2N6509 2N6509 3–26 BTA06–800A T2500NFP 3–199
2N877 MCR102 3–156 BTA06–800C T2500NFP 3–199
2N878 MCR103 3–156 BTA08–200A MAC229A4FP 3–112
2N879 MCR100–3 3–154 BTA08–200C MAC229A4FP 3–112
2N880 MCR100–4 3–154 BTA08–400A MAC229A6FP 3–112

Motorola Thyristor Device Data Index and Cross Reference

6–3
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

BTA08–400C MAC229A6FP 3–112 BTB12–600B MAC212A8 3–83

BTA08–600A MAC229A8FP 3–112 BTB12–600C MAC310A8 3–114
BTA08–600C MAC229A8FP 3–112 BTB12–800B MAC212A10 3–83
BTA08–800A MAC229A10FP 3–112 BTB16–400BW MAC15D 3–55
BTA08–800C MAC229A10FP 3–112 BTB16–400CW MAC15D 3–55
BTA10–200B MAC210A4FP 3–79 BTB16–600BW MAC15M 3–55
BTA10–200C MAC210A4FP 3–79 BTB16–600CW MAC15M 3–55
BTA10–400B MAC210A6FP 3–79 BTB16–800BW MAC15N 3–55
BTA10–400C MAC210A6FP 3–79 BTB16–800CW MAC15N 3–55
BTA10–600B MAC210A8FP 3–79 BTB16–200B MAC320A4 3–116
BTA10–600C MAC210A8FP 3–79 BTB16–400B MAC320A6 3–116
BTA10–800B MAC210A10FP 3–79 BTB16–600B MAC320A8 3–116
BTA10–800C MAC210A10FP 3–79 BTB16–800B MAC320A10 3–116
BTA12–200B MAC212A4FP 3–87 BTB24–200B MAC223A4FP 3–100
BTA12–200C MAC212A4FP 3–87 BTB24–400B MAC223A6FP 3–100
BTA12–400B MAC212A6FP 3–87 BTB24–600B MAC223A8FP 3–100
BTA12–400C MAC212A6FP 3–87 BTB24–800B MAC223A10FP 3–100
BTA12–600B MAC212A8FP 3–87 C103A 2N5062 3–2
BTA12–600C MAC212A8FP 3–87 C103B 2N5064 3–2
BTA12–800B MAC212A10FP 3–87 C103Y 2N5060 3–2
BTA12–800C MAC212A10FP 3–87 C103YY 2N5061 3–2
BTA16–200B MAC320A4FP 3–120 C106A C106A 3–34
BTA16–200C MAC320A4FP 3–120 C106B C106B 3–34
BTA16–400B MAC320A6FP 3–120 C106D C106D 3–34
BTA16–400C MAC320A6FP 3–120 C106E C106M 3–34
BTA16–600B MAC320A8FP 3–120 C106E1 C106M 3–34
BTA16–600C MAC320A8FP 3–120 C106E2 C106M 3–34
BTA16–800B MAC320A10FP 3–120 C106F C106F 3–34
BTA16–800C MAC320A10FP 3–120 C106M C106M 3–34
BTA20C T2801D MAC9D 3–49 C106M1 C106M 3–34
BTA20D T2801D MAC9D 3–49 C106M2 C106M 3–34
BTA20E T2801M MAC9M 3–49 C106M41 C106M 3–34
BTA21C MAC9D 3–49 C106N C106M 3–34
BTA21D MAC9D 3–49 C106Q1 C106M 3–34
BTA21E MAC9M 3–49 C106Q11 C106M 3–34
BTA22B MAC12D 3–53 C106Q2 C106M 3–34
BTA22C MAC12D 3–53 C106Q21 C106M 3–34
BTA22D MAC12D 3–53 C106Q4 C106M 3–34
BTA22E MAC12M 3–53 C106S C106M 3–34
BTA22M MAC12M 3–53 C107E C106M 3–34
BTA23B 2N6346A 3–22 C107M C106M 3–34
BTA23C 2N6347A 3–22 C108A1 MCR106–2 3–158
BTA23D 2N6347A 3–22 C108B1 MCR106–4 3–158
BTA23E 2N6348A 3–22 C108C1 MCR106–6 3–158
BTA23M 2N6348A 3–22 C108D1 MCR106–6 3–158
BTB06–200B MAC9D 3–49 C108E1 MCR106–8 3–158
BTB06–400B MAC9D 3–49 C108M1 MCR106–8 3–158
BTB06–700B MAC9N 3–49 C108M2 MCR106–8 3–158
BTB08–400BW MAC9D 3–49 C108Y1 MCR106–2 3–158
BTB08–400CW MAC9D 3–49 C10A MCR12D 3–141
BTB08–600BW MAC9M 3–49 C10B MCR12D 3–141
BTB08–600CW MAC9M 3–49 C10F MCR12D 3–141
BTB08–800BW MAC9N 3–49 C10G MCR12D 3–141
BTB08–800CW MAC9N 3–49 C10V MCR12D 3–141
BTB08–200C MAC229A4 3–110 C11A MCR12D 3–141
BTB08–200S MAC228A4 3–106 C11B MCR12D 3–141
BTB08–400C MAC229A6 3–110 C11C MCR12D 3–141
BTB08–400S MAC228A6 3–106 C11D MCR12D 3–141
BTB08–700S MAC228A10 3–106 C11E MCR12M 3–141
BTB08–800C MAC229A10 3–110 C11F MCR12D 3–141
BTB10–200B MAC12D 3–53 C11G MCR12D 3–141
BTB10–200C MAC310A4 3–114 C11H MCR12D 3–141
BTB10–400C MAC310A6 3–114 C11M MCR12M 3–141
BTB10–600C MAC310A8 3–114 C11U MCR12D 3–141
BTB10–700B MAC12N 3–53 C122A C122A1 3–37
BTB10–800C MAC210A10 3–75 C122B C122B1 3–37
BTB12–200B MAC212A4 3–83 C122D C122D1 3–37
BTB12–200C MAC310A4 3–114 C122D1 MCR8D 3–137
BTB12–400B MAC212A6 3–83 C122F C122F1 3–37
BTB12–400C MAC310A6 3–114 C122F1 MCR8D 3–137

Index and Cross Reference Motorola Thyristor Device Data

6–4
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

C122F1 C122F1 3–37 L2001L5 T2322B 3–195

C122M C122M1 3–37 L2001L7 T2322B 3–195
C122M1 MCR8M 3–137 L2001L9 T2322B 3–195
C122M1 C122M1 3–37 L2001M7 2N6071A 3–10
C122N C122N1 3–37 L2001M9 2N6071 3–10
C122N1 MCR8N 3–137 L2003M3 2N6071A 3–10
C122N1 C122N1 3–37 L2003M7 2N6071A 3–10
C122S C122N1 3–37 L2003M9 2N6071 3–10
C122S1 C122N1 3–37 L2004F51 2N6071A 3–10
C126A MCR12D 3–141 L2004F71 2N6071 3–10
C126B MCR12D 3–141 L2004F91 2N6071 3–10
C126C MCR12D 3–141 L2004L5 2N6071A 3–10
C126D MCR12D 3–141 L2004L9 2N6071A 3–10
C126E MCR12M 3–141 L2006L6 MAC228A4 3–106
C126F MCR12D 3–141 L2006L7 MAC228A4 3–106
C126M MCR12M 3–141 L2008L6 MAC228A4 3–106
C127A MCR16D 3–143 L2008L7 MAC228A4 3–106
C127B MCR16D 3–143 L2008L9 MAC228A4 3–106
C127C MCR16D 3–143 L200E3 MAC97A4 3–71
C127D MCR16D 3–143 L200E5 MAC97A4 3–71
C15B MCR12D 3–141 L200E7 MAC97–4 3–71
C15C MCR12D 3–141 L200E9 MAC97–4 3–71
C15D MCR12D 3–141 L4001F71 2N6073A 3–10
C15F MCR12D 3–141 L4001F91 2N6073 3–10
C15G MCR12D 3–141 L4001L7 T2322D 3–195
C15H MCR12D 3–141 L4001L9 T2322D 3–195
C20A MCR12D 3–141 L4001M7 2N6073A 3–10
C20B MCR12D 3–141 L4001M9 2N6073 3–10
C20C MCR12D 3–141 L4003M7 2N6073A 3–10
C20D MCR12D 3–141 L4003M9 2N6073 3–10
C20F MCR12D 3–141 L4004F51 2N6073A 3–10
C20U MCR12D 3–141 L4004F71 2N6073 3–10
EC103A 2N5062 3–2 L4004F91 2N6073 3–10
EC103A1 MCR22–3 3–145 L4004L5 2N6073A 3–10
EC103A2 MCR22–3 3–145 L4004L7 2N6073A 3–10
EC103A3 MCR22–3 3–145 L4004L9 2N6073A 3–10
EC103B MCR100–4 3–154 L4006L6 MAC228A6 3–106
EC103B MCR22–4 3–145 L4006L7 MAC228A6 3–106
EC103B1 MCR22–4 3–145 L4006L9 MAC228A6 3–106
EC103B3 MCR22–4 3–145 L4008L6 MAC228A6 3–106
EC103C MCR100–6 3–154 L4008L7 MAC228A6 3–106
EC103C1 MCR22–6 3–145 L4008L9 MAC228A6 3–106
EC103C2 MCR22–6 3–145 L400E3 MAC97A6 3–71
EC103C3 MCR22–6 3–145 L400E5 MAC97A6 3–71
EC103D MCR100–6 3–154 L400E7 MAC97–6 3–71
EC103D1 MCR22–6 3–145 L400E9 MAC97–6 3–71
EC103D2 MCR22–6 3–145 MAC08BTI MAC08BTI 3–40
EC103D3 MCR22–6 3–145 MAC08DTI MAC08DTI 3–40
EC103E MCR22–8 3–145 MAC08MTI MAC08MTI 3–40
EC103E1 MCR22–8 3–145 MAC10–4 MAC210A4 3–75
EC103E2 MCR22–8 3–145 MAC10–6 MAC210A6 3–75
EC103E3 MCR22–8 3–145 MAC10–8 MAC210A8 3–75
EC103M MCR22–8 3–145 MAC11–4 MAC210A4 3–75
EC103M1 MCR22–8 3–145 MAC11–6 MAC210A6 3–75
EC103M2 MCR22–8 3–145 MAC11–8 MAC210A8 3–75
EC103M3 MCR22–8 3–145 MAC137G500 MAC8D 3–45
EC103Y MCR102 3–156 MAC137G600 MAC8M 3–45
EC103Y1 MCR22–2 3–145 MAC137G700 MAC8N 3–45
EC103Y2 MCR22–2 3–145 MAC137G800 MAC8N 3–45
EC103Y3 MCR22–2 3–145 MAC137–500 MAC9D 3–49
F0810BH MCR218–4 3–161 MAC137–600 MAC9M 3–49
F0810DH MCR218–6 3–161 MAC137–700 MAC9M 3–49
F0810MH MCR218–8 3–161 MAC137–800 MAC9N 3–49
F0810NH MCR218–10 3–161 MAC15–10 MAC16N 3–67
F1612BH MCR12D 3–141 MAC15–6 MAC16D 3–67
F1612DH MCR12M 3–141 MAC15–8 MAC16M 3–67
F1612NH MCR12N 3–141 MAC154 MAC15–4 3–59
L2001F71 2N6071A 3–10 MAC156 MAC15–6 3–59
L2001F91 2N6071 3–10 MAC15A10 MAC16N 3–67
L2001L3 2N6071A 3–10 MAC15A10 MAC15A10 3–59

Motorola Thyristor Device Data Index and Cross Reference

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 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

MAC15A10FP MAC15A10FP 3–63 MAC212–10FP MAC212–10FP 3–87

MAC15A4 MAC16D 3–67 MAC212–4 MAC212–4 3–83
MAC15A4FP MAC15A4FP 3–63 MAC212–4FP MAC212–4FP 3–87
MAC15A5 MAC15A6 3–59 MAC212–6 MAC212–6 3–83
MAC15A6 MAC16D 3–67 MAC212–6FP MAC212–6FP 3–87
MAC15A6 MAC15A6 3–59 MAC212–8 MAC212–8 3–83
MAC15A6FP MAC15A6FP 3–63 MAC212–8FP MAC212–8FP 3–87
MAC15A7 MAC15A8 3–59 MAC213–10 MAC12N 3–53
MAC15A8 MAC16M 3–67 MAC213–4 MAC12D 3–53
MAC15A8 MAC15A8 3–59 MAC213–6 MAC12D 3–53
MAC15A8FP MAC15A8FP 3–63 MAC213–8 MAC12M 3–53
MAC15A9 MAC15A10 3–59 MAC218A10 MAC218A10 3–91
MAC15–10 MAC15–10 3–59 MAC218A10FP MAC218A10FP 3–94
MAC15–10FP MAC15–10FP 3–63 MAC218A4 MAC218A4 3–91
MAC15–4 MAC16D 3–67 MAC218A4FP MAC218A4FP 3–94
MAC15–4 MAC15–4 3–59 MAC218A6 MAC218A6 3–91
MAC15–4FP MAC15–4FP 3–63 MAC218A6FP MAC218A6FP 3–94
MAC15–5 MAC15–6 3–59 MAC218A8 MAC218A8 3–91
MAC15–6 MAC15–6 3–59 MAC218A8FP MAC218A8FP 3–94
MAC15–6FP MAC15–6FP 3–63 MAC218–10 MAC218–10 3–91
MAC15–8 MAC15–8 3–59 MAC218–10FP MAC218–10FP 3–94
MAC15–8FP MAC15–8FP 3–63 MAC218–4 MAC218–4 3–91
MAC15–9 MAC15–10 3–59 MAC218–4FP MAC218–4FP 3–94
MAC16–10 MAC16N 3–67 MAC218–6 MAC218–6 3–91
MAC16–4 MAC16D 3–67 MAC218–6FP MAC218–6FP 3–94
MAC16–6 MAC16D 3–67 MAC218–8 MAC218–8 3–91
MAC16–8 MAC16M 3–67 MAC218–8FP MAC218–8FP 3–94
MAC20A10 MAC15–10FP 3–63 MAC219–10 MAC9N 3–49
MAC20A4 MAC15–4FP 3–63 MAC219–4 MAC9D 3–49
MAC20A5 MAC15–6FP 3–63 MAC219–6 MAC9D 3–49
MAC20A6 MAC15–6FP 3–63 MAC219–8 MAC9M 3–49
MAC20A7 MAC15–8FP 3–63 MAC223A1 MAC223A4 3–97
MAC20A9 MAC15–8FP 3–63 MAC223A10 MAC223A10 3–97
MAC20–10 MAC15–10FP 3–63 MAC223A10FP MAC223A10FP 3–100
MAC20–4 MAC15–4FP 3–63 MAC223A2 MAC223A4 3–97
MAC20–5 MAC15–6FP 3–63 MAC223A3 MAC223A4 3–97
MAC20–6 MAC15–6FP 3–63 MAC223A4 MAC223A4 3–97
MAC20–7 MAC15–8FP 3–63 MAC223A4FP MAC223A4FP 3–100
MAC20–8 MAC15–8FP 3–63 MAC223A5 MAC223A6 3–97
MAC210A10 MAC210A10 3–75 MAC223A6 MAC223A6 3–97
MAC210A10FP MAC210A10FP 3–79 MAC223A6FP MAC223A6FP 3–100
MAC210A4 MAC210A4 3–75 MAC223A7 MAC223A8 3–97
MAC210A4FP MAC210A4FP 3–79 MAC223A8 MAC223A8 3–97
MAC210A5 MAC210A6 3–75 MAC223A8FP MAC223A8FP 3–100
MAC210A6 MAC210A6 3–75 MAC223A9 MAC223A10 3–97
MAC210A6FP MAC210A6FP 3–79 MAC223–1 MAC223–4 3–97
MAC210A7 MAC210A8 3–75 MAC223–10 MAC223–10 3–97
MAC210A8 MAC210A8 3–75 MAC223–10FP MAC223–10FP 3–100
MAC210A8FP MAC210A8FP 3–79 MAC223–2 MAC223–4 3–97
MAC210A9 MAC210A10 3–75 MAC223–3 MAC223–4 3–97
MAC210–10 MAC210–10 3–75 MAC223–4 MAC223–4 3–97
MAC210–10FP MAC210–1OFP 3–79 MAC223–4FP MAC223–4FP 3–100
MAC210–4 MAC210–4 3–75 MAC223–5 MAC223–6 3–97
MAC210–4FP MAC210–4FP 3–79 MAC223–6 MAC223–6 3–97
MAC210–5 MAC210–6 3–75 MAC223–6FP MAC223–6FP 3–100
MAC210–6 MAC210–6 3–75 MAC223–7 MAC223–8 3–97
MAC210–6FP MAC210–6FP 3–79 MAC223–8 MAC223–8 3–97
MAC210–7 MAC210–8 3–75 MAC223–8FP MAC223–8FP 3–100
MAC210–8 MAC210–8 3–75 MAC223–9 MAC223–10 3–97
MAC210–8FP MAC210–8FP 3–79 MAC224A10 MAC224A10 3–103
MAC210–9 MAC210–10 3–75 MAC224A4 MAC224A4 3–103
MAC212A10 MAC212A10 3–83 MAC224A5 MAC224A6 3–103
MAC212A10FP MAC212A10FP 3–87 MAC224A6 MAC224A6 3–103
MAC212A4 MAC212A4 3–83 MAC224A7 MAC224A8 3–103
MAC212A4FP MAC212A4FP 3–87 MAC224A8 MAC224A8 3–103
MAC212A6 MAC212A6 3–83 MAC224A9 MAC224A10 3–103
MAC212A6FP MAC212A6FP 3–87 MAC224–10 MAC224–10 3–103
MAC212A8 MAC212A8 3–83 MAC224–4 MAC224–4 3–103
MAC212A8FP MAC212A8FP 3–87 MAC224–5 MAC224–6 3–103
MAC212–10 MAC212–10 3–83 MAC224–6 MAC224–6 3–103

Index and Cross Reference Motorola Thyristor Device Data

6–6
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

MAC224–7 MAC224–8 3–103 MAC320A8FP MAC320A8FP 3–120

MAC224–8 MAC224–8 3–103 MAC320–10 MAC320–10 3–116
MAC224–9 MAC224–10 3–103 MAC320–10FP MAC320–10FP 3–120
MAC228A10 MAC228A10 3–106 MAC320–4 MAC320–4 3–116
MAC228A10FP MAC228A10FP 3–108 MAC320–4FP MAC320–4FP 3–120
MAC228A2 MAC228A4 3–106 MAC320–6 MAC320–6 3–116
MAC228A3 MAC228A4 3–106 MAC320–6FP MAC320–6FP 3–120
MAC228A4 MAC228A4 3–106 MAC320–8 MAC320–8 3–116
MAC228A4FP MAC228A4FP 3–108 MAC320–8FP MAC320–8FP 3–120
MAC228A5 MAC228A6 3–106 MAC321–10 MAC321–10 3–124
MAC228A6 MAC228A6 3–106 MAC321–4 MAC321–4 3–124
MAC228A6FP MAC228A6FP 3–108 MAC321–6 MAC321–6 3–124
MAC228A7 MAC228A8 3–106 MAC321–8 MAC321–8 3–124
MAC228A8 MAC228A8 3–106 MAC515A10 MAC15–10FP 3–63
MAC228A8FP MAC228A8FP 3–108 MAC515A4 MAC15–4FP 3–63
MAC228A9 MAC228A10 3–106 MAC515A5 MAC15–6FP 3–63
MAC228–10 MAC228–10 3–106 MAC515A6 MAC15–6FP 3–63
MAC228–10FP MAC228–10FP 3–108 MAC515A7 MAC15–8FP 3–63
MAC228–2 MAC228–4 3–106 MAC515A8 MAC15–8FP 3–63
MAC228–3 MAC228–4 3–106 MAC515A9 MAC15–10FP 3–63
MAC228–4 MAC228–4 3–106 MAC515–10 MAC15–10FP 3–63
MAC228–4FP MAC228–4FP 3–108 MAC515–4 MAC15–4FP 3–63
MAC228–5 MAC228–6 3–106 MAC515–5 MAC15–6FP 3–63
MAC228–6 MAC228–6 3–106 MAC515–6 MAC15–6FP 3–63
MAC228–6FP MAC228–6FP 3–108 MAC515–7 MAC15–8FP 3–63
MAC228–7 MAC228–8 3–106 MAC515–8 MAC15–8FP 3–63
MAC228–8 MAC228–8 3–106 MAC515–9 MAC15–10FP 3–63
MAC228–8FP MAC228–8FP 3–108 MAC525A10 MAC223–10FP 3–100
MAC228–9 MAC228–10 3–106 MAC525A9 MAC223–10FP 3–100
MAC229A10 MAC229A10 3–110 MAC525–10 MAC223–10FP 3–100
MAC229A10FP MAC229A10FP 3–112 MAC525–4 MAC223–4 3–97
MAC229A4 MAC229A4 3–110 MAC525–5 MAC223–6 3–97
MAC229A4FP MAC229A4FP 3–112 MAC525–6 MAC223–6 3–97
MAC229A6 MAC229A6 3–110 MAC525–7 MAC223–8 3–97
MAC229A6FP MAC229A6FP 3–112 MAC525–8 MAC223–8 3–97
MAC229A8FP MAC229A8FP 3–112 MAC525–9 MAC223–10 3–97
MAC229–10 MAC229–10 3–110 MAC77–2 2N6071 3–10
MAC229–10FP MAC229–10FP 3–112 MAC77–3 2N6071 3–10
MAC229–4 MAC229–4 3–110 MAC77–4 2N6071 3–10
MAC229–4FP MAC229–4FP 3–112 MAC77–6 2N6073 3–10
MAC229–6 MAC229–6 3–110 MAC77–8 2N6075 3–10
MAC229–6FP MAC229–6FP 3–112 MAC91A1 MAC97A4 3–71
MAC229–8 MAC229–8 3–110 MAC91A2 MAC97A4 3–71
MAC229–8FP MAC229–8FP 3–112 MAC91A3 MAC97A4 3–71
MAC25A10 MAC223–10FP 3–100 MAC91A4 MAC97A4 3–71
MAC25A4 MAC223–4 3–97 MAC91A5 MAC97A6 3–71
MAC25A9 MAC223–10FP 3–100 MAC91A6 MAC97A6 3–71
MAC25–10 MAC223–10FP 3–100 MAC91A7 MAC97A8 3–71
MAC25–9 MAC223–10FP 3–100 MAC91A8 MAC97A8 3–71
MAC310A4 MAC310A4 3–114 MAC91–1 MAC97–4 3–71
MAC310A6 MAC310A6 3–114 MAC91–2 MAC97–4 3–71
MAC310A8 MAC310A8 3–114 MAC91–3 MAC97–4 3–71
MAC310–4 MAC310–4 3–114 MAC91–4 MAC97–4 3–71
MAC310–6 MAC310–6 3–114 MAC91–5 MAC97–6 3–71
MAC310–8 MAC310–8 3–114 MAC91–6 MAC97–6 3–71
MAC320–10 MAC16N 3–67 MAC91–7 MAC97–8 3–71
MAC320–4 MAC16D 3–67 MAC91–8 MAC97–8 3–71
MAC320–6 MAC16D 3–67 MAC92A1 MAC97A4 3–71
MAC320–8 MAC16M 3–67 MAC92A2 MAC97A4 3–71
MAC320A10 MAC16N 3–67 MAC92A3 MAC97A4 3–71
MAC320A10 MAC320A10 3–116 MAC92A4 MAC97A4 3–71
MAC320A10FP MAC320A10FP 3–120 MAC92A5 MAC97A6 3–71
MAC320A4 MAC16D 3–67 MAC92A6 MAC97A6 3–71
MAC320A4 MAC320A4 3–116 MAC92A7 MAC97A8 3–71
MAC320A4FP MAC320A4FP 3–120 MAC92A8 MAC97A8 3–71
MAC320A6 MAC16D 3–67 MAC92–1 MAC97–4 3–71
MAC320A6 MAC320A6 3–116 MAC92–2 MAC97–4 3–71
MAC320A6FP MAC320A6FP 3–120 MAC92–3 MAC97–4 3–71
MAC320A8 MAC16M 3–67 MAC92–4 MAC97–4 3–71
MAC320A8 MAC320A8 3–116 MAC92–5 MAC97–6 3–71

Motorola Thyristor Device Data Index and Cross Reference

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 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

MAC92–6 MAC97–6 3–71 MAC97A4 MAC97A4 3–71

MAC92–7 MAC97–8 3–71 MAC97A5 MAC97A6 3–71
MAC92–8 MAC97–8 3–71 MAC97A6 MAC97A6 3–71
MAC93A1 MAC97A4 3–71 MAC97A7 MAC97A8 3–71
MAC93A2 MAC97A4 3–71 MAC97A8 MAC97A8 3–71
MAC93A3 MAC97A4 3–71 MAC97B1 MAC97B4 3–71
MAC93A4 MAC97A4 3–71 MAC97B2 MAC97B4 3–71
MAC93A5 MAC97A6 3–71 MAC97B3 MAC97B4 3–71
MAC93A6 MAC97A6 3–71 MAC97B4 MAC97B4 3–71
MAC93A7 MAC97A8 3–71 MAC97B5 MAC97B6 3–71
MAC93A8 MAC97A8 3–71 MAC97B6 MAC97B6 3–71
MAC93–1 MAC97–4 3–71 MAC97B7 MAC97B8 3–71
MAC93–2 MAC97–4 3–71 MAC97B8 MAC97B8 3–71
MAC93–3 MAC97–4 3–71 MAC97–1 MAC97–4 3–71
MAC93–4 MAC97–4 3–71 MAC97–2 MAC97–4 3–71
MAC93–5 MAC97–6 3–71 MAC97–3 MAC97–4 3–71
MAC93–6 MAC97–6 3–71 MAC97–4 MAC97–4 3–71
MAC93–7 MAC97–8 3–71 MAC97–5 MAC97–6 3–71
MAC93–8 MAC97–8 3–71 MAC97–6 MAC97–6 3–71
MAC94A1 MAC97–4 3–71 MAC97–7 MAC97–6 3–71
MAC94A2 MAC97–4 3–71 MAC97–8 MAC97–8 3–71
MAC94A3 MAC97–4 3–71 MACH15D MAC15D 3–55
MAC94A4 MAC97–4 3–71 MACH15M MAC15M 3–55
MAC94A5 MAC97–6 3–71 MACH15N MAC15N 3–55
MAC94A6 MAC97–6 3–71 MBS4991 MBS4991 3–128
MAC94A7 MAC97–8 3–71 MBS4992 MBS4992 3–128
MAC94A8 MAC97–6 3–71 MBS4993 MBS4993 3–128
MAC94–1 MAC97–4 3–71 MCR08BT1 MCR08BT1 3–132
MAC94–2 MAC97–4 3–71 MCR08DT1 MCR08DT1 3–132
MAC94–3 MAC97–4 3–71 MCR08MT1 MCR08MT1 3–132
MAC94–4 MAC97–4 3–71 MCR100–3 MCR100–3 3–154
MAC94–5 MAC97–6 3–71 MCR100–4 MCR100–4 3–154
MAC94–6 MAC97–6 3–71 MCR100–5 MCR100–6 3–154
MAC94–7 MAC97–8 3–71 MCR100–6 MCR100–6 3–154
MAC94–8 MAC97–8 3–71 MCR100–7 MCR100–8 3–154
MAC95A1 MAC97A4 3–71 MCR100–8 MCR100–8 3–154
MAC95A2 MAC97A4 3–71 MCR101 MCR102 3–156
MAC95A3 MAC97A4 3–71 MCR102 MCR102 3–156
MAC95A4 MAC97A4 3–71 MCR103 MCR103 3–156
MAC95A5 MAC97A6 3–71 MCR104 MCR100–3 3–154
MAC95A6 MAC97A6 3–71 MCR106–1 MCR106–2 3–158
MAC95A7 MAC97A8 3–71 MCR106–2 MCR106–2 3–158
MAC95A8 MAC97A8 3–71 MCR106–3 MCR106–3 3–158
MAC95–1 MAC97A4 3–71 MCR106–4 MCR106–4 3–158
MAC95–2 MAC97A4 3–71 MCR106–5 MCR106–6 3–158
MAC95–3 MAC97A4 3–71 MCR106–6 MCR106–6 3–158
MAC95–4 MAC97A4 3–71 MCR106–7 MCR106–8 3–158
MAC95–5 MAC97A6 3–71 MCR106–8 MCR106–8 3–158
MAC95–6 MAC97A6 3–71 MCR107–2 MCR106–2 3–158
MAC95–7 MAC97A8 3–71 MCR107–2 MCR106–2 3–158
MAC95–8 MAC97A8 3–71 MCR107–3 MCR106–3 3–158
MAC96A1 MAC97A4 3–71 MCR107–4 MCR106–4 3–158
MAC96A2 MAC97A4 3–71 MCR107–5 MCR106–6 3–158
MAC96A3 MAC97A4 3–71 MCR107–6 MCR106–6 3–158
MAC96A4 MAC97A4 3–71 MCR107–7 MCR106–8 3–158
MAC96A5 MAC97A6 3–71 MCR107–8 MCR106–8 3–158
MAC96A6 MAC97A6 3–71 MCR115 MCR100–4 3–154
MAC96A7 MAC97A8 3–71 MCR120 MCR100–4 3–154
MAC96A8 MAC97A8 3–71 MCR218–10 MCR8N 3–137
MAC96–1 MAC97A4 3–71 MCR218–4 MCR8D 3–137
MAC96–2 MAC97A4 3–71 MCR218–6 MCR8D 3–137
MAC96–3 MAC97A4 3–71 MCR218–8 MCR8M 3–137
MAC96–4 MAC97A4 3–71 MCR218–10 MCR218–10 3–161
MAC96–5 MAC97A6 3–71 MCR218–2 MCR218–2 3–161
MAC96–6 MAC97A6 3–71 MCR218–3 MCR218–3 3–161
MAC96–7 MAC97A8 3–71 MCR218–4 MCR218–4 3–161
MAC96–8 MAC97A8 3–71 MCR218–5 MCR218–6 3–161
MAC97A1 MAC97A4 3–71 MCR218–6 MCR218–6 3–161
MAC97A2 MAC97A4 3–71 MCR218–7 MCR218–8 3–161
MAC97A3 MAC97A4 3–71 MCR218–8 MCR218–8 3–161

Index and Cross Reference Motorola Thyristor Device Data

6–8
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

MCR218–9 MCR218–10 3–161 MCR569–6 MCR12M 3–141

MCR220–5 MCR12D 3–141 MCR68–2 MCR12D 3–141
MCR220–7 MCR12M 3–141 MCR68–3 MCR12D 3–141
MCR220–9 MCR12N 3–141 MCR68–4 MCR12D 3–141
MCR221–5 MCR16D 3–143 MCR69–2 MCR16D 3–143
MCR221–9 MCR16D 3–143 MCR69–3 MCR16D 3–143
MCR225–10FP MCR225–10FP 3–168 MCR69–6 MCR16M 3–143
MCR225–2FP MCR225–2FP 3–168 MCR703A MCR703A 3–182
MCR225–4FP MCR225–4FP 3–168 MCR703A1 MCR703A1 3–182
MCR225–5 2N6507 3–26 MCR704A1 MCR704A1 3–182
MCR225–6FP MCR225–6FP 3–168 MCR706A MCR706A 3–182
MCR225–7 2N6508 3–26 MCR706A1 MCR706A1 3–182
MCR225–8FP MCR225–8FP 3–168 MCR708A MCR708A 3–182
MCR225–9 2N6509 3–26 MCR708A1 MCR708A1 3–182
MCR22–2 MCR22–2 3–145 MCR72–10 MCR8SN 3–139
MCR22–3 MCR22–3 3–145 MCR72–4 MCR8SD 3–139
MCR22–4 MCR22–4 3–145 MCR72–6 MCR8SD 3–139
MCR22–5 MCR22–6 3–145 MCR72–8 MCR8SM 3–139
MCR22–6 MCR22–6 3–145 MCR72–1 MCR72–2 3–151
MCR22–7 MCR22–8 3–145 MCR72–2 MCR72–2 3–151
MCR264–10 MCR264–10 3–172 MCR72–3 MCR72–3 3–151
MCR264–4 MCR264–4 3–172 MCR72–4 MCR72–4 3–151
MCR264–6 MCR264–6 3–172 MCR72–5 MCR72–6 3–151
MCR264–8 MCR264–8 3–172 MCR72–6 MCR72–6 3–151
MCR265–10 MCR265–10 3–175 MCR72–8 MCR72–8 3–151
MCR265–2 MCR265–2 3–175 MK1V115 MKP3V110 3–187
MCR265–4 MCR265–4 3–175 MK1V125 MKP3V120 3–187
MCR265–6 MCR265–6 3–175 MK1V135 MKP3V130 3–187
MCR265–8 MCR265–8 3–175 MKP1V120 MKP1V120 3–184
MCR3000–10C MCR218–10 3–161 MKP1V130 MKP1V130 3–184
MCR3000–2 MCR218–2 3–161 MKP3V120 MKP3V120 3–187
MCR3000–3C MCR218–3 3–161 MKP3V130 MKP3V130 3–187
MCR3000–5C MCR218–6 3–161 MKP9V120 MKP1V120 3–184
MCR3000–6 MCR218–6 3–161 MKP9V130 MKP1V130 3–184
MCR3000–7C MCR218–8 3–161 PO100BA MCR100–4 3–154
MCR3000–8 MCR218–8 3–161 PO100DA MCR100–6 3–154
MCR3000–9C MCR218–10 3–161 PO100MA MCR100–8 3–154
MCR300–4 MCR218–4 3–161 PO102AA MCR100–4 3–154
MCR306–1 2N6237 3–15 PO102BA MCR100–4 3–154
MCR306–2 2N6237 3–15 PO102CA MCR100–4 3–154
MCR306–3 2N6238 3–15 PO102DA MCR100–6 3–154
MCR306–4 2N6239 3–15 PO103BA MCR100–4 3–154
MCR306–5 2N6240 3–15 PO103DA MCR100–6 3–154
MCR306–6 2N6240 3–15 PO103MA MCR100–8 3–154
MCR310–10 MCR310–10 3–178 Q2001L3 T2322B 3–195
MCR310–2 MCR310–2 3–178 Q2001L4 T2322B 3–195
MCR310–3 MCR310–3 3–178 Q2001M3 T2322B 3–195
MCR310–4 MCR310–4 3–178 Q2001M4 2N6071 3–10
MCR310–6 MCR310–6 3–178 Q2003L3 2N6071A 3–10
MCR310–8 MCR310–8 3–178 Q2003L4 2N6071A 3–10
MCR506–1 MCR506–2 3–180 Q2003M3 2N6071A 3–10
MCR506–2 MCR506–2 3–180 Q2003M4 2N6071 3–10
MCR506–3 MCR506–3 3–180 Q2003P3 2N6071A 3–10
MCR506–4 MCR506–4 3–180 Q2003P4 2N6071 3–10
MCR506–6 MCR506–6 3–180 Q2004F31 2N6071A 3–10
MCR506–8 MCR506–8 3–180 Q2004F41 2N6071 3–10
MCR525–10 2N6509 3–26 Q2004L3 2N6071A 3–10
MCR525–4 2N6506 3–26 Q2004L4 2N6071A 3–10
MCR525–5 2N6507 3–26 Q2006F31 2N6071 3–10
MCR525–6 2N6507 3–26 Q2006F41 2N6071 3–10
MCR525–7 2N6508 3–26 Q2006L5 MAC9D 3–49
MCR525–8 2N6508 3–26 Q2006R4 T2500B 3–197
MCR525–9 2N6509 3–26 Q2008F41 T2800B 3–201
MCR568–1 MCR12D 3–141 Q2008L4 T2800B 3–201
MCR568–2 MCR12D 3–141 Q2008R4 T2800B 3–201
MCR568–3 MCR12D 3–141 Q200E3 MAC97–4 3–71
MCR568–6 MCR12M 3–141 Q200E4 MAC97–4 3–71
MCR569–1 MCR12D 3–141 Q2010F41 MAC12D 3–53
MCR569–2 MCR12D 3–141 Q2010L4 MAC210A4FP 3–79
MCR569–3 MCR12D 3–141 Q2010L45 MAC12D 3–53

Motorola Thyristor Device Data Index and Cross Reference

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 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

Q2010R4 MAC12D 3–53 Q6010L5 MAC210A8FP 3–79

Q2012L5 MAC212A4FP 3–87 Q6010R5 MAC12M 3–53
Q2012R5 2N6346A 3–22 Q6012L5 MAC212A8FP 3–87
Q2015L5 MAC15A4FP 3–63 Q6012R5 2N6348A 3–22
Q2015R5 MAC15A4 3–59 Q6015L5 MAC15A8FP 3–63
Q201E3 MAC97–4 3–71 Q6015R5 MAC15A8 3–59
Q201E4 MAC97–4 3–71 Q6015R5 MAC16M 3–67
Q2025L5 MAC223A4FP 3–100 Q6015R5 MAC16N 3–67
Q2025R5 MAC223A4 3–97 Q6025L5 MAC223A8FP 3–100
Q4001M3 2N6073A 3–10 Q6025R5 MAC223A8 3–97
Q4001M4 2N6073 3–10 Q8008R4 MAC9N 3–49
Q4003L3 2N6073A 3–10 Q8010L5 MAC12N 3–53
Q4003L4 2N6073A 3–10 Q8010R5 MAC12N 3–53
Q4003M3 2N6073A 3–10 Q8015L5 MAC15A10 3–59
Q4003M4 2N6073 3–10 Q8015R5 MAC15A10 3–59
Q4003P3 2N6073A 3–10 S0303LS3 MCR106–2 3–158
Q4003P4 2N6073 3–10 S0303MS2 2N6237 3–15
Q4004F31 2N6073A 3–10 S0303MS3 2N6237 3–15
Q4004F41 2N6073 3–10 S0306FS21 MCR72–2 3–151
Q4004L3 2N6073A 3–10 S0306FS31 MCR72–2 3–151
Q4004L4 2N6073A 3–10 S0306L S2800F 3–193
Q4006F41 2N6073 3–10 S1001L MCR106–3 3–158
Q4006L4 T2500D 3–197 S1001LS1 MCR106–3 3–158
Q4006L5 MAC9D 3–49 S1001LS3 MCR106–3 3–158
Q4006R4 T2500D 3–197 S1003L MCR106–3 3–158
Q4008F41 T2800D 3–201 S1003LS1 MCR106–3 3–158
Q4008L4 MAC218A6FP 3–94 S1003LS2 MCR106–3 3–158
Q4008L4A T2800D 3–201 S1003LS3 MCR106–3 3–158
Q4008R4 MAC9D 3–49 S1003MS2 2N6238 3–15
Q4008R4 T2800D 3–201 S1003MS3 2N6238 3–15
Q400E3 MAC97–6 3–71 S1006FS21 MCR72–3 3–151
Q400E4 MAC97–6 3–71 S1006FS31 MCR72–3 3–151
Q4010F41 MAC12D 3–53 S1006L S2800A 3–193
Q4010L4 MAC210A6FP 3–79 S1006LS2 MCR72–3 3–151
Q4010L5 MAC12D 3–53 S1006LS3 MCR72–3 3–151
Q4010R4 MAC12D 3–53 S1008F1 MCR218–3 3–161
Q4012L5 MAC212A6FP 3–87 S1008F3 MCR218–3 3–161
Q4012R5 2N6347A 3–22 S1008FS21 MCR72–3 3–151
Q4015L5 MAC15A6FP 3–63 S1008FS31 MCR72–3 3–151
Q4015R5 MAC15A6 3–59 S1008L MCR218–3 3–161
Q4015R5 MAC16D 3–67 S1008LS2 MCR72–3 3–151
Q4025L6 MAC223A6FP 3–100 S1008LS3 MCR72–3 3–151
Q4025P MAC223–6 3–97 S1008R S2800A 3–193
Q4025R5 MAC223A6 3–97 S1010F1 MCR12D 3–141
Q5004F41 2N6075 3–10 S1010L MCR12D 3–141
Q5006F41 T2500M 3–197 S1012L MCR12D 3–141
Q5006L4 T2500M 3–197 S1012R MCR12D 3–141
Q5006L5 MAC9M 3–49 S1015L MCR16D 3–143
Q5006R4 T2500M 3–197 S1016R MCR16D 3–143
Q5008F41 T2800D 3–201 S1020L 2N6505 3–26
Q5008L4 T2800M 3–201 S1025R 2N6505 3–26
Q5008L4A T2800M 3–201 S106E C106M 3–34
Q5008R4 T2800M 3–201 S106M C106M 3–34
Q5010F41 MAC12M 3–53 S107M C106M 3–34
Q5010L4 MAC12M 3–53 S1207BH MCR12D 3–141
Q5010L5 MAC12M 3–53 S1207DH MCR12D 3–141
Q5010R4 MAC12M 3–53 S1207MH MCR12M 3–141
Q5012L5 2N6348A 3–22 S1207NH MCR12N 3–141
Q5012R5 2N6348A 3–22 S1210BH MCR12M 3–141
Q5015L5 MAC15A8 3–59 S1210DH MCR12M 3–141
Q5015R5 MAC15A8 3–59 S1210MH MCR12M 3–141
Q5025L5 MAC223A8 3–97 S1210NH MCR12N 3–141
Q5025R5 MAC223A8 3–97 S1610BH MCR16D 3–143
Q6004F41 2N6075 3–10 S1610DH MCR16D 3–143
Q6006F51 2N6075 3–10 S1610NH MCR16D 3–143
Q6006L5 MAC9M 3–49 S2001L MCR106–4 3–158
Q6006R5 MAC9M 3–49 S2001LS1 MCR106–4 3–158
Q6008F51 MAC9M 3–49 S2001LS2 MCR106–4 3–158
Q6008L5 MAC218A8FP 3–94 S2001LS3 MCR106–4 3–158
Q6008R4 MAC9M 3–49 S2003L MCR106–4 3–158

Index and Cross Reference Motorola Thyristor Device Data

6–10
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

S2003LS1 MCR106–4 3–158 S2800N S2800N 3–193

S2003LS2 MCR106–4 3–158 S4001L MCR106–6 3–158
S2003LS3 MCR106–4 3–158 S4001LS1 MCR106–6 3–158
S2003MS2 2N6239 3–15 S4001LS2 MCR106–6 3–158
S2003MS3 2N6239 3–15 S4001LS2 MCR106–6 3–158
S2006FS21 MCR72–4 3–151 S4003L MCR106–6 3–158
S2006FS31 MCR72–4 3–151 S4003LS1 MCR106–6 3–158
S2006L S2800B 3–193 S4003LS2 MCR106–6 3–158
S2006LS2 MCR72–4 3–151 S4003LS3 MCR106–6 3–158
S2006LS3 MCR72–4 3–151 S4003MS2 2N6240 3–15
S2008F1 MCR218–4 3–161 S4003MS3 2N6240 3–15
S2008F3 MCR218–4 3–161 S4006FS21 MCR72–6 3–151
S2008FS21 MCR72–4 3–151 S4006FS31 MCR72–6 3–151
S2008FS31 MCR72–4 3–151 S4006L S2800D 3–193
S2008LS2 MCR72–4 3–151 S4006LS2 MCR72–6 3–151
S2008LS3 MCR72–4 3–151 S4006LS3 MCR72–6 3–151
S2008R S2800B 3–193 S4008F1 MCR218–6 3–161
S2010L MCR12D 3–141 S4008F3 MCR218–6 3–161
S2012L MCR12D 3–141 S4008FS21 MCR72–6 3–151
S2012R MCR12D 3–141 S4008FS31 MCR72–6 3–151
S2015L MCR16D 3–143 S4008L MCR218–6 3–161
S2016R MCR16D 3–143 S4008LS2 MCR72–6 3–151
S2020L 2N6506 3–26 S4008LS3 MCR72–6 3–151
S2025R 2N6506 3–26 S4008R MCR8D 3–137
S2060A 2N6238 3–15 S4008R S2800D 3–193
S2060B 2N6239 3–15 S4010L MCR12D 3–141
S2060C MCR106–6 3–158 S4012L MCR12D 3–141
S2060D 2N6240 3–15 S4012R MCR12D 3–141
S2060E MCR106–8 3–158 S4012R MCR12D 3–141
S2060F 2N6237 3–15 S4015L MCR16D 3–143
S2060M 2N6241 3–15 S4016R MCR12D 3–141
S2060Q 2N6237 3–15 S4016R MCR16D 3–143
S2060Y 2N6237 3–15 S4020L 2N6507 3–26
S2061A 2N6238 3–15 S4025R 2N6507 3–26
S2061B 2N6239 3–15 S5008L MCR218–8 3–161
S2061C MCR106–6 3–158 S6000C MCR12D 3–141
S2061D 2N6240 3–15 S6000E MCR12M 3–141
S2061E MCR106–8 3–158 S6000S MCR12N 3–141
S2061F 2N6237 3–15 S6001L MCR106–8 3–158
S2061M 2N6241 3–15 S6003L MCR106–8 3–158
S2061Q 2N6237 3–15 S6006L S2800M 3–193
S2061Y 2N6237 3–15 S6008F MCR218–8 3–161
S2062A 2N6238 3–15 S6008F1 S2800M 3–193
S2062B 2N6239 3–15 S6008F3 MCR218–8 3–161
S2062C MCR106–6 3–158 S6008L S2800M 3–193
S2062D 2N6240 3–15 S6008R MCR8M 3–137
S2062E MCR106–8 3–158 S6008R S2800M 3–193
S2062F 2N6237 3–15 S6010L MCR12M 3–141
S2062M 2N6241 3–15 S6012L MCR12M 3–141
S2062Q 2N6237 3–15 S6012R MCR12M 3–141
S2062Y 2N6237 3–15 S6012R MCR12M 3–141
S2610B S2800B 3–193 S6016R MCR12M 3–141
S2610D S2800D 3–193 S6020 2N6508 3–26
S2610M S2800M 3–193 S6025R 2N6508 3–26
S2620B S2800B 3–193 S6100C MCR16D 3–143
S2620D S2800D 3–193 S6100S MCR16D 3–143
S2620M S2800M 3–193 S8008R MCR8N 3–137
S2710B S2800B 3–193 S8012R MCR12N 3–141
S2710D S2800D 3–193 S8016R MCR12N 3–141
S2710M S2800M 3–193 S8016R MCR16D 3–143
S2800A S2800A 3–193 S8020L 2N6509 3–26
S2800B S2800B 3–193 S8025R 2N6509 3–26
S2800C S2800D 3–193 SC129B MAC223A4 3–97
S2800D MCR12D 3–141 SC129D MAC223A6 3–97
S2800D S2800D 3–193 SC129E MAC223A8 3–97
S2800E S2800M 3–193 SC129M MAC223A8 3–97
S2800F S2800F 3–193 SC136A 2N6071 3–10
S2800M MCR12M 3–141 SC136B 2N6071 3–10
S2800M S2800M 3–193 SC136C 2N6073 3–10
S2800N MCR12N 3–141 SC136D 2N6073 3–10

Motorola Thyristor Device Data Index and Cross Reference

6–11
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

SC136E 2N6075 3–10 SO306LS3 MCR72–2 3–151

SC136M 2N6075 3–10 SO308F1 MCR218–2 3–161
SC141A MAC9D 3–49 SO308F3 MCR218–2 3–161
SC141B MAC9D 3–49 SO308FS21 MCR72–2 3–151
SC141C MAC9D 3–49 SO308FS31 MCR72–2 3–151
SC141D MAC9D 3–49 SO308FS4 MCR72–2 3–151
SC141D MAC9D 3–49 SO308LS2 MCR72–2 3–151
SC141E MAC9M 3–49 SO308LS3 MCR72–2 3–151
SC141M MAC9M 3–49 SO310F1 MCR12D 3–141
SC141M MAC9M 3–49 SO312L MCR12D 3–141
SC141N MAC9N 3–49 SO312R MCR12D 3–141
SC141N MAC9N 3–49 SO315L MCR16D 3–143
SC143B MAC9D 3–49 SO316R MCR16D 3–143
SC143D MAC9D 3–49 SO320L 2N6504 3–26
SC143E MAC9M 3–49 SO325R 2N6504 3–26
SC143M MAC9M 3–49 SO501L MCR106–2 3–158
SC146A MAC12D 3–53 SO501LS1 MCR106–2 3–158
SC146B MAC12D 3–53 SO501LS2 MCR106–2 3–158
SC146C MAC12D 3–53 SO501LS3 MCR106–2 3–158
SC146D MAC12D 3–53 SO503L MCR106–2 3–158
SC146E MAC12M 3–53 SO503LS1 MCR106–2 3–158
SC146F MAC12D 3–53 SO503LS2 MCR106–2 3–158
SC146M MAC12M 3–53 SO503LS3 MCR106–2 3–158
SC146N MAC12M 3–53 SO503MS2 2N6238 3–15
SC146S MAC12N 3–53 SO503MS3 2N6238 3–15
SC149B MAC12N 3–53 SO505FS21 MCR72–2 3–151
SC149D MAC12D 3–53 SO505FS31 MCR72–2 3–151
SC149E MAC12M 3–53 SO506FS21 MCR72–2 3–151
SC149F MAC12D 3–53 SO506FS31 MCR72–2 3–151
SC149M ‘ MAC12M 3–53 SO506LS2 MCR72–2 3–151
SC151B MAC15A4 3–59 SO506LS3 MCR72–2 3–151
SC151D MAC15A6 3–59 SO508F1 MCR218–2 3–161
SC151E MAC15A8 3–59 SO508F3 MCR218–2 3–161
SC151M MAC15A8 3–59 SO508FS31 MCR72–2 3–151
SC160B MAC223–4 3–97 SO508LS2 MCR72–2 3–151
SC160D MAC223–6 3–97 SO508LS3 MCR72–2 3–151
SC160E MAC223–8 3–97 SO508S21 MCR72–2 3–151
SC160M MAC223–8 3–97 SO510L MCR12D 3–141
SC92A MAC97A4 3–71 SO512L MCR12D 3–141
SC92B MAC97A4 3–71 SO512R MCR12D 3–141
SC92D MAC97A6 3–71 SO515L MCR12D 3–141
SC92F MAC97A4 3–71 SO516R MCR16D 3–143
SISC141C MAC9D 3–49 SO520L 2N6504 3–26
SISC141D MAC9D 3–49 SO802BH MCR72–4 3–151
SISC141E MAC9M 3–49 SO802DH MCR72–6 3–151
SISC141M MAC9M 3–49 SO802NH MCR72–10 3–151
SISC141N MAC9N 3–49 T1012BH MAC210A4 3–75
SISC141S MAC9N 3–49 T1012DH MAC210A6 3–75
SISC146C MAC12D 3–53 T1012MH MAC210A8 3–75
SISC146D MAC12D 3–53 T1012NH MAC210A10 3–75
SISC146M MAC12M 3–53 T1013BH MAC210A4 3–75
SISC146N MAC12N 3–53 T1013DH MAC210A6 3–75
SISC146S MAC12M 3–53 T1013MH MAC210A8 3–75
SISC149C 2N6347A 3–22 T1013NH MAC210A10 3–75
SISC149D 2N6347A 3–22 T106E1 C106M 3–34
SISC149E 2N6348A 3–22 T106M1 C106M 3–34
SISC149M 2N6348A 3–22 T107E1 C106M 3–34
SM1ZG45 MAC15D 3–55 T107M1 C106M 3–34
SM1ZS45 MAC15M 3–55 T1213BH MAC212A4 3–83
SM8G45A MAC9D 3–49 T1213DH MAC212A6 3–83
SM8J45A MAC9M 3–49 T1213MH MAC212A8 3–83
SO301L MCR106–2 3–158 T1213NH MAC212A10 3–83
SO301L MCR12D 3–141 T1612BH MAC15A4 3–59
SO301LS1 MCR106–2 3–158 T1612DH MAC15A6 3–59
SO301LS2 MCR106–2 3–158 T1612MH MAC15A8 3–59
SO301LS3 MCR106–2 3–158 T1612NH MAC15A10 3–59
SO303L MCR106–2 3–158 T1613BH MAC15A4 3–59
SO303LS1 MCR106–2 3–158 T1613DH MAC15A6 3–59
SO303LS2 MCR106–2 3–158 T1613MH MAC15A8 3–59
SO306LS2 MCR72–2 3–151 T1613NH MAC15A10 3–59

Index and Cross Reference Motorola Thyristor Device Data

6–12
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

T2301D 2N6073B 3–10 T2513NH MAC223A10 3–97

T2301F 2N6071B 3–10 T2800A T2800B 3–201
T2301M 2N6075B 3–10 T2800B T2800B 3–201
T2302A 2N6071A 3–10 T2800C T2800D 3–201
T2302B 2N6071A 3–10 T2800D MAC8D 3–45
T2302C 2N6073A 3–10 T2800D T2800D 3–201
T2302D 2N6073A 3–10 T2800E T2800M 3–201
T2302F 2N6071A 3–10 T2800F T2800B 3–201
T2302PA 2N6071A 3–10 T2800M MAC8M 3–45
T2302PB 2N6071A 3–10 T2800M T2800M 3–201
T2302PC 2N6073A 3–10 T2800N 2N6349 3–18
T2302PD 2N6073A 3–10 T2800N MAC8N 3–45
T2302PF 2N6071A 3–10 T2801A T2801B MAC8D 3–45
T2303F 2N6071A 3–10 T2801B T2801B MAC8D 3–45
T2304B 2N6071A 3–10 T2801C T2801D MAC8D 3–45
T2304D 2N6073A 3–10 T2801D T2801D MAC8D 3–45
T2305B 2N6071A 3–10 T2801E T2801M MAC8M 3–45
T2305D 2N6073A 3–10 T2801M T2801M MAC8M 3–45
T2306A 2N6071A 3–10 T2801N T2801N MAC8N 3–45
T2306B 2N6071A 3–10 T2802A T2802B MAC9D 3–49
T2306D 2N6073A 3–10 T2802B T2802B MAC9D 3–49
T2311A 2N6071A 3–10 T2802C T2802D MAC9D 3–49
T2312A 2N6071A 3–10 T2802D T2802D MAC9D 3–49
T2312B 2N6071A 3–10 T2802E T2802M MAC9M 3–49
T2312D 2N6071A 3–10 T2802F T2802B MAC9D 3–49
T2312F 2N6071A 3–10 T2802M T2802M MAC9M 3–49
T2313A 2N6071A 3–10 T2802N 2N6345 3–18
T2313B 2N6071A 3–10 T2806B T2800B 3–201
T2313D 2N6071A 3–10 T2806C T2800D 3–201
T2313F 2N6071A 3–10 T2806D T2800D 3–201
T2322A T2322B 3–195 T2806N MAC218A10 3–91
T2322B T2322B 3–195 T2850A 2N6346A 3–22
T2322C T2322D 3–195 T2850B 2N6346A 3–22
T2322D T2322D 3–195 T2850D 2N6347A 3–22
T2322E T2322M 3–195 T2850E 2N6347A 3–22
T2322F T2322B 3–195 T2850M T2800M 3–201
T2322M T2322M 3–195 T2851B MAC9D 3–49
T2322N T2322M 3–195 T2851C MAC9D 3–49
T2323A T2323B 3–195 T2851D MAC9D 3–49
T2323B T2323B 3–195 T2851E MAC9M 3–49
T2323C T2323D 3–195 T2856B T2800B 3–201
T2323D T2323D 3–195 T2856C T2800D 3–201
T2323E T2323M 3–195 T2856D T2800D 3–201
T2323F T2323B 3–195 T2856M T2800M 3–201
T2323M T2323M 3–195 T4700B MAC15A4 3–59
T2323N T2323M 3–195 T4700C MAC15A6 3–59
T2500A T2500B 3–197 T4700D MAC15A6 3–59
T2500B T2500B 3–197 T4700E MAC15A8 3–59
T2500BFP T2500BFP 3–199 T4700F MAC15A4 3–59
T2500C T2500D 3–197 T4700M MAC15A8 3–59
T2500D MAC8D 3–45 T4700N MAC15A10 3–59
T2500D T2500D 3–197 T4706B MAC15A4 3–59
T2500DFP T2500DFP 3–199 T4706D MAC15A6 3–59
T2500E T2500M 3–197 T6000A MAC15A4 3–59
T2500M MAC8M 3–45 T6000B MAC15A4 3–59
T2500M T2500M 3–197 T6000C MAC15A6 3–59
T2500MFP T2500MFP 3–199 T6000D MAC15A6 3–59
T2500N MAC8N 3–45 T6000E MAC15A8 3–59
T2500N T2500N 3–197 T6000F MAC15A4 3–59
T2500NFP T2500NFP 3–199 T6000M MAC15A8 3–59
T2500S T2500N 3–197 T6000N MAC15A10 3–59
T2506B T2500B 3–197 T6001A MAC15A4 3–59
T2506D T2500D 3–197 T6001B MAC15A4 3–59
T2512BH MAC223A4 3–97 T6001C MAC15A6 3–59
T2512DH MAC223A6 3–97 T6001D MAC15A6 3–59
T2512MH MAC223A8 3–97 T6001E MAC15A8 3–59
T2512NH MAC223A10 3–97 T6001F MAC15A4 3–59
T2513BH MAC223A4 3–97 T6001M MAC15A8 3–59
T2513DH MAC223A6 3–97 T6001N MAC15A10 3–59
T2513MH MAC223A8 3–97 T6006A MAC15A4 3–59

Motorola Thyristor Device Data Index and Cross Reference

6–13
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

T6006B MAC15A4 3–59 TL8003 MCR218–10 3–161

T6006C MAC15A6 3–59 TL8006 MCR218–10 3–161
T6006D MAC15A6 3–59 TLC111A T2322B 3–195
T6006E MAC15A8 3–59 TLC111B T2322B 3–195
T6006F MAC15A4 3–59 TLC113A T2322B 3–195
T6006M MAC15A8 3–59 TLC113B T2322B 3–195
T6006N MAC15A10 3–59 TLC221A T2322B 3–195
TE205 MCR100–4 3–154 TLC221B T2322B 3–195
TE305 MCR100–6 3–154 TLC223A T2322B 3–195
TE405 MCR100–6 3–154 TLC223B T2322B 3–195
TE505 MCR100–8 3–154 TLC226A MCR706A1 3–182
TE605 MCR100–8 3–154 TLS106–05 MCR106–2 3–158
TIC126A MCR12D 3–141 TLS106–1 MCR106–3 3–158
TIC126B MCR12D 3–141 TLS106–2 MCR106–4 3–158
TIC126C MCR12D 3–141 TLS106–4 MCR106–6 3–158
TIC126D MCR12D 3–141 TLS106–6 MCR106–8 3–158
TIC126E MCR12M 3–141 TLS107–05 MCR106–2 3–158
TIC126F MCR12D 3–141 TLS107–1 MCR106–3 3–158
TIC126M MCR12M 3–141 TLS107–2 MCR106–4 3–158
TIC206A 2N6071A 3–10 TLS107–4 MCR106–6 3–158
TIC206B 2N6071A 3–10 TLS107–6 MCR106–8 3–158
TIC206D 2N6073A 3–10 TO1010BH MAC210A4 3–75
TIC215A 2N6071A 3–10 TO1010DH MAC210A6 3–75
TIC215B 2N6071A 3–10 TO1010MH MAC210A8 3–75
TIC215D 2N6073A 3–10 TO1010NH MAC210A10 3–75
TIC216A MAC228A4 3–106 TO409BJ T2500BFP 3–199
TIC216B MAC228A4 3–106 TO409DJ T2500DFP 3–199
TIC216D MAC228A6 3–106 TO409MJ T2500MFP 3–199
TIC226B MAC9N 3–49 TO409NJ T2500NFP 3–199
TIC226D MAC9D 3–49 TO410BJ T2500BFP 3–199
TIC246B MAC15A4 3–59 TO410DJ T2500DFP 3–199
TIC246D MAC15A6 3–59 TO410MJ T2500MFP 3–199
TIC253B MAC15–4FP 3–63 TO410NJ T2500NFP 3–199
TIC253D MAC15–6FP 3–63 TO505BH T2500B 3–197
TIC253E MAC15–8FP 3–63 TO505DH T2500D 3–197
TIC253M MAC15–8FP 3–63 TO505MH T2500M 3–197
TIC39A 2N6238 3–15 TO505NH T2500N 3–197
TIC39B 2N6239 3–15 TO509BH T2500B 3–197
TIC39C MCR100–6 3–154 TO509DH T2500D 3–197
TIC39D 2N6240 3–15 TO509MH T2500M 3–197
TIC39E MCR100–8 3–154 TO509NH T2500N 3–197
TIC39F 2N6237 3–15 TO510BH T2500B 3–197
TIC39Y 2N6237 3–15 TO510DH T2500D 3–197
TIC44 2N5060 3–2 TO510MH T2500M 3–197
TIC45 2N5061 3–2 TO510NH T2500N 3–197
TIC46 2N5062 3–2 TO512BH T2500B 3–197
TIC47 2N5064 3–2 TO512DH T2500D 3–197
TIC60 2N5060 3–2 TO512MH T2500M 3–197
TIC61 2N5061 3–2 TO512NH T2500N 3–197
TIC62 2N5062 3–2 TO610BH T2500B 3–197
TIC63 2N5064 3–2 TO610BJ T2500BFP 3–199
TIC64 2N5064 3–2 TO610DH T2500D 3–197
TL1003 MCR218–3 3–161 TO610DJ T2500DFP 3–199
TL1006 MCR218–3 3–161 TO610MH T2500M 3–197
TL106–05 MCR106–2 3–158 TO610MJ T2500MFP 3–199
TL106–1 MCR106–3 3–158 TO610NH T2500N 3–197
TL106–2 MCR106–4 3–158 TO610NJ T2500NFP 3–199
TL106–4 MCR106–6 3–158 TO612BH T2500B 3–197
TL106–6 MCR106–8 3–158 TO612BJ T2500BFP 3–199
TL107–05 MCR106–2 3–158 TO612DH T2500D 3–197
TL107–1 MCR106–3 3–158 TO612DJ T2500DFP 3–199
TL107–2 MCR106–4 3–158 TO612MH T2500M 3–197
TL107–4 MCR106–6 3–158 TO612MJ T2500MFP 3–199
TL107–6 MCR106–8 3–158 TO612NH T2500N 3–197
TL2003 MCR218–4 3–161 TO612NJ T2500NFP 3–199
TL2006 MCR218–4 3–161 TO805BH MAC228A4 3–106
TL4003 MCR218–6 3–161 TO805DH MAC228A6 3–106
TL4006 MCR218–6 3–161 TO805MH MAC228A8 3–106
TL6003 MCR218–8 3–161 TO805NH MAC228A10 3–106
TL6006 MCR218–8 3–161 TO809BH MAC228A4 3–106

Index and Cross Reference Motorola Thyristor Device Data

6–14
 Motorola Motorola Motorola Motorola
Industry Nearest Similar Page Industry Nearest Similar Page
Part Number Replacement Replacement Number Part Number Replacement Replacement Number

TO809DH MAC228A6 3–106 TYN216 MCR16D 3–143

TO809MH MAC228A8 3–106 TYN408 MCR8D 3–137
TO809NH MAC228A10 3–106 TYN412 MCR12D 3–141
TO810BH MAC229A4 3–110 TYN416 MCR12D 3–141
TO810BJ MAC229A4FP 3–112 TYN608 MCR218–8FP 3–164
TO810DH MAC229A6 3–110 TYN608 MCR8M 3–137
TO810DJ MAC229A6FP 3–112 TYN612 MCR12M 3–141
TO810MJ MAC229A8FP 3–112 TYN612 MCR12M 3–141
TO810NH MAC229A10 3–110 TYN616 MCR12M 3–141
TO810NJ MAC229A10FP 3–112 TYN682 2N6504 3–26
TXN058 MCR218–2FP 3–164 TYN683 2N6505 3–26
TXN108 MCR218–4FP 3–164 TYN685 2N6506 3–26
TXN208 MCR218–4FP 3–164 TYN688 2N6507 3–26
TXN408 MCR218–6FP 3–164 TYN690 2N6508 3–26
TXN608 MCR218–8FP 3–164 TYN692 2N6509 3–26
TXN808 MCR218–10FP 3–164 TYN808 MCR218–10FP 3–164
TY1004 MCR218–3 3–161 TYN808 MCR8N 3–137
TY1008 MCR218–3 3–161 TYN812 MCR12N 3–141
TY1010 MCR12D 3–141 TYN812 MCR12N 3–141
TY2004 MCR218–4 3–161 TYN816 MCR12N 3–141
TY2008 MCR218–4 3–161 TYNO516 MCR16D 3–143
TY2010 MCR12D 3–141 TYS406–6 MCR106–8 3–158
TY3004 MCR218–6 3–161 TYS407–6 MCR106–8 3–158
TY3008 MCR218–6 3–161 TYS606–1 MCR72–3 3–151
TY3010 MCR218–6 3–161 TYS606–2 MCR72–4 3–151
TY4004 MCR218–6 3–161 TYS606–4 MCR72–6 3–151
TY4008 MCR218–6 3–161 TYS606–5 MCR72–2 3–151
TY4010 MCR12D 3–141 TYS606–8 MCR72–10 3–151
TY5004 MCR218–8 3–161 TYS806–1 MCR72–3 3–151
TY5008 MCR218–8 3–161 TYS806–2 MCR72–4 3–151
TY5010 MCR12M 3–141 TYS806–4 MCR72–6 3–151
TY504 MCR218–2 3–161 TYS806–5 MCR72–2 3–151
TY508 MCR218–2 3–161 XO102BA 2N5064 3–2
TY510 MCR12D 3–141 XO102DA MCR100–6 3–154
TY6004 MCR218–8 3–161 XO102MA MCR100–8 3–154
TY6008 MCR218–8 3–161 XO202BA MCR22–4 3–145
TY6010 MCR12M 3–141 XO202DA MCR22–6 3–145
TY8008 MCR218–10 3–161 XO202MBA MCR22–8 3–145
TY8010 MCR12M 3–141 XO402ME C106M 3–34
TYAL–1110B MAC12D 3–53 ZO109BA MCR100–4 3–154
TYAL–1110M MAC12M 3–53 ZO109DA MCR100–6 3–154
TYAL–1115B MAC15A4 3–59 ZO109MA MCR100–8 3–154
TYAL–1115M MAC15A4 3–59 ZO402ME 2N6075B 3–10
TYAL–118M MAC9D 3–49 ZO402MF 2N6075B 3–10
TYN0512 MCR12D 3–141 ZO405ME 2N6075B 3–10
TYN112 MCR12D 3–141 ZO409ME C106M 3–34
TYN116 MCR16D 3–143 ZO410BE MCR106–4 3–158
TYN208 MCR218–4 3–161 ZO410DE MCR106–6 3–158
TYN212 MCR12D 3–141 ZO410ME MCR106–8 3–158

Motorola Thyristor Device Data Index and Cross Reference

6–15
Index and Cross Reference Motorola Thyristor Device Data
6–16
For:colleen
Printed on:Tue, Jun 30, 1998 10:17:58
From book:SALESOFF (MAR95) VIEW in DL137_BACK (6D) VIE
Document:SALES_US (MAR95) VIEW
Last saved on:Mon, Jun 29, 1998 22:03:57
Document:SALES_EURO (MAR95) VIEW
Last saved on:Mon, Jun 29, 1998 22:04:00
Document:DL137_BK_TABS VIEW
Last saved on:Mon, Jun 29, 1998 22:04:03
 3/1/95

MOTOROLA DISTRIBUTOR AND WORLDWIDE SALES OFFICES

AUTHORIZED NORTH AMERICAN DISTRIBUTORS
UNITED STATES Woodland Hills Itasca
ALABAMA Hamilton Hallmark . . . . . . . . . . . . (818)594-0404 Arrow/Schweber Electronics . . . (708)250-0500
Huntsville Richardson Electronics . . . . . . . (615)594-5600 LaFox
Arrow/Schweber Electronics . . . . (205)837-6955 COLORADO Richardson Electronics . . . . . . . (708)208-2401
Future Electronics . . . . . . . . . . . . (205)830-2322 Lakewood Schaumburg
Hamilton Hallmark . . . . . . . . . . . . (205)837-8700 Future Electronics . . . . . . . . . . . . (303)232-2008 Newark . . . . . . . . . . . . . . . . . . . . . (708)310-8980
Newark . . . . . . . . . . . . . . . . . . . . . (205)837-9091 Denver Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (303)757-3351 INDIANA
Wyle Laboratories . . . . . . . . . . . . (205)830–1119 Englewood Indianapolis
ARIZONA Arrow/Schweber Electronics . . . . (303)799-0258 Arrow/Schweber Electronics . . . . (317)299-2071
Phoenix Hamilton Hallmark . . . . . . . . . . . (303)790-1662 Hamilton Hallmark . . . . . . . . . . . (317)872-8875
Future Electronics . . . . . . . . . . . . (602)968-7140 Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (317)259-0085
Hamilton Hallmark . . . . . . . . . . . . . (602)437-1200 Thornton Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Wyle Laboratories . . . . . . . . . . . . (602)437-2088 Wyle Laboratories . . . . . . . . . . . . (303)457-9953 Ft. Wayne
Tempe CONNECTICUT Newark . . . . . . . . . . . . . . . . . . . . . (219)484-0766
Arrow/Schweber Electronics . . . . (602)431-0030 Bloomfield IOWA
Newark . . . . . . . . . . . . . . . . . . . . . (602)966-6340 Newark . . . . . . . . . . . . . . . . . . . . . (203)243-1731 Cedar Rapids
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Chesire Newark . . . . . . . . . . . . . . . . . . . . . (319)393-3800
Future Electronics . . . . . . . . . . . . (203)250-0083 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
CALIFORNIA
Hamilton Hallmark . . . . . . . . . . . (203)271-2844 KANSAS
Agoura Hills
Time Electronics Corporate . . . . 1-800-789-TIME Southbury Lenexa
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Arrow/Schweber Electronics . . . . (913)541-9542
Belmont
Richardson Electronics . . . . . . . (415)592-9225 Wallingfort Hamilton Hallmark . . . . . . . . . . . (913)888-4747
Arrow/Schweber Electronics . . . . (203)265-7741 Overland Park
Calabassas
Arrow/Schweber Electronics . . . . (818)880-9686 FLORIDA Future Electronics . . . . . . . . . . . . (913)649-1531
Wyle Laboratories . . . . . . . . . . . . (818)880-9000 Altamonte Springs Newark . . . . . . . . . . . . . . . . . . . . . (913)677-0727
Chatsworth Future Electronics . . . . . . . . . . . . (407)767-8414 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Future Electronics . . . . . . . . . . . . (818)865-0040 Clearwater MARYLAND
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Future Electronics . . . . . . . . . . . . (813)530-1222 Columbia
Costa Mesa Deerfield Beach Arrow/Schweber Electronics . . . . (301)596-7800
Hamilton Hallmark . . . . . . . . . . . . (714)641-4100 Arrow/Schweber Electronics . . . . (305)429-8200 Future Electronics . . . . . . . . . . . . (410)290-0600
Culver City Wyle Laboratories . . . . . . . . . . . . (305)420-0500 Hamilton Hallmark . . . . . . . . . . . (410)988-9800
Hamilton Hallmark . . . . . . . . . . . . (213)558-2000 Ft. Lauderdale Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Garden Grove Future Electronics . . . . . . . . . . . . (305)436-4043 Wyle Laboratories . . . . . . . . . . . . (410)312-4844
Newark . . . . . . . . . . . . . . . . . . . . . (714-893-4909 Hamilton Hallmark . . . . . . . . . . . . (305)484-5482 Hanover
Irvine Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (410)712-6922
Arrow/Schweber Electronics . . . (714)587-0404 Lake Mary MASSACHUSETTS
Future Electronics . . . . . . . . . . . . (714)250-4141 Arrow/Schweber Electronics . . . . (407)333-9300 Boston
Wyle Laboratories Corporate . . . . (714)753-9953 Largo/Tampa/St. Petersburg Arrow/Schweber Electronics . . . . (617)271-9953
Wyle Laboratories . . . . . . . . . . . . (714)863-9953 Hamilton Hallmark . . . . . . . . . . . . (813)541-7440 Bolton
Los Angeles Newark . . . . . . . . . . . . . . . . . . . . . (813)287-1578 Future Corporate . . . . . . . . . . . . . (508)779-3000
Wyle Laboratories . . . . . . . . . . . . (818)880-9000 Wyle Laboratories . . . . . . . . . . . . (813)576-3004 Burlington
Mountain View Orlando Wyle Laboratories . . . . . . . . . . . . (617)271-9953
Richardson Electronics . . . . . . . (415)960-6900 Newark . . . . . . . . . . . . . . . . . . . . . (407)896-8350 Norwell
Orange Time Electronics . . . . . . . . . . . . 1-800-789-TIME Richardson Electronics . . . . . . . (617)871-5162
Newark . . . . . . . . . . . . . . . . . . . . . (714)634-8224 Plantation Peabody
Palo Alto Newark . . . . . . . . . . . . . . . . . . . . . (305)424-4400 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Newark . . . . . . . . . . . . . . . . . . . . . (415)812-6300 Winter Park Hamiltion Hallmark . . . . . . . . . . . (508)532-3701
Rocklin Hamilton Hallmark . . . . . . . . . . . (407)657-3300 Woburn
Hamilton Hallmark . . . . . . . . . . . (916)624-9781 Richardson Electronics . . . . . . . (407)644-1453 Newark . . . . . . . . . . . . . . . . . . . . . (617)935-8350
Sacramento GEORGIA MICHIGAN
Newark . . . . . . . . . . . . . . . . . . . . . (916)721-1633 Atlanta Detroit
Wyle Laboratories . . . . . . . . . . . . (916)638-5282 Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (313)967-0600
San Diego Wyle Laboratories . . . . . . . . . . . . (404)441-9045 Grand Rapids
Arrow/Schweber Electronics . . . (619)565-4800 Future Electronics . . . . . . . . . . . . (616)698-6800
Duluth
Future Electronics . . . . . . . . . . . . (619)625-2800 Arrow/Schweber Electronics . . . . (404)497-1300 Livonia
Hamilton Hallmark . . . . . . . . . . . . (619)571-7540 Hamilton Hallmark . . . . . . . . . . . (404)623-5475 Arrow/Schweber Electronics . . . . (313)462-2290
Newark . . . . . . . . . . . . . . . . . . . . . . (619)453-8211 Future Electronics . . . . . . . . . . . . (313)261-5270
Norcross
Wyle Laboratories . . . . . . . . . . . . (619)565-9171 Future Electronics . . . . . . . . . . . . (404)441-7676 Hamilton Hallmark . . . . . . . . . . . (313)347-4020
San Jose Newark . . . . . . . . . . . . . . . . . . . . . (404)448-1300 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Arrow/Schweber Electronics . . . . (408)441-9700 Wyle Laboratories . . . . . . . . . . . . (404)441-9045 MINNESOTA
Arrow/Schweber Electronics . . . . (408)428-6400 Bloomington
ILLINOIS Wyle Laboratories . . . . . . . . . . . . . (612)853-2280
Future Electronics . . . . . . . . . . . . . (408)434-1122 Addison
Santa Clara Wyle Laboratories . . . . . . . . . . . . (708)620-0969 Eden Prairie
Wyle Laboratories . . . . . . . . . . . . (408)727-2500 Arrow/Schweber Electronics . . . . (612)941-5280
Bensenville Future Electronics . . . . . . . . . . . . (612)944-2200
Sunnyvale Hamilton Hallmark . . . . . . . . . . . . (708)860-7780
Hamilton Hallmark . . . . . . . . . . . . (408)435-3500 Hamilton Hallmark . . . . . . . . . . . (612)881-2600
Chicago
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark Electronics Corp. . . . . . (312)784-5100 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Torrance Hoffman Estates Minneapolis
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Future Electronics . . . . . . . . . . . . (708)882-1255 Newark . . . . . . . . . . . . . . . . . . . . . (612)331-6350
Tustin Earth City
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Hamilton Hallmark . . . . . . . . . . . (314)291-5350
West Hills
Newark . . . . . . . . . . . . . . . . . . . . . (818)888-3718

For changes to this information contact Technical Publications at FAX (602) 244-6561
 3/1/95

AUTHORIZED DISTRIBUTORS – continued

UNITED STATES – continued Mayfield Heights WASHINGTON

MISSOURI Future Electronics . . . . . . . . . . . . (216)449-6996 Bellevue
St. Louis Solon Almac Electronics Corp. . . . . . . (206)643-9992
Arrow/Schweber Electronics . . . . (314)567-6888 Arrow/Schweber Electronics . . . . (216)248-3990 Newark . . . . . . . . . . . . . . . . . . . . . (206)641-9800
Future Electronics . . . . . . . . . . . . (314)469-6805 Hamilton Hallmark . . . . . . . . . . . . (216)498-1100 Richardson Electronics . . . . . . . (206)646-7224
Newark . . . . . . . . . . . . . . . . . . . . . (314)298-2505 Worthington Bothell
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Hamilton Hallmark . . . . . . . . . . . (614)888-3313 Future Electronics . . . . . . . . . . . . (206)489-3400
NEW JERSEY OKLAHOMA Redmond
Cherry Hill Tulsa Hamilton Hallmark . . . . . . . . . . . . (206)881-6697
Hamilton Hallmark . . . . . . . . . . . . (609)424-0100 Hamilton Hallmark . . . . . . . . . . . . (918)254-6110 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Newark . . . . . . . . . . . . . . . . . . . . . (918)252-5070 Wyle Laboratories . . . . . . . . . . . . . (206)881-1150
East Brunswick
Newark . . . . . . . . . . . . . . . . . . . . . (908)937-6600 OREGON Seattle
Marlton Beaverton Wyle Laboratories. . . . . . . . . . . . . . (206)881-1150
Arrow/Schweber Electronics . . . . (609)596-8000 Arrow/Almac Electronics Corp. . . (503)629-8090 Spokane
Future Electronics . . . . . . . . . . . . (609)596-4080 Future Electronics . . . . . . . . . . . . (503)645-9454 Arrow/Almac Electronics Corp. . . (509)924-9500
Pinebrook Hamilton Hallmark . . . . . . . . . . . (503)528-6200 WISCONSIN
Arrow/Schweber Electronics . . . . (201)227-7880 Wyle Laboratories . . . . . . . . . . . . (503)643-7900 Brookfield
Wyle Laboratories . . . . . . . . . . . . (201)882-8358 Portland Arrow/Schweber Electronics . . . . (414)792-0150
Parsippany Newark . . . . . . . . . . . . . . . . . . . . . (503)297-1984 Future Electronics . . . . . . . . . . . . (414)879-0244
Future Electronics . . . . . . . . . . . . (201)299-0400 Time Electronics . . . . . . . . . . . . 1-800-789-TIME Milwaukee
Hamilton Hallmark . . . . . . . . . . . (201)515-1641 PENNSYLVANIA Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Wayne Ft. Washington New Berlin
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (215)654-1434 Hamilton Hallmark . . . . . . . . . . . (414)780-7200
NEW MEXICO Mt. Laurel Wauwatosa
Wyle Laboratories . . . . . . . . . . . . . (609)439-9110 Newark . . . . . . . . . . . . . . . . . . . . . (414)453-9100
Albuquerque
Alliance Electronics . . . . . . . . . . (505)292-3360 Montgomeryville Waukesha
Richardson Electronics . . . . . . . (215)628-0805 Wyle Laboratories . . . . . . . . . . . . (414)879-0434
Hamilton Hallmark . . . . . . . . . . . . (505)828-1058
Newark . . . . . . . . . . . . . . . . . . . . . (505)828-1878 Philadelphia
Time Electronics . . . . . . . . . . . . 1-800-789-TIME
NEW YORK Wyle Laboratories . . . . . . . . . . . . . (609)439-9110
CANADA
Commack ALBERTA
Newark . . . . . . . . . . . . . . . . . . . . . (516)499-1216 Pittsburgh Calgary
Arrow/Schweber Electronics . . . . (412)963-6807 Electro Sonic Inc. . . . . . . . . . . . (403)255-9550
Hauppauge
Arrow/Schweber Electronics . . . . (516)231-1000 Newark . . . . . . . . . . . . . . . . . . . . . (412)788-4790 Future Electronics . . . . . . . . . . . . (403)250-5550
Future Electronics . . . . . . . . . . . . (516)234-4000 Time Electronics . . . . . . . . . . . . 1-800-789-TIME Hamilton/Hallmark . . . . . . . . . . . . (800)663–5500
Hamilton Hallmark . . . . . . . . . . . (516)434-7400 TENNESSEE Edmonton
Konkoma Franklin Future Electronics . . . . . . . . . . . . (403)438-2858
Richardson Electronics . . . . . . . (615)791-4900
Hamilton Hallmark . . . . . . . . . . . (516)737-0600 Hamilton/Hallmark . . . . . . . . . . . (800)663-5500
Knoxville Saskatchewan
Melville Newark . . . . . . . . . . . . . . . . . . . . . (615)588-6493
Wyle Laboratories . . . . . . . . . . . . (516)293-8446 Hamilton/Hallmark . . . . . . . . . . . (800)663–5500
Pittsford TEXAS
Austin BRITISH COLUMBIA
Newark . . . . . . . . . . . . . . . . . . . . . (716)381-4244 Vancouver
Arrow/Schweber Electronics . . . . (512)835-4180
Rochester Future Electronics . . . . . . . . . . . . (512)502-0991
Arrow Electronics . . . . . . . . . . . . (604)421-2333
Arrow/Schweber Electronics . . . . (716)427-0300 Electro Sonic Inc. . . . . . . . . . . . . . (604)273-2911
Future Electronics . . . . . . . . . . . . . (716)272-1120 Hamilton Hallmark . . . . . . . . . . . (512)258-8818
Future Electronics . . . . . . . . . . . . . (604)294-1166
Hamilton Hallmark . . . . . . . . . . . . (716)475-9130 Newark . . . . . . . . . . . . . . . . . . . . . (512)338-0287
Hamilton/Hallmark . . . . . . . . . . . . (604)420-4101
Richardson Electronics . . . . . . . . (716)264-1100 Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Wyle Laboratories . . . . . . . . . . . . (512)345-8853 MANITOBA
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Winnipeg
Rockville Centre Carollton
Arrow/Schweber Electronics . . . . (214)380-6464 Electro Sonic Inc. . . . . . . . . . . . (204)783-3105
Richardson Electronics . . . . . . . (516)872-4400 Future Electronics . . . . . . . . . . . . (204)944-1446
Syracuse Dallas
Future Electronics . . . . . . . . . . . . (214)437-2437 Hamilton/Hallmark . . . . . . . . . . . . (800)663-5500
Future Electronics . . . . . . . . . . . . (315)451-2371
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Hamilton Hallmark . . . . . . . . . . . (214)553-4300 ONTARIO
Richardson Electronics . . . . . . . (214)239-3680 Ottawa
NORTH CAROLINA Arrow Electronics ............ (613)226-6903
Charlotte Time Electronics . . . . . . . . . . . . 1-800-789-TIME
Future Electronics . . . . . . . . . . . . (704)455-9030 Wyle Laboratories . . . . . . . . . . . . (214)235-9953 Electro Sonic Inc. ............ (613)728-8333
Richardson Electronics . . . . . . . (704)548-9042 Ft. Worth Future Electronics ............ (613)820-8313
Allied Electronics . . . . . . . . . . . . . (817)336-5401 Hamilton/Hallmark ............ (613)226-1700
Raleigh
Arrow/Schweber Electronics . . . . (919)876-3132 Houston Toronto
Future Electronics . . . . . . . . . . . . . (919)790-7111 Arrow/Schweber Electronics . . . . (713)530-4700 Arrow Electronics . . . . . . . . . . . . (905)670-7769
Hamilton Hallmark . . . . . . . . . . . (919)872-0712 Future Electronics . . . . . . . . . . . . . (713)785-1155 Electro Sonic Inc. . . . . . . . . . . . . (416)494-1666
Newark . . . . . . . . . . . . . . . . . . . . . (919)781-7677 Hamilton Hallmark . . . . . . . . . . . (713)781-6100 Future Electronics . . . . . . . . . . . . (905)612-9200
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (713)270-4800 Hamilton Hallmark . . . . . . . . . . . . (905)564-6060
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Newark . . . . . . . . . . . . . . . . . . . . . (519)685–4280
OHIO
Centerville Wyle Laboratories . . . . . . . . . . . . (713)879-9953 (905)670–2888
Arrow/Schweber Electronics . . . . (513)435-5563 Richardson (800)463–9275
Cleveland Newark . . . . . . . . . . . . . . . . . . . . . (214)235-1998 Richardson Electronics . . . . . . . (905)795–6300
Newark . . . . . . . . . . . . . . . . . . . . . (216)391-9330 UTAH FAI . . . . . . . . . . . . . . . . . . . . . . . . . (905)612–9888
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Salt Lake City QUEBEC
Columbus Arrow/Schweber Electronics . . . . (801)973-6913 Montreal
Newark . . . . . . . . . . . . . . . . . . . . . (614)326-0352 Future Electronics . . . . . . . . . . . . (801)467-4448 Arrow Electronics . . . . . . . . . . . . . (514)421-7411
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Hamilton Hallmark . . . . . . . . . . . . (801)266-2022 Future Electronics . . . . . . . . . . . . (514)694-7710
Dayton Newark . . . . . . . . . . . . . . . . . . . . . (801)261-5660 Hamilton Hallmark . . . . . . . . . . . . (514)335-1000
Future Electronics . . . . . . . . . . . . (513)426-0090 Wyle Laboratories . . . . . . . . . . . . (801)974–9953 Newark . . . . . . . . . . . . . . . . . . . . . (800)463-9275
Hamilton Hallmark . . . . . . . . . . . (513)439-6735 West Valley City Richardson Electronics . . . . . . . (514)748–1770
Newark . . . . . . . . . . . . . . . . . . . . . (513)294-8980 Time Electronics . . . . . . . . . . . . 1-800-789-TIME Quebec City
Time Electronics . . . . . . . . . . . . 1-800-789-TIME Wyle Laboratories . . . . . . . . . . . . (801)974-9953 Future Electronics . . . . . . . . . . . . (418)877-6666

For changes to this information contact Technical Publications at FAX (602) 244-6561
 3/1/95

SALES OFFICES
UNITED STATES Worthington . . . . . . . . . . . . . . (614)431-8492 JAPAN, Fukuoka . . . . . . . . . 81-92–725–7583
ALABAMA, Huntsville . . . . . . (205)464-6800 OHIO, Dayton . . . . . . . . . . . . . . (513)495-6800 JAPAN, Gotanda . . . . . . . . . . 81-3-5487-8311
ALASKA, . . . . . . . . . . . . . . . . . (800)635-8291 OKLAHOMA, Tulsa . . . . . . . . (800)544-9496 JAPAN, Nagoya . . . . . . . . . . 81-52-232-3500
ARIZONA, Tempe . . . . . . . . . . (602)302-8056 OREGON, Portland . . . . . . . . . (503)641-3681 JAPAN, Osaka . . . . . . . . . . . . . 81-6-305-1802
CALIFORNIA, Agoura Hills . . . (818)706-1929 PENNSYLVANIA, Colmar . . . . (215)997-1020 JAPAN, Sendai . . . . . . . . . . . 81-22-268-4333
CALIFORNIA, Los Angeles . . (310)417-8848 Philadelphia/Horsham . . . . . (215)957-4100 JAPAN, Takamatsu . . . . . . . . 81-878-37-9972
CALIFORNIA, Irvine . . . . . . . . (714)753-7360 TENNESSEE, Knoxville . . . . . (615)690-5593 JAPAN, Tokyo . . . . . . . . . . . . 81-3-3440-3311
CALIFORNIA, San Diego . . . . (619)541-2163 TEXAS, Austin . . . . . . . . . . . . . (512)502-2100 KOREA, Pusan . . . . . . . . . . . 82(51)4635-035
CALIFORNIA, Sunnyvale . . . . (408)749-0510 TEXAS, Houston . . . . . . . . . . . (800)343-2692 KOREA, Seoul . . . . . . . . . . . . . 82(2)554-5118
COLORADO, TEXAS, Plano . . . . . . . . . . . . . (214)516-5100 MALAYSIA, Penang . . . . . . . . . 60(4)374514
Colorado Springs . . . . . . . . . . (719)599-7497 TEXAS, Seguin . . . . . . . . . . . . (210)372-7620 MEXICO, Mexico City . . . . . . . 52(5)282-0230
COLORADO, Denver . . . . . . . (303)337-3434 VIRGINIA, Richmond . . . . . . . (804)285-2100 MEXICO, Guadalajara . . . . . . 52(36)21-8977
CONNECTICUT, UTAH, CSI @ . . . . . . . . . . . . . . (801)561-5099 Marketing . . . . . . . . . . . . . . . . 52(36)21-2023
Wallingford . . . . . . . . . . . . . . . (203)949-4100 WASHINGTON, Bellevue . . . . (206)454-4160 Customer Service . . . . . . . . 52(36)669-9160
FLORIDA, Maitland . . . . . . . . . (407)628-2636 Seattle Access . . . . . . . . . . . (206)622-9960 NETHERLANDS, Best . . . . (31)4998 612 11
FLORIDA, Pompano Beach/ WISCONSIN, Milwaukee/ PUERTO RICO, San Juan . . . (809)793-2170
Ft. Lauderdale . . . . . . . . . . . . (305)351-6040 Brookfield . . . . . . . . . . . . . . . . (414)792-0122 SINGAPORE . . . . . . . . . . . . . . . (65)4818188
FLORIDA, Clearwater . . . . . . (813)538-7750
Field Applications Engineering Available SPAIN, Madrid . . . . . . . . . . . . . 34(1)457-8204
GEORGIA, Atlanta . . . . . . . . . (404)729-7100
Through All Sales Offices or . . . . . . . . . . . . . . . . . . . . . . . 34(1)457-8254
IDAHO, Boise . . . . . . . . . . . . . . (208)323-9413
CANADA SWEDEN, Solna . . . . . . . . . . . 46(8)734-8800
ILLINOIS, Chicago/ BRITISH COLUMBIA, SWITZERLAND, Geneva . . 41(22)799 11 11
Hoffman Estates . . . . . . . . . . (708)413-2500 Vancouver . . . . . . . . . . . . . . . . (604)293-7650
Shaumburg . . . . . . . . . . . . . . (708)413-2500 SWITZERLAND, Zurich . . . . . 41(1)730-4074
ONTARIO, Toronto . . . . . . . . . (416)497-8181 TAIWAN, Taipei . . . . . . . . . . . 886(2)717-7089
INDIANA, Fort Wayne . . . . . . (219)436-5818
ONTARIO, Ottawa . . . . . . . . . . (613)226-3491 THAILAND, Bangkok . . . . . . . 66(2)254-4910
INDIANA, Indianapolis . . . . . . (317)571-0400
QUEBEC, Montreal . . . . . . . . . (514)333-3300
INDIANA, Kokomo . . . . . . . . . (317)455-5100 UNITED KINGDOM,
INTERNATIONAL Aylesbury . . . . . . . . . . . . . . . 44(296)395-252
IOWA, Cedar Rapids . . . . . . . (319)378-0383
KANSAS, Kansas City/ AUSTRALIA, Melbourne . . . (61-3)887-0711
FULL LINE REPRESENTATIVES
Mission . . . . . . . . . . . . . . . . . . (913)451-8555 AUSTRALIA, Sydney . . . . . . . 61(2)906-3855
CALIFORNIA, Loomis
MARYLAND, Columbia . . . . . (410)381-1570 BRAZIL, Sao Paulo . . . . . . . 55(11)815-4200
Galena Technology Group . . . (916)652-0268
MASSACHUSETTS, CHINA, Beijing . . . . . . . . . . . . . . 86-505-2180
NEVADA, Reno
Marlborough . . . . . . . . . . . . . . (508)481-8100 FINLAND, Helsinki . . . . . . . 358-0-351 61191
Galena Tech. Group . . . . . . . (702)746-0642
MASSACHUSETTS, car phone . . . . . . . . . . . . . . . 358(49)211501
NEW MEXICO, Albuquerque
Woburn . . . . . . . . . . . . . . . . . . (617)932-9700 FRANCE, Paris . . . . . . . . . . . . 33134 635900
S&S Technologies, Inc. . . . . (505)298-7177
MICHIGAN, Detroit . . . . . . . . . (313)347-6800 GERMANY, Langenhagen/
UTAH, Salt Lake City
MINNESOTA, Minnetonka . . . . (612)932-1500 Hannover . . . . . . . . . . . . . . . 49(511)786880
Utah Comp. Sales, Inc. . . . . . (801)561-5099
MISSOURI, St. Louis . . . . . . . (314)275-7380 GERMANY, Munich . . . . . . . . . 49 89 92103-0
GERMANY, Nuremberg . . . . 49 911 96-3190 WASHINGTON, Spokane
NEW JERSEY, Fairfield . . . . . (201)808-2400
GERMANY, Sindelfingen . . . . 49 7031 79 710 Doug Kenley . . . . . . . . . . . . . (509)924-2322
NEW YORK, Fairport . . . . . . . (716)425-4000
NEW YORK, Hauppauge . . . . (516)361-7000 GERMANY, Wiesbaden . . . . . 49 611 973050 HYBRID/MCM COMPONENT
NEW YORK, Fishkill . . . . . . . . (914)896-0511 HONG KONG, Kwai Fong . . . . 852-6106888 SUPPLIERS
NORTH CAROLINA, Tai Po . . . . . . . . . . . . . . . . . . . . 852-6668333 Chip Supply . . . . . . . . . . . . . . . (407)298-7100
Raleigh . . . . . . . . . . . . . . . . . . (919)870-4355 INDIA, Bangalore . . . . . . . . . (91-812)627094 Elmo Semiconductor . . . . . . . . (818)768-7400
OHIO, Cleveland . . . . . . . . . . . (216)349-3100 ISRAEL, Herzlia . . . . . . . . . . 972–9–590222 Minco Technology Labs Inc. . . (512)834-2022
OHIO, Columbus/ ITALY, Milan . . . . . . . . . . . . . . . . . 39(2)82201 Semi Dice Inc. . . . . . . . . . . . . . (310)594-4631

For changes to this information contact Technical Publications at FAX (602) 244-6561
 3/1/95

SALES OFFICES
INTERNATIONAL MOTOROLA DISTRIBUTOR AND SALES OFFICES
AUTHORIZED DISTRIBUTORS
AUSTRALIA JAPAN Future Electronics . . . . . . . . . (403)250-5550
VSI Electronics (NZ) Ltd . . . . . . . . (64)9 579-6603 AMSC Co., Ltd. . . . . . . . . . . . . . . . 81-422-54-6800 Hamilton/Hallmark . . . . . . . . (800)663–5500
VSI Promark Elec. Pty Ltd . . . . . . . (61)2 439-4655 Marubun Corporation . . . . . . . . . . 81-3-3639-8951 Edmonton
Veltek Pty Ltd . . . . . . . . . . . . . . . . . (61)3 808-7511 OMRON Corporation . . . . . . . . . . 81-3-3779–9053 Future Electronics . . . . . . . . . (403)438-2858
AUSTRIA Fuji Electronics Co., Ltd. . . . . . . . 81-3-3814-1411 Hamilton/Hallmark . . . . . . . . (800)663-5500
EBV Austria . . . . . . . . . . . . . . . . (43) 222 894 1774 Tokyo Electron Ltd. . . . . . . . . . . . 81-3-5561–7254 Saskatchewan
Elbatex GmbH . . . . . . . . . . . . . . . (43) 222 86 3211 Nippon Motorola Micro Elec. . . . . . 81-3-3280-7300 Hamilton/Hallmark . . . . . . . . (800)663–5500
BENELUX KOREA
Diode Belgium . . . . . . . . . . . . . . . (32) 2 725 4660 Lite-On Korea Ltd. . . . . . . . . . . . . . (82)2 858-3853 BRITISH COLUMBIA
Lee Ma Industrial Co. Ltd. . . . . . . . (82)2 739-5257 Vancouver
Diode Components BV . . . . . . . (31) 340 29 1234
Jung Kwang Sa . . . . . . . . . . . . . . (82)51 802-2153 Arrow Electronics . . . . . . . . . (604)421–2333
EBV Belgium . . . . . . . . . . . . . . . . . (32) 2 720 9936
Electro Sonic Inc. . . . . . . . . . (604)273–2911
EBV Holland . . . . . . . . . . . . . . . . (31) 3465 623 53 NORWAY
Avnet Nortec A/S Norway . . . . . . (47) 6 664 6210 Future Electronics . . . . . . . . . . (604)294-1166
Rodelco Electronics . . . . . . . . . . . . (31) 767 84911
Hamilton/Avnet Electronics . (604)420-4101
Rodelco N.V. . . . . . . . . . . . . . . . . . (32) 2 460 0560 SCANDINAVIA
CHINA ITT Multikomponent AB . . . . . . . . . . (46) 8 830 020 MANITOBA
Advanced Electronics Ltd. . . . . . . (852)305-3633 Avnet Nortec (S) . . . . . . . . . . . . . . (46) 8 705 1800 Winnipeg
China El. App. Corp. Xiamen Co. . . (86)592 553-487 Avnet Nortec (DK) . . . . . . . . . . . . (45) 42 842 000 Electro Sonic Inc. . . . . . . . . (209)783-3105
Nanco Electronics Supply Ltd. . . . . . (852) 333-5121 Avnet Nortec (N) . . . . . . . . . . . . . . . . (47) 6 684 210 Future Electronics . . . . . . . . . (204)944-1446
Qing Cheng Enterprises Ltd. . . . . (852) 493-4202 SINGAPORE Hamilton/Hallmark . . . . . . . . (800)663–5500
DENMARK Alexan Commercial . . . . . . . . . . . . . (63)2 405-952
Avnet Nortec A/S Denmark . . . . . . (45) 428 42000 GEIC . . . . . . . . . . . . . . . . . . . . . . . . . (65) 298-7633 ONTARIO
EBV Denmark . . . . . . . . . . . . . . . . . (45) 398 905 11 P.T. Ometraco . . . . . . . . . . . . . . . . . (62)22 630-805 Ottawa
FINLAND Uraco Impex Asia Pte Ltd. . . . . . . . . (65)5457811 Arrow Electronics . . . . . . . . . (613)226-6903
Arrow Field OY . . . . . . . . . . . . . . . (35) 807 775 71 Shapiphat Ltd. . . . . . . . . . . . . . . . . . (66)2 221-5384 Electro Sonic Inc. . . . . . . . . . (613)728-8333
SPAIN Future Electronics . . . . . . . . . (613)820-8313
FRANCE
Arrow Electronique . . . . . . . . . . (33) 1 49 78 49 78 Amitron Arrow . . . . . . . . . . . . . . . . (34) 1 304 30 40 Hamilton/Hallmark . . . . . . . . (613)226-1700
Avnet Components . . . . . . . . . . (33) 1 49 65 25 00 EBV Spain . . . . . . . . . . . . . . . . . . . (34) 9 358 86 08 Toronto
EBV France . . . . . . . . . . . . . . . . (33) 1 64 68 86 00 Selco S.A. . . . . . . . . . . . . . . . . . . . (34) 1 359 43 48 Arrow Electronics . . . . . . . . . (416)670-7769
Scaib . . . . . . . . . . . . . . . . . . . . . (33) 1 46 87 23 13 SWEDEN Electro Sonic Inc. . . . . . . . . . (416)494-1666
GERMANY Avnet Nortec AB . . . . . . . . . . . . . . (48) 8 629 14 00 Future Electronics . . . . . . . . . (905)612–9200
Avnet E2000 . . . . . . . . . . . . . . . . . (49) 89 4511001 SWITZERLAND Hamilton/Hallmark . . . . . . . . (905)564–6060
EBV Germany . . . . . . . . . . . . . . . . . (49) 89 456100 EBV Switzerland . . . . . . . . . . . . . . (41) 1 740 10 90 Newark . . . . . . . . . . . . . . . . . . (519)685–4280
Future Electronics GmbH . . . . . (49) 89-957 195-0 Elbatex AG . . . . . . . . . . . . . . . . . . (41) 56 275 165 (905)670–2888
Jermyn GmbH . . . . . . . . . . . . . . . . . (49) 6431-5080 TAIWAN Richardson Electronics . . . . (905)795–6300
Muetron, Mueller Mercuries & Assoc. Ltd . . . . . . . (886)2 503-1111 FAI . . . . . . . . . . . . . . . . . . . . . . (905)612–9888
GmbH & Co. . . . . . . . . . . . . . . . (49) 421-305 60 Solomon Technology Corp. . . . . . (886)2 760-5858
Sasco GmbH . . . . . . . . . . . . . . . . . . . (49) 89-46110 Strong Electronics Co. Ltd. . . . . . . (886)2 917-9917 QUEBEC
Spoerle Electronic . . . . . . . . . . . . (49) 6103-304-0 UNITED KINGDOM Montreal
HONG KONG Arrow Electronics (UK) Ltd . . . . . (44) 234 272733 Arrow Electronics . . . . . . . . . . (514)421-7411
Nanshing Clr. & Chem. Co. Ltd . . . . (852) 333-5121 Avnet/Access . . . . . . . . . . . . . . . . (44) 462 480888 Future Electronics . . . . . . . . . (514)694-7710
Wong’s Kong King Semi. Ltd. . . . . (852) 357-8888 Future Electronics Ltd. . . . . . . . . (44) 753 687000 Hamilton/Hallmark . . . . . . . . (514)335-1000
INDIA Macro Marketing Ltd. . . . . . . . . . (44) 628 604 383 Richardson . . . . . . . . . . . . . . . (514)748–1770
Canyon Products Ltd . . . . . . . . . . . (852) 755-2583 CANADA Quebec City
ITALY All Provinces – Newark . . . . . . . . . (800)463-9275 Arrow Electronics . . . . . . . . . (418)687-4231
Avnet Adelsy SpA . . . . . . . . . . . . (39) 2 38103100 ALBERTA Future Electronics . . . . . . . . . (418)682-8092
EBV Italy . . . . . . . . . . . . . . . . . . . . (39) 2 66017111 Calgary St. Laurent
Silverstar SpA . . . . . . . . . . . . . . . . . (39) 2 66 12 51 Electro Sonic Inc. . . . . . . . . (403)255-9550 Richardson Electronics . . . . (514)748-1770

SALES OFFICES
CANADA Hannover . . . . . . . . . . . . . . . . . . . . . 49(511)786880 KOREA, Seoul . . . . . . . . . . . . . . . . . . . 82(2)554-5118
BRITISH COLUMBIA, Vancouver . . . . (604)293-7650 GERMANY, Munich . . . . . . . . . . . . . . . 49 89 92103-0 MALAYSIA, Penang . . . . . . . . . . . . . . . 60(4)374514
ONTARIO, Toronto . . . . . . . . . . . . . . (416)497-8181 GERMANY, Nuremberg . . . . . . . . . . 49 911 96-3190 MEXICO, Mexico City . . . . . . . . . . . . 52(5)282-0230
ONTARIO, Ottawa . . . . . . . . . . . . . . . (613)226-3491 GERMANY, Sindelfingen . . . . . . . . . 49 7031 79 710 MEXICO, Guadalajara . . . . . . . . . . . 52(36)21-8977
QUEBEC, Montreal . . . . . . . . . . . . . . (514)333-3300 GERMANY, Wiesbaden . . . . . . . . . . 49 611 973050 Marketing . . . . . . . . . . . . . . . . . . . . . 52(36)21-2023
INTERNATIONAL HONG KONG, Kwai Fong . . . . . . . . . . 852-6106888 Customer Service . . . . . . . . . . . . 52(36)669-9160
AUSTRALIA, Melbourne . . . . . . . . . (61-3)887-0711 Tai Po . . . . . . . . . . . . . . . . . . . . . . . . . . 852-6668333 NETHERLANDS, Best . . . . . . . . . . (31)4998 612 11
AUSTRALIA, Sydney . . . . . . . . . . . . 61(2)906-3855 INDIA, Bangalore . . . . . . . . . . . . . . (91-812)627094 PHILIPPINES, Manila . . . . . . . . . . . . (63)2 822-0625
BRAZIL, Sao Paulo . . . . . . . . . . . . . 55(11)815-4200 ISRAEL, Herzlia . . . . . . . . . . . . . . . . 972–9–590222 PUERTO RICO, San Juan . . . . . . . . (809)793-2170
CHINA, Beijing . . . . . . . . . . . . . . . . . . . . 86-505-2180 ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . 39(2)82201 SINGAPORE . . . . . . . . . . . . . . . . . . . . . (65)4818188
CHINA, Guangzhou . . . . . . . . . . . (86) 20 331-1626 JAPAN, Fukuoka . . . . . . . . . . . . . . 81-92–725–7583 SPAIN, Madrid . . . . . . . . . . . . . . . . . . 34(1)457-8204
CHINA, Shanghai . . . . . . . . . . . . . (86) 21 279-8206 JAPAN, Gotanda . . . . . . . . . . . . . . . 81-3-5487-8311 or . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)457-8254
CHINA, Singapore . . . . . . . . . . . . . . . . (65) 481-8188 JAPAN, Nagoya . . . . . . . . . . . . . . . 81-52-232-3500 SWEDEN, Solna . . . . . . . . . . . . . . . . 46(8)734-8800
CHINA, Tianjin . . . . . . . . . . . . . . . . . (86) 22 506-972 JAPAN, Osaka . . . . . . . . . . . . . . . . . . 81-6-305-1802 SWITZERLAND, Geneva . . . . . . . . 41(22)799 11 11
FINLAND, Helsinki . . . . . . . . . . . . . 358-0-351 61191 JAPAN, Sendai . . . . . . . . . . . . . . . . 81-22-268-4333 SWITZERLAND, Zurich . . . . . . . . . . 41(1)730-4074
car phone . . . . . . . . . . . . . . . . . . . . . 358(49)211501 JAPAN, Takamatsu . . . . . . . . . . . . . 81-878-37-9972 TAIWAN, Taipei . . . . . . . . . . . . . . . . 886(2)717-7089
FRANCE, Paris . . . . . . . . . . . . . . . . . . 33134 635900 JAPAN, Tokyo . . . . . . . . . . . . . . . . . 81-3-3440-3311 THAILAND, Bangkok . . . . . . . . . . . . 66(2)254-4910
GERMANY, Langenhagen/ KOREA, Pusan . . . . . . . . . . . . . . . . 82(51)4635-035 UNITED KINGDOM, Aylesbury . . . . . 44(296)395-252

For changes to this information contact Technical Publications at FAX (602) 244-6561
 Theory and Applications
1
(Chapters 1 thru 9)

2 Selector Guide

3 Data Sheets

Surface Mount
4 Package Information and
Tape and Reel Specifications

Outline Dimensions
5
and Leadform Options

Index and
6
Cross Reference