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Digital Electronic Circuits

Assignment- Week 9
TYPE OF QUESTION: MCQ/Short answer
Number of questions: 20 Total mark: 20 X 1 = 20
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QUESTION 1:
A mod-6 ripple counter is given below. The output of the 2-input gate is used to clear the J-K
flip-flops .

The 2-input gate is _______?

a. AND gate
b. OR gate
c. NOR gate
d. NAND gate

Correct Answer: b

Detailed Solution:

In the modulo - 6 ripple counter at the end of sixth pulse (i.e. after 101 or at 110) all states must be
cleared. Thus, when CB is 11, all states must be cleared.

Since the CLEAR is active low, the input to 2-input gate(C’ and B’) and the desired output should be
low to clear the FFs.
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Thus when C and B are 0 and 0 then output must be 0. In all other cases, the output must be 1. OR
gate can implement this.

The output of 2-input gate: Y = (CB)’ = C’+B’

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QUESTION 2:

The following ripple counter functions as: (Assume that the counter starts in the initial state 111
and the Q output of flip-flop C acts as MSB)

a. Mod-3 up counter
b. Mod-3 down counter
c. Mod-5 up counter
d. Mod-5 down counter

Correct Answer:d

Detailed Solution:

Preset=Active HIGH Asynchronous input

On preset operation,

Preset Clock C B A State

1 0 1 1 1 7

0 1 1 1 0 6

0 2 1 0 1 5
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0 3 1 0 0 4

0 4 0 1 1 3

1 5 0 1 0

1 1 1

After 5 clock pulses A and C becomes 0 and through AND gate, the output becomes 1. Since
preset is active high, it will set the contents to 111. When the output of AND gate becomes 1, the
counter goes to initial state (111).

Output of AND gate = A’BC’=1 when A=0, B=1, C=0.

So, A=0, B=1, C=0 (010 - undesired state)

When the counter enters in to 010 states (Undesired State), preset operation takes place and it
takes the control towards initial state of 111.

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QUESTION 3:

A ripple counter with positive edge triggered flip-flop is given below. If the present state of
counter is Q2Q1Q0 = 011 then its next state will be_____?

a. 001
b. 010
c. 101
d. 111
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Correct Answer: a

Detailed Solution:

Present state Present input Next state

Q2 Q1 Q0 T2 T1 T0 Q2 Q1 Q0

0 1 1 1 1 1 1 0 0

This will act as an up-counter. The state will move from 011(3) to 100(4).

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QUESTION 4:

Given that Q3 acts as MSB, the following circuit is a/an ____________. Assume that J and K
inputs are 1 for all flip-flops.

a. Synchronous binary upcounter

b. Asynchronous binary up counter
c. Synchronous binary down counter
d. Asynchronous binary down counter

Correct Answer: b

Detailed Solution:
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Refer to Asynchronous counters, lecture 41, slide no.9, NPTEL online certification courses

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QUESTION 5:

Consider the following figure:

Logic gate

Suppose you are asked to make a decoding circuit such that the output Y=1 when the counter is
at state 0, 1, 6 and 7. Which of the following gates can be used in the logic gate block above to
implement the required operation?

a) AND
b) OR
c) XNOR
d) XOR

Correct Answer: c

Detailed Solution:

It is given in question that Y=1 when counter is at state 0, 1, 6 and 7. Hence,

Count C B A Y

0 0 0 0 1

1 0 0 1 1
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2 0 1 0 0

3 0 1 1 0

4 1 0 0 0

5 1 0 1 0

6 1 1 0 1

7 1 1 1 1

The K-map for the following truth table can be drawn as,

B’A’ B’A BA BA’

C’ 1 1 0 0

C 0 0 1 1

From the K-map, we get Y= B’C’+BC, which is equivalent to a logic XNOR operation.
Therefore, correct answer is(c)

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QUESTION 6:
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For the following figure, consider the statements given below:

Statement 1: In asynchronous sequential circuits, the problem of glitch appears in the decoding
circuit due to finite propagation delay of the constituent flip-flops of counter circuit.

Statement 2:In asynchronous sequential circuits, the problem of glitch can be prevented by
�������� as an input to the decoding gate along with the respective counter state output
using 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶

a) Statement 1 is TRUE but Statement 2 is FALSE

b) Statement 1 is FALSE but Statement 2 is TRUE
c) Both statement 1 and 2 are TRUE
d) Both statement 1 and 2 are FALSE

Correct Answer: a

Detailed Solution:

The problem of Glitch in asynchronous decoding circuit can be prevented by using 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 as
�������� .
an input to the decoding gate along with the respective counter state output, and not 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶

Refer to Lecture-42, Decoding logic and Synchronous Counter, NPTEL online certification
courses and reference books.

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QUESTION 7:
Consider the following figure:

Assume the initial state of the JK flip flop (denoted Q) to be 0 and the counter to be 0000. The
number of clock pulses after which the counter again goes back to its initial state
is_____________.

a) 8
b) 7
c) 15
d) 16

Correct Answer: d

Detailed Solution:

If M = 0, the counter (DCBA)acts an up-counter. If M = 1, the counter (DCBA)acts an down-

counter.

Here, initial condition of M = Q = 0.

The states taken by the counter are:

Count Q D C B A

0 0 0 0 0 0

1 0 0 0 0 1

2 0 0 0 1 0

3 0 0 0 1 1

4 0 0 1 0 0
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5 0 0 1 0 1

6 0 0 1 1 0

7 0 0 1 1 1

8 1 1 0 0 0

As M becomes 1 after 8 cycles, the counter now becomes a down-counter. Continuing the above
truth table, we have,

Count Q D C B A

9 1 0 1 1 1

10 1 0 1 1 0

11 1 0 1 0 1

12 1 0 1 0 0

13 1 0 0 1 1

14 1 0 0 1 0

15 1 0 0 0 1

16 1 0 0 0 0

Hence, correct answer is (d)

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QUESTION 8:
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In the given figure, various states taken by the counter are:

a) ABC000, 111,010,101,001,110,011,100,000
b) ABC000,100,010,110,001,101,011,111,000
c) ABC000,100,011,111,001,101,010,110,000
d) ABC000,101,011,110,110,111,001,010,000

Correct Answer: c

Detailed Solution:

The truth table below shows different states that the given circuit takes:

Count A B C

0 0 0 0

1 1 0 0

2 0 1 1

3 1 1 1

4 0 0 1

5 1 0 1

6 0 1 0

7 1 1 0
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8 0 0 0

Hence, correct answer is (c)

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QUESTION 9:
What is the minimum number of flip-flops required to make a mod-117 counter?

a) 5
b) 6
c) 7
d) 8

Correct Answer: c

Detailed Solution:

Mod- N means that the counter is capable of having N different states (including initial state). To
make a mod-117 counter, it must cycle through 117 states.

With 𝑚𝑚 flip-flops, we can design a counter to cycle through a maximum of 2𝑚𝑚 states. Hence,

2𝑚𝑚 ≥ 117

⇒ 𝑚𝑚 ≥ 7

Hence, correct answer is (c).

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QUESTION 10:

The clock frequency of 12MHz is applied to a cascaded counter of modulus-3 counters,

modulus-4 counters and modulus-5 counters. What are the lowest output frequency and overall
modulus respectively?
a. 200 KHz, 60
b. 1MHz, 60
c. 2 MHz, 12
d. 4MHz, 12
Correct Answer: a
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Detailed Solution:

Lowest output frequency = (12× (1000))/ (3×4×5) KHz= 200 KHz

Overall modulus= 3×4×5=60
Refer to Lecture-43, Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter, NPTEL online
certification courses.

QUESTION 11:

Suppose you are asked to make decoration lights for Diwali at your home. You have to use LED
lights. The decoration is such that LEDs are arranged in a sequence, which turn ON one at a time
and the rest are OFF. This cycle repeats. You have a decoder and a mod-N counter for the
purpose connected as shown in figure below. Each of the decoder output is connected to an LED.

4 X 10 Decoder

CLK Mod-N

What should be the value of ‘N’ and clock frequency if lights should turn ON after interval of
0.5 seconds?

a) 10, 2Hz
b) 16, 0.5Hz
c) 10, 0.5Hz
d) 16, 2Hz
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Correct Answer: a

Detailed Solution:

Since we have a 4x10 decoder, 10 LEDs can be connected to the output of decoder which must
turn ON consecutively. Therefore, the number of states (N) that the counter must have to get
HIGH output from decoder for every light is 10.

Also, if lights are to turn ON every 0.5 seconds, the duration of clock pulse must also be 0.5
seconds or the clock frequency must be 2Hz.

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QUESTION 12:
Two cascaded decade counters will divide the input frequency by a factor of:

a. 2
b. 10
c. 20
d. 100

Correct Answer: d

Detailed Solution:

Each decade counter counts through 10 states and divides the clock frequency by 10.

For 2 decade-counters, divide by 102 = 100.

Refer to Lecture-43, Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 Counter, NPTEL online
certification courses.

QUESTION 13:
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Clock

Figure above shows mod-N counter. The value of N is _____________.

Correct Answer: 3

Detailed Solution:

The states that the counter show in figure above assumes are:

Clock Q3 Q2 Q1 State

0 0 0 0 0

1 0 1 0 2

2 0 1 1 3

3 (Cycle 0
0 0 0
repeats)

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QUESTION 14:

A certain JK flip-flop has propagation delay of 16ns.The largest modulus of ripple counter that
can be constructed from such flip-flop and still operate up to 12MHz is

a. 6
b. 32
c. 64
d. 128
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Correct Answer: b

Detailed Solution: 𝑓𝑓𝑚𝑚𝑚𝑚𝑚𝑚 = 1�(𝑁𝑁. 𝑡𝑡 ) where N is the number of flip-flops in the ripple counter.
𝑝𝑝𝑝𝑝

N=1/(16ns.12MHz)=5.20≈5

The largest modulus of ripple counter that can be constructed=2𝑁𝑁 =25 =32

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QUESTION 15:

Which of the following statements are TRUE?

I. Synchronous mod counters do not have glitches that arise when using asynchronous
preset/clear based counter design.
II. Lockout occurs when a counter remains trapped in unused state(s), if any, and cannot
move to valid state(s) on its own.
III. Avoidance of lockout can be included in design steps of a synchronous counter.
IV. Counters can be used in parallel to serial conversion through time multiplexing.

a. I, II, III
b. II, III, IV
c. I, IV
d. All of the above

Correct answer: d
Detailed solution:

Refer to Lecture-45, Counter Design with Asynchronous Reset and preset, NPTEL online
certification courses.

QUESTION 16:
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The number of unused states of the synchronous counter shown in the following figure is
_____________:

Correct answer: 2

Detailed solution:
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QUESTION 17:
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Consider the design of a counter with the following state diagram using JK flip-flops. Determine
the logic equations of the J and K inputs for the MSB flip-flop. (Assume 𝑄𝑄2 𝑄𝑄1 𝑄𝑄0 denotes the
counter output.)

a. 𝐽𝐽 = 1, 𝐾𝐾 = 1
b. 𝐽𝐽 = 𝑄𝑄2 ′, 𝐾𝐾 = 1
c. 𝐽𝐽 = 𝑄𝑄2′ 𝑄𝑄0 , 𝐾𝐾 = 𝑄𝑄2 + 𝑄𝑄0
d. 𝐽𝐽 = 𝑄𝑄1 𝑄𝑄0 , 𝐾𝐾 = 1

Correct answer: d

Detailed solution:

State Table: Here Q2 is the MSB.

Previous State Next State FF2 FF1 FF0

Count Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

2 0 1 0 0 1 1 0 X X 0 1 X
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3 0 1 1 1 0 0 1 X X 1 X 1

4 1 0 0 0 0 0 X 1 0 X 0 X

5 1 0 1 0 0 0 X 1 0 X X 1

6 1 1 0 0 0 0 X 1 X 1 0 X
7 1 1 1 0 0 0 X 1 X 1 X 1

From the table it can be easily found that:

J2=Q1Q0; J1=Q2’Q0; J0=Q2’
K2=1; K1=Q2+Q0=(Q2’Q0’)’; K0=1

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QUESTION 18:

Which of the following switch positions implement a divide-by-4 clock frequency divider?

a. 3
b. 4
c. 2 and 4
d. 2 and 5

Correct answer: d
Detailed Solution:

Let clock frequency be 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 .

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Switch position Output frequency, 𝒇𝒇𝟎𝟎

1 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 /2

2 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 /4

3 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 /6

4 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 /8

5 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 /4

(a) The switch position at 2 implements a 2-stage Johnson counter. An n-stage Johnson counter
𝑓𝑓 𝑐𝑐𝑐𝑐𝑐𝑐
acts as a divide-by-2n frequency divider. Hence, the output has frequency , where 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 is the
4
clock frequency.

(d) The switch position at 5 implements a 4-stage Ring counter. An n-stage Ring counter acts a
𝑓𝑓 𝑐𝑐𝑐𝑐𝑐𝑐
divide-by-n frequency divider. Hence, the output has frequency , where 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 is the clock
4
frequency.

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QUESTION 19:
For the circuit below, which of the following statements are TRUE?

I. The output 𝑌𝑌1 𝑌𝑌2 𝑌𝑌3 𝑌𝑌4 cycles through 4 different states.
II. The flip-flop outputs cycle through 4 different states.
III. The output waveforms 𝑌𝑌1 , 𝑌𝑌2 , 𝑌𝑌3 and 𝑌𝑌4 are in quadrature (90° out-of-phase with
respect to each other).
𝑓𝑓
IV. The output waveform at 𝑄𝑄𝐴𝐴 has frequency 𝑐𝑐𝑐𝑐𝑐𝑐 where 𝑓𝑓𝑐𝑐𝑐𝑐𝑐𝑐 is the clock frequency.
2

a. I, II only
b. II, IV only
c. I, II, III only
d. All the above
Correct answer: c
Detailed Solution:

(I) The outputs 𝑌𝑌1 𝑌𝑌2 𝑌𝑌3 𝑌𝑌4 cycle through the following states:

1000, 0100, 0010, 0001

(II) The flip-flop outputs 𝑄𝑄𝐴𝐴 𝑄𝑄𝐵𝐵 cycle through the following states:

11, 01, 00, 10

(III) Because of the state sequence in (a), the outputs are 90° phase-shifted with respect to each
other.
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(IV) is FALSE because the flip-flops are connected to implement a 2-stage Johnson counter,
which acts as a divide-by-4 frequency divider.

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QUESTION 20:

Consider the following implementation of a sequence generator.

The minimum number of flip-flops needed to generate a sequence of length 𝑆𝑆 is:

a. 𝑆𝑆
b. 2𝑆𝑆
c. log 2 𝑆𝑆 + 1
d. log 2 (𝑆𝑆)

Correct answer: d
Detailed solution:
The Mod n counter cycles through n states, which is also equal to the sequence length. Here, the
length of sequence is specified as S. Let the number of flip-flops be m. Then,

2𝑚𝑚 ≥ 𝑆𝑆

⇒ 𝑚𝑚 ≥ 𝑙𝑙𝑙𝑙𝑔𝑔2 𝑆𝑆

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