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Sample Vlsi Resume

The document provides a summary of expertise and experience for Gedela Anil Kumar. It details his 2.5 years of experience in DFT for VLSI design. It lists his technical skills including scan insertion, ATPG, simulation tools, and languages. It then summarizes his roles and responsibilities on 4 projects involving DDR_PHY, JELLYFISH, SUMACHI, and LEONARDO chips where he performed tasks like scan insertion, ATPG pattern generation, simulation, and debugging.

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Pavan Kumar
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483 views

Sample Vlsi Resume

The document provides a summary of expertise and experience for Gedela Anil Kumar. It details his 2.5 years of experience in DFT for VLSI design. It lists his technical skills including scan insertion, ATPG, simulation tools, and languages. It then summarizes his roles and responsibilities on 4 projects involving DDR_PHY, JELLYFISH, SUMACHI, and LEONARDO chips where he performed tasks like scan insertion, ATPG pattern generation, simulation, and debugging.

Uploaded by

Pavan Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Gedela Anil Kumar

Summary of Expertise:

 2.5 years of Experience in DFT in VLSI Design.

Technical skills:

 Exposure to scan insertion, exposure to module level ATPG DRC analysis and pattern validation.
 Good understanding on scan compression.
 ATPG pattern generation and simulations.
 Basics of MBIST & JTAG (IEEE 1149.1) concepts.
 Tools used: Cadence Genus, Tessent Scan, TestKompress, QuestaSim.
 Languages: Tcl
 Platforms: Unix, Linux, Windows.

Project Summary:

1. Project: DDR_PHY

Role : DFT Engineer


Design Tool : DC compiler,TetraMAX
Technology : 12nm

Roles & Responsibilities:


 Performed Scan insertion by defining constraints, scan configurations, analyzed and fixed DRCs.
Performed full scan methodology with Cadence slices.
 ATPG pattern generation for stuck-at and Transition fault models.
 Worked with Cadence Coustamized OPCG.
 ATPG patterns verification with gate level simulation.

2. Project: JELLYFISH

Role : DFT Engineer


Design Tool : Synopsis, Mentor Graphics TestKompress,
Technology : 16nm
Flop count : 1M

Roles & Responsibilities:


 Scan DRC debugging
 ATPG Stuck-At & At-Speed using Mentor TestKompress.
 ATPG DRC analysis and debug for SOC Clusters.
 Test Coverage Improvement.
 Simulations using VCS and Debugging SimFailures.

3. Project: SUMACHI

Role : DFT Engineer


Design Tool : Cadence RTL Complier, Mentor Graphics TestKompress
Technology : 28nm

Roles & Responsibilities:


 Work with DFT lead for design flow implementation.
 Scan insertion and ATPG patterns generations.
 ATPG patterns verification with gate level simulations.
 Analyze DRC issues in ATPG.

4. Project : LEONARDO

Role : DFT Engineer


Design Tool : Cadence RTL Complier, Mentor Graphics TestKompress
Technology : 55nm

Roles & Responsibilities:


 Block level Scan insertion using Cadence RTL Compiler.
 Fixing the DRC’s issues.
 ATPG Stuck-At & At-Speed

Education:

 B. Tech in Electronics and Communications Engineering from Raghu Institute of Technology, AP in


2016 with 6.7 CGPA

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