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1 - Lenovo-Y510 - VIQY1 - NM - A032-2013-03-19 Rev1.0-compalnma032r10schematics.-OK!OK! - Podxodit K-Y500 PDF

1. The document is an engineering drawing schematic for an Intel Haswell processor-based computer with DDR3 memory and Lynx Point PCH chipset. 2. The schematic shows the components including the Intel CPU, two Nvidia GPUs, memory interfaces, I/O interfaces like HDMI, USB, ethernet. 3. It provides details on the component specifications and connections between various chips on the motherboard.

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GAMMA GER
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382 views70 pages

1 - Lenovo-Y510 - VIQY1 - NM - A032-2013-03-19 Rev1.0-compalnma032r10schematics.-OK!OK! - Podxodit K-Y500 PDF

1. The document is an engineering drawing schematic for an Intel Haswell processor-based computer with DDR3 memory and Lynx Point PCH chipset. 2. The schematic shows the components including the Intel CPU, two Nvidia GPUs, memory interfaces, I/O interfaces like HDMI, USB, ethernet. 3. It provides details on the component specifications and connections between various chips on the motherboard.

Uploaded by

GAMMA GER
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 70

A B C D E

1 1

VIQY1
2
(Y510) 2

NM_A032 Rev1.0 Schematic

Intel Haswell Processor with DDRIII + Lynx point PCH


3
nVIDIA N14P GT + 2nd VGA N14P GT 3

2013-03-19 Rev1.0

4 4

Security Classification LC Future Center Secret Data Title


Cover Page
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 1 of 69

A B C D E
A B C D E

PCI-Express 16X Gen3


PEG 8~15 PEG 0~7
Intel CPU
Haswell Memory BUS (DDRIII) DDR3-SO-DIMM X2
2nd VGA, N14P-GT1 N14P-GT1 Dual Channel
1 BANK 0, 1, 2, 3 1

VRAM 64*32 VRAM 64*32


rPGA946
1.35V DDRIIIL 1066/1333/1600 MT/s
GDDR5* 8 GDDR5* 8 37.5mm*37.5mm UP TO 16G
Page 11,12
Sub/B Page 32 Page 23,24,25,26,27,28,29,30,31,33
Page 5,6,7,8,9,10

MUX HDMI
Page 37
FDI *2 DMI *4
2.7GT/s 5GT/s
HDMI Conn. CRT Conn. MUX CRT
Page 39 Page 36 Page 37
HDMI1.4b
eDP USB Charger IC USB Charger
LVDS eDP to LVDS USB 2.0 Port1
LVDS Conn. PS8625 MUX eDP
Page 35 Page 34 Page 38 5V 480MHz GL887T Conn.
Page 50 Sub/B Page 50

2
Atheros Intel PCH 2

RJ45 Conn. PCIe Gen1 USB Left USB Left


QCA8171-BL3A-R USB 2.0
Page 42
PCIe port 3 Page 41
1.5V 5GT/s Lynx point 5V 480MHz
USB 2.0 Port 2
USB 3.0 Port 2
USB 2.0 Port 3
USB 3.0 Port 5
Page 49 Page 49
SPI ROM SPI BUS
(4MB+2MB) 3.3V 33MHz
Int. Camera Touch panel
Page 17 FCBGA 695Balls USB 3.0
5V 5GT/s USB 2.0 Port 0 USB 2.0 Port 8
20mm*20mm Page 35 Page 50
SATA HDD
SATA Port 5
SATA Gen3 Port 5
page 44 3V 6GHz(600MB/s)
USB 2.0
PCIeMini Card NGFF SSD
SATA ODD 5V 480MHz
SATA Port 2 SATA Gen1 Port2 WLAN
PCIe Port 4 SATA Port 4
page 44 3V 3GHz(300MB/s) PCIe Gen1 page 40 page 40
5V 480MHz
3 PCIeMini Card 3
USB 3.0 Port6
Card reader Card reader IC SATA Gen3 WLAN
5V 5GT/s USB Port 10
5V 6GHz(600MB/s) page 40
Conn. GL3213 USB 2.0 Port4 Page 13,14,15,16,17,18,19,20,21,22
Page 48 Page 48 5V 480MHz
HD Audio
LPC BUS
3.3V 33MHz
3.3V 24MHz

Debug Port EC Codec


SPK Conn.
Page 40 ITE IT8586E-FX ALC282CG Page 45
Page 45
Page 46
Power Circuit DC/DC
Page 56,57,58,59,60,61,
62,63,64,65,66

4 DC/DC Interface CKT. RTC CKT. Thermal Sensor Int. MIC Conn. 4

Page 55 Page 56 Touch Pad Int.KBD Ext. MIC Conn. HP Conn.


(JCMOS Conn.)
EMC 1403 Page 35 Page 50 Page 50
Page 47 Page 47 Page 43 Sub/B Sub/B
POWER/B Conn. AUDIO, USB/B Conn. Security Classification LC Future Center Secret Data Title
Page 52 Page 50 Block Diagram
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
ODD/B Conn. NOVO/B Conn. Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
page 44 Page 52 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 2 of 69

A B C D E
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
+VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+V1.5S_VCCP 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_CORE
+3VALW
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +1.5V
+GFX_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS
+1.05VS
State +0.75VS
+3.3VS_VGA
+1.5VS_VGA
USB Port Table BOM Structure Table
+1.05VS_VGA
4 External BOM Structure BTO Item
USB 2.0 USB 3.0 Port USB Port GT@ NV GT750M
Camera GT1@ NV GT755M
S0 O O O O 0
CMOS@ CMOS Camera part
XHCI 1 QCA8171 LAN surge part
USB Port (Right Side) SURGE@
X76@ X76 Level part for VRAM
S3 O O O X EHCI1 2 2
USB Port (Left Side)
GC6@ NV CG6 support part
2 3 NV no CG6 support part 2
5 USB Port (Left Side) NOGC6@
6 Card Reader AOAC@ AOAC support part
S5 S4/AC Only O O X X 4
5 KBL@ K/B Light part
6 ME@ ME part
S5 S4 @ Unpop
Battery only O X X X 7
Touch panel DS3@ Deep S3 support part
EHCI2 8
9 daul@ Support daul channel panel function
887T@ GENESYS 887T USB charger solution
S5 S4 10 Mini Card(WLAN)
887@ GENESYS 887 USB charger solution
AC & Battery X X X X 11
TI@ TI USB charger solution
12
don't exist EDP@ Support EDP panel function
13
SLI@ For SLI function part
47W@ For 47W CPU part
SMBUS Control Table
37W@ For 37W CPU part
Main 2nd WLAN Thermal PCH TP PCIE PORT LIST
SOURCE VGA VGA BATT IT8580E SODIMM WiMAX Sensor Module Port Device
3 3

1
EC_SMB_CK1 IT8580E
X X V X X X X X X 2
EC_SMB_DA1 +3VALW
+3VALW 3
4 LAN
EC_SMB_CK2 IT8580E
EC_SMB_DA2 +3VS
V V X X X X V V X 5 WLAN
+3VS +3VS +3VS +3V_PCH 6
7
SMB_CLK_S3 PCH
SMB_DATA_S3 +3VS
X X X X V V X V V 8
+3VS +3VS +3V_PCH +3VS

Address
EC SM Bus1 address EC SM Bus2 address PCH SM Bus address ZZZ1
4 4

Device Device Address Device Address


Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb DDR DIMM0 1001 000Xb
DAZ0SF00100
Master VGA 0x9E DDR DIMM2 1001 010Xb
Slave VGA 0x9C Security Classification LC Future Center Secret Data Title
Notes List
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 3 of 69

A B C D E
5 4 3 2 1

Hot plug detect for IFP link E


Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N14Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO0 IN - FB_CLAMP_MON N14X


128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - NA GDDR5

GPIO2 OUT - VGA_BL_PWM Physical Logical Logical Logical Logical


Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT - VGA_ENVDD ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT - VGA_ENBKL ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - NA
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - FB_CLAMP_TOGGLE_REQ# STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT - NA
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 OUT - OVERT# STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - VGA_ALERT#
Device ID setting I2C Slave addrees ID
GPIO10 OUT - Memory VREF Control N13P-GT SMB_ALT_ADDR
(28nm) 0x0FCD 0 0x9E
(ROM_SO Bit 1)
GPIO11 OUT - NVVDD PWM_VID
C C
1 0x9C
GPIO12 IN - AC Power Detect Input (10K pull High)

GPIO13 OUT - DPRSLPVR_VGA

GPIO14 OUT - NA

GPIO15 IN - NA GPU ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

GPIO16 OUT - NA PU 10K PD 15K PU 45K PD 5K PD 25K PU 5K PD 45K Master


N14P-GT
GPIO17 IN - VGA_EDP_HPD 28nm PU 20K PU 25K PU 45K PD 35K PD 10K PD 5K PD 10K Slave
GPIO18 IN - DGPU_HDMI_HPD

GPIO19 IN - NA

GPU N14P-GT N14P-GT1

FB Memory (GDDR5) ROM_SI ROM_SI


B
+3VS_VGA B
Samsung K4G20325FD-FC03
3000MHz
+VGA_CORE 64Mx32 PD 30K

tNVVDD >0 Hynix H5GQ2H24AFR-R0C


+1.5VS_VGA 3000MHz
tFBVDDQ >0 64Mx32 PD 25K
+1.05VS_VGA
tPEX_VDD >0
Samsung K4G20325FD-FC04
2500MHz
64Mx32 PD 30K
1. all power rail ramp up time should be larger than 40us
Hynix H5GQ2H24AFR-T2C
2500MHz
64Mx32 PD 25K

Other Power rail

+3VS_VGA
A A

Tpower-off <10ms

Security Classification LC Future Center Secret Data Title


VGA Notes List
Issued Date 2012/07/01 Deciphered Date 2014/07/01
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 4 of 69

5 4 3 2 1
5 4 3 2 1

D +VCCIOA_OUT D

PEG_COMP 2 1
24.9_0402_1% RC2

CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.

Haswell rPGA EDS


JCPUA

E23 PEG_COMP
PEG_RCOMP PCIE_CRX_GTX_N[0..15] <23,32>
M29PCIE_CRX_GTX_N0
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28PCIE_CRX_GTX_N1
<15> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1 PEG Static Lane Reversal - CFG2 is for the 16x
DMI_CRX_PTX_N1 C21 M31PCIE_CRX_GTX_N2
<15> DMI_CRX_PTX_N1 DMI_RXN_1 PEG_RXN_2
DMI_CRX_PTX_N2 B21 L30 PCIE_CRX_GTX_N3
<15> DMI_CRX_PTX_N2 DMI_RXN_2 PEG_RXN_3
DMI_CRX_PTX_N3 A21 M33PCIE_CRX_GTX_N4 1: Normal Operation; Lane # definition matches
<15> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PCIE_CRX_GTX_N5 CFG2
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35PCIE_CRX_GTX_N6 socket pin map definition
<15> DMI_CRX_PTX_P0

PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PCIE_CRX_GTX_N7
<15> DMI_CRX_PTX_P1 DMI_RXP_1 PEG_RXN_7
DMI_CRX_PTX_P2 B20 E29PCIE_CRX_GTX_N8 0:Lane Reversed
<15>
<15>
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P3 A20 DMI_RXP_2 PEG_RXN_8 D28PCIE_CRX_GTX_N9
*

DMI
DMI_RXP_3 PEG_RXN_9 E31PCIE_CRX_GTX_N10
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30PCIE_CRX_GTX_N11
<15> DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 C17 DMI_TXN_0 PEG_RXN_11 E35PCIE_CRX_GTX_N12
C <15> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34PCIE_CRX_GTX_N13 C
<15> DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 A17 DMI_TXN_2 PEG_RXN_13 E33PCIE_CRX_GTX_N14
<15> DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32PCIE_CRX_GTX_N15
PEG_RXN_15 PCIE_CRX_GTX_P[0..15] <23,32>
DMI_CTX_PRX_P0 D17 L29 PCIE_CRX_GTX_P0
<15> DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 C18 DMI_TXP_0 PEG_RXP_0 L28 PCIE_CRX_GTX_P1
<15> DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PCIE_CRX_GTX_P2
<15> DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30PCIE_CRX_GTX_P3
<15> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PCIE_CRX_GTX_P4
PEG_RXP_4 K32PCIE_CRX_GTX_P5
PEG_RXP_5 L35 PCIE_CRX_GTX_P6
PEG_RXP_6 K34PCIE_CRX_GTX_P7
PEG_RXP_7 F29PCIE_CRX_GTX_P8
2 1 FDI_CSYNC_R H29 PEG_RXP_8 E28PCIE_CRX_GTX_P9
<15> FDI_CSYNC

FDI
RC3 2 1 0_0402_5% FDI_INT_R J29 FDI_CSYNC PEG_RXP_9 F31PCIE_CRX_GTX_P10
<15> FDI_INT FDI_INT PEG_RXP_10
RC87 0_0402_5% E30PCIE_CRX_GTX_P11
PEG_RXP_11 F35PCIE_CRX_GTX_P12
PEG_RXP_12 E34PCIE_CRX_GTX_P13
PEG_RXP_13 F33PCIE_CRX_GTX_P14
PEG_RXP_14 D32PCIE_CRX_GTX_P15
PEG_RXP_15 H35PCIE_CTX_GRX_N0 1 2 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N[0..15] <23,32>
CC1 0.22U_0402_10V6K
PEG_TXN_0 H34PCIE_CTX_GRX_N1 CC2 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1
PEG_TXN_1 J33 PCIE_CTX_GRX_N2 CC3 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2
PEG_TXN_2 H32PCIE_CTX_GRX_N3 CC4 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3
PEG_TXN_3 J31 PCIE_CTX_GRX_N4 CC5 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4
PEG_TXN_4 G30PCIE_CTX_GRX_N5 CC6 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5
PEG_TXN_5 C33PCIE_CTX_GRX_N6 CC7 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6
PEG_TXN_6 B32PCIE_CTX_GRX_N7 CC8 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7
PEG_TXN_7 B31PCIE_CTX_GRX_N8 CC9 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N8
PEG_TXN_8 A30PCIE_CTX_GRX_N9 CC10 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N9
PEG_TXN_9 B29PCIE_CTX_GRX_N10 CC11 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N10
PEG_TXN_10 A28PCIE_CTX_GRX_N11 CC12 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N11
PEG_TXN_11 B27PCIE_CTX_GRX_N12 CC13 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N12
B PEG_TXN_12 A26PCIE_CTX_GRX_N13 CC14 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N13 B
PEG_TXN_13 B25PCIE_CTX_GRX_N14 CC15 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N14
PEG_TXN_14 A24PCIE_CTX_GRX_N15 CC16 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15
PEG_TXN_15 J35 PCIE_CTX_GRX_P0 1 2 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P[0..15] <23,32>
CC20 0.22U_0402_10V6K
PEG_TXP_0 G34PCIE_CTX_GRX_P1 CC23 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P1
PEG_TXP_1 H33PCIE_CTX_GRX_P2 CC25 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2
PEG_TXP_2 G32PCIE_CTX_GRX_P3 CC30 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3
PEG_TXP_3 H31PCIE_CTX_GRX_P4 CC18 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4
PEG_TXP_4 H30PCIE_CTX_GRX_P5 CC22 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5
PEG_TXP_5 B33PCIE_CTX_GRX_P6 CC28 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6
PEG_TXP_6 A32PCIE_CTX_GRX_P7 CC32 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7
PEG_TXP_7 C31PCIE_CTX_GRX_P8 CC19 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P8
PEG_TXP_8 B30PCIE_CTX_GRX_P9 CC24 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P9
PEG_TXP_9 C29PCIE_CTX_GRX_P10 CC29 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P10
PEG_TXP_10 B28PCIE_CTX_GRX_P11 CC17 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P11
PEG_TXP_11 C27PCIE_CTX_GRX_P12 CC21 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P12
PEG_TXP_12 B26PCIE_CTX_GRX_P13 CC27 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P13
PEG_TXP_13 C25PCIE_CTX_GRX_P14 CC26 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P14
PEG_TXP_14 B24PCIE_CTX_GRX_P15 CC31 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15
PEG_TXP_15

INTEL_HASWELL_HASWELL 1 OF 9

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU (1/7) DMI, FDI, PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 20, 2013 Sheet 5 of 69
5 4 3 2 1
5 4 3 2 1

+1.35V
XDP Connector

1
RC60 JXDP @
1 2 RC62 @ +1.05VS
0_0402_5% 1K_0402_5% XDP_PREQ#_R 1
XDP_PRDY#_R 2

0.1U_0402_25V6K

0.1U_0402_25V6K
3
Place near JXDP1

2
RC1543 XDP_OBS0 4 1 1
3 1 1 2 5

D
H_DRAMRST# DDR3_DRAMRST#_R XDP_OBS1
DDR3_DRAMRST# <11,12>

CC65

CC66
0_0402_5% 6 @ @

2
@ QC3 XDP_OBS2 7
RC1544 BSS138_NL_SOT23-3 XDP_OBS3 8 2 2

G
2
D 4.99K_0402_1% @ 9 D
RC5 need to close to JCPU1
H_CPUPWRGD RC5 1 2 1K_0402_1% H_CPUPWRGD_XDP 10
RC6 1 @ 2 0_0402_5% CFD_PWRBTN#_XDP 11
<15> SIO_PWRBTN#_R

1
CPU_PWR_DEBUG 12
<9> CPU_PWR_DEBUG VGATE 13
<15,64> VGATE
1 @ 2 DRAMRST_CNTRL CLK_CPU_ITP 14
<17> DRAMRST_CNTRL_PCH <16> CLK_CPU_ITP
RC42 0_0402_5% 1 CLK_CPU_ITP# 15
<16> CLK_CPU_ITP#
16
<7> DRAMRST_CNTRL +1.05VS BUF_CPU_RST# 1 2 XDP_RST#_R 17
CC50
1 RC15452 18
<46> DRAMRST_CNTRL_EC @ 0.047U_0402_16V4Z 1K_0402_1% RC8 XDP_DBRESET#
2 19
R_short 0_0402_5% XDP_TDO_R 20
Reserve for Deep S3 XDP_TRST#_R 21
XDP_TDI_R 22
XDP_TMS_R 23
24
25
XDP_TCK_R 26
27
28

MOLEX 52435-2671
20120806 VA
change XDP connector to 28 pin

PU/PD for JTAG signals DDR3 COMPENSATION SIGNALS


+3VS RC1539
C SM_RCOMP0 1 2 100_0402_1% C
Haswell rPGA EDS
XDP_DBRESET#_R RC19 2 1 1K_0402_1% JCPUB SM_RCOMP1 RC55 1 2 75_0402_1%

AP32 MISC AP3 SM_RCOMP0 SM_RCOMP2 RC49 1 2 100_0402_1%


+1.05VS SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1
SM_RCOMP_1

DDR3
AN32 AP2

THERMAL
H_CATERR# SM_RCOMP2 CAD Note:
XDP_TMS @ RC27 2 1 51_0402_1% H_PECI AR27 CATERR SM_RCOMP_2 AN3 H_DRAMRST#
<46> H_PECI PECI SM_DRAMRST
PAD T55 @ AK31
RSVD
Trace width=12~15 mil, Spcing=20 mils
XDP_TDI @ RC29 2 1 51_0402_1% RC57 1 2 56_0402_5% H_PROCHOT#_R AM30 AR29 XDP_PRDY# RC47 1 2 0_0402_5% XDP_PRDY#_R
<46,57> H_PROCHOT#
H_THRMTRIP# AM35 PROCHOT PRDY AT29 XDP_PREQ# RC48 1 2 0_0402_5% XDP_PREQ#_R Max trace length= 500 mil
<19> H_THRMTRIP# THERMTRIP PREQ
XDP_PREQ# @ RC32 2 1 51_0402_1% AM34 XDP_TCLK RC50 1 2 0_0402_5% XDP_TCK_R
TCK AN33 XDP_TMS RC53 1 2 0_0402_5% XDP_TMS_R
XDP_TDO @ RC35 2 1 51_0402_1% TMS AM33 XDP_TRST# RC54 1 2 0_0402_5% XDP_TRST#_R

JTAG
H_PM_SYNC AT28 TRST AM31 XDP_TDI RC23 1 2 0_0402_5% XDP_TDI_R
<15> H_PM_SYNC

PWR
RC25 1 2 VCCPWRGOOD_0_R AL34 PM_SYNC TDI AL33 XDP_TDO RC24 1 2 0_0402_5% XDP_TDO_R VCCPWRGOOD_0_R
<19> H_CPUPWRGD PWRGOOD TDO
PM_DRAM_PWRGD_CPU AC10 AP33 XDP_DBRESET#_R RC26 2 1 0_0402_5% XDP_DBRESET#
SM_DRAMPWROK DBR

10K_0402_5%
XDP_TCLK RC40 2 1 51_0402_1% R_short 0_0402_5% BUF_CPU_RST# AT26
PLTRSTIN

1
AR30 XDP_OBS0_R RC30 1 2 0_0402_5% XDP_OBS0
BPM_N_0

RC130
XDP_TRST# RC41 2 1 51_0402_1% AN31 XDP_OBS1_R RC31 1 2 0_0402_5% XDP_OBS1
RC51 2 1 0_0402_5% CPU_DPLL# G28 BPM_N_1 AN29 XDP_OBS2_R RC33 1 2 0_0402_5% XDP_OBS2
<16> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2

CLOCK
RC52 2 1 0_0402_5% CPU_DPLL H28 AP31 XDP_OBS3_R RC34 1 2 0_0402_5% XDP_OBS3
<16> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3
RC43 2 1 0_0402_5% CPU_SSC_DPLL# F27 AP30 XDP_OBS4_R RC36 1 2 0_0402_5%
<16> CLK_CPU_SSC_DPLL#

2
RC22 2 1 0_0402_5% CPU_SSC_DPLL E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28 XDP_OBS5_R RC37 1 2 0_0402_5%
<16> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5
<16> CLK_CPU_DMI# CLK_CPU_DMI# D26 AP29 XDP_OBS6_R RC38 1 2 0_0402_5%
CLK_CPU_DMI E26 BCLKN BPM_N_6 AP28 XDP_OBS7_R RC39 1 2 0_0402_5%
<16> CLK_CPU_DMI BCLKP BPM_N_7

INTEL_HASWELL_HASWELL 2 OF 9
CAD Note:
Avoid stub in the PWRGD path
BUF_CPU_RST# VCCPWRGOOD_0_R
SM_DRAMPWROK with DDR Power Gating Topology while placing resistors RC25 & RC130
B B
497750_497750_SHRKBY_MBL_SCH_CHKLST 0.5 For ESD 1 1
page19 item 3.6 SM_DRAMPWROK @ @
CC61 CC60
220P_0402_25V8J 220P_0402_25V8J
2 2
+3V_PCH
For ESD concern, please put near CPU
+1.35V_CPU_VDDQ
+3V_PCH +VCCIO_OUT
1

1
100K_0402_5%

200_0402_5%

+1.05VS
1.8K_0402_1%

CC156 CPU_SSC_DPLL 1 2
Buffered Reset to CPU
RC89

RC84

1 2 10K_0402_5% RC20 @
RC16

@ RC1261 @ 2 H_THRMTRIP# CPU_SSC_DPLL# 1 2


0.1U_0402_25V6K 100_0402_1% 10K_0402_5% RC21 @
2

RC1281 @ 2 H_CATERR#
2
5

@ 49.9_0402_1%
2 1 1 RC44 1 2 H_PROCHOT#
P

<15> SYS_PWROK B +VCCIO_OUT


RC88 0_0402_5% 4 RUNPWROK_AND 2 1 PM_DRAM_PWRGD_CPU 62_0402_5%
2 O RC28 0_0402_5%
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21
<15> PM_DRAM_PWRGD A
G

UC4
3.3K_0402_1%

74AHC1G09GW_TSSOP5
3

1
39_0402_5%
2
@ RC64

RC14

2 1 1.05V
RC1547 @ 0_0402_5%
2
1

SSM3K7002FU_SC70-3

1 2 BUF_CPU_RST#
<19> CPU_PLTRST#
0_0402_5%
1

D
RC46
@ QC1

2
A <10> RUN_ON_CPU1.5VS3# A
G
S
3

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU (2/7) PM, XDP, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 6 of 69
5 4 3 2 1
5 4 3 2 1

Haswell rPGA EDS


JCPUD
<12> DDRB_DQ[0..63]
Haswell rPGA EDS DDRB_DQ0 AR18 AG8 @ T63 PAD
JCPUC DDRB_DQ1 AT18 SB_DQ_0 RSVD Y4
<11> DDRA_DQ[0..63] DDRB_DQ2 AM17 SB_DQ_1 SB_CKN0 AA4 DDRB_CLK0# <12>
DDRA_DQ0 AR15 AC7 DDRB_DQ3 AM18 SB_DQ_2 SB_CK0 AF10 DDRB_CLK0 <12>
@T64
@ T64 PAD
DDRA_DQ1 AT14 SA_DQ_0 RSVD_AC7 U4 DDRB_DQ4 AR17 SB_DQ_3 SB_CKE_0 Y3 DDRB_CKE0 <12>
DDRA_DQ2 AM14 SA_DQ_1 SA_CK_N_0 V4 DDRA_CLK0# <11> DDRB_DQ5 AT17 SB_DQ_4 SB_CKN1 AA3 DDRB_CLK1# <12>
AN14 SA_DQ_2 SA_CK_P_0 AD9 DDRA_CLK0 <11> SB_DQ_5 SB_CK1 DDRB_CLK1 <12>
DDRA_DQ3 DDRB_DQ6 AN17 AG10
D DDRA_DQ4 AT15 SA_DQ_3 SA_CKE_0 U3 DDRA_CKE0 <11> DDRB_DQ7 AN18 SB_DQ_6 SB_CKE_1 Y2 DDRB_CKE1 <12> D
DDRA_DQ5 AR14 SA_DQ_4 SA_CK_N_1 V3 DDRA_CLK1# <11> DDRB_DQ8 AT12 SB_DQ_7 SB_CKN2 AA2
DDRA_DQ6 AN15 SA_DQ_5 SA_CK_P_1 AC9 DDRA_CLK1 <11> DDRB_DQ9 AR12 SB_DQ_8 SB_CK2 AG9
AM15 SA_DQ_6 SA_CKE_1 U2 DDRA_CKE1 <11> SB_DQ_9 SB_CKE_2
DDRA_DQ7 DDRB_DQ10 AN12 Y1
DDRA_DQ8 AM9 SA_DQ_7 SA_CK_N_2 V2 DDRB_DQ11 AM11 SB_DQ_10 SB_CKN3 AA1
DDRA_DQ9 AN9 SA_DQ_8 SA_CK_P_2 AD8 DDRB_DQ12 AT11 SB_DQ_11 SB_CK3 AF9
DDRA_DQ10 AM8 SA_DQ_9 SA_CKE_2 U1 DDRB_DQ13 AR11 SB_DQ_12 SB_CKE_3
DDRA_DQ11 AN8 SA_DQ_10 SA_CK_N_3 V1 DDRB_DQ14 AM12 SB_DQ_13 P4
DDRA_DQ12 AR9 SA_DQ_11 SA_CK_P_3 AC8 DDRB_DQ15 AN11 SB_DQ_14 SB_CS_N_0 R2 DDRB_CS0# <12>
AT9 SA_DQ_12 SA_CKE_3 SB_DQ_15 SB_CS_N_1 DDRB_CS1# <12>
DDRA_DQ13 DDRB_DQ16 AR5 P3
DDRA_DQ14 AR8 SA_DQ_13 M7 DDRB_DQ17 AR6 SB_DQ_16 SB_CS_N_2 P1
DDRA_DQ15 AT8 SA_DQ_14 SA_CS_N_0 L9 DDRA_CS0# <11> DDRB_DQ18 AM5 SB_DQ_17 SB_CS_N_3
DDRA_DQ16 AJ9 SA_DQ_15 SA_CS_N_1 M9 DDRA_CS1# <11> DDRB_DQ19 AM6 SB_DQ_18 R4
DDRA_DQ17 AK9 SA_DQ_16 SA_CS_N_2 M10 DDRB_DQ20 AT5 SB_DQ_19 SB_ODT_0 R3 DDRB_ODT0 <12>
DDRA_DQ18 AJ6 SA_DQ_17 SA_CS_N_3 M8 DDRB_DQ21 AT6 SB_DQ_20 SB_ODT_1 R1 DDRB_ODT1 <12>
DDRA_DQ19 AK6 SA_DQ_18 SA_ODT_0 L7 DDRA_ODT0 <11> DDRB_DQ22 AN5 SB_DQ_21 SB_ODT_2 P2
DDRA_DQ20 AJ10 SA_DQ_19 SA_ODT_1 L8 DDRA_ODT1 <11> DDRB_DQ23 AN6 SB_DQ_22 SB_ODT_3 R7
DDRA_DQ21 AK10 SA_DQ_20 SA_ODT_2 L10 DDRB_DQ24 AJ4 SB_DQ_23 SB_BS_0 P8 DDRB_BS0# <12>
AJ7 SA_DQ_21 SA_ODT_3 V5 SB_DQ_24 SB_BS_1 DDRB_BS1# <12>
DDRA_DQ22 DDRB_DQ25 AK4 AA9
DDRA_DQ23 AK7 SA_DQ_22 SA_BS_0 U5 DDRA_BS0# <11> DDRB_DQ26 AJ1 SB_DQ_25 SB_BS_2 DDRB_BS2# <12>
DDRA_DQ24 AF4 SA_DQ_23 SA_BS_1 AD1 DDRA_BS1# <11> DDRB_DQ27 AJ2 SB_DQ_26 R10
DDRA_DQ25 AF5 SA_DQ_24 SA_BS_2 DDRA_BS2# <11> DDRB_DQ28 AM1 SB_DQ_27 RSVD R6
DDRA_DQ26 AF1 SA_DQ_25 V10 DDRB_DQ29 AN1 SB_DQ_28 SB_RAS P6 DDRB_RAS# <12>
DDRA_DQ27 AF2 SA_DQ_26 RSVD_V10 U6 DDRB_DQ30 AK2 SB_DQ_29 SB_WE P7 DDRB_WE# <12>
DDRA_DQ28 AG4 SA_DQ_27 SA_RAS U7 DDRA_RAS# <11> DDRB_DQ31 AK1 SB_DQ_30 SB_CAS DDRB_CAS# <12>
AG5 SA_DQ_28 SA_WE U8 DDRA_WE# <11> L2 SB_DQ_31 R8 DDRB_MA0 DDRB_MA[0..15] <12>
DDRA_DQ29 DDRB_DQ32
DDRA_DQ30 AG1 SA_DQ_29 SA_CAS DDRA_CAS# <11> DDRB_DQ33 M2 SB_DQ_32 SB_MA_0 Y5 DDRB_MA1
DDRA_DQ31 AG2 SA_DQ_30 V8 DDRA_MA0 DDRA_MA[0..15] <11> DDRB_DQ34 L4 SB_DQ_33 SB_MA_1 Y10DDRB_MA2
DDRA_DQ32 J1 SA_DQ_31 SA_MA_0 AC6DDRA_MA1 DDRB_DQ35 M4 SB_DQ_34 SB_MA_2 AA5DDRB_MA3
DDRA_DQ33 J2 SA_DQ_32 SA_MA_1 V9 DDRA_MA2 DDRB_DQ36 L1 SB_DQ_35 SB_MA_3 Y7 DDRB_MA4
DDRA_DQ34 J5 SA_DQ_33 SA_MA_2 U9 DDRA_MA3 DDRB_DQ37 M1 SB_DQ_36 SB_MA_4 AA6DDRB_MA5
DDRA_DQ35 H5 SA_DQ_34 SA_MA_3 AC5DDRA_MA4 DDRB_DQ38 L5 SB_DQ_37 SB_MA_5 Y6 DDRB_MA6
C DDRA_DQ36 H2 SA_DQ_35 SA_MA_4 AC4DDRA_MA5 DDRB_DQ39 M5 SB_DQ_38 SB_MA_6 AA7DDRB_MA7 C
DDRA_DQ37 H1 SA_DQ_36 SA_MA_5 AD6DDRA_MA6 DDRB_DQ40 G7 SB_DQ_39 SB_MA_7 Y8 DDRB_MA8
DDRA_DQ38 J4 SA_DQ_37 SA_MA_6 AC3DDRA_MA7 DDRB_DQ41 J8 SB_DQ_40 SB_MA_8 AA10
DDRB_MA9
DDRA_DQ39 H4 SA_DQ_38 SA_MA_7 AD5DDRA_MA8 DDRB_DQ42 G8 SB_DQ_41 SB_MA_9 R9 DDRB_MA10
DDRA_DQ40 F2 SA_DQ_39 SA_MA_8 AC2DDRA_MA9 DDRB_DQ43 G9 SB_DQ_42 SB_MA_10 Y9 DDRB_MA11
DDRA_DQ41 F1 SA_DQ_40 SA_MA_9 V6 DDRA_MA10 DDRB_DQ44 J7 SB_DQ_43 SB_MA_11 AF7DDRB_MA12
DDRA_DQ42 D2 SA_DQ_41 SA_MA_10 AC1DDRA_MA11 DDRB_DQ45 J9 SB_DQ_44 SB_MA_12 P9 DDRB_MA13
DDRA_DQ43 D3 SA_DQ_42 SA_MA_11 AD4DDRA_MA12 DDRB_DQ46 G10 SB_DQ_45 SB_MA_13 AA8DDRB_MA14
DDRA_DQ44 D1 SA_DQ_43 SA_MA_12 V7 DDRA_MA13 DDRB_DQ47 J10 SB_DQ_46 SB_MA_14 AG7DDRB_MA15
DDRA_DQ45 F3 SA_DQ_44 SA_MA_13 AD3DDRA_MA14 DDRB_DQ48 A8 SB_DQ_47 SB_MA_15
DDRA_DQ46 C3 SA_DQ_45 SA_MA_14 AD2DDRA_MA15 DDRB_DQ49 B8 SB_DQ_48
B3 SA_DQ_46 SA_MA_15 A9 SB_DQ_49 AP18 DDRB_DQS#[0..7] <12>
DDRA_DQ47 DDRB_DQ50 DDRB_DQS#0
DDRA_DQ48 B5 SA_DQ_47 DDRB_DQ51 B9 SB_DQ_50 SB_DQS_N_0 AP11
DDRB_DQS#1
E6 SA_DQ_48 AP15 DDRA_DQS#[0..7] <11> D8 SB_DQ_51 SB_DQS_N_1 AP5DDRB_DQS#2
DDRA_DQ49 DDRA_DQS#0 DDRB_DQ52
DDRA_DQ50 A5 SA_DQ_49 SA_DQS_N_0 AP8DDRA_DQS#1 DDRB_DQ53 E8 SB_DQ_52 SB_DQS_N_2 AJ3DDRB_DQS#3
DDRA_DQ51 D6 SA_DQ_50 SA_DQS_N_1 AJ8DDRA_DQS#2 DDRB_DQ54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDRB_DQS#4
DDRA_DQ52 D5 SA_DQ_51 SA_DQS_N_2 AF3DDRA_DQS#3 DDRB_DQ55 E9 SB_DQ_54 SB_DQS_N_4 H9 DDRB_DQS#5
DDRA_DQ53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDRA_DQS#4 DDRB_DQ56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDRB_DQS#6
DDRA_DQ54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDRA_DQS#5 DDRB_DQ57 D15 SB_DQ_56 SB_DQS_N_6 C14DDRB_DQS#7
DDRA_DQ55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDRA_DQS#6 DDRB_DQ58 A15 SB_DQ_57 SB_DQS_N_7 AP17
DDRB_DQS0 DDRB_DQS[0..7] <12>
DDRA_DQ56 E12 SA_DQ_55 SA_DQS_N_6 C11DDRA_DQS#7 DDRB_DQ59 B15 SB_DQ_58 SB_DQS_P_0 AP12
DDRB_DQS1
D12 SA_DQ_56 SA_DQS_N_7 AP14 DDRA_DQS[0..7] <11> SB_DQ_59 SB_DQS_P_1
DDRA_DQ57 DDRA_DQS0 DDRB_DQ60 E14 AP6DDRB_DQS2
DDRA_DQ58 B11 SA_DQ_57 SA_DQS_P_0 AP9DDRA_DQS1 DDRB_DQ61 D14 SB_DQ_60 SB_DQS_P_2 AK3DDRB_DQS3
DDRA_DQ59 A11 SA_DQ_58 SA_DQS_P_1 AK8DDRA_DQS2 DDRB_DQ62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDRB_DQS4
DDRA_DQ60 E11 SA_DQ_59 SA_DQS_P_2 AG3DDRA_DQS3 DDRB_DQ63 B14 SB_DQ_62 SB_DQS_P_4 H8 DDRB_DQS5
DDRA_DQ61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDRA_DQS4 SB_DQ_63 SB_DQS_P_5 C9 DDRB_DQS6
DDRA_DQ62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDRA_DQS5 SB_DQS_P_6 C15DDRB_DQS7
DDRA_DQ63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDRA_DQS6 SB_DQS_P_7
+VREF_CA_R AM3 SA_DQ_63 SA_DQS_P_6 C12DDRA_DQS7
+VREF_CA_R SM_VREF SA_DQS_P_7
+V_DDR_REFA_R F16 4 OF 9 INTEL_HASWELL_HASWELL
+V_DDR_REFB_R F13 SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
B B

3 OF 9 INTEL_HASWELL_HASWELL

DRAMRST_CNTRL
<6> DRAMRST_CNTRL
2

QC11 BSS138_SOT23
G

1 3
D

+VREF_DQ_DIMMA_R RC1548 1 2 0_0402_5% +V_DDR_REFA_R


+VREF_DQ_DIMMB_R RC92 1 2 0_0402_5% +V_DDR_REFB_R
1

@
1 3
D

RC144 @ @ RC143
QC9 BSS138_SOT23 1K_0402_1% 1K_0402_1%
G
2

DRAMRST_CNTRL

A A

6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU (3/7) DDRIII


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 7 of 69
5 4 3 2 1
5 4 3 2 1

CFG STRAPS for CPU


CFG2

1K_0402_1%
1
@ RC76
2
D D

PEG Static Lane Reversal - CFG2 is for the 16x


* 1:(Default) Normal Operation; Lane #
20120829 VA1 CFG2 definition matches socket pin map definition
Add net for add HDMI MUX
0:Lane Reversed
Haswell rPGA EDS
JCPUH

<37> CPU_HDMI_TX2- T28 M27 CPU_EDP_AUX#


U28 DDIB_TXBN_0 EDP_AUXN N27 CPU_EDP_AUX CPU_EDP_AUX# <38>
<37> CPU_HDMI_TX2+ DDIB_TXBP_0 EDP_AUXP CPU_EDP_AUX <38>
<37> CPU_HDMI_TX1- T30 P27 EDP_HPD_IN#
U30 DDIB_TXBN_1 eDP
EDP_HPD E24 EDP_COMP
<37> CPU_HDMI_TX1+ DDIB_TXBP_1 EDP_RCOMP
<37> CPU_HDMI_TX0- U29 R27
V29 DDIB_TXBN_2 RSVD PAD T69 @
<37> CPU_HDMI_TX0+ CFG4
U31 DDIB_TXBP_2
<37> CPU_HDMI_CLK- DDIB_TXBN_3
V31

1K_0402_1%
check CLK item <37> CPU_HDMI_CLK+ DDIB_TXBP_3

1
P35 CPU_EDP_TX0-
T34 EDP_TXN_0 R35 CPU_EDP_TX0- <38>

RC77
CPU_EDP_TX0+
U34 DDIC_TXCN_0 EDP_TXP_0 N34 CPU_EDP_TX1- CPU_EDP_TX0+ <38>
U35 DDIC_TXCP_0 EDP_TXN_1 P34 CPU_EDP_TX1+ CPU_EDP_TX1- <38>
V35 DDIC_TXCN_1 EDP_TXP_1 P33 CPU_EDP_TX1+ <38>
FDI_CTX_PRX_N0
DDIC_TXCP_1 FDI_TXN_0 FDI_CTX_PRX_N0 <15>

2
U32 R33 FDI_CTX_PRX_P0
COMPENSATION PU FOR eDP T32 DDIC_TXCN_2 FDI_TXP_0 N32 FDI_CTX_PRX_N1 FDI_CTX_PRX_P0 <15>
U33 DDIC_TXCP_2 FDI_TXN_1 P32 FDI_CTX_PRX_P1 FDI_CTX_PRX_N1 <15>
2 1 H_CPU_TESTLO V33 DDIC_TXCN_3 FDI_TXP_1 FDI_CTX_PRX_P1 <15>
+VCCIOA_OUT RC45 49.9_0402_1% DDIC_TXCP_3
2 1 CFG_RCOMP P29
C RC58 49.9_0402_1% R29 DDID_TXDN_0 C
EDP_COMP 2 1 2 1 H_CPU_RSVD N28 DDID_TXDP_0 Display Port Presence Strap
24.9_0402_1% RC1 RC59 49.9_0402_1% P28 DDID_TXDN_1 DDI

P31 DDID_TXDP_1

CAD Note:Trace width=20 mils ,Spacing=25mil, R31 DDID_TXDN_2 1 : Disabled; No Physical Display Port
N30 DDID_TXDP_2
Max length=100 mils. P30 DDID_TXDN_3 CFG4 attached to Embedded Display Port
DDID_TXDP_3
* 0 : Enabled; An external Display Port device is
INTEL_HASWELL_HASWELL 8 OF 9
connected to the Embedded Display Port
+VCCIO_OUT CFG5
10K_0402_5%

CFG6
2
RC65

HPD INVERSION FOR EDP Haswell rPGA EDS

1K_0402_1%
1

1
1K_0402_1%
JCPUI

@RC83
@
1

RC83

RC85
@ T70 PAD AT1
EDP_HPD_IN# @ T71 PAD AT2 RSVD_TP C23 PAD T86 @

2
@ T72 PAD AD10 RSVD_TP RSVD_TP B23 PAD T78 @
RSVD RSVD_TP
BSS138_SOT23

D24 PAD T87 @


RSVD_TP
1

D @ T73 PAD A34 D23 PAD T88 @


RSVD_TP RSVD_TP
QC6

2 @ T77 PAD A35


<38> CPU_EDP_HPD RSVD_TP
G
S @ T76 PAD W29
PCIE Port Bifurcation Straps
3

RSVD
100K_0402_5%

@ T80 PAD W28 AT31 CFG_RCOMP


RSVD CFG_RCOMP
1

H_CPU_RSVD G26 AR21 CFG16 PAD T156 @


RSVD CFG_16 11: (Default) x16 - Device 1 functions 1 and 2 disabled
RC75

W33 AR23 CFG18 PAD T164 @


B @ T79 PAD AL30 RSVD CFG_18 AP21 CFG17 PAD T165 @ B
@ T94 PAD AL29
F25
RSVD
RSVD
CFG_17
CFG_19
AP23 CFG19 PAD T166 @ * 10: x8, x8 - Device 1 function 1 enabled ; function 2
+VCC_CORE CFG[6:5] disabled
2

VCC
@ T82 PAD C35 AR33 PAD T91 @ 01: Reserved - (Device 1 function 1 disabled ; function
@ T81 PAD B35 RSVD_TP RSVD G6 PAD T90 @
RSVD_TP RSVD AM27 PAD T92 @ 2 enabled)
@ T85 PAD AL25 RSVD AM26 PAD T89 @
RSVD_TP RSVD F5 PAD T93 @ 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
@ T84 PAD W30 RSVD AM2 PAD T95 @
@ T83 PAD W31 RSVD RSVD K6 PAD T104@
H_CPU_TESTLO W34 RSVD RSVD CFG7
TESTLO E18 PAD T96 @
RSVD

1
1K_0402_1%
@ T173PAD CFG0 AT20
CFG_0

@ RC86
@ T116PAD CFG1 AR20 U10 PAD T98 @
@ T117PAD CFG2 AP20 CFG_1 RSVD P10 PAD T97 @
@ T126PAD CFG3 AP22 CFG_2 RSVD
@ T129PAD CFG4 AT22 CFG_3 B1

2
@ T130PAD CFG5 AN22 CFG_4 NC A2 PAD T100 @
@ T131PAD CFG6 AT25 CFG_5 RSVD AR1 PAD T99 @
@ T132PAD CFG7 AN23 CFG_6 RSVD_TP
@ T133PAD CFG8 AR24 CFG_7 E21 PAD T102 @
@ T134PAD CFG9 AT23 CFG_8 RSVD_TP E20 PAD T101 @
@ T135PAD CFG10 AN20 CFG_9 RSVD_TP
@ T136PAD CFG11 AP24 CFG_10 AP27
@ T137PAD CFG12 AP26 CFG_11 RSVD AR26 PEG DEFER TRAINING
@ T138PAD CFG13 AN25 CFG_12 RSVD
@ T142PAD CFG14 AN26
AP25
CFG_13
CFG_14 RSVD
AL31
AL32
* 1: (Default) PEG Train immediately
@ T143PAD CFG15
CFG_15 RSVD CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A INTEL_HASWELL_HASWELL 9 OF 9 A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU (4/7) RSVD,CFG


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 8 of 69
5 4 3 2 1
5 4 3 2 1

Haswell rPGA EDS +VCC_CORE


JCPUE

AA26
VCC AA28
@ T107 PAD K27 VCC AA34
@ T106 PAD L27 RSVD VCC AA30
@ T112 PAD T27 RSVD VCC AA32
D @ T113 PAD V27 RSVD VCC AB26 D
RSVD VCC AB29
+1.35V_CPU_VDDQ VCC AB25
+1.35V VCC AB27
VCC AB28
CC151 2 1 0.1U_0402_25V6K AB11 VCC AB30
AB2 VDDQ VCC AB31
CC152 2 1 0.1U_0402_25V6K AB5 VDDQ VCC AB33
AB8 VDDQ VCC AB34
AE11 VDDQ VCC AB32
placement AE2 VDDQ VCC AC26
AE5 VDDQ VCC AB35
AE8 VDDQ VCC AC28
AH11 VDDQ VCC AD25
K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
N8 VDDQ VCC AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
@ T115 PAD N26 VCC AD35
K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
@ T151 PAD AK27 RSVD VCC AE28
@ T152 PAD RSVD VCC AE30
+VCC_CORE VCC AG28
C VCC AG34 C

VCC_SENSE VCC
VCC
AE34
100_0402_1%

AF25
VCC
1

AF26
VCC
RC66

VCCSENSE_R AL35 AF27


@ T153 PAD E17 VCC_SENSE VCC AF28
AN35 RSVD VCC AF29
RC4 +VCCIO_OUT VCCIO_OUT VCC
A23 AF30
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU +1.05VS
2

2 1 F22 VCCIO2PCH VCC AF31


+1.05VS +VCCIO_OUT +VCCIOA_OUT VCCIOA_OUT VCC
W32 AF32
VCCSENSE RC67 2 1 VCCSENSE_R 0_0603_5% @ @ T160 PAD AL16 RSVD VCC AF33
<64> VCCSENSE J27 RSVD VCC AF34
R_short 0_0402_5% @ T159 PAD
AL13 VSS VCC AF35
need connect to power CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU RC61 43_0402_5%
@ T154 PAD RSVD VCC
VCC
AG26
AH26
1 2 VR_SVID_ALRT#_R AM28 VCC AH29
<64> VR_SVID_ALRT# VIDALERT VCC
VSSSENSE RC68 2 1 VSSSENSE_R
VSSSENSE_R <10>
VR_SVID_CLK AM29 AG30
<64> VSSSENSE <64> VR_SVID_CLK VR_SVID_DAT AL28 VIDSCLK VCC AG32
R_short 0_0402_5%
<64> VR_SVID_DAT VIDSOUT VCC AH32
VCC
1
100_0402_1%

AP35 AH35
VSS VCC

1
CPU_PWR_DEBUG H27 AH25
PWR_DEBUG VCC
RC70

RC63 AP34 AH27


@ AT35 RSVD VCC AH28
130_0402_1% RSVD VCC
@ T157 PAD AR35 AH30
2

@ T158 PAD AR32 RSVD VCC AH31

2
@ T162 PAD AL26 RSVD VCC AH33
@ T163 PAD AT34 RSVD VCC AH34
AL22 RSVD VCC AJ25
AT33 RSVD VCC AJ26
+VCCIO_OUT AM21 RSVD VCC AJ27
AM25 RSVD VCC AJ28
AM22 RSVD VCC AJ29
B AM20 RSVD VCC AJ30 B
AM24 RSVD VCC AJ31
AL19 RSVD VCC AJ32
AM23 RSVD VCC AJ33
AT32 RSVD VCC AJ34
RSVD VCC AJ35
+1.05VS VCC G25
VCC H25
+1.35V_CPU_VDDQ Power VCC J25
VDDQ DECOUPLING VCC
150_0402_1%
K25
VCC
1

+VCC_CORE L25
VCC
RC69

@ M25
Y25 VCC N25
VCC VCC
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D2_2VM_R6M

330U_D2_2VM_R6M

1 1 Y26 P25
Y27 VCC VCC R25
1 1 1 1 1 1 1 1 1 1
2

VCC VCC
CC167

CC172

+ + Y28 T25
VCC VCC
CC171

CC170

CC169

CC168

CC161

CC162

CC163

CC164

CC165

CC166

Y29
@ @ CPU_PWR_DEBUG Y30 VCC U25
2 2 2 2 2 2 2 2 2 2 2 2 CPU_PWR_DEBUG <6> VCC VCC
Y31 U26
VCC VCC
10K_0402_5%

Y32 V25
VCC VCC
1

Y33 V26
VCC VCC
@

Y34
need connect to power VCC
RC71

Y35 W26
VCC VCC W27
VCC
2

INTEL_HASWELL_HASWELL 5 OF 9
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1 1 1 1 1 1 1 1 1 1 1
CC33

CC34

CC35

CC36

CC37

CC38

CC39

CC40

CC41

CC42

CC43

A A
2 2 2 2 2 2 2 2 2 2 2
@ @

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU (5/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 9 of 69
5 4 3 2 1
5 4 3 2 1

Haswell rPGA EDS Haswell rPGA EDS


JCPUF JCPUG

A10 AK34 B34 K10


A13 VSS VSS AK5 B4 VSS VSS K2
A16 VSS VSS AL1 B7 VSS VSS K29
A19 VSS VSS AL10 C1 VSS VSS K3
A22 VSS VSS AL11 C10 VSS VSS K31
A25 VSS VSS AL12 C13 VSS VSS K33
A27 VSS VSS AL14 C16 VSS VSS K35
A29 VSS VSS AL15 C19 VSS VSS K4
A3 VSS VSS AL17 C2 VSS VSS K5
A31 VSS VSS AL18 C22 VSS VSS K7
A33 VSS VSS AL2 C24 VSS VSS K8
A4 VSS VSS AL20 C26 VSS VSS K9
D A7 VSS VSS AL21 C28 VSS VSS L11 D
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AA31 VSS VSS AL4 C4 VSS VSS M26
AA29 VSS VSS AL5 C7 VSS VSS M28
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AC27 VSS VSS AM16 D27 VSS VSS N2
AB4 VSS VSS AM19 D29 VSS VSS N29
AB6 VSS VSS E25 D31 VSS VSS N3
AB7 VSS VSS AM32 D33 VSS VSS N31
AB9 VSS VSS AM4 D35 VSS VSS N33
AC11 VSS VSS AM7 D4 VSS VSS N35
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
AC31 VSS VSS AN16 E10 VSS VSS N6
AC33 VSS VSS AN19 E13 VSS VSS N7
AC35 VSS VSS AN2 E16 VSS VSS N9
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE29 VSS VSS AN34 F12 VSS VSS R26
AE3 VSS VSS AN4 F14 VSS VSS R28
AE27 VSS VSS AN7 F15 VSS VSS R30
AE35 VSS VSS AP1 F17 VSS VSS R32
AE4 VSS VSS AP10 F18 VSS VSS R34
C AE6 VSS VSS AP13 F20 VSS VSS R5 C
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AG25 VSS RSVD AR13 F32 VSS VSS T35
AE31 VSS VSS AR16 F34 VSS VSS T4
AG31 VSS VSS AR19 F4 VSS VSS T6
AE33 VSS VSS AR2 F6 VSS VSS T7
AG6 VSS VSS AR22 F7 VSS VSS T9
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
AH4 VSS VSS AT16 G31 VSS VSS W10
AH5 VSS VSS AT19 G33 VSS VSS W3
AH6 VSS VSS AT21 G35 VSS VSS W35
AH7 VSS VSS AT24 G4 VSS VSS W4
AH8 VSS VSS AT27 G5 VSS VSS W6
AH9
AJ11
VSS
VSS
VSS
VSS
AT3
AT30
+1.35V_CPU_VDDQ H10
H26
VSS
VSS
VSS
VSS
W7
W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11 RC237 0_0402_5%
AK11 VSS VSS AT7 H7 VSS VSS H11 1 2 RC238 0_0402_5%
AK25 VSS VSS B10 J11 VSS RSVD AL24 1 2
AK26 VSS VSS B13 @ J15 J26 VSS RSVD F19
AK28 VSS VSS B16 2 1 J28 VSS RSVD T26
B VSS VSS +1.35V 2 1 +1.35V_CPU_VDDQ RSVD RSVD B
AK29 B19 J30 AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE_R <9>
AK32 VSS VSS B22 JUMP_43X79 J34 VSS RSVD PAD T65 @
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS
+1.35V +1.35V_CPU_VDDQ

INTEL_HASWELL_HASWELL 6 OF 9 CC287 1 2 0.1U_0402_10V6K INTEL_HASWELL_HASWELL 7 OF 9

CC286 1 2 0.1U_0402_10V6K

CC96 1 2 0.1U_0402_10V6K
For Deep S3
CC95 1 2 0.1U_0402_10V6K

+3VALW +VSB UC3


8 1
7 2
1

R56 need to check on SDV 6 3


5
1

RC1537 @ @ RC56 @
100K_0402_5% 100K_0402_5% AO4304L_SO8
4

AO4304L @ RC1487
2

Vgs=10V,Id=18A, 470_0603_5%
RUN_ON_CPU1.5VS3 1 RC1349 2 @
Rds<6.7m ohm
2

470K_0402_5% P/N: SB00000RV00 QC5


1

RC1538 D@ D @
1

1 @ 2 RUN_ON_CPU1.5VS3# 2 1 2 SUSP
<40,55,61> SUSP G QC4 @ G
1

D @ 2N7002KW_SOT323-3 @ RC1546 CC97 2N7002KW_SOT323-3


S S
3

A 0_0402_5% 2 470K_0402_5% 0.01U 50V K X7R 0603 A


<46> CPU1.5V_S3_GATE 2
G QC156
2

S 2N7002KW_SOT323-3
3

RUN_ON_CPU1.5VS3# <6> Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CPU (6/7) PWR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 10 of 69
5 4 3 2 1
5 4 3 2 1

DDR3 SO-DIMM A
+VREF_DQ_DIMMA_R
DDRA_DQ[0..63] <7>
+1.35V +1.35V +1.35V
DDRA_DQS[0..7] <7>

1
RD78
DDRA_DQS#[0..7] <7>
1K_0402_1% [email protected]
For RF request DDRA_MA[0..15] <7>
RD91 2 JDDRL1
1 2 +VREF_DQ_DIMMA 1 2
0_0402_5% 3 VREF_DQ VSS1 4 DDRA_DQ7
VSS2 DQ4
1

0.047U_0402_16V4Z

0.047U_0402_16V4Z

0.047U_0402_16V4Z
D D

0.1U_0402_10V6K
5 6

2.2U_0603_6.3V6K
DDRA_DQ4 DDRA_DQ6
RD79 DDRA_DQ0 7 DQ0 DQ5 8
1 1 1 DQ1 VSS3 1 1 1
1K_0402_1%

CD141 CD140 9 10 DDRA_DQS#0 CD51 CD52 CD53


CD180 11 VSS4 DQS#0 12 DDRA_DQS0 @ @ @
0.1U_0402_10V6K 13 DM0 DQS0 14
2

2 2 2 DDRA_DQ1 15 VSS5 VSS6 16 DDRA_DQ2 2 2 2


DQ2 DQ6
1

DDRA_DQ5 17 18 DDRA_DQ3
RD90 19 DQ3 DQ7 20
DDRA_DQ13 21 VSS7 VSS8 22 DDRA_DQ15
24.9_0402_1% DDRA_DQ12 23 DQ8 DQ12 24 DDRA_DQ14
25 DQ9 DQ13 26
2

DDRA_DQS#1 27 VSS9 VSS10 28


DDRA_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# <12,6>
DDRA_DQ9 33 VSS11 VSS12 34 DDRA_DQ11
DDRA_DQ8 35 DQ10 DQ14 36 DDRA_DQ10
37 DQ11 DQ15 38
DDRA_DQ20 39 VSS13 VSS14 40 DDRA_DQ16
20120727 VA DDRA_DQ21 41 DQ16 DQ20 42 DDRA_DQ17 Layout Note: OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
SWAP DQ for layout 43 DQ17 DQ21 44
DDRA_DQS#2 45 VSS15 VSS16 46 Place near DIMM (10uF_0603_6.3V)*8
DDRA_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDRA_DQ22 (0.1uF_402_10V)*4
DDRA_DQ23 51 VSS18 DQ22 52 DDRA_DQ18 20120727 VA
DDRA_DQ19 53 DQ18 DQ23 54 SWAP DQ for layout
55 DQ19 VSS19 56 DDRA_DQ31
DDRA_DQ25 57 VSS20 DQ28 58 DDRA_DQ29
DDRA_DQ28 59 DQ24 DQ29 60 +1.35V
61 DQ25 VSS21 62 DDRA_DQS#3
63 VSS22 DQS#3 64 DDRA_DQS3
65 DM3 DQS3 66
DDRA_DQ27 67 VSS23 VSS24 68 DDRA_DQ24

10U_0603_6.3V6M

10U_0603_6.3V6M
1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
C DDRA_DQ26 69 DQ26 DQ30 70 DDRA_DQ30 C
71 DQ27 DQ31 72 CD1511 CD1421 CD1431 CD1521 CD1441 CD1451 CD1531 CD1461 CD1541 CD1551 CD1471 CD1561 + CD148
VSS25 VSS26 220U_6.3V_M
2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_CKE0 73 74 DDRA_CKE1
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 76
77 VDD1 VDD2 78 DDRA_MA15
DDRA_BS2# 79 NC1 A15 80 DDRA_MA14
<7> DDRA_BS2# BA2 A14
81 82
DDRA_MA12 83 VDD3 VDD4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD5 VDD6 90 DDRA_MA6 +1.35V +VREF_CA_R
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
VDD7 VDD8

1
DDRA_MA3 95 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
Note:
99 A1 A0 100 RD80 VREF trace width:20 mils at least
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1 1K_0402_1%
<7> DDRA_CLK0
DDRA_CLK0# 103 CK0 CK1 104 DDRA_CLK1# DDRA_CLK1 <7> Spacing:20mils to other signal/planes
<7> DDRA_CLK0# DDRA_CLK1# <7>

2
CK0# CK1#
105
VDD11 VDD12
106 Place near DIMM scoket
DDRA_MA10 107 108 DDRA_BS1# RD89
DDRA_BS0# 109 A10/AP BA1 110 DDRA_RAS# DDRA_BS1# <7> +VREF_CA 2 1
<7> DDRA_BS0# BA0 RAS# DDRA_RAS# <7>
111 112 0_0402_5% 1
DDRA_WE# 113 VDD13 VDD14 114 DDRA_CS0#
<7> DDRA_WE# WE# S0# DDRA_CS0# <7>
DDRA_CAS# 115 116 DDRA_ODT0 CD179 0.1U_0402_10V6K
<7> DDRA_CAS# CAS# ODT0 DDRA_ODT0 <7>

1
117 118
DDRA_MA13 119 VDD15 VDD16 120 DDRA_ODT1 2
A13 ODT1 DDRA_ODT1 <7>

1
DDRA_CS1# 121 122 RD81
<7> DDRA_CS1# S1# NC2
123 124 1K_0402_1% RD88
125 VDD17 VDD18 126 +VREF_CA
+VREF_CA <12>

2
B 127 NCTEST VREF_CA 128 24.9_0402_1% B
VSS27 VSS28
0.1U_0402_10V6K

2.2U_0603_6.3V6K

DDRA_DQ32 129 130 DDRA_DQ38

2
DDRA_DQ33 131 DQ32 DQ36 132 DDRA_DQ34
DQ33 DQ37 1 1
133 134 CD149 CD150
DDRA_DQS#4 135 VSS29 VSS30 136
DDRA_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDRA_DQ39 2 2
DDRA_DQ37 141 VSS32 DQ38 142 DDRA_DQ35
DDRA_DQ36 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRA_DQ45
DDRA_DQ40 147 VSS34 DQ44 148 DDRA_DQ47
DDRA_DQ41 149 DQ40 DQ45 150
DQ41 VSS35 Layout Note: Layout Note:
151 152 DDRA_DQS#5
153 VSS36 DQS#5 154 DDRA_DQS5 Place near DIMM Place near DIMM
20120727 VA 155 DM5 DQS5 156
SWAP DQ for layout DDRA_DQ42 157 VSS37 VSS38 158 DDRA_DQ43
DDRA_DQ44 159 DQ42 DQ46 160 DDRA_DQ46
161 DQ43 DQ47 162
DDRA_DQ52 163 VSS39 VSS40 164 DDRA_DQ49
DDRA_DQ53 165 DQ48 DQ52 166 DDRA_DQ51 20120727 VA +0.675VS
DQ49 DQ53 DDR_A_DM[0:7] connect to GND
167 168 SWAP DQ for layout
DDRA_DQS#6 169 VSS41 VSS42 170
DDRA_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDRA_DQ54
VSS44 DQ54

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRA_DQ48 175 176 DDRA_DQ55
DDRA_DQ50 177 DQ50 DQ55 178
DQ51 VSS45 1 1 1 1
179 180 DDRA_DQ56 CD288 CD158 CD159 CD160
DDRA_DQ61 181 VSS46 DQ60 182 DDRA_DQ57
DDRA_DQ60 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRA_DQS#7 2 2 2 2
187 VSS48 DQS#7 188 DDRA_DQS7
189 DM7 DQS7 190
A DDRA_DQ58 191 VSS49 VSS50 192 DDRA_DQ62 A
DDRA_DQ59 193 DQ58 DQ62 194 DDRA_DQ63
195 DQ59 DQ63 196
1 RD82 2 197 VSS51 VSS52 198
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS 201 VDDSPD SDA 202 SMB_CLK_S3 SMB_DATA_S3 <12,17,40,47>
SA1 SCL SMB_CLK_S3 <12,17,40,47>
1

1 1 203 204
VTT1 VTT2 +0.675VS
CD290 CD162 RD83 205 206 [email protected] Security Classification LC Future Center Secret Data Title
2.2U_0603_6.3V6K 0.1U_0402_10V6K 10K_0402_5% G1 G2
2 2 LCN_DAN06-K4806-0102
Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII SO-DIMM A
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
ME@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 11 of 69
5 4 3 2 1
5 4 3 2 1

+VREF_DQ_DIMMB_R
DDR3 SO-DIMM B
+1.35V
+1.35V +1.35V

1
RD84
DDRB_DQ[0..63] <7>
1K_0402_1% [email protected] DDRB_DQS[0..7] <7>
For RF request
RD93 JDDRL2
DDRB_DQS#[0..7] <7>

2
1 2 +VREF_DQ_DIMMB 1 2
0_0402_5% 3 VREF_DQ VSS1 4 DDRB_DQ0
VSS2 DQ4 DDRB_MA[0..15] <7>

0.047U_0402_16V4Z

0.047U_0402_16V4Z

0.047U_0402_16V4Z
0.1U_0402_10V6K
DDRB_DQ5 5 6 DDRB_DQ1

2.2U_0603_6.3V6K
RD85 DDRB_DQ4 7 DQ0 DQ5 8
1 1 1 DQ1 VSS3 1 1 1
D CD157 9 10 DDRB_DQS#0 CD54 CD55 CD56 D
VSS4 DQS#0

1K_0402_1%
CD181 11 12 DDRB_DQS0 @ @ @
0.1U_0402_10V6K 2 CD289 13 DM0 DQS0 14
2 2 2 DDRB_DQ2 15 VSS5 VSS6 16 DDRB_DQ6 2 2 2
DQ2 DQ6
1

DDRB_DQ3 17 18 DDRB_DQ7
RD92 19 DQ3 DQ7 20
DDRB_DQ13 21 VSS7 VSS8 22 DDRB_DQ8
24.9_0402_1% DDRB_DQ12 23 DQ8 DQ12 24 DDRB_DQ9
25 DQ9 DQ13 26
2

DDRB_DQS#1 27 VSS9 VSS10 28


DDRB_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# <11,6>
DDRB_DQ15 33 VSS11 VSS12 34 DDRB_DQ14
DDRB_DQ11 35 DQ10 DQ14 36 DDRB_DQ10
37 DQ11 DQ15 38
DDRB_DQ20 39 VSS13 VSS14 40 DDRB_DQ17
DDRB_DQ16 41 DQ16 DQ20 42 DDRB_DQ21
43 DQ17 DQ21 44
DDRB_DQS#2 45 VSS15 VSS16 46
DDRB_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDRB_DQ18
DDRB_DQ22 51 VSS18 DQ22 52 DDRB_DQ19 Layout Note: (10uF_0603_6.3V)*8
DDRB_DQ23 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRB_DQ30 Place near DIMM (0.1uF_402_10V)*4
DDRB_DQ28 57 VSS20 DQ28 58 DDRB_DQ31
DDRB_DQ29 59 DQ24 DQ29 60 20120727 VA
61 DQ25 VSS21 62 DDRB_DQS#3 SWAP DQ for layout
63 VSS22 DQS#3 64 DDRB_DQS3
65 DM3 DQS3 66
DDRB_DQ26 67 VSS23 VSS24 68 DDRB_DQ25
DDRB_DQ27 69 DQ26 DQ30 70 DDRB_DQ24 +1.35V
71 DQ27 DQ31 72
C VSS25 VSS26 C

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M
DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0
75 CKE0 CKE1 76 DDRB_CKE1 <7> CD1611 CD2821 CD1631 CD1641 CD1651 CD1661 CD1671 CD1681 CD1691 CD1701 CD1711 CD1721
77 VDD1 VDD2 78 DDRB_MA15
DDRB_BS2# 79 NC1 A15 80 DDRB_MA14
<7> DDRB_BS2# BA2 A14 2 2 2 2 2 2 2 2 2 2 2 2
81 82
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7
87 A9 A7 88
DDRB_MA8 89 VDD5 VDD6 90 DDRB_MA6 20120727 VA
DDRB_MA5 91 A8 A6 92 DDRB_MA4 SWAP DQ for layout
93 A5 A4 94
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1#
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 106
DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
109 A10/AP BA1 110 DDRB_BS1# <7>
DDRB_BS0# DDRB_RAS#
<7> DDRB_BS0# BA0 RAS# DDRB_RAS# <7>
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0#
<7> DDRB_WE# WE# S0# DDRB_CS0# <7>
DDRB_CAS# 115 116 DDRB_ODT0
<7> DDRB_CAS# CAS# ODT0 DDRB_ODT0 <7>
117 118
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
121 A13 ODT1 122 DDRB_ODT1 <7>
<7> DDRB_CS1# DDRB_CS1#
123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128 +VREF_CA <11>
VSS27 VSS28
0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDRB_DQ39 129 130 DDRB_DQ35
B DDRB_DQ33 131 DQ32 DQ36 132 DDRB_DQ37 B
DQ33 DQ37 1 1
133 134 CD280 CD281
DDRB_DQS#4 135 VSS29 VSS30 136
DDRB_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDRB_DQ38 2 2
DDRB_DQ32 141 VSS32 DQ38 142 DDRB_DQ34
DDRB_DQ36 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRB_DQ41
DDRB_DQ44 147 VSS34 DQ44 148 DDRB_DQ47
DQ40 DQ45 Layout Note: Layout Note:
DDRB_DQ45 149 150
151 DQ41 VSS35 152 DDRB_DQS#5 Place near DIMM Place near DIMM
153 VSS36 DQS#5 154 DDRB_DQS5
155 DM5 DQS5 156
DDRB_DQ40 157 VSS37 VSS38 158 DDRB_DQ43
DDRB_DQ42 159 DQ42 DQ46 160 DDRB_DQ46
161 DQ43 DQ47 162
DDRB_DQ53 163 VSS39 VSS40 164 DDRB_DQ54 +0.675VS
DQ48 DQ52 DDR_B_DM[0:7] connect to GND
DDRB_DQ55 165 166 DDRB_DQ52
167 DQ49 DQ53 168 20120727 VA
DDRB_DQS#6 169 VSS41 VSS42 170 SWAP DQ for layout
DDRB_DQS6 171 DQS#6 DM6 172
DQS6 VSS43

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
173 174 DDRB_DQ51
DDRB_DQ49 175 VSS44 DQ54 176 DDRB_DQ50
DQ50 DQ55 1 1 1 1
DDRB_DQ48 177 178 CD173 CD174 CD175 CD176
179 DQ51 VSS45 180 DDRB_DQ61
DDRB_DQ56 181 VSS46 DQ60 182 DDRB_DQ57
DDRB_DQ60 183 DQ56 DQ61 184 2 2 2 2
185 DQ57 VSS47 186 DDRB_DQS#7
187 VSS48 DQS#7 188 DDRB_DQS7
189 DM7 DQS7 190
DDRB_DQ63 191 VSS49 VSS50 192 DDRB_DQ59
DDRB_DQ62 193 DQ58 DQ62 194 DDRB_DQ58
A 195 DQ59 DQ63 196 A
1 RD95 2 197 VSS51 VSS52 198
10K_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
1 2 201 VDDSPD SDA 202 SMB_DATA_S3 <11,17,40,47>
SMB_CLK_S3
+3VS 203 SA1 SCL 204 SMB_CLK_S3 <11,17,40,47>
RD9710K_0402_5% +0.675VS
VTT1 VTT2
1 1
205
G1 G2
206 [email protected]
CD177 CD178 Title
2.2U_0603_6.3V6K 0.1U_0402_10V6K FOX_AS0A621-U4SG-7H Security Classification LC Future Center Secret Data
2 2
Issued Date 2012/07/01 Deciphered Date 2014/07/01 DDRIII SO-DIMM B
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 12 of 69
5 4 3 2 1
5 4 3 2 1

Place JUMPER under RAM door LPT_PCH_M_EDS


UHA
CMOS
BC8
+RTCVCC PCH_RTCX1 B5 REV = 5 SATA_RXN_0 BE8
1 RTCX1 SATA_RXP_0

1
CH202
1U_0603_10V4Z @ JME1 PCH_RTCX2 B4 AW8
SHORT PADS RTCX2 SATA_TXN_0 AY8

RTC
2
RH1481 2 20K_0402_5% 2 PCH_SRTCRST# B9 SATA_TXP_0
D SRTCRST# BC10 D
SM_INTRUDER#A8 SATA_RXN_1 BE10
INTRUDER# SATA_RXP_1
G10
PCH_INTVRMEN AV10
INTVRMEN SATA_TXN_1 AW10
RH1461 2 20K_0402_5% PCH_RTCRST# D9 SATA_TXP_1
RTCRST#

SATA
1 BB9 SATA_PRX_DTX_N2 ODD
SATA_RXN_2 SATA_PRX_DTX_N2 <44>

1
CH229 JCMOS2 BD9 SATA_PRX_DTX_P2
SATA_RXP_2 SATA_PRX_DTX_P2 <44>
1U_0603_10V4Z @ SHORT PADS HDA_BIT_CLK B25
HDA_BCLK AY13 SATA_PTX_DRX_N2 CH1862 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N2
SATA_PTX_C_DRX_N2 <44>

2
2 HDA_SYNC A22 SATA_TXN_2 AW13 SATA_PTX_DRX_P2 CH1872 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P2
HDA_SYNC SATA_TXP_2 SATA_PTX_C_DRX_P2 <44>
HDA_SPKR AL10 BC12
<45> HDA_SPKR SPKR SATA_RXN_3 BE12
HDA_RST# C24 SATA_RXP_3
HDA_RST# AR13
SATA_TXN_3 SATA_PTX_DRX_N0 <40>
L22 AT13

AZALIA
@ HDA_SDIN0 SATA_PTX_DRX_P0 <40>
RH121 <45> HDA_SDIN0 HDA_SDI0 SATA_TXP_3
1 2 K22
+3VS HDA_SDI1
10K_0402_5% BD13 SATA_PRX_DTX_N0 SSD
SATA_RXN4/PERN1 SATA_PRX_DTX_N0 <40>
G22 BB13 SATA_PRX_DTX_P0
HDA_SDI2 SATA_RXP4/PERP1 SATA_PRX_DTX_P0 <40>
CRT_SWITCH_1 RH110 1 2 0_0402_5% PCH_GPIO33 @
<37> CRT_SWITCH_1
F22 AV15 SATA_PTX_DRX_N0 CH1842 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N0
HDA_SDI3 SATA_TXN4/PETN1 SATA_PTX_C_DRX_N0 <40>
AW15 SATA_PTX_DRX_P0 CH1852 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_P0 <40>
ME_FLASH RH109 1 2 R_short 0_0402_5% HDA_SDOUT A24 SATA_TXP4/PETP1 @
<46> ME_FLASH HDA_SDO BC14 SATA_PRX_DTX_N1
SATA_RXN5/PERN2
HDD SATA_PRX_DTX_N1 <44>
RH1071 @ 2 1K_0402_1% PCH_GPIO33 B17 BE14 SATA_PRX_DTX_P1
SATA_PRX_DTX_P1 <44>
DOCKEN#/GPIO33 SATA_RXP5/PERP2
+3V_PCH RH3172 @ 1 10K_0402_5% PCH_GPIO13 C22 AP15 SATA_PTX_DRX_N1 CH2732 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1
+3V_PCH HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_PTX_C_DRX_N1 <44>
AR15 SATA_PTX_DRX_P1 CH2722 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P1
SATA_TXP5/PETP2 SATA_PTX_C_DRX_P1 <44>
1
0_0603_5%
RH288

C AY5 SATA_COMP C
@ SATA_RCOMP
AP3 HDD_LED# RH1202 1 10K_0402_5%
SATALED# +3VS
2

RH59 2 @ 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 PCH_GPIO21 RH1192 1 10K_0402_5%


+3VS
JTAG_TCK SATA0GP/GPIO21 HDD_LED# <51>
+3.3V_ALW_PCH_JTAG RH44 1 @ 2 210_0402_1% PCH_JTAG_TMS AD1 AU2 SATA_DET# RH3162 1 10K_0402_5%
+3VS
JTAG_TMS SATA1GP/GPIO19
RH45 1 @ 2 210_0402_1% PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1

JTAG
JTAG_TDI SATA_IREF +1.5VS SATA_DET# <40>
0_0402_5% RH41
RH46 1 @ 2 210_0402_1% PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9 PAD T161 @
1 @ 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%

100_0402_1%

100_0402_1%

RH1508 0_0402_5% PAD T155 @


1

C26
TP22
RH48

RH49

RH47

@ T108 PAD W=20mils W=20mils


@ @ @ AB6
@ T109 PAD TP20 +RTCBATT +RTCVCC
RH99 1
2

2
LYNXPOINT_BGA695 1 OF 11 1
1K_0402_5%
CH179
1U_0603_10V4Z
2

PCH_RTCX1

1 RH145 2 PCH_RTCX2
+RTCVCC
10M_0402_5% SATA Impedance Compensation
B Y3 RH1491 2 1M_0402_5% SM_INTRUDER# B
1 2 +3VS +1.5VS
RH1501 2 330K_0402_5% PCH_INTVRMEN
32.768KHZ_12.5PF_CM31532768DZFT RH1051 @ 2 1K_0402_5% HDA_SPKR SATA_COMP 1 2
1 1 7.5K_0402_1% RH40
INTVRMEN HIGH= Enable ( No Reboot )
：：Integrated
CH189 CH188
LOW= Disable (Default) CAD note:
18P_0402_50V8J 18P_0402_50V8J
H VRM enable (Default) *
2 2 * L Integrated VRM disable
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
(INTVRMEN should always be pull high.)

<Intel update spec>


If RH1509 = stuff
RH1353 = @
QH10 = @
HDA AUDIO RH108 = @
+5VS +3V_PCH
+3V_PCH
<45> HDA_BITCLK_AUDIO RH1121 2 HDA_BIT_CLK QH10 RH1082 1 1K_0402_5% HDA_SYNC
2
G

33_0402_5% BSS138_NL_SOT23-3 RH1062 @ 1 1K_0402_5% HDA_SDOUT


This signal has a weak internal pull-down
RH1141 2 HDA_SYNC_R 3 1 HDA_SYNC Low = Disabled (Default)
<45> HDA_SYNC_AUDIO
33_0402_5% *
S

On Die PLL VR Select is supplied by High = Enabled


1

RH1161 2 HDA_RST# 1 @ 2 1.5V when smapled high (Default) [Flash Descriptor Security Overide]
<45> HDA_RST_AUDIO#
33_0402_5% RH1509 0_0402_5% * 1.8V when sampled low
RH1353 Needs to be pulled High for Chief River platfrom
<45> HDA_SDOUT_AUDIO RH1181 2 HDA_SDOUT 1M_0402_5%
2

A 33_0402_5% A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (1/9) SATA,HDA,SPI, LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 13 of 69

5 4 3 2 1
5 4 3 2 1

+3VS

RH8501 2 2.2K_0402_5% PCH_CRT_DDC_CLK

D RH8511 2 2.2K_0402_5% PCH_CRT_DDC_DAT D

150_0402_1% 2 RH339 1 PCH_CRT_B

150_0402_1% 2 RH340 1 PCH_CRT_G

150_0402_1% 2 RH341 1 PCH_CRT_R

20120829 VA1
Add net for add CRT MUX +3VS
PPT EDS DOC#474146
LPT_PCH_M_EV 1 2
UHE REV = 5 RH314 @ 8.2K_0402_5% PCH_GPIO51

PCH_CRT_B T45 R40 DDPB_CLK RH318 1 @ 2 8.2K_0402_5% DGPU_GC6_EN


<37> PCH_CRT_B VGA_BLUE DDPB_CTRLCLK DDPB_CLK <37>
PCH_CRT_G U44 R39 DDPB_DATA RH313 1 2 8.2K_0402_5% PIRQH#
<37> PCH_CRT_G VGA_GREEN DDPB_CTRLDATA DDPB_DATA <37>
PCH_CRT_R V45 R35 RH312 1 2 8.2K_0402_5% PCH_WL_OFF#
<37> PCH_CRT_R VGA_RED DDPC_CTRLCLK 20120829 VA1
<37> PCH_CRT_DDC_CLK PCH_CRT_DDC_CLK M43 R36 Add net for add HDMI MUX RH320 1 2 8.2K_0402_5% CRT_DET#_R
VGA_DDC_CLK DDPC_CTRLDATA
<37> PCH_CRT_DDC_DAT PCH_CRT_DDC_DAT M45 N40 RH311 1 2 8.2K_0402_5% DGPU_HOLD_RST#

CRT
VGA_DDC_DATA DDPD_CTRLCLK
PCH_CRT_HSYNC N42 N38 RH323 1 2 8.2K_0402_5% PCI_PIRQC#
<37> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA
PCH_CRT_VSYNC N44 RH324 1 2 8.2K_0402_5% PCH_GPIO2
<37> PCH_CRT_VSYNC VGA_VSYNC H45
2 RH302 1 CRT_IREF U40 DDPB_AUXN RH325 2 1 10K_0402_5% DGPU_PWR_EN
649_0402_1% DAC_IREF K43
U39 DDPC_AUXN

DISPLAY
VGA_IRTN J42
C DDPD_AUXN C
PCH_EDP_PWM N36 H43 @
<35> PCH_EDP_PWM EDP_BKLTCTL DDPB_AUXP 1 2
RH310 8.2K_0402_5% DGPU_GC6_EN

LVDS
PCH_ENBKL K36 K45
<35> PCH_ENBKL EDP_BKLTEN DDPC_AUXP 1 2 DGPU_HOLD_RST#
RH315 @ 8.2K_0402_5%
PCH_ENVDD G36 J44
<35> PCH_ENVDD EDP_VDDEN DDPD_AUXP
K40 TMDS_B_HPD
PCI_PIRQA# H20 DDPB_HPD TMDS_B_HPD <37>
PIRQA# K38
PCI_PIRQB# L20 DDPC_HPD
PIRQB# H39
PCI_PIRQC# K17 DDPD_HPD
PIRQC#
PCI_PIRQD# M20 RH308 2 @ 1 1K_0402_5% PCH_WL_OFF#
PIRQD# PCI G17 PCH_GPIO2
1 2 PCH_DGPU_HOLD_RST# A12 PIRQE#/GPIO2
<23,54> DGPU_HOLD_RST# GPIO50 F17 ODD_DA#_R
RH1519 0_0402_5%
1 2 NVDD_PWR_EN_R B13 PIRQF#/GPIO3 ODD_DA#_R <44>
NVDD_PWR_EN
<54,63> NVDD_PWR_EN GPIO52 L15 CRT_DET#_R 1 2 CRT_DET#
RH1526 0_0402_5% A16 swap overide Strap/Top-Block
DGPU_PWR_EN 1 2 DGPU_PWR_EN_R C12 PIRQG#/GPIO4 CRT_DET# <36>
RH1522 0_0402_5%
<23,54,55> DGPU_PWR_EN GPIO54 M15 Swap Override jumper
RH1525 0_0402_5% PIRQH#
PCH_GPIO51 C10 PIRQH#/GPIO5
GPIO51 AD10 @ T114 PAD
DGPU_GC6_EN A10 PME#
<27,54> DGPU_GC6_EN GPIO53 Low = A16 swap
Y11 PLT_RST#
PCH_WL_OFF# AL6 PLTRST# PLT_RST# <23,32,40,41,46> override/Top-Block
<40> PCH_WL_OFF# GPIO55 PCI_GNT3#
Swap Override enabled
LYNXPOINT_BGA695 5 OF 11

B
***High=Default B
PLT_RST#

1
RH301
100K_0402_5%

2
PCH_GPIO51 RH307 1 @ 2 1K_0402_5%

+3VS
RPH5
8 1 PCI_PIRQD#
7 2 PCI_PIRQA# Boot BIOS Strap
6 3 ODD_DA#_R
5 4 PCI_PIRQB# BBS_BIT1 SATA_SLPD
8.2K_0804_8P4R_5% SWAP (GPIO51) (BBS_BIT0) Boot BIOS Location

0 0 LPC

0 1 Reserved (NAND)
ODD_DA#_R
1 0 PCI
For ESD 1
A @ CC63 A
220P_0402_25V8J
2 * 1 1 SPI

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 14 of 69
5 4 3 2 1
5 4 3 2 1

+3VS
+RTCVCC
+3V_PCH
1

1
CH1071
0.1U_0402_16V4Z RH189
D 330K_0402_5% D
RH202 2 1 10K_0402_5% SUSWARN# 2

2
5
+3VALW VGATE 2 DSWODVREN

P
<6,64> VGATE B 4
2 1 1 Y SYS_PWROK <6>
RH222 200K_0402_5% PCH_AC_PRESENT_R PCH_PWROK
A

1
* ：
DSWODVREN - On Die DSW VR Enable RH291

3
：
UH7 @ RH182 H Enable @ 330K_0402_5%
MC74VHC1G08DFT2G SC70 5P 100K_0402_1%
L Disable

2
PCH_PWROK

1
RH203
10K_0402_5%
For Intel checklist V0.5

2
LPT_PCH_M_EDS
UHB REV = 5

<5> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0AW22


DMI_CTX_PRX_N1AR20 DMI_RXN_0
<5> DMI_CTX_PRX_N1 DMI_RXN_1 AJ35 FDI_CTX_PRX_N0
FDI_RXN_0 FDI_CTX_PRX_N0 <8>
DMI_CTX_PRX_N2AP17
<5> DMI_CTX_PRX_N2 DMI_RXN_2
DMI_CTX_PRX_N3AV20 AL35 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <8>
DMI_CTX_PRX_P0AY22 AJ36 FDI_CTX_PRX_P0
C <5> DMI_CTX_PRX_P0 DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P0 <8> C
DMI_CTX_PRX_P1AP20
<5> DMI_CTX_PRX_P1 DMI_RXP_1 FDI AL36 FDI_CTX_PRX_P1 PCH_DPWROK_R
FDI_RXP_1 FDI_CTX_PRX_P1 <8>
<5> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2AR17
DMI_RXP_2

1
DMI_CTX_PRX_P3AW20 DMI AV43 PAD T144 @
<5> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 For Intel checklist V0.6
DMI_CRX_PTX_N0BD21 AY45 PAD T141 @ RH184
<5> DMI_CRX_PTX_N0 DMI_CRX_PTX_N1BE20 DMI_TXN_0 TP5 100K_0402_1%
<5> DMI_CRX_PTX_N1 DMI_TXN_1 AV45 PAD T147 @

2
DMI_CRX_PTX_N2BD17 TP15
<5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3BE18 DMI_TXN_2 AW44 PAD T148 @
<5> DMI_CRX_PTX_N3 DMI_TXN_3 TP10
DMI_CRX_PTX_P0BB21 AL39 FDI_CSYNC
<5> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <5>
DMI_CRX_PTX_P1BC20
<5> DMI_CRX_PTX_P1 DMI_TXP_1 AL40 FDI_INT
DMI_CRX_PTX_P2BB17 FDI_INT FDI_INT <5>
<5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P3BC18 DMI_TXP_2 AT45 FDI_IREF 2 1
<5> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF +1.5VS
0_0402_5% RH42
2 1 DMI_IREF BE16 AU42 PAD T145 @ +3VS
+1.5VS DMI_IREF TP17
RH43 0_0402_5%
AW17 AU44 PAD T146 @
@ T139 PAD TP12 TP13
AV17 AR44 FDI_RCOMP 2 1 PM_CLKRUN# 8.2K_0402_5% 2 RH185 1
TP7 FDI_RCOMP +1.5VS
@ T111 PAD 7.5K_0402_1% RH206
1 2 DMI_RCOMP AY17
+1.5VS DMI_RCOMP
RH204 7.5K_0402_1%
For Deep S3

<46> SUSACK# RH1488 2 1 R_short 0_0402_5% SUSACK#_R R6 C8 DSWODVREN


SUSACK# DSWVRMEN
2 1 AM1 System Power L13 1 2 R_short 0_0402_5%
RH188 10K_0402_5% SYS_RESET# PCH_DPWROK_R RH292 DPWROK_EC For Deep S3
+3VS SYS_RESET# Management DPWROK DPWROK_EC <46>
SYS_PWROK AD7 K3 WAKE# RH294 1 2 R_short 0_0402_5% PCIE_WAKE#
B SYS_PWROK WAKE# PCIE_WAKE# <19,40,41> B
note need connect to GPIO27
RH196 1 2 PWROK F10 AN7 PM_CLKRUN#
<46> PCH_PWROK PWROK CLKRUN#
R_short 0_0402_5%
APWROK can be connect to RH1510 1 2 APWROK AB7 U7 SUS_STAT#
APWROK SUS_STAT#/GPIO61 PAD T66
PWROK if iAMT disable R_short 0_0402_5%
PM_DRAM_PWRGD H3 Y6 SUSCLK
<6> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 PAD T67
RH1511 1 2 R_short 0_0402_5% PCH_RSMRST#_R J2 Y7 PM_SLP_S5#
<46> EC_RSMRST# RSMRST# SLP_S5#/GPIO63 PAD T68
RH1489 1 2 R_short 0_0402_5% SUSWARN#_R J4 C6 PM_SLP_S4#
<46> SUSWARN# SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# <46>
For Deep S3
<6> SIO_PWRBTN#_R
<46> PBTN_OUT# RH1512 1 2 R_short 0_0402_5% K1 H1 PM_SLP_S3#
PWRBTN# SLP_S3# PM_SLP_S3# <46>
RH234 1 2R_short 0_0402_5%PCH_AC_PRESENT_R E6 F3 Can be left NC when IAMT is not support on the platfrom
<46> AC_PRESENT ACPRESENT/GPIO31 SLP_A#
RH246 1 2 8.2K_0402_5% PCH_GPIO72 K7 F1 PM_SLP_SUS#_R RH1456 2 1 R_short 0_0402_5% For Deep S3
+3VALW BATLOW#/GPIO72 SLP_SUS# PM_SLP_SUS# <46,55>
RH290 2 1 10K_0402_5% RI# N4 AY3 H_PM_SYNC
+3V_PCH RI# PMSYNCH H_PM_SYNC <6>
@ T140 PAD AB10 G5 PCH_GPIO29
TP21 SLP_LAN# PAD T110
D2 Can be left NC if no use integrated LAN.
<38> EDP_SEL SLP_WLAN#/GPIO29 Add one to +3VALW next Rev.
10/06 Test point request
LYNXPOINT_BGA695 4 OF 11
+3V_PCH

WAKE# RH1871 2 10K_0402_5%

RH319 2 1 10K_0402_5% PCH_RSMRST#_R


A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (3/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 15 of 69
5 4 3 2 1
5 4 3 2 1

LPT_PCH_M_EDS
UHC REV = 5

D Y43 AB35 CLK_PCIE_VGA# D


CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_VGA# <23>
Y45 AB36 CLK_PCIE_VGA
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <23>
CLK_REQ_GPU#_R <23>
PCH_GPIO73 AB1 AF6 CLK_REQ_GPU#_R RH1513 1 2 10K_0402_5%
PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 +3V_PCH
AA44 Y39 CLK_PCIE_2VGA#
AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B CLK_PCIE_2VGA# <32>
CLKOUT_PCIE_P_1 2nd VGA
Y38 CLK_PCIE_2VGA
AF1 CLKOUT_PEG_B_P CLK_PCIE_2VGA <32>
PCH_GPIO18 CLK2_REQ_GPU#_R <32>
PCIECLKRQ1#/GPIO18 U4 CLK2_REQ_GPU#_R RH170 1 2 10K_0402_5%
PEGB_CLKRQ#/GPIO56 +3V_PCH
AB43
CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
AB45 CLKOUT_DMI CLK_CPU_DMI# <6>
CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI
CLKREQ_TV#_R AF3 CLKOUT_DMI_P CLK_CPU_DMI <6>
PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
CLK_PCIE_LAN#AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <6>
<41> CLK_PCIE_LAN# CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <6>
LAN CLK_PCIE_LAN AD45
<41> CLK_PCIE_LAN CLKREQ_LAN# T3 CLKOUT_PCIE_P_3 AF35 CLK_CPU_DPLL#
<41> CLKREQ_LAN# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL# <6>
CLK_PCIE_WLAN#AF43 CLKOUT_DPNS_P CLK_CPU_DPLL <6>
<40> CLK_PCIE_WLAN# CLK_PCIE_WLAN AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_CPU_DMI# RPH1
WLAN <40> CLK_PCIE_WLAN CLKOUT_PCIE_P_4 CLKIN_DMI
<40> WLAN_CLKREQ1# WLAN_CLKREQ1# V3 AW24 CLK_BUF_CPU_DMI CLKIN_DMI2# 4 5
PCIECLKRQ4#/GPIO26 CLKIN_DMI_P CLKIN_DMI2 3 6
AE44 AR24 CLKIN_DMI2# CLK_BUF_CPU_DMI# 2 7
AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLKIN_DMI2 CLK_BUF_CPU_DMI 1 8
PCH_GPIO44 AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DREF_96M# RH1621 2 10K_0402_5%
AB40 CLKIN_DOT96N G33 CLK_BUF_DREF_96M RH1631 2 10K_0402_5% 10K_0804_8P4R_5%
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
PCH_GPIO45 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_PCIE_SATA# RH1641 2 10K_0402_5%
C PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_PCIE_SATA RH1661 2 10K_0402_5% C
AJ44 CLKIN_SATA_P
CLKOUT_PCIE_N_7 F45 CLK_BUF_ICH_14M RH1671 2 10K_0402_5%
AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
PCH_GPIO46 Y3 AL44 XTAL25_IN
PCIECLKRQ7#/GPIO46 XTAL25_IN AM43 XTAL25_OUT
RH280 2 1 0_0402_5% CLK_BCLK_ITP#AH43 XTAL25_OUT
<6> CLK_CPU_ITP# CLKOUT_ITPXDP C40 EDP_AUX_SEL <38> +3VS
CLKOUTFLEX0/GPIO64 S_DGPU_PWROK <32,54>
RH281 2 1 0_0402_5% CLK_BCLK_ITP AH45
<6> CLK_CPU_ITP CLKOUT_ITPXDP_P F38 RH1505 1 2 R_short 0_0402_5% RH1832 1 10K_0402_5%
D44 CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0 F36 S_DGPU_RST_R RH1504 1 2 R_short 0_0402_5%
1 2 CLKOUTFLEX2/GPIO66 S_DGPU_RST <32,54>
RH253 22_0402_5% CLK_PCI_EC_R E44
<46> CLK_PCI_EC CLKOUT_33MHZ1 F39 PCH_GPIO67
RH174 2 1 22_0402_5% CLK_PCI_DB_R B42 CLKOUTFLEX3/GPIO67 PCH_GPIO67 <19> BIOS Request SKU ID
<40> CLK_PCI_DB CLKOUT_33MHZ2 AM45 ICLK_IREF 1 2
@ +1.5VS
F41 ICLK_IREF 0_0402_5% RH54
CLKOUT_33MHZ3 AD39
TP19 GPIO64, 65 that only for GC6
CLK_PCI_LOOPBACK RH1514 2 1 22_0402_5% PCI_LOOPBACKOUT A40 AD38 PAD T149 @
CLKOUT_33MHZ4 TP18 PAD T150 @ 1. GPIO64 : S_DGPU_GC6_EN
AN44 PCH_CLK_BIASREF 1 2 2. GPIO65 : S_DGPU_PWROK
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
CLOCK SIGNAL 7.5K_0402_1% RH208

LYNXPOINT_BGA695 2 OF 11

+3V_PCH

B B
RH1522 1 10K_0402_5% PCH_GPIO73
Change C196, C197 value of Cap
RH1682 1 10K_0402_5% CLKREQ_LAN# from 33pF to 10pF for TXC recommend
RH1652 1 10K_0402_5% WLAN_CLKREQ1#

RH1472 1 10K_0402_5% PCH_GPIO44 XTAL25_IN

1 RH169 2
XTAL25_OUT
1M_0402_5%
RH1722 1 10K_0402_5% PCH_GPIO45

RH1772 1 10K_0402_5% PCH_GPIO46 Y2

Reserve for EMI please close to 1 3


1 3
+3VS
PCH GND GND
1 1
CH196 CH197
2 4
RH1582 1 10K_0402_5% PCH_GPIO18 12P_0402_50V8F 25MHZ_10PF_7V25000014 12P_0402_50V8F
2 2
RH3292 1 10K_0402_5% CLKREQ_TV#_R

@RH176
@ RH176 @CH199
@ CH199
33_0402_5% 22P_0402_50V8J
CLK_PCI_LOOPBACK 2 1 1 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (3/9) DMI, FDI, PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 16 of 69
5 4 3 2 1
5 4 3 2 1

D D
LPT_PCH_M_EDS
UHD
+3V_PCH
EC and Mini card debug port
N7 PCH_GPIO11
LPC_AD0 A20 SMBALERT#/GPIO11 PCH_GPIO11 2 RH134 1
10K_0402_5%
<40,46> LPC_AD0 LAD_0 R10 PCH_SMBCLK
SMBus
LPC_AD1 C20 SMBCLK DRAMRST_CNTRL_PCH 2 RH335 1 10K_0402_5%
<40,46> LPC_AD1 LAD_1 U11PCH_SMBDATA
LPC_AD2 A18 SMBDATA SML0CLK 1 RH336 2 10K_0402_5%

LPC
<40,46> LPC_AD2 LAD_2 N8
LPC_AD3 C18 SML0ALERT#/GPIO60 DRAMRST_CNTRL_PCH <6> SML0DATA 1 RH337 2 10K_0402_5%
<40,46> LPC_AD3 LAD_3 U8 SML0CLK
LPC_FRAME# B21 SML0CLK PCH_HOT# 2 RH140 1
10K_0402_5%
<40,46> LPC_FRAME# LFRAME# R7 SML0DATA
D21 SML0DATA
LDRQ0# H6 PCH_HOT#
G20 SML1ALERT#/PCHHOT#/GPIO74
<46> SERIRQ LDRQ1#/GPIO23 K6 SML1CLK
1 2 SERIRQ AL11 SML1CLK/GPIO58
+3VS SERIRQ
10K_0402_5% RH104 N11SML1DATA
SML1DATA/GPIO75

SPI_CLK_PCH_0 RH3311 2 33_0402_5% AF11


SPI_CLK_PCH_1_R RH3321 2 33_0402_5% SPI_CLK_PCH AJ11 CL_CLK

SPI
SPI_CLK AF10
SPI_SB_CS0#_R 2 RH130 1 R_short 0_0402_5% SPI_SB_CS0# AJ7 C-Link CL_DATA
SPI_CS0# AF7
SPI_CS1#_R 2 RH333 1 R_short 0_0402_5% SPI_CS1# AL7 CL_RST#
SPI_CS1#
AJ10
C SPI_SI_R RH1331 2 33_0402_5% SPI_CS2# BA45 PAD T118 @ C
SPI_SI_R1 RH2051 2 33_0402_5% SPI_SI AH1 TP1
SPI_MOSI BC45 PAD T119 @
SPI_SO_L RH1312 1 33_0402_5% SPI_SO_R AH3 Thermal TP2
SPI_SO_L1 RH3342 1 33_0402_5% SPI_MISO BE43 PAD T120 @
AJ4 TP4
SPI_IO2 BE44 PAD T121 @
AJ2 TP3
SPI_IO3 AY43 1
PCH_TD_IREF 2
TD_IREF RH322 8.2K_0402_1%

LYNXPOINT_BGA695 3 OF 11 REV = 5

+3VS VGA, EC, Thermal Sensor

SPI_CS1#_R
<46> SPI_CS1#_R +3VS
1 RH136 2 2N7002KDWH 2 RH137 1
+3V_PCH 2.2K_0402_5% 2.2K_0402_5%
SPI_SI_R1 Vth= min 1V, max 2.5V

2
<46> SPI_SI_R1 1 RH135 2 ESD 2KV 2 RH138 1
2.2K_0402_5% 2.2K_0402_5%

G
SPI_SO_L1
<46> SPI_SO_L1 PCH_SMBCLK 6 1 SMB_CLK_S3
SMB_CLK_S3 <11,12,40,47>

D
5

S
SPI_CLK_PCH_1 RH338 2 1 0_0402_5% SPI_CLK_PCH_1_R QH162A

G
<46> SPI_CLK_PCH_1
2N7002KDWH_SOT363-6
@
PCH_SMBDATA 3 4 SMB_DATA_S3
B SMB_DATA_S3 <11,12,40,47> B
QH162B

S
2N7002KDWH_SOT363-6

For EMI For EMI DIMM1, DIMM2, Mini CARD, TP


RH111 10_0402_5% RH115 10_0402_5%
SPI_CLK_PCH_0 1 2 SPI_CLK_PCH_1_R 1 2
1 RH141 2
@ 1 @ 1 +3V_PCH 2.2K_0402_5% +3VS

2
1 RH142 2
@ CH190 @ CH200 2.2K_0402_5%

G
+3VS 16Mb Flash ROM +3VS 32Mb Flash ROM
2 2
SML1CLK 6 1 EC_SMB_CK2
EC_SMB_CK2 <23,32,34,36,43,46>
RH1271 2 3.3K_0402_5% SPI_WP# 10P_0402_50V8J RH3301 2 3.3K_0402_5% SPI_WP#_1 10P_0402_50V8J

D
5

S
RH1291 2 3.3K_0402_5% SPI_HOLD# RH2571 2 3.3K_0402_5% SPI_HOLD#_1 QH61A

G
2N7002KDWH_SOT363-6
+3VS +3VS
UH52 UH53 SML1DATA 3 4 EC_SMB_DA2
1 8 1 8 EC_SMB_DA2 <23,32,34,36,43,46>
SPI_SB_CS0#_R SPI_CS1#_R QH61B

D
1 1

S
SPI_SO_L 2 CS# VCC 7 SPI_HOLD# /CS VCC 2N7002KDWH_SOT363-6
SPI_WP# 3 DO HOLD# 6 SPI_CLK_PCH_0 CH191 SPI_SO_L1 2 7 SPI_HOLD#_1 CH275
4 WP# CLK 5 SPI_SI_R 0.1U_0402_16V4Z DO /HOLD 0.1U_0402_16V4Z
GND DI 2 SPI_WP#_1 3 6 SPI_CLK_PCH_1_R 2
W25Q16DVSSIQ_SO8 /WP CLK
4 5 SPI_SI_R1
GND DIO

W25Q32FVSSIQ_SO8
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (4/9) LVDS, CRT,DP,HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 17 of 69
5 4 3 2 1
5 4 3 2 1

D D

LPT_PCH_M_EDS
UHI

USB30_RX_N5 AW31 B37 USB20_N0


<49> USB30_RX_N5 USB30_RX_P5 AY31 PERN1/USB3RN3 USB2N0 D37 USB20_P0 USB20_N0 <35>
<49> USB30_RX_P5 PERP1/USB3RP3 USB2P0 A38 USB20_N1 USB20_P0 <35> Camera
USB2N1 USB20_N1 <50>
USB30_TX_N5 BE32 C38 USB20_P1
<49> USB30_TX_N5 USB30_TX_P5 BC32 PETN1/USB3TN3 USB2P1 A36 USB20_N2
USB20_P1 <50> RIGHT USB 1 (SUB/B)
<49> USB30_TX_P5 PETP1/USB3TP3 USB2N2 C36 USB20_P2 USB20_N2 <49>
USB30_RX_N6 AT31 USB2P2 A34 USB20_N3 USB20_P2 <49> LEFT USB
<48> USB30_RX_N6 USB30_RX_P6 AR31 PERN2/USB3RN4 USB2N3 C34 USB20_P3 USB20_N3 <49>
<48> USB30_RX_P6 PERP2/USB3RP4 USB2P3 B33 USB20_N4
USB20_P3 <49> LEFT USB
USB30_TX_N6 BD33 USB2N4 D33 USB20_P4 USB20_N4 <48>
<48> USB30_TX_N6 USB30_TX_P6 BB33 PETN2/USB3TN4 USB2P4 F31 USB20_P4 <48> Card reader
<48> USB30_TX_P6 PETP2/USB3TP4 USB2N5 G31
USB2P5
Some PCH config not support USB port 6 & 7.
K31
AW33 USB2N6 L31
AY33 PERN_3 USB2P6 G29
PERP_3 USB2N7 H29
BE34 USB2P7 A32 USB20_N8
BC34 PETN_3 USB2N8 C32 USB20_P8 USB20_N8 <50> Touch panel
PETP_3 USB2P8 A30 USB20_P8 <50>
PAD T180 @
PCIE_PRX_DTX_N4 AT33 USB2N9 C30
<41> PCIE_PRX_DTX_N4 PERN_4 USB2P9
PAD T181 @ Debug port, reserved test point
PCIE_PRX_DTX_P4 AR33 B29 USB20_N10
<41> PCIE_PRX_DTX_P4 PERP_4 USB2N10 USB20_N10 <40>
D29 USB20_P10
C
LAN CH192 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 BE36 USB2P10 A28 USB20_P10 <40> WLAN C
<41> PCIE_PTX_C_DRX_N4 PETN_4 USB2N11
CH193 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BC36 C28
<41> PCIE_PTX_C_DRX_P4 PETP_4 USB2P11 G26

PCIe
PCIE_PRX_DTX_N5 AW36 USB2N12 F26
<40> PCIE_PRX_DTX_N5

USB
PCIE_PRX_DTX_P5 AV36 PERN_5 USB2P12 F24
<40> PCIE_PRX_DTX_P5 PERP_5 USB2N13
WLAN G24
CH194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N5 BD37 USB2P13
<40> PCIE_PTX_C_DRX_N5 PETN_5
CH195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P5 BB37
<40> PCIE_PTX_C_DRX_P5 PETP_5 AR26
USB3RN1
AY38
AW38 PERN_6 USB3RP1
AP26
BE24
USB3.0
PERP_6 USB3TN1 BD23
BC38 USB3TP1 AW26 USB30_RX_N2
PETN_6 USB3RN2 USB30_RX_N2 <49> Port1
BE38 AV26 USB30_RX_P2
PETP_6 USB3RP2 BD25 USB30_TX_N2 USB30_RX_P2 <49>
AT40 USB3TN2 BC24 USB30_TX_P2 USB30_TX_N2 <49>
PERN_7 USB3TP2 USB30_TX_P2 <49> Port2 LEFT USB
AT39 AW29
PERP_7 USB3RN5 AV29
BE40 USB3RP5 BE26
PETN_7 USB3TN5 Port5 LEFT USB
BC40 BC26
PETP_7 USB3TP5 AR29
AN38 USB3RN6 AP29
PERN_8 USB3RP6 Port6 Card reader
AN39 BD27
PERP_8 USB3TN6 BE28
BD42 USB3TP6
BD41 PETN_8 K24 USBRBIAS 1 RH218 2
PETP_8 USBRBIAS# K26
USBRBIAS Within 500 mils 22.6_0402_1%
1 2 PCH_PCIE_IREF BE30 M33 PAD T122 @ +3V_PCH
+1.5VS PCIE_IREF TP24
RH51 0_0402_5% L33 PAD T123 @
TP23 RPH3
@ T124 PAD BC30 P3 USB_OC0# USB_OC5# 4 5
B TP11 OC0#/GPIO59 V1 USB_OC0# <50> 3 6 B
USB_OC1# USB_OC2#
OC1#/GPIO40 U2 USB_OC2# USB_OC1# <49> USB_OC7# 2 7
@ T125 PAD BB29 OC2#/GPIO41 P1 USB_OC3# USB_OC0# 1 8
TP6 OC3#/GPIO42 M3 USB_OC4#
OC4#/GPIO43 T1 USB_OC5# 10K_1206_8P4R_5%
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6#
+1.5VS PCIE_RCOMP OC6#/GPIO10
RH210 7.5K_0402_1% M1 USB_OC7#
OC7#/GPIO14
RPH4
LYNXPOINT_BGA695 9 OF 11 REV = 5 USB_OC6# 4 5
USB_OC1# 3 6
USB_OC4# 2 7
USB_OC3# 1 8

10K_1206_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (5/9) PCI, USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 18 of 69
5 4 3 2 1
5 4 3 2 1

Function PCH_GPIO38 PCH_GPIO67 PCH_GPIO70


CMOS_ON# 1 2 PCH_GPIO68
<35> CMOS_ON#
RH156 0_0402_5%
X
@
0_0402_5% 2 1 RH225 GC6_EVENT#_R
<23,54> GC6_EVENT# X
RH233 1 2 10K_0402_5%
+3VS X
LPT_PCH_M_EDS
UHF
D AT8
Reserve 1 1 X D
BMBUSY#/GPIO0
RH227 1 2 10K_0402_5% PCH_GPIO1 F13
TACH1/GPIO1 14" X X 0
RH228 1 2 10K_0402_5% PCH_GPIO6 A14
+3VS TACH2/GPIO6
CPU/Misc
15" X X 1
EC_SCI# G15
<46> EC_SCI# TACH3/GPIO7
EC_SMI# Y1
<46> EC_SMI# GPIO8
RH229 1 @ 2 10K_0402_5% PCH_GPIO12 K13 RH2361 2 10K_0402_5%
+3V_PCH LAN_PHY_PWR_CTRL/GPIO12 +3VS
AN10
1 2 10K_0402_5% EC_LID_OUT# AB11 TP14 GATEA20 <46>
RH230
GPIO15 AY1
<46> EC_LID_OUT# PCH_GPIO16 AN2 PECI +3VS
SATA4GP/GPIO16 SKU ID
+3VS RH232 1 2@ 10K_0402_1% AT6 KBRST#
GPIO RCIN# KBRST# <46>
waiting check
<27,54,62,63> DGPU_PWROK 0_0402_5% 2 1 RH231 PCH_DGPU_PWROK C14
TACH0/GPIO17 AV3
1 2 10K_0402_5% BB4 PROCPWRGD H_CPUPWRGD <6>
+3VS RH238 PCH_BT_DISABLE# RH711 RH708 RH704
SCLOCK/GPIO22 AV1PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
<40> PCH_BT_DISABLE# THRMTRIP# H_THRMTRIP# <6>

@ 2

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
ODD_EN Y10 RH239 390_0402_5%
<44> ODD_EN GPIO24 AU4 CPU_PLTRST# PCH_THRMTRIP#_R <23,32>
@ PLTRST_PROC# CPU_PLTRST# <6>
waiting check 0_0402_5% 2 1 RH224 DS3_WAKE#_R R11
<15,40,41> PCIE_WAKE# GPIO27 N10 @
RH2411 2 10K_0402_5% PCH_GPIO28 AD11 VSS
+3V_PCH

1
GPIO28 PCH_GPIO38
<40> PCH_BT_ON#
1 2 10K_0402_5% PCH_BT_ON# AN6
+3VS GPIO34
RH242 PCH_GPIO67
1 2 10K_0402_5% PCH_GPIO35 AP1 <16> PCH_GPIO67
waiting check +3VS RH243
GPIO35/NMI#
@ PCH_GPIO70
ODD_DETECT# AT3
<44> ODD_DETECT# SATA2GP/GPIO36
C
waiting C
PCH_GPIO37 AK1
check SATA3GP/GPIO37
PCH_GPIO38 AT7
SLOAD/GPIO38 RH712 RH709 RH706

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
RH247 1 2 10K_0402_5% PCH_GPIO39 AM3 A2
+3VS SDATAOUT0/GPIO39 VSS

@
A41
RH248 1 2 10K_0402_5% PCH_GPIO48 AN4 VSS A43 @
+3VS
RH252 SDATAOUT1/GPIO48 VSS A44
1 2 SLAVE_PRESENT# PCH_GPIO49 AK3 VSS B1
+3V_PCH 10K_0402_5% 2 1 RH1493EC_SCI#

1
SATA5GP/GPIO49 VSS B2
10K_0402_5% SLAVE_PRESENT# U12 VSS B44
<32> SLAVE_PRESENT# +3V_PCH
GPIO57 VSS B45
PCH_GPIO68 C16 VSS BA1
TACH4/GPIO68 VSS BC1 RH235 2 1 10K_0402_5% EC_SMI#
RH249 2 1 0_0402_5% PCH_S_DGPU_PWR_EN D13 VSS BD1
<32,54,55> S_DGPU_PWR_EN TACH5/GPIO69 VSS BD2
G13 VSS BD44
Reseve for SKU ID PCH_GPIO70 TACH6/GPIO70 VSS BD45
RH251 2 1 0_0402_5% PCH_S_NVDD_PWR_EN H15 VSS BE2
<32,54> S_NVDD_PWR_EN TACH7/GPIO71 VSS BE3
VSS D1
BE41 VSS E1 +3VS
1 2 TP_VSS_NCTF BE5 VSS NCTF VSS E45
RH154 0_0402_5% C45 VSS VSS A4 2 1 PCH_GPIO16 +3VS
A5 VSS VSS RH265 10K_0402_5%
GPIO28 VSS 2 1 PCH_GPIO49 10K_0402_5% 2 1 PCH_GPIO68
RH255
On-Die PLL Voltage Regulator RH266 10K_0402_5%
This signal has a weak internal pull up LYNXPOINT_BGA695 6 OF 11 REV = 5 10K_0402_5% 2 1 RH226 KBRST#

* H
L
：：On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable
@ RH272
1

2
2

1
PCH_GPIO16
10K_0402_5%
PCH_GPIO49
0_0402_5% @ RH268 10K_0402_5%
B RH240 1 @ 2 1K_0402_5% PCH_GPIO28 1 2 PCH_GPIO39 B
<37> HDSW_DDC
RH161
0_0402_5%
1 2 PCH_GPIO48
<37> HDSW_MAIN
RH171

+3VS
Config GPIO16,49
10K_0402_5% 2 1 RH1517 S_DGPU_PWR_EN

PCH_GPIO27 (Have internal Pull-High)


* USB X4,PCIEX8,SATAX6 11
* High: VCCVRM VR Enable
Low: VCCVRM VR Disable USB X6,PCIEX8,SATAX4 01

+3VALW

DS3@
RH207 2 1 10K_0402_5%

DS3_WAKE#_R

A A
@
200K_0402_5% 1 2 RH250 ODD_DETECT#
+3VS

RH259 1 2 10K_0402_5% PCH_GPIO37


Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (6/9) GPIO, CPU, MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 19 of 69
5 4 3 2 1
5 4 3 2 1

70mA
2 RH1 1
+VCCADAC
D +1.5VS D
1_0603_1%

0.01U_0402_16V7K

0.1U_0402_10V7K

10U_0603_6.3V6M
1 1 1

CH57

CH80

CH56
2 2 2

1.312 A LPT_PCH_M_EDS
UHG
+1.05VS +1.05VS_PCH_VCC +1.05V_+1.5V_RUN
P45
J1 VCCADAC1_5

10U_0603_6.3V6M
2 1 +1.05VS_PCH_VCC AA24 P43
2 1 AA26 VCC CRT DAC VSS +1.05VS_PCH_VCCIO
VCC
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 AD20 M31 1
JUMP_43X39 VCC VCCADACBG3_3 +3VS

1U_0402_6.3V6K

@ CH81
AD22
VCC
CH30

CH32

CH33

CH31
AD24 1
AD26 VCC BB44
2 2 2 2 VCC VCCVRM 2

CH48
AD28
AE18 VCC FDI AN34
AE20 VCC VCCIO +3VS_PCH_VCC3_3 2
AE22 VCC AN35
AE24 VCC VCCIO
AE26 VCC R30 +3VS_PCH_VCC3_3
VCC HVCMOS VCC3_3_R30

0.1U_0402_10V7K
AG18 R32
AG20 VCC VCC3_3_R32
VCC 1
AG22 Y12 +PCH_USB_DCPSUS1 +3VPCH_PCH_VCCSUS3_3
VCC DCPSUS1

CH38
AG24
Y26 VCC AJ30 +3VPCH_PCH_VCCSUS3_3
670mA VCC VCCSUS3_3 2

Core
AJ32
C +1.05VS +1.05VS_PCH_VCCASW VCCSUS3_3 C
AJ26 +PCH_USB_DCPSUS3 +1.05V_+1.5V_RUN
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28
1 RH209 2 +1.05VS_PCH_VCCASW AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05VS_PCH_VCCIO
U18 AK26
R_short 0_0603_5% VCCASW VCCVRM +1.05V_+1.5V_RUN
22U_0805_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
U20 AK28 1
VCCASW VCCVRM

@ CH82
1 1 1 U22
U24 VCCASW BE22
VCCASW VCCVRM
CH64

CH35

CH36

V18 PCIe/DMI
VCCASW +1.05V_+1.5V_RUN 2

10U_0603_6.3V6M
V20 AK18 1
2 2 2 VCCASW VCCIO +1.05VS_PCH_VCCIO

@ CH83
V22
V24 VCCASW AN11
VCCASW VCCVRM

10U_0603_6.3V6M
Y18
Y20 VCCASW SATA
AK22 2
VCCASW VCCIO 1

@ CH85
Y22 +1.05VS_PCH_VCCIO
VCCASW AM18
VCCIO AM20
VCCIO AM22 2
VCCMPHY VCCIO AP22
VCCIO

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
AR22 1 1 1 1 1
VCCIO AT22
VCCIO

CH86

CH47

CH46

CH45

CH44
LYNXPOINT_BGA695 7 OF 11 REV = 5 2 2 2 2 2

1 2 +PCH_VCCDSW
RH37 5.11_0402_1%
+PCH_VCCDSW_R

B B
1U_0402_6.3V6K

1
+1.05VS
CH34

2 +PCH_USB_DCPSUS1 2 1
0_0402_5% RH360 @

1U_0402_6.3V6K
1

@ CH61
2

+1.05VS

+PCH_USB_DCPSUS3 1 2
0_0603_5% RH199 @

10U_0603_6.3V6M

1U_0402_6.3V6K
1 1

@CH40
@

@CH39
@
CH40

CH39
2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (7/9) PWR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 20 of 69
5 4 3 2 1
5 4 3 2 1

+3VPCH_PCH_VCCSUS3_3
15mA

0.1U_0402_10V7K
2 1
LPT_PCH_M_EDS +3V_PCH
UHH 0_0402_5% RH201 @

0.1U_0402_10V7K
1 R_short 0_0402_5% 2 1 RH1515
+3VALW
+3VPCH_PCH_VCCSUS3_3

CH60
1

CH55
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22 2
VCCSUS3_3 VCCSUS3_3

0.1U_0402_10V7K
R28
D +1.05VS U26 VCCSUS3_3 GPIO/LPC 2 D
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3 +3VS_PCH_VCC3_3

CH59
M24
VSS AA14 +PCH_VCCSST 1 2
2 +3VS_PCH_VCC3_3 DCPSST

0.1U_0402_10V7K
U35 CH84 0.1U_0402_10V7K
VCCUSBPLL AE14
1

USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3

CH62

0.1U_0402_10V7K
AG14
VCC3_3 +3VPCH_VCCSUSHDA

0.1U_0402_10V7K
U30 1
2 +1.05VS_PCH_VCCIO V28 VCCIO
1 VCCIO +1.05VS_PCH_VCCIO

CH63

CH65
V30 U36
Y30 VCCIO VCCIO
VCCIO +3VPCH_PCH_VCCSUS3_3 2
2

0.1U_0402_10V7K
+1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2

1U_0402_6.3V6K
1 A26 1
AF34 VCCSUSHDA
VCCVRM

CH37

CH66
+RTCVCC

10U_0603_6.3V6M

1U_0402_6.3V6K
1 +PCH_VCC AP45 K8 1
2 VCC VCCSUS3_3 2

CH42

CH58
Y32 A6
+PCH_VCCCLK VCCCLK VCCRTC
2 RTC 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
M29 P14 +PCH_DCPRTC CH70
+PCH_VCCCLK3_3 VCCCLK3_3 DCPRTC P16 1 2 1 1 1
L29 DCPRTC
+1.05VS VCCCLK3_3

CH69

CH68

CH67
0.1U_0402_10V7K
L26 AJ12 +PCH_VPROC
1 2 +PCH_USB_DCPSUS2 M26 VCCCLK3_3 V_PROC_IO AJ14 2 2 2
CPU
@ RH361 0_0402_5% VCCCLK3_3 V_PROC_IO +3VS_PCH_VCCSPI
1U_0402_6.3V6K

U32
VCCCLK3_3

1U_0402_6.3V6K
V32 AD12

ICC
1 VCCCLK3_3 SPI VCCSPI
@ CH87

AD34 1
C +PCH_VCCCLK VCCCLK C
P18 +PCH_VCCCFUSE
2 VCC

CH74
AA30 P20
AA32 VCCCLK VCC
VCCCLK L17 2
AD35 Fuse VCCASW
VCCCLK R18
VCCASW +1.05VS_PCH_VCCASW
AG30
AG32 VCCCLK
VCCCLK AW40
VCCVRM +1.05V_+1.5V_RUN +1.05VS
AD36
+1.05VS VCCCLK AK30 +3VS_PCH_VCC3_3
@ AE30 Thermal
VCC3_3 +PCH_VPROC 2 RH219 1
LH100 AE32 VCCCLK AK32
VCCCLK VCC3_3 R_short 0_0805_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
1 2 +PCH_VCC
4.7UH_LQM18FN4R7M00D_20% 1 1 1 1
10U_0603_6.3V6M

1U_0402_6.3V6K

1RH1516

CH76

CH73

CH72

CH71
2 1 1 LYNXPOINT_BGA695 8 OF 11 REV = 5
CH43

CH49

R_short 0_0603_5% 2 2 2 2
+3V_PCH +3VPCH_VCCSUSHDA
2 2

2 RH215 1

R_short 0_0603_5% 10mA


Place near pin AP45
@
+3VS +3VS_PCH_VCCSPI +PCH_VCCCFUSE 2 1
+1.05VS +3VS
306mA +PCH_VCCCLK 0_0805_5% RH220

1U_0402_6.3V6K
2 1
RH213 1 RH200 2 +1.05VS
2 1 1 0_0805_5% RH221
R_short 0_0603_5% 22mA R_short 0_0805_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

CH75
B B
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2
1 1 1 1 1
CH50

CH77

CH78

CH79

CH88
+1.05VS +1.05VS_PCH_VCCIO 2 2 2 2 2

J2
1 2 3.629A
1 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
JUMP_43X39 Place near pin AG30,AG32,AE30,AE32

+3VS +PCH_VCCCLK3_3
+1.5VS +1.05V_+1.5V_RUN 55mA
1 RH212 2
2 RH197 1
R_short 0_0805_5%
R_short 0_0603_5% 183mA
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.05VS
1 1 1 1
CH51

CH52

CH53

CH54
2 1
@ RH198 0_0603_5%
2 2 2 2

+3V_PCH +3VPCH_PCH_VCCSUS3_3 Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A
2 RH211 1
261mA
R_short 0_0603_5%

+3VS +3VS_PCH_VCC3_3
Security Classification LC Future Center Secret Data Title

2 RH214 1
133mA
Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (8/9) PWR
R_short 0_0603_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 21 of 69
5 4 3 2 1
5 4 3 2 1

D D

LPT_PCH_M_EDS LPT_PCH_M_EDS
UHJ UHK

AL34 K39 AA16 B19


AL38 VSS VSS L2 AA20 VSS VSS B23
AL8 VSS VSS L44 AA22 VSS VSS B27
AM14 VSS VSS M17 AA28 VSS VSS B31
AM24 VSS VSS M22 AA4 VSS VSS B35
AM26 VSS VSS N12 AB12 VSS VSS B39
AM28 VSS VSS N35 AB34 VSS VSS B7
AM30 VSS VSS N39 AB38 VSS VSS BA40
AM32 VSS VSS N6 AB8 VSS VSS BD11
AM16 VSS VSS P22 AC2 VSS VSS BD15
AN36 VSS VSS P24 AC44 VSS VSS BD19
AN40 VSS VSS P26 AD14 VSS VSS AY36
C AN42 VSS VSS P28 AD16 VSS VSS AT43 C
AN8 VSS VSS P30 AD18 VSS VSS BD31
AP13 VSS VSS P32 AD30 VSS VSS BD35
AP24 VSS VSS R12 AD32 VSS VSS BD39
AP31 VSS VSS R14 AD40 VSS VSS BD7
AP43 VSS VSS R16 AD6 VSS VSS D25
AR2 VSS VSS R2 AD8 VSS VSS AV7
AK16 VSS VSS R34 AE16 VSS VSS F15
AT10 VSS VSS R38 AE28 VSS VSS F20
AT15 VSS VSS R44 AF38 VSS VSS F29
AT17 VSS VSS R8 AF8 VSS VSS F33
AT20 VSS VSS T43 AG16 VSS VSS BC16
AT26 VSS VSS U10 AG2 VSS VSS D4
AT29 VSS VSS U16 AG26 VSS VSS G2
AT36 VSS VSS U28 AG28 VSS VSS G38
AT38 VSS VSS U34 AG44 VSS VSS G44
D42 VSS VSS U38 AJ16 VSS VSS G8
AV13 VSS VSS U42 AJ18 VSS VSS H10
AV22 VSS VSS U6 AJ20 VSS VSS H13
AV24 VSS VSS V14 AJ22 VSS VSS H17
AV31 VSS VSS V16 AJ24 VSS VSS H22
AV33 VSS VSS V26 AJ34 VSS VSS H24
BB25 VSS VSS V43 AJ38 VSS VSS H26
AV40 VSS VSS W2 AJ6 VSS VSS H31
AV6 VSS VSS W44 AJ8 VSS VSS H36
AW2 VSS VSS Y14 AK14 VSS VSS H40
F43 VSS VSS Y16 AK24 VSS VSS H7
AY10 VSS VSS Y24 AK43 VSS VSS K10
AY15 VSS VSS Y28 AK45 VSS VSS K15
AY20 VSS VSS Y34 AL12 VSS VSS K20
AY26 VSS VSS Y36 AL2 VSS VSS K29
AY29 VSS VSS Y40 BC22 VSS VSS K33
B AY7 VSS VSS Y8 BB42 VSS VSS BC28 B
B11 VSS VSS VSS VSS
B15 VSS
VSS
LYNXPOINT_BGA695 11 OF 11 REV = 5

LYNXPOINT_BGA695 10 OF 11 REV = 5

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PCH (9/9) VSS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 22 of 69
5 4 3 2 1
5 4 3 2 1

+3VS_VGA
UV1A
PCIE_CTX_C_GRX_N[0..15] +3VS_VGA
<32,5> PCIE_CTX_C_GRX_N[0..15] PCIE_CTX_C_GRX_P7 AN12 PCH_THRMTRIP#_R
Part 1 of 7 @
PEX_RX0 PCH_THRMTRIP#_R <19,32>

1
PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_N7 AM12 P6 FB_CLAMP_MON 1 2
<32,5> PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_P6 AN14 PEX_RX0_N GPIO0 M3 FB_CLAMP <23,27,54>
RV138 0_0402_5% RV208
PEX_RX1 GPIO1

3
10K_0402_5%
PCIE_CRX_GTX_N[0..15] PCIE_CTX_C_GRX_N6 AM14 L6 VGA_BL_PWM 10K_0402_5%
<32,5> PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2 VGA_BL_PWM <35>

2
PCIE_CTX_C_GRX_P5 AP14 P5 VGA_ENVDD QV7B
PEX_RX2 GPIO3 VGA_ENVDD <35>

RV65
PCIE_CRX_GTX_P[0..15] PCIE_CTX_C_GRX_N5 AP15 P7 VGA_ENBKL DMN66D0LDW-7 2N_SOT363-6

2
<32,5> PCIE_CRX_GTX_P[0..15] PCIE_CTX_C_GRX_P4 AN15 PEX_RX2_N GPIO4 L7 VGA_ENBKL <35> 5
PCIE_CTX_C_GRX_N4 AM15 PEX_RX3 GPIO5 M7 FB_CLAMP_TOGGLE_REQ#
PEX_RX3_N GPIO6 @

6
PCIE_CTX_C_GRX_P3 AN17 N8 @

4
PCIE_CTX_C_GRX_N3 AM17 PEX_RX4 GPIO7 M1 OVERT# QV7A
PCIE_CTX_C_GRX_P2 AP17 PEX_RX4_N GPIO8 M2 VGA_ALERT#
D
Under GPU(below 150mils) AP18 PEX_RX5 GPIO9 L1 2
DMN66D0LDW-7 2N_SOT363-6
D
150mA PCIE_CTX_C_GRX_N2 OVERT#
PCIE_CTX_C_GRX_P1 AN18 PEX_RX5_N GPIO10 M5 NVVDD PWM_VID MEM_VREF <28,29,30,31>
LV1 BLM18PG181SN1D_2P

GPIO
1 2 +SP_PLLVDD PCIE_CTX_C_GRX_N1 AM18 PEX_RX6 GPIO11 N3 VGA_AC_DET_R NVVDD PWM_VID <63>
+1.05VS_VGA @

1
PEX_RX6_N GPIO12 VGA_AC_DET_R <32>

10K_0402_5%
22U_0805_6.3V6M

4.7U_0402_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K
PCIE_CTX_C_GRX_P0 AN20 M4
PEX_RX7 GPIO13 DPRSLPVR_VGA <63>

1
CV112

CV113

CV4

CV5
180ohms (ESR=0.2) Bead 1 1 1 1 PCIE_CTX_C_GRX_N0 AM20 N4
PEX_RX7_N GPIO14

RV223
AP20 P2
AP21 PEX_RX8 GPIO15 R8
AN21 PEX_RX8_N GPIO16 M6 VGA_EDP_HPD
PEX_RX9 GPIO17 VGA_EDP_HPD <38>

1
2 2 2 2 AM21 R1 DGPU_HDMI_HPD D
DGPU_HDMI_HPD <37,39>

2
+3VS_VGA AN23 PEX_RX9_N GPIO18 P3 PLT_RST_VGA# 2
AM23 PEX_RX10 GPIO19 P4 G QV5
+3VS_VGA AP23 PEX_RX10_N GPIO20 P1 2N7002KW_SOT323-3
S

3
AP24 PEX_RX11 GPIO21 DV2
PEX_RX11_N
2

RV25 AN24 RB751V-40_SOD323-2


RV24 2.2K_0402_5% AM24 PEX_RX12 VGA_AC_DET_R 2 1
AN26 PEX_RX12_N VGA_AC_DET <46>
2.2K_0402_5% Vendor recommand reserve PU/PD resistor 2012-0418 --> Stuff QV7, RV208
AM26 PEX_RX13
PEX_RX13_N
5

AP26 2012-0429 --> Add QV5, C38 has abnormal shutdown issue
1

QV1B AP27 PEX_RX14


VGA_SMB_CK2 4 3 AN27 PEX_RX14_N AK9 VGA_CRT_R PLT_RST_VGA#
EC_SMB_CK2 <17,32,34,36,43,46> PEX_RX15 DACA_RED VGA_CRT_R <37>

0.1U_0402_10V7K
AM27 AL10 VGA_CRT_G
PEX_RX15_N DACA_GREEN VGA_CRT_G <37> +3VS_VGA
2N7002DW-T/R7_SOT363-6 AL9 VGA_CRT_B 1
DACA_BLUE VGA_CRT_B <37>
@

DACs

CV151
PCIE_CRX_GTX_P7 CV24 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P7 AK14
PCIE_CRX_GTX_N7 CV26 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 AJ14 PEX_TX0 AM9 VGA_CRT_HSYNC

2
PCIE_CRX_GTX_P6 1 2 PCIE_CRX_C_GTX_P6 AH14 PEX_TX0_N DACA_HSYNC AN9 VGA_CRT_VSYNC VGA_CRT_HSYNC <37> 2
CV21 0.22U_0402_10V6K
PEX_TX1 DACA_VSYNC VGA_CRT_VSYNC <37>
2

PCIE_CRX_GTX_N6 CV23 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N6 AG14 RV52


QV1A PCIE_CRX_GTX_P5 CV25 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 AK15 PEX_TX1_N 100K_0402_5%
VGA_SMB_DA2 1 6 PCIE_CRX_GTX_N5 CV27 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 AJ15 PEX_TX2 AG10 +DACA_VDD
EC_SMB_DA2 <17,32,34,36,43,46> PEX_TX2_N DACA_VDD

PCI EXPRESS
PCIE_CRX_GTX_P4 CV29 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AL16 AP9 +DACA_VREF

1
PEX_TX3 DACA_VREF

2
G
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N4 CV31 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AK16 AP8 DACA_RSET
PEX_TX3_N DACA_RSET

0.1U_0402_10V7K
PCIE_CRX_GTX_P3 CV33 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AK17
PEX_TX4

CV130
C PCIE_CRX_GTX_N3 CV28 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 AJ17 1 FB_CLAMP_TOGGLE_REQ# 3 1 C
PCIE_CRX_GTX_P2 1 2 PCIE_CRX_C_GTX_P2 AH17 PEX_TX4_N GC6_EVENT# <19,54>
CV30 0.22U_0402_10V6K RV107

D
PCIE_CRX_GTX_N2 1 2 PCIE_CRX_C_GTX_N2 AG17 PEX_TX5
PU AT EC SIDE, +3VS AND 4.7K CV32 0.22U_0402_10V6K
PEX_TX5_N
124_0402_1%
PCIE_CRX_GTX_P1 CV36 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P1 AK18
PCIE_CRX_GTX_N1 1 2 PCIE_CRX_C_GTX_N1 AJ18 PEX_TX6 2 QV6
CV41 0.22U_0402_10V6K GPIO 14 of GPU connect to PCH GPIO 0

2
PCIE_CRX_GTX_P0 CV34 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AL19 PEX_TX6_N 2N7002KW_SOT323-3 +3VS_VGA
PCIE_CRX_GTX_N0 CV35 1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 AK19 PEX_TX7 R4 VGA_CRT_CLK
PEX_TX7_N I2CA_SCL VGA_CRT_CLK <37>
AK20 R5 VGA_CRT_DATA
VGA_CRT_DATA <37>
+3VS
AJ20 PEX_TX8
PEX_TX8_N
I2CA_SDA CRT
AH20 R7 I2CB_SCL VGA_ALERT# 1 2
AG20 PEX_TX9 I2CB_SCL R6 I2CB_SDA RV14 2.2K_0402_5%
AK21 PEX_TX9_N I2CB_SDA VGA_CRT_DATA 1 2

I2C
1 PEX_TX10
C1061 AJ21 R2 I2CC_SCL RV16 100K_0402_5% RV10 2.2K_0402_5%
0.1U_0402_16V4Z AL22 PEX_TX10_N I2CC_SCL R3 I2CC_SDA VGA_BL_PWM 1 2 VGA_CRT_CLK 1 2
AK22 PEX_TX11 I2CC_SDA RV11 2.2K_0402_5%
2 AK23 PEX_TX11_N T4 VGA_SMB_CK2 I2CB_SCL 1 2
AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2 LVDS RV12 2.2K_0402_5%
AH23 PEX_TX12_N I2CS_SDA I2CB_SDA 1 2
5

UV2 AG23 PEX_TX13 RV13 2.2K_0402_5%


PLT_RST# 2 PEX_TX13_N
P

<14,32,40,41,46> PLT_RST# B AK24 OVERT# 1 2


4 PLT_RST_VGA# AJ24 PEX_TX14
Y RV1 10K_0402_5%
DGPU_HOLD_RST# 1 AL25 PEX_TX14_N VGA_AC_DET_R 1 2
<14,54> DGPU_HOLD_RST# A 60mA Close to GPU
G

PEX_TX15
2

AK25 +PLLVDD RV2 10K_0402_5%


PEX_TX15_N
3

RV111
10K_0402_5% AD8 1 2 VGA_CRT_R 1 2
NC7SZ08P5X_NL_SC70-5 AJ11 PLLVDD RV112 @ 0_0402_5% RV106 150_0402_1% I2CC_SCL 1 2
PEX_WAKE_N AE8
45mA VGA_CRT_G 1 2 RV15 2.2K_0402_5%
SP_PLLVDD
1

CLK_PCIE_VGA AL13 45mA RV108 150_0402_1% I2CC_SDA 1 2


<16> CLK_PCIE_VGA PEX_REFCLK
CLK_PCIE_VGA# AK13 AD7 +SP_PLLVDD VGA_CRT_B 1 2 RV17 2.2K_0402_5%
<16> CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD
CLK_REQ_GPU# AK12 RV109 150_0402_1%

CLK
PEX_CLKREQ_N
1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTAL_IN
B R1495 @ 0_0402_5% Differential signal RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT B
1 2 PEX_TSTCLK_OUT_N XTAL_OUT
PLT_RST_VGA# AJ12 J4 XTALOUT 220 ohms @100MHz (ESR=0.05)
AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN 1 2
PEX_TERMP XTAL_SSIN 120mA

1
1 2 PEX_TERMP 10K_0402_5% RV26 LV5
RV22 2.49K_0402_1% RV27 +DACA_VDD
Under GPU Near GPU 2 1
+3VS_VGA

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
10K_0402_5% BLM18PG181SN1D_0603

@ CV125

@ CV126

CV139

CV122

CV127

CV128
1U_0402_6.3V6K
FB_CLAMP_MON 1 1 1 1 1 1

2
N14P-GT1-A2_FCBGA908 Internal Thermal Sensor
2

RV238 2 2 2 2 2 2
GT1@
0_0402_5%
+3VS GC6@ +3VS_VGA UV1
1

1 2
RV23 10M_0402_5%
1

RV235 YV1
10K_0402_5% RV230 GT@ Crystal
GC6@ 10K_0402_5% N14P-GT-A2_FCBGA908 4 3XTAL_OUT
GND OUT
1

@
RV231
2

RV236 XTAL_IN 1 2
1

10K_0402_5% 2 1 +3VS_VGA IN GND +PLLVDD LV7 1 2 0_0402_5%


<14,23,54,55> DGPU_PWR_EN +1.05VS_VGA
1

22U_0805_6.3V6M
0.1U_0402_10V7K
RV239 GC6@ 1 1

CV131
2 1 2 27MHZ_10PF_7V27000050 1 1
2

10K_0402_5%

CV40
1K_0402_5% GC6@ G QV2 CV37 CV38
2

GC6@ S 10P_0402_50V8J 10P_0402_50V8J


3

LP2301ALT1G_SOT-23 RV32 2 2
10K_0402_5% 2 2
2

For GC6
G
1

D
0.1U_0402_10V7K

1 QV16
1

A <14,23,54,55> DGPU_PWR_EN 2 1 3 CLK_REQ_GPU# A


GC6@ <16> CLK_REQ_GPU#_R
CV148
G
Under GPU Near GPU
D

FB_CLAMP <23,27,54>
QV3 S
3

2N7002KW_SOT323-3 2 2N7002H 1N_SOT23-3


GC6@ @ RV232
@RV232
1

10K_0402_5%
RV237 @ Title
10K_0402_5% 1 2 Security Classification LC Future Center Secret Data
1

GC6@ RV233 0_0402_5%


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_PCIE/ DAC/ GPIO
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 23 of 69

5 4 3 2 1
5 4 3 2 1

UV1D

Part 4 of 7
AM6
AN6 IFPA_TXC P8
AP3 IFPA_TXC_N NC AC6
AN3 IFPA_TXD0 NC AJ28
AN5 IFPA_TXD0_N NC AJ4
AM5 IFPA_TXD1 NC AJ5
AL6 IFPA_TXD1_N NC AL11
AK6 IFPA_TXD2 NC C15
IFPA_TXD2_N NC

NC
AJ6 D19
AH6 IFPA_TXD3 NC D20
D IFPA_TXD3_N NC D23 D
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
for 15" dual channel AM7 IFPB_TXD4_N
AL7 IFPB_TXD5
AN8 IFPB_TXD5_N
AM8 IFPB_TXD6
AK8 IFPB_TXD6_N
AL8 IFPB_TXD7
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <63>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA <63>
AJ2
AH3 IFPC_L1_N
IFPC_L2 trace width: 16mils
AH4
AG5 IFPC_L2_N differential voltage sensing.
IFPC_L3
AG4
IFPC_L3_N differential signal routing.
TEST
<38> VGA_EDP_TX0+ VGA_EDP_TX0+ AM1 AK11 TESTMODE
VGA_EDP_TX0- AM2 IFPD_L0 TESTMODE
<38> VGA_EDP_TX0- IFPD_L0_N
<38> VGA_EDP_TX1+ VGA_EDP_TX1+ AM3 AM10
IFPD_L1 JTAG_TCK TV2

1
<38> VGA_EDP_TX1- VGA_EDP_TX1- AM4 AM11
IFPD_L1_N JTAG_TDI TV3
AL3 AP12
IFPD_L2 JTAG_TDO TV4 10K_0402_5%
C AL4 AP11 C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
AK5 IFPD_L3 JTAG_TRST_N RV34 10K_0402_5%

2
IFPD_L3_N

LVDS/TMDS
<37> GPU_HDMI_TX2+ GPU_HDMI_TX2+ AD2
GPU_HDMI_TX2- AD3 IFPE_L0
<37> GPU_HDMI_TX2- IFPE_L0_N
GPU_HDMI_TX1+ AD1
<37>
<37>
GPU_HDMI_TX1+
GPU_HDMI_TX1- GPU_HDMI_TX1- AC1 IFPE_L1 SERIAL
GPU_HDMI_TX0+ AC2 IFPE_L1_N H6 ROM_CS#
<37> GPU_HDMI_TX0+ IFPE_L2 ROM_CS_N
<37> GPU_HDMI_TX0- GPU_HDMI_TX0- AC3 H4 ROM_SCLK ROM_SCLK <33>
GPU_HDMI_CLK+ AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI
<37> GPU_HDMI_CLK+ IFPE_L3 ROM_SI ROM_SI <33>
<37> GPU_HDMI_CLK- GPU_HDMI_CLK- AC5 H7 ROM_SO ROM_SO <33>
IFPE_L3_N ROM_SO

AE3
20120829 VA1 AE4 IFPF_L0
Change net name for add HDMI MUX AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N GENERAL RV35 10K_0402_5%
AD5 IFPF_L2 L2 2 1
100K_0402_5% RV19 AG1 IFPF_L2_N BUFRST_N
2 1 VGA_EDP_AUX AF1 IFPF_L3 L3
IFPF_L3_N CEC
100K_0402_5% RV30 J1 1 2
2 1 VGA_EDP_AUX# MULTI_STRAP_REF0_GND RV38 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW _SCL
IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <33>
J7 STRAP1 STRAP1 <33>
B
VGA_EDP_AUX AK3 STRAP1 J6 STRAP2 B
+3VS_VGA <38> VGA_EDP_AUX IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <33>
VGA_EDP_AUX# AK2 J5 STRAP3 STRAP3 <33>
<38> VGA_EDP_AUX# IFPD_AUX_I2CX_SDA_N STRAP3 J3 STRAP4 STRAP4 <33>
RV113 47K_0402_5% STRAP4
1 2 GPU_HDMI_CLK GPU_HDMI_CLK AB3
HDMI <37> GPU_HDMI_CLK
GPU_HDMI_DATA AB4 IFPE_AUX_I2CY_SCL
<37> GPU_HDMI_DATA IFPE_AUX_I2CY_SDA_N
RV114 47K_0402_5% K3 For EMI
1 2 GPU_HDMI_DATA THERMDP K4 RH123 10_0402_5%
20120829 VA1 AF3 THERMDN ROM_SCLK_R 1 2
Change net name for add HDMI MUX AF2 IFPF_AUX_I2CZ_SCL @
IFPF_AUX_I2CZ_SDA_N 1
@ CH201
2
1MB SPI ROM FOR VBIOS ROM (SLI)
N14P-GT-A2_FCBGA908 10P_0402_50V8J
+3VS_VGA
CV295
2 1 20mils

1
@
0.1U_0402_16V4Z
RV229 @ @ RV225
10K_0402_5% SA00004EK0J(2012/0813) 10K_0402_5%
@

2
RV224 @0_0402_5% UV15
ROM_CS#1 2 ROM_CS#_R 1 8
ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
RV226 @0_0402_5% 3 DO HOLD# 6
A W P# CLK A
4 5 RV228 @ 0_0402_5%
GND DIO ROM_SCLK_R1 2 ROM_SCLK
MX25L2006EMIT-12G SOP ROM_SI_R 1 2 ROM_SI
RV227 @ 0_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_LVDS/ HDMI/ THERM


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 24 of 69

5 4 3 2 1
5 4 3 2 1

UV1E
Near GPU
+1.5VS_VGA
For GDDR5 setting. Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CV273

CV274

CV275

CV276

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV263

CV264

CV265

CV266

CV267

CV268

CV269

CV270

CV271

CV272

CV43

CV44

CV45

CV46

CV47

CV48

CV49

CV50

CV51

CV52
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 1 1 2 2 2 2 1 1 1 1 AB27 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 1 1 1 1 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
FBVDDQ_9 PEX_IOVDDQ_1 Under GPU(below 150mils) +1.05VS_VGA
D B16 AG16 D
FBVDDQ_10 PEX_IOVDDQ_2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 AG18
+1.5VS_VGA FBVDDQ_11 PEX_IOVDDQ_3

CV54

CV53

CV56

CV55
E13 AG25 1 1 1 1
E16 FBVDDQ_12 PEX_IOVDDQ_4 AH15
FBVDDQ_13 PEX_IOVDDQ_5

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
E19 AH18
FBVDDQ_14 PEX_IOVDDQ_6
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV277

CV281

CV282

CV278

CV279

CV280

CV292

CV287

CV294

CV284

CV285

CV286
1 1 1 1 1 1 1 1 1 1 1 1 H10 AH26
H11 FBVDDQ_15 PEX_IOVDDQ_7 AH27 2 2 2 2
H12 FBVDDQ_16 PEX_IOVDDQ_8 AJ27
H13 FBVDDQ_17 PEX_IOVDDQ_9 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27

POWER
H15 FBVDDQ_19 PEX_IOVDDQ_11 AM28
H16 FBVDDQ_20 PEX_IOVDDQ_12 AN28 +3VS_VGA
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22
H20 FBVDDQ_23
H21 FBVDDQ_24 AH12
FBVDDQ_25 PEX_PLL_HVDD

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H22
FBVDDQ_26

CV70

CV74

CV73
H23 1 1 1
H24 FBVDDQ_27
H8 FBVDDQ_28 AG12
H9 FBVDDQ_29 PEX_SVDD_3V3
L27 FBVDDQ_30 2 2 2
M27 FBVDDQ_31
N27 FBVDDQ_32 AG26 +PEX_PLLVDD
P27 FBVDDQ_33 PEX_PLLVDD
R27 FBVDDQ_34
FBVDDQ_35 Under GPU(below 150mils)
T27
T30 FBVDDQ_36 J8
T33 FBVDDQ_37 VDD33_0 K8 +3VS_VGA
FBVDDQ_38 VDD33_1 Place near balls Place near GPU
V27 L8
FBVDDQ_39 VDD33_2 RV5
W27 M8 +VDD33 2 1
FBVDDQ_40 VDD33_3

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
W30
FBVDDQ_41 R_short 0_0603_5%

1U_0402_6.3V6K
CV109

CV111

CV293

CV75
W33 1 1 1 1
Y27 FBVDDQ_42
FBVDDQ_43 AH8 +IFPAB_PLLVDD 1 @ 2
C IFPAB_PLLVDD AJ8 10K_0402_5% RV45 2 1 C
RV141 1 2 R_short 0_0402_5% FB_VDDQ_SENSE IFPAB_RSET 1K_0402_1% RV40 2 2 2 2
<61> VDDQ_SENSE
AG8 +IFPAB_IOVDD 1 @ 2 @
IFPA_IOVDD AG9 10K_0402_5% RV47
RV142 1 2 R_short 0_0402_5% FB_VSS_SENSE F1 IFPB_IOVDD
FB_VDDQ_SENSE
AF7 +IFPC_PLLVDD 1 @ 2
+1.5VS_VGA F2 IFPC_PLLVDD AF8 10K_0402_5% RV42 2 1
FB_GND_SENSE IFPC_RSET 1K_0402_1% @ RV43
AF6 +IFPC_IOVDD 1 @ 2
1 2 J27 IFPC_IOVDD 10K_0402_5% RV44
RV6 40.2_0402_1% FB_CAL_PD_VDDQ IFPAB & IFPEF have to use
CALIBRATION PIN GDDR5 AG7 +IFPD_PLLVDD
1 2 H27 IFPD_PLLVDD AN2 2 1
RV8 40.2_0402_1% FB_CAL_PU_GND IFPD_RSET 1K_0402_1% RV46
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD
1 2 H25 IFPD_IOVDD
RV9 60.4_0402_1% FB_CAL_TERM_GND
FB_CAL_x_PU_GND 40.2Ohm AB8 +IFPEF_PLLVDD
IFPEF_PLVDD AD6 2 1
IFPEF_RSET 1K_0402_1% RV50
FB_CAL_xTERM_GND 60.4Ohm AC7 +IFPE_IOVDD
IFPE_IOVDD AC8
Place near balls IFPF_IOVDD

+1.05VS_VGA
120mA RV4
+PEX_PLLVDD 2 1

1U_0603_10V6K

4.7U_0805_25V6-K
0.1U_0402_10V7K
N14P-GT-A2_FCBGA908

CV65

CV3

CV66
1 1 1 0_0603_5%

2 2 2
B 300ohms @100MHz (ESR=0.25) B

P/N: SM010031680 120ohms @100MHz (ESR=0.18)


+3VS_VGA
LV9 220mA +3VS_VGA P/N:SM01000BZ00
2 1 +IFPEF_PLLVDD LV6 200mA Place near balls
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

BLM18PG181SN1D_0603 2 1 +IFPD_PLLVDD
1U_0402_6.3V6K
CV149

CV147

CV171

CV173

CV150
4.7U_0603_6.3V6K

1 1 1 1 1 BLM18PG181SN1D_0603
0.1U_0402_10V7K
1U_0402_6.3V6K
CV146

CV140

CV141

1 1 1
2 2 2 2 2
4.7U_0603_6.3V6K

2 2 2

Place near balls


Place near balls
180ohms @100MHz (ESR=0.2)
220ohms @100MHz (ESR=0.05) P/N: SM010030710
+1.05VS_VGA +1.05VS_VGA
LV10 570mA LV4
0.1U_0402_10V7K

0.1U_0402_10V7K

2 1 +IFPE_IOVDD 2 1 +IFPD_IOVDD
0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0402_6.3V6K
CV152

CV172

CV153

CV158

BLM18PG181SN1D_0603 1 1 1 1 BLM18PG181SN1D_0603 IFPA_IOVDD and


1U_0402_6.3V6K
CV156

CV176

CV216

CV197

1 1 1 1
IFPB_IOVDD combined
4.7U_0603_6.3V6K

2 2 2 2
4.7U_0603_6.3V6K

2 2 2 2

A A
Place near balls

Place near balls

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 25 of 69

5 4 3 2 1
5 4 3 2 1

UV1F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
UV1G +VGA_CORE AB12 GND_4 GND_104 E25
+VGA_CORE AB14 GND_5 GND_105 E5
AB16 GND_6 GND_106 E7
Part 7 of 7 V17 AB19 GND_7 GND_107 F28
AA12 VDD_56 V18 AB2 GND_8 GND_108 F7
AA14 VDD_0 VDD_57 V20 AB21 GND_9 GND_109 G10
D
AA16 VDD_1 VDD_58 V22 A33 GND_10 GND_110 G13 D

AA19 VDD_2 VDD_59 W12 AB23 GND_11 GND_111 G16


AA21 VDD_3 VDD_60 W14 AB28 GND_12 GND_112 G19
AA23 VDD_4 VDD_61 W16 AB30 GND_13 GND_113 G2
AB13 VDD_5 VDD_62 W19 AB32 GND_14 GND_114 G22
AB15 VDD_6 VDD_63 W21 AB5 GND_15 GND_115 G25
AB17 VDD_7 VDD_64 W23 AB7 GND_16 GND_116 G28
AB18 VDD_8 VDD_65 Y13 AC13 GND_17 GND_117 G3
AB20 VDD_9 VDD_66 Y15 AC15 GND_18 GND_118 G30
AB22 VDD_10 VDD_67 Y17 AC17 GND_19 GND_119 G32
AC12 VDD_11 VDD_68 Y18 AC18 GND_20 GND_120 G33
AC14 VDD_12 VDD_69 Y20 AA13 GND_21 GND_121 G5
AC16 VDD_13 VDD_70 Y22 AC20 GND_22 GND_122 G7
AC19 VDD_14 VDD_71 AC22 GND_23 GND_123 K2
AC21 VDD_15 AE2 GND_24 GND_124 K28
AC23 VDD_16 U1 AE28 GND_25 GND_125 K30
M12 VDD_17 XVDD_1 U2 AE30 GND_26 GND_126 K32
M14 VDD_18 XVDD_2 U3 AE32 GND_27 GND_127 K33
VDD_19 XVDD_3 GND_28 GND_128
POWER
M16 U4 AE33 K5
M19 VDD_20 XVDD_4 U5 AE5 GND_29 GND_129 K7
M21 VDD_21 XVDD_5 U6 AE7 GND_30 GND_130 M13
M23 VDD_22 XVDD_6 U7 AH10 GND_31 GND_131 M15
N13 VDD_23 XVDD_7 U8 AA15 GND_32 GND_132 M17
N15 VDD_24 XVDD_8 AH13 GND_33 GND_133 M18
N17 VDD_25 AH16 GND_34 GND_134 M20
N18 VDD_26 V1 AH19 GND_35 GND_135 M22
N20 VDD_27 XVDD_9 V2 AH2 GND_36 GND_136 N12
N22 VDD_28 XVDD_10 V3 AH22 GND_37 GND_137 N14
P12 VDD_29 XVDD_11 V4 AH24 GND_38 GND_138 N16
C P14 VDD_30 XVDD_12 V5 AH28 GND_39 GND_139 N19 C
P16 VDD_31 XVDD_13 V6 AH29 GND_40 GND_140 N2
P19 VDD_32 XVDD_14 V7 AH30 GND_41 GND_141 N21
P21 VDD_33 XVDD_15 V8 AH32 GND_42 GND_142 N23

GND
P23 VDD_34 XVDD_16 AH33 GND_43 GND_143 N28
R13 VDD_35 AH5 GND_44 GND_144 N30
R15 VDD_36 W2 AH7 GND_45 GND_145 N32
R17 VDD_37 XVDD_17 W3 AJ7 GND_46 GND_146 N33
R18 VDD_38 XVDD_18 W4 AK10 GND_47 GND_147 N5
R20 VDD_39 XVDD_19 W5 AK7 GND_48 GND_148 N7
R22 VDD_40 XVDD_20 W7 AL12 GND_49 GND_149 P13
T12 VDD_41 XVDD_21 W8 AL14 GND_50 GND_150 P15
T14 VDD_42 XVDD_22 AL15 GND_51 GND_151 P17
T16 VDD_43 AL17 GND_52 GND_152 P18
T19 VDD_44 Y1 AL18 GND_53 GND_153 P20
T21 VDD_45 XVDD_23 Y2 AL2 GND_54 GND_154 P22
T23 VDD_46 XVDD_24 Y3 AL20 GND_55 GND_155 R12
U13 VDD_47 XVDD_25 Y4 AL21 GND_56 GND_156 R14
U15 VDD_48 XVDD_26 Y5 AL23 GND_57 GND_157 R16
U17 VDD_49 XVDD_27 Y6 AL24 GND_58 GND_158 R19
U18 VDD_50 XVDD_28 Y7 AL26 GND_59 GND_159 R21
U20 VDD_51 XVDD_29 Y8 AL28 GND_60 GND_160 R23
U22 VDD_52 XVDD_30 AL30 GND_61 GND_161 T13
V13 VDD_53 AL32 GND_62 GND_162 T15
V15 VDD_54 AA1 AL33 GND_63 GND_163 T17
VDD_55 XVDD_31 AA2 AL5 GND_64 GND_164 T18
XVDD_32 AA3 AM13 GND_65 GND_165 T2
XVDD_33 AA4 AM16 GND_66 GND_166 T20
XVDD_34 AA5 AM19 GND_67 GND_167 T22
XVDD_35 AA6 AM22 GND_68 GND_168 AG11
B XVDD_36 AA7 AM25 GND_69 GND_169 T28 B
XVDD_37 AA8 AN1 GND_70 GND_170 T32
XVDD_38 AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
N13P-GT1-A2_FCBGA908 AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
A C7 GND_98 GND_198 AH11 A
GND_99 GND_199 C16
GND_OPT W32
GND_OPT

Security Classification LC Future Center Secret Data Title


N13P-GT1-A2_FCBGA908
Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_+VGA CORE, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 26 of 69
5 4 3 2 1
5 4 3 2 1

FBC_D[0..63]
FBA_D[0..63] <30,31> FBC_D[0..63]
<28,29> FBA_D[0..63]

30ohms (ESR=0.01) Bead


UV1B PU for X16 mode PU for X16 mode
P/N;SM010007W00 UV1C
Part 2 of 7
+1.05VS_VGA +FB_PLLAVDD FBA_D0 L28 U30 FBA_CS#_L Part 3 of 7
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_MA3_BA3_L FBA_CS#_L <28> FBC_D0 G9 D13 FBC_CS#_L
200mA FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_MA2_BA0_L FBA_MA3_BA3_L <28> FBC_D1 E9 FBB_D0 FBB_CMD0 E14 FBC_MA3_BA3_L FBC_CS#_L <30>
FBMA-L11-160808300LMA25T_2P
1 2 +FB_PLLAVDD FBA_D3 M28 FBA_D2
FBA_D3
FBA_CMD2
FBA_CMD3
R34 FBA_MA4_BA2_L FBA_MA2_BA0_L
FBA_MA4_BA2_L
<28>
<28>
FBC_D2 G8 FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
F14 FBC_MA2_BA0_L FBC_MA3_BA3_L
FBC_MA2_BA0_L
<30>
<30>
GDDR5
D FBA_D4 N31 R33 FBA_MA5_BA1_L FBC_D3 F9 A12 FBC_MA4_BA2_L D
LV3 FBA_D5 P29
R29
FBA_D4
FBA_D5
FBA_CMD4
FBA_CMD5
U32
U33
FBA_WE#_L FBA_MA5_BA1_L
FBA_WE#_L <28>
<28>
+1.5VS_VGA FBC_D4 F11
G11
FBB_D3
FBB_D4
FBB_CMD3
FBB_CMD4
B12
C14
FBC_MA5_BA1_L FBC_MA4_BA2_L
FBC_MA5_BA1_L
<30>
<30>
+1.5VS_VGA
Mode H - Mirror Mode Mapping
Place close to BGA FBA_D6
FBA_D6 FBA_CMD6
FBA_MA7_MA8_L
FBA_MA7_MA8_L <28>
FBC_D5
FBB_D5 FBB_CMD5
FBC_WE#_L
FBC_WE#_L <30>
FBA_D7 P28 U28 FBA_MA6_MA11_L FBC_D6 F12 B14 FBC_MA7_MA8_L
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <28> FBB_D6 FBB_CMD6 FBC_MA7_MA8_L <30>

1
FBA_D8 J28 V28 FBA_ABI#_L FBC_D7 G12 G15 FBC_MA6_MA11_L DATA Bus
FBA_D8 FBA_CMD8 FBA_ABI#_L <28> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <30>

1
FBA_D9 H29 V29 FBA_MA12_RFU_L RV209 FBC_D8 G6 F15 FBC_ABI#_L
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L <28> FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA12_RFU_L FBC_ABI#_L <30>
FBA_D10 FBA_CMD10 FBA_MA0_MA10_L <28> 10K_0402_5% FBB_D9 FBB_CMD9 FBC_MA12_RFU_L <30>
RV210 Address 0..31 32..63
FBA_D11 H28 U34 FBA_MA1_MA9_L FBC_D10 E6 D15 FBC_MA0_MA10_L 10K_0402_5%
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_RAS#_L FBA_MA1_MA9_L <28> FBC_D11 F6 FBB_D10 FBB_CMD10 A14 FBC_MA1_MA9_L FBC_MA0_MA10_L <30>
FBx_CMD0 CS#

2
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_RST#_L FBA_RAS#_L <28> FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_RAS#_L FBC_MA1_MA9_L <30>

2
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CKE_L FBA_RST#_L <28> FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_RST#_L FBC_RAS#_L <30>
FBA_D14 FBA_CMD14 FBA_CKE_L <28> FBB_D13 FBB_CMD13 FBC_RST#_L <30> FBx_CMD1 A3_BA3
FBA_D15 F30 Y32 FBA_CAS#_L FBC_D14 E2 B15 FBC_CKE_L
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS#_H FBA_CAS#_L <28> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#_L FBC_CKE_L <30>
FBA_D16 FBA_CMD16 FBA_CS#_H <29> FBB_D15 FBB_CMD15 FBC_CAS#_L <30> FBx_CMD2 A2_BA0
FBA_D17 D32 AA29 FBA_MA3_BA3_H FBC_D16 C2 D18 FBC_CS#_H
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H <29> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_MA3_BA3_H FBC_CS#_H <31>
FBA_D18 FBA_CMD18 FBA_MA2_BA0_H <29> FBB_D17 FBB_CMD17 FBC_MA3_BA3_H <31> FBx_CMD3 A4_BA2
FBA_D19 C33 AC34 FBA_MA4_BA2_H FBC_D18 D3 F18 FBC_MA2_BA0_H
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA5_BA1_H FBA_MA4_BA2_H <29> FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H <31>
FBA_D20 FBA_CMD20 FBA_MA5_BA1_H <29>
+1.5VS_VGA FBB_D19 FBB_CMD19 FBC_MA4_BA2_H <31> FBx_CMD4 A5_BA1
FBA_D21 F32 AA32 FBA_WE#_H FBC_D20 B3 B20 FBC_MA5_BA1_H
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA7_MA8_H FBA_WE#_H <29> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_WE#_H FBC_MA5_BA1_H <31>
+1.5VS_VGA
FBA_D22 FBA_CMD22 FBA_MA7_MA8_H <29> FBB_D21 FBB_CMD21 FBC_WE#_H <31> FBx_CMD5 WE#
FBA_D23 H32 Y28 FBA_MA6_MA11_H FBC_D22 B5 B18 FBC_MA7_MA8_H
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <29> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <31>

MEMORY INTERFACE

1
FBA_D24 P34 Y29 FBA_ABI#_H FBC_D23 C5 G18 FBC_MA6_MA11_H FBx_CMD6 A7_A8
FBA_D24 FBA_CMD24 FBA_ABI#_H <29> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <31>

1
FBA_D25 P32 W31 FBA_MA12_RFU_H RV221 FBC_D24 A11 G17 FBC_ABI#_H
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_MA0_MA10_H FBA_MA12_RFU_H <29> FBC_D25 C11 FBB_D24 FBB_CMD24 F17 FBC_MA12_RFU_H FBC_ABI#_H <31>
10K_0402_5% RV222 FBx_CMD7 A6_A11

MEMORY INTERFACE B
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_MA1_MA9_H FBA_MA0_MA10_H <29> FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_MA0_MA10_H FBC_MA12_RFU_H <31>
FBA_D27 FBA_CMD27 FBA_MA1_MA9_H <29> FBB_D26 FBB_CMD26 FBC_MA0_MA10_H <31> 10K_0402_5%
FBA_D28 L31 Y31 FBA_RAS#_H FBC_D27 B11 A18 FBC_MA1_MA9_H FBx_CMD8 ABI#

2
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_RST#_H FBA_RAS#_H <29> FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_RAS#_H FBC_MA1_MA9_H <31>

2
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CKE_H FBA_RST#_H <29> FBC_D29 A8 FBB_D28 FBB_CMD28 A17 FBC_RST#_H FBC_RAS#_H <31>
FBA_D30 FBA_CMD30 FBA_CKE_H <29> FBB_D29 FBB_CMD29 FBC_RST#_H <31> FBx_CMD9 A12_RFU
FBA_D31 L33 V31 FBA_CAS#_H FBC_D30 C8 B17 FBC_CKE_H
FBA_D32 AG28 FBA_D31 FBA_CMD31 FBA_CAS#_H <29> FBC_D31 B8 FBB_D30 FBB_CMD30 E17 FBC_CAS#_H FBC_CKE_H <31>
FBA_D32 FBB_D31 FBB_CMD31 FBC_CAS#_H <31> FBx_CMD10 A0_A10
FBA_D33 AF29 FBC_D32 F24
FBA_D34 AG29 FBA_D33 FBC_D33 G23 FBB_D32
FBA_D34 FBB_D33 FBx_CMD11 A1_A9
FBA_D35 AF28 R32 FBC_D34 E24
C FBA_D36 AD30 FBA_D35 FBA_CMD_RFU0 AC32 FBC_D35 G24 FBB_D34 C12 C
FBA_D36 FBA_CMD_RFU1 FBB_D35 FBB_CMD_RFU0 FBx_CMD12 RAS#
FBA_D37 AD29 FBC_D36 D21 C20
FBA_D38 AC29 FBA_D37 FBC_D37 E21 FBB_D36 FBB_CMD_RFU1
FBA_D38 FBB_D37 FBx_CMD13 RST#
FBA_D39 AD28 @ FBC_D38 G21
FBA_D39 FBB_D38

A
FBA_D40 AJ29 R28 60.4_0402_1%
1 2RV58 FBC_D39 F21 @ FBx_CMD14 CKE#
FBA_D40 FBA_DEBUG0 +1.5VS_VGA FBB_D39
FBA_D41 AK29 AC28 60.4_0402_1%
1 2RV59 FBC_D40 G27 G14 60.4_0402_1%
1 2RV60
FBA_D41 FBA_DEBUG1 FBB_D40 FBB_DEBUG0 +1.5VS_VGA
FBA_D42 AJ30 FBC_D41 D27 G20 60.4_0402_1%
1 2RV61 FBx_CMD15 CAS#
FBA_D43 AK28 FBA_D42 FBC_D42 G26 FBB_D41 FBB_DEBUG1
FBA_D43 @ FBB_D42
FBA_D44 AM29 FBC_D43 E27 @ FBx_CMD16 CS#
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D44 E29 FBB_D43
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 <28> FBC_D45 F29 FBB_D44 D12 FBC_CLK0
FBA_D46 FBA_CLK0_N FBA_CLK0# <28> FBB_D45 FBB_CLK0 FBC_CLK0 <30> FBx_CMD17 A3_BA3
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D46 E30 E12 FBC_CLK0#
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 <29> FBC_D47 D30 FBB_D46 FBB_CLK0_N E20 FBC_CLK1 FBC_CLK0# <30>
FBA_D48 FBA_CLK1_N FBA_CLK1# <29> FBB_D47 FBB_CLK1 FBC_CLK1 <31> FBx_CMD18 A2_BA0
FBA_D49 AN32 FBC_D48 A32 F20 FBC_CLK1#
FBA_D50 AP30 FBA_D49 FBC_D49 C31 FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
FBA_D50 FBB_D49 FBx_CMD19 A4_BA2
FBA_D51 AP32 FBC_D50 C32
FBA_D52 AM33 FBA_D51 K31 FBA_WCK0 FBC_D51 B32 FBB_D50
FBA_D52 FBA_WCK01 FBA_WCK0 <28> FBB_D51 FBx_CMD20 A5_BA1
FBA_D53 AL31 L30 FBA_WCK0_N FBC_D52 D29 F8 FBC_WCK0
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK1 FBA_WCK0_N <28> FBC_D53 A29 FBB_D52 FBB_WCK01 E8 FBC_WCK0_N FBC_WCK0 <30>
FBA_D54 FBA_WCK23 FBA_WCK1 <28> FBB_D53 FBB_WCK01_N FBC_WCK0_N <30> FBx_CMD21 WE#
FBA_D55 AK32 J34 FBA_WCK1_N FBC_D54 C29 A5 FBC_WCK1
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK2 FBA_WCK1_N <28> FBC_D55 B29 FBB_D54 FBB_WCK23 A6 FBC_WCK1_N FBC_WCK1 <30>
FBA_D56 FBA_WCK45 FBA_WCK2 <29> FBB_D55 FBB_WCK23_N FBC_WCK1_N <30> FBx_CMD22 A7_A8
FBA_D57 AD32 AG31 FBA_WCK2_N FBC_D56 B21 D24 FBC_WCK2
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK3 FBA_WCK2_N <29> FBC_D57 C23 FBB_D56 FBB_WCK45 D25 FBC_WCK2_N FBC_WCK2 <31>
FBA_D58 FBA_WCK67 FBA_WCK3 <29> FBB_D57 FBB_WCK45_N FBC_WCK2_N <31> FBx_CMD23 A6_A11
FBA_D59 AD33 AK34 FBA_WCK3_N FBC_D58 A21 B27 FBC_WCK3
FBA_D60 AF31 FBA_D59 FBA_WCK67_N FBA_WCK3_N <29> FBC_D59 C21 FBB_D58 FBB_WCK67 C27 FBC_WCK3_N FBC_WCK3 <31>
FBA_D60 FBB_D59 FBB_WCK67_N FBC_WCK3_N <31> FBx_CMD24 ABI#
FBA_D61 AG34 FBC_D60 B24
FBA_D62 AG32 FBA_D61 FBC_D61 C24 FBB_D60
FBA_D62 FBB_D61 FBx_CMD25 A12_RFU
FBA_D63 AG33 J30 FBC_D62 B26
FBA_D63 FBA_WCKB01 J31 FBC_D63 C26 FBB_D62 D6
FBA_WCKB01_N FBB_D63 FBB_WCKB01 FBx_CMD26 A0_A10
FBA_DBI0# P30 J32 D7
<28> FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 FBA_WCKB23 J33 FBC_DBI0# E11 FBB_WCKB01_N C6
<28> FBA_DBI1# FBA_DQM1 FBA_WCKB23_N GC6 support on 15" <30> FBC_DBI0# FBB_DQM0 FBB_WCKB23 FBx_CMD27 A1_A9
FBA_DBI2# F34 AH31 FBC_DBI1# E3 B6
B <28> FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 FBA_WCKB45 AJ31 <30> FBC_DBI1# FBC_DBI2# A3 FBB_DQM1 FBB_WCKB23_N F26 B
<28> FBA_DBI3# FBA_DQM3 FBA_WCKB45_N <30> FBC_DBI2# FBB_DQM2 FBB_WCKB45 FBx_CMD28 RAS#
FBA_DBI4# AD31 AJ32 FB_CLAMP FBC_DBI3# C9 E26
<29> FBA_DBI4# FBA_DBI5# AL29 FBA_DQM4 FBA_WCKB67 AJ33 FB_CLAMP <23,54> <30> FBC_DBI3# FBC_DBI4# F23 FBB_DQM3 FBB_WCKB45_N A26
<29> FBA_DBI5# FBA_DQM5 FBA_WCKB67_N <31> FBC_DBI4# FBB_DQM4 FBB_WCKB67 FBx_CMD29 RST#
FBA_DBI6# AM32 FBC_DBI5# F27 A27
<29> FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 <31> FBC_DBI5# FBC_DBI6# C30 FBB_DQM5 FBB_WCKB67_N
<29> FBA_DBI7# FBA_DQM7 <31> FBC_DBI6# FBB_DQM6 FBx_CMD30 CKE#
RV66 NOGC6@ 10K_0402_5% FBC_DBI7# A24
FBA_EDC0 M31 E1 2 1 <31> FBC_DBI7# FBB_DQM7
FBA_DQS_WP0 FB_CLAMP FBx_CMD31 CAS#
FBA_EDC1 G31 FBC_EDC0 D10
<28> FBA_EDC[3..0] FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP0
FBA_EDC2 E33 FBC_EDC1 D5
FBA_EDC3 M33 FBA_DQS_WP2 CV106 0.1U_0402_10V7K FBC_EDC2 C3 FBB_DQS_WP1
<29> FBA_EDC[7..4] FBA_EDC4 AE31 FBA_DQS_WP3 K27 1 2 FBC_EDC3 B9 FBB_DQS_WP2
FBA_EDC5 AK30 FBA_DQS_WP4 FB_DLL_AVDD FBC_EDC4 E23 FBB_DQS_WP3 H17
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD +FB_PLLAVDD

0.1U_0402_10V7K
FBA_EDC6 AN33 Place close to ball FBC_EDC5 E28
FBA_DQS_WP6 FBB_DQS_WP5

CV108
FBA_EDC7 AF33 FBC_EDC6 B30 1
FBA_DQS_WP7 U27 FBC_EDC7 A23 FBB_DQS_WP6
FBA_PLL_AVDD +FB_PLLAVDD FBB_DQS_WP7

22U_0805_6.3V6M
0.1U_0402_10V7K

M30
FBA_DQS_RN0
CV107

CV110
1U_0402_6.3V6K

H30 1 1 1 D9
FBA_DQS_RN1 <30> FBC_EDC[3..0] FBB_DQS_RN0 2

CV39
E34 E4
M34 FBA_DQS_RN2 H26 B2 FBB_DQS_RN1
AF30 FBA_DQS_RN3 FB_VREF <31> FBC_EDC[7..4] A9 FBB_DQS_RN2
AK31 FBA_DQS_RN4 2 2 2 D22 FBB_DQS_RN3
AM34 FBA_DQS_RN5 D28 FBB_DQS_RN4
FBA_DQS_RN6 FBB_DQS_RN5
Place close to ball
AF32 A30
FBA_DQS_RN7 B23 FBB_DQS_RN6 FBC_RST#_L
FBB_DQS_RN7
Place close to ball Place close to BGA FBC_RST#_H

+3VS

1
N14P-GT-A2_FCBGA908
N14P-GT-A2_FCBGA908 RV74 RV73
1

D @ RV172 @ FBA_RST#_L 10K_0402_5% 10K_0402_5%


2 QV4 1 2 FBA_RST#_H
<14,54> DGPU_GC6_EN S_GC6_EN <32,54>
G 2N7002_SOT23

2
A RV169 0_0402_5% A
S
3

1 @ 2 DV3
0_0402_5% DAN202UT106_SC70-3 RV71 RV72
FB_CLAMP 1 GC6@ 2 GC6_EN 2 10K_0402_5% 10K_0402_5%
RV18 0_0402_5% 1
3 FBVDDQ_PWR_EN <61>
2

2 1 Title
Security Classification LC Future Center Secret Data
1

10K_0402_5% @ RV68 GC6@


RV29 Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_MEM Interface
RV156 200K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
1 2 Size Document Number Rev
Y501 NM-A032
<19,54,62,63> DGPU_PWROK GC6@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2

NOGC6@ DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
0_0402_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 27 of 69

5 4 3 2 1
5 4 3 2 1

Memory - Lower 32 bits UV3 UV4

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBA_D0 A4 FBA_D24
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1 FBA_EDC3 C2 DQ24 DQ0 A2 FBA_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D26
R13 EDC1 EDC2 DQ26 DQ2 B2 R13 EDC1 EDC2 DQ26 DQ2 B2
<27> FBA_D[0..31]
FBA_EDC2
EDC2 EDC1 DQ27 DQ3
FBA_D3 BYTE0 FBA_EDC1
EDC2 EDC1 DQ27 DQ3
FBA_D27
R2 E4 FBA_D4 R2 E4 FBA_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_D29
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D30
<27> FBA_EDC[3..0] DQ30 DQ6 DQ30 DQ6
FBA_DBI0# D2 F2 FBA_D7 FBA_DBI3# D2 F2 FBA_D31
<27> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBA_DBI3# DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBA_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBA_DBI2# DBI2# DBI1# DQ17 DQ9 <27> FBA_DBI1# DBI2# DBI1# DQ17 DQ9
D
P2 B11 P2 B11 D
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_CLK0 J12 DQ19 DQ11 E11
<27> FBA_CLK0 CK DQ20 DQ12 CK DQ20 DQ12
FBA_CLK0# J11 E13 FBA_CLK0# J11 E13
<27> FBA_CLK0# CK# DQ21 DQ13 CK# DQ21 DQ13
FBA_CKE_L J3 F11 FBA_CKE_L J3 F11
<27> FBA_CKE_L CKE# DQ22
DQ23
DQ14
DQ15
F13 CKE# DQ22
DQ23
DQ14
DQ15
F13 GDDR5
U11 FBA_D16 U11 FBA_D8
<27> FBA_MA2_BA0_L
FBA_MA2_BA0_L H11
K10 BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13
T11
FBA_D17 FBA_MA4_BA2_L H11
K10 BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13
T11
FBA_D9 Mode H - Mirror Mode Mapping
FBA_MA5_BA1_L FBA_D18 FBA_MA3_BA3_L FBA_D10
<27> FBA_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA4_BA2_L K11 T13 FBA_D19 FBA_MA2_BA0_L K11 T13 FBA_D11 BYTE1
<27> FBA_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA3_BA3_L H10 N11 FBA_D20 BYTE2 FBA_MA5_BA1_L H10 N11 FBA_D12 DATA Bus
<27> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 BA3/A3 BA1/A5 DQ12 DQ20
N13 FBA_D21 N13 FBA_D13
DQ13 DQ21 M11 DQ13 DQ21 M11 Address
DQ14 DQ22
FBA_D22
DQ14 DQ22
FBA_D14 0..31 32..63
FBA_MA7_MA8_L K4 M13 FBA_D23 FBA_MA0_MA10_L K4 M13 FBA_D15
<27> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_MA6_MA11_L H5 U4 FBx_CMD0 CS#
<27> FBA_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 A9/A1 A11/A6 DQ0 DQ24
FBA_MA0_MA10_L H4 U2 FBA_MA7_MA8_L H4 U2
<27> FBA_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25
FBA_MA6_MA11_L K5 T4 FBA_MA1_MA9_L K5 T4 FBx_CMD1 A3_BA3
<27> FBA_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 A11/A6 A9/A1 DQ2 DQ26
FBA_MA12_RFU_L J5 T2 FBA_MA12_RFU_L J5 T2
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4 FBx_CMD2 A2_BA0
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC DQ5 DQ29 M4 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30 FBx_CMD3 A4_BA2
2 RV115 1 M2 2 RV116 1 M2
DQ7 DQ31 DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
1K_0402_1%
+1.5VS_VGA
FBx_CMD4 A5_BA1
J1 J1
2 RV117 1 J10 MF 2 RV118 1 J10 MF
SEN SEN FBx_CMD5 WE#
2 RV119 1 1K_0402_1% J13 B1 2 RV120 1 1K_0402_1% J13 B1
ZQ VDDQ D1 ZQ VDDQ D1
121_0402_1%
VDDQ
121_0402_1%
VDDQ FBx_CMD6 A7_A8
F1 F1
J4 VDDQ M1 J4 VDDQ M1
Follow DG <27> FBA_ABI#_L
FBA_ABI#_L
ABI# VDDQ
FBA_ABI#_L
ABI# VDDQ FBx_CMD7 A6_A11
FBA_RAS#_L G3 P1 FBA_CAS#_L G3 P1
<27> FBA_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ
FBA_CS#_L G12 T1 FBA_WE#_L G12 T1 FBx_CMD8 ABI#
<27> FBA_CS#_L CS# WE# VDDQ CS# WE# VDDQ
FBA_CLK0 1 2 FBA_CAS#_L L3 G2 FBA_RAS#_L L3 G2
<27> FBA_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ
RV21 40.2_0402_1% FBA_WE#_L L12 L2 FBA_CS#_L L12 L2 FBx_CMD9 A12_RFU
<27> FBA_WE#_L WE# CS# VDDQ WE# CS# VDDQ
B3 B3
2

VDDQ D3 VDDQ D3
VDDQ VDDQ FBx_CMD10 A0_A10
RV123 F3 F3
D5 VDDQ H3 D5 VDDQ H3
160_0402_1% <27> FBA_WCK0_N
FBA_WCK0_N
WCK01# WCK23# VDDQ
FBA_WCK1_N
WCK01# WCK23# VDDQ FBx_CMD11 A1_A9
C @ FBA_WCK0 D4 K3 FBA_WCK1 D4 K3 C
<27> FBA_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3 FBx_CMD12 RAS#
1

FBA_CLK0# 1 2 FBA_WCK1_N P5 VDDQ P3 FBA_WCK0_N P5 VDDQ P3


<27> FBA_WCK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
RV28 40.2_0402_1% FBA_WCK1 P4 T3 FBA_WCK0 P4 T3 FBx_CMD13 RST#
<27> FBA_WCK1 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
VDDQ VDDQ FBx_CMD14 CKE#
A10 E10 A10 E10
CV155

+FBA_VREFD_L +FBA_VREFD_L
0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ


U10 N10 U10 N10 FBx_CMD15 CAS#
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
2 VDDQ VDDQ FBx_CMD16 CS#
F12 F12
VDDQ H12 VDDQ H12
VDDQ VDDQ FBx_CMD17 A3_BA3
FBA_RST#_L J2 K12 FBA_RST#_L J2 K12
<27> FBA_RST#_L RESET# VDDQ RESET# VDDQ
M12 M12 FBx_CMD18 A2_BA0
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
+1.5VS_VGA VDDQ VDDQ FBx_CMD19 A4_BA2
G13 G13
H1 VDDQ L13 H1 VDDQ L13
VSS VDDQ VSS VDDQ FBx_CMD20 A5_BA1
K1 B14 K1 B14
VSS VDDQ VSS VDDQ
1

B5 D14 B5 D14 FBx_CMD21 WE#


RV127 G5 VSS VDDQ F14 G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
549_0402_1%
VSS VDDQ VSS VDDQ FBx_CMD22 A7_A8
T5 P14 T5 P14
RV212 VSS VDDQ VSS VDDQ
B10 T14 B10 T14 FBx_CMD23 A6_A11
2

1 2 +FBA_VREFC0 D10 VSS VDDQ D10 VSS VDDQ


G10 VSS G10 VSS
931_0402_1% FBx_CMD24 ABI#
820P_0402_25V7

VSS VSS
1

L10 A1 L10 A1
CV42

1 16 mil VSS VSSQ VSS VSSQ


RV128 P10 C1 P10 C1 FBx_CMD25 A12_RFU
1.33K_0402_1% T10 VSS VSSQ E1 T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
2 VSS VSSQ VSS VSSQ FBx_CMD26 A0_A10
K14 R1 K14 R1
2

+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1


VSSQ VSSQ FBx_CMD27 A1_A9
H2 H2
G1 VSSQ K2 G1 VSSQ K2
VDD VSSQ VDD VSSQ FBx_CMD28 RAS#
L1 A3 L1 A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ FBx_CMD29 RST#
L4 E3 L4 E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
B
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD30 CKE# B
R5 R3 R5 R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ
FBx_CMD31 CAS#
R10 C4 R10 C4
VDD VSSQ VDD VSSQ
1

D11 R4 D11 R4
RV129 G11 VDD VSSQ F5 G11 VDD VSSQ F5
549_0402_1% L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
RV213 VDD VSSQ VDD VSSQ
G14 M10 G14 M10
2

1 2 +FBA_VREFD_L L14 VDD VSSQ C11 L14 VDD VSSQ C11


931_0402_1% VDD VSSQ R11 VDD VSSQ R11
820P_0402_25V7

VSSQ VSSQ
1

A12 A12
CV58

1 VSSQ VSSQ
RV130 C12 C12
VSSQ VSSQ
1

D 1.33K_0402_1% E12 E12


2 VSSQ N12 VSSQ N12
<23,29,30,31> MEM_VREF G 2 VSSQ R12 VSSQ R12
2

QV9 170-BALL VSSQ U12 170-BALL VSSQ U12


S
3

2N7002W-T/R7_SOT323-3 VSSQ H13 VSSQ H13


SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
X76@ X76@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV68

CV69

CV77

CV78

CV71

CV76

CV79

CV80
CV166

CV129

CV132

CV133

CV174

CV134

CV135

CV136
2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1

1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_GDDR5_A Lower


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 28 of 69

5 4 3 2 1
5 4 3 2 1

Memory - Upper 32 bits UV6


UV5
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 FBA_D56
A4 FBA_D32 FBA_EDC7 C2 DQ24 DQ0 A2 FBA_D57
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60
<27> FBA_D[63..32] EDC2 EDC1 DQ27 DQ3 BYTE4 EDC3 EDC0 DQ28 DQ4 BYTE7
R2 E4 FBA_D36 E2 FBA_D61
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37 DQ29 DQ5 F4 FBA_D62
DQ29 DQ5 F4 FBA_D38 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
<27> FBA_EDC[7..4] DQ30 DQ6 <27> FBA_DBI7# DBI0# DBI3# DQ31 DQ7
FBA_DBI4# D2 F2 FBA_D39 D13 A11
<27> FBA_DBI4# DBI0# DBI3# DQ31 DQ7 DBI1# DBI2# DQ16 DQ8
D13 A11 FBA_DBI5# P13 A13
DBI1# DBI2# DQ16 DQ8 <27> FBA_DBI5# DBI2# DBI1# DQ17 DQ9
D FBA_DBI6# P13 A13 P2 B11 D
<27> FBA_DBI6# DBI2# DBI1# DQ17 DQ9 DBI3# DBI0# DQ18 DQ10
P2 B11 B13
DBI3# DBI0# DQ18 DQ10 B13 FBA_CLK1 J12 DQ19 DQ11 E11
FBA_CLK1 J12 DQ19 DQ11 E11 FBA_CLK1# J11 CK DQ20 DQ12 E13
<27> FBA_CLK1 CK DQ20 DQ12 CK# DQ21 DQ13
FBA_CLK1# J11 E13 FBA_CKE_H J3 F11
<27> FBA_CLK1# CK# DQ21 DQ13 CKE# DQ22 DQ14
FBA_CKE_H J3 F11 F13
<27> FBA_CKE_H CKE# DQ22 DQ14 DQ23 DQ15
F13 U11 FBA_D40
DQ23 DQ15 U11 FBA_D48 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
FBA_MA2_BA0_H H11 DQ8 DQ16 U13 FBA_D49 FBA_MA3_BA3_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D42
<27> FBA_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA5_BA1_H K10 T11 FBA_D50 FBA_MA2_BA0_H K11 T13 FBA_D43 BYTE5
<27> FBA_MA5_BA1_H BA1/A5 BA3/A3 DQ10 DQ18 BA2/A4 BA0/A2 DQ11 DQ19
FBA_MA4_BA2_H K11 T13 FBA_D51 FBA_MA5_BA1_H H10 N11 FBA_D44
<27>
<27>
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA3_BA3_H H10 BA2/A4
BA3/A3
BA0/A2
BA1/A5
DQ11
DQ12
DQ19
DQ20
N11 FBA_D52 BYTE6 BA3/A3 BA1/A5 DQ12
DQ13
DQ20
DQ21
N13 FBA_D45 GDDR5
N13 FBA_D53 M11 FBA_D46

K4
DQ13
DQ14
DQ21
DQ22
M11
M13
FBA_D54 FBA_MA0_MA10_H K4
H5 A8/A7 A10/A0
DQ14
DQ15
DQ22
DQ23
M13
U4
FBA_D47 Mode H - Mirror Mode Mapping
FBA_MA7_MA8_H FBA_D55 FBA_MA6_MA11_H
<27> FBA_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 A9/A1 A11/A6 DQ0 DQ24
FBA_MA1_MA9_H H5 U4 FBA_MA7_MA8_H H4 U2
<27> FBA_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 A10/A0 A8/A7 DQ1 DQ25
FBA_MA0_MA10_H H4 U2 FBA_MA1_MA9_H K5 T4 DATA Bus
<27> FBA_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A11/A6 A9/A1 DQ2 DQ26
FBA_MA6_MA11_H K5 T4 FBA_MA12_RFU_H J5 T2
<27> FBA_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 A12/RFU/NC DQ3 DQ27
FBA_MA12_RFU_H J5 T2 N4 Address 0..31 32..63
<27> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 A5 N2
A5 DQ4 DQ28 N2 +1.5VS_VGA U5 VPP/NC DQ5 DQ29 M4
VPP/NC DQ5 DQ29 VPP/NC DQ6 DQ30
FBx_CMD0 CS#
U5 M4 2 RV132 1 M2
2 RV131 1 VPP/NC DQ6 DQ30 M2 DQ7 DQ31
DQ7 DQ31
1K_0402_1%
+1.5VS_VGA
FBx_CMD1 A3_BA3
1K_0402_1% J1
J1 +1.5VS_VGA 2 RV134 1 J10 MF
MF SEN FBx_CMD2 A2_BA0
2 RV133 1 J10 2 RV136 1 1K_0402_1% J13 B1
2 RV135 1 J13 SEN B1 ZQ VDDQ D1
1K_0402_1%
ZQ VDDQ
121_0402_1%
VDDQ
FBx_CMD3 A4_BA2
121_0402_1% D1 F1
VDDQ F1 J4 VDDQ M1
Follow DG VDDQ
FBA_ABI#_H
ABI# VDDQ
FBx_CMD4 A5_BA1
FBA_ABI#_H J4 M1 FBA_CAS#_H G3 P1
<27> FBA_ABI#_H ABI# VDDQ RAS# CAS# VDDQ
FBA_RAS#_H G3 P1 FBA_WE#_H G12 T1 FBx_CMD5 WE#
<27> FBA_RAS#_H RAS# CAS# VDDQ CS# WE# VDDQ
FBA_CS#_H G12 T1 FBA_RAS#_H L3 G2
<27> FBA_CS#_H CS# WE# VDDQ CAS# RAS# VDDQ
FBA_CLK1 1 2 FBA_CAS#_H L3 G2 FBA_CS#_H L12 L2 FBx_CMD6 A7_A8
<27> FBA_CAS#_H CAS# RAS# VDDQ WE# CS# VDDQ
RV31 40.2_0402_1% FBA_WE#_H L12 L2 B3
<27> FBA_WE#_H WE# CS# VDDQ VDDQ
B3 D3 FBx_CMD7 A6_A11
VDDQ VDDQ
2

D3 F3
VDDQ F3 D5 VDDQ H3
RV139
VDDQ
FBA_WCK3_N
WCK01# WCK23# VDDQ
FBx_CMD8 ABI#
C 160_0402_1% FBA_WCK2_N D5 H3 FBA_WCK3 D4 K3 C
<27> FBA_WCK2_N WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ
@ FBA_WCK2 D4 K3 M3 FBx_CMD9 A12_RFU
<27> FBA_WCK2 WCK01 WCK23 VDDQ VDDQ
M3 FBA_WCK2_N P5 P3
1

1 2 P5 VDDQ P3 P4 WCK23# WCK01# VDDQ T3


FBA_CLK1#
<27> FBA_WCK3_N
FBA_WCK3_N
WCK23# WCK01# VDDQ
FBA_WCK2
WCK23 WCK01 VDDQ
FBx_CMD10 A0_A10
RV36 40.2_0402_1% FBA_WCK3 P4 T3 E5
<27> FBA_WCK3 WCK23 WCK01 VDDQ VDDQ
E5 N5 FBx_CMD11 A1_A9
VDDQ N5 +FBA_VREFD_H A10 VDDQ E10
A10 VDDQ E10 U10 VREFD VDDQ N10
CV175

+FBA_VREFD_H FBx_CMD12 RAS#


0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ


U10 N10 +FBA_VREFC1 J14 B12
J14 VREFD VDDQ B12 VREFC VDDQ D12
+FBA_VREFC1
VREFC VDDQ VDDQ
FBx_CMD13 RST#
D12 F12
2 VDDQ F12 VDDQ H12
VDDQ VDDQ
FBx_CMD14 CKE#
H12 FBA_RST#_H J2 K12
J2 VDDQ K12 RESET# VDDQ M12
<27> FBA_RST#_H
FBA_RST#_H
RESET# VDDQ VDDQ
FBx_CMD15 CAS#
M12 P12
VDDQ P12 VDDQ T12
VDDQ VDDQ
FBx_CMD16 CS#
T12 G13
VDDQ G13 H1 VDDQ L13
VDDQ VSS VDDQ FBx_CMD17 A3_BA3
H1 L13 K1 B14
+1.5VS_VGA K1 VSS VDDQ B14 B5 VSS VDDQ D14
VSS VDDQ VSS VDDQ
FBx_CMD18 A2_BA0
B5 D14 G5 F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14 FBx_CMD19 A4_BA2
1

L5 VSS VDDQ M14 T5 VSS VDDQ P14


T5 VSS VDDQ P14 B10 VSS VDDQ T14
RV143
VSS VDDQ VSS VDDQ
FBx_CMD20 A5_BA1
549_0402_1% B10 T14 D10
D10 VSS VDDQ G10 VSS
RV214 VSS VSS
FBx_CMD21 WE#
G10 L10 A1
2

1 2 +FBA_VREFC1 L10 VSS A1 P10 VSS VSSQ C1


VSS VSSQ VSS VSSQ FBx_CMD22 A7_A8
931_0402_1% 16 mil P10 C1 T10 E1
820P_0402_25V7

VSS VSSQ VSS VSSQ


1

T10 E1 H14 N1
CV59

1 VSS VSSQ VSS VSSQ


FBx_CMD23 A6_A11
RV144 H14 N1 K14 R1
K14 VSS VSSQ R1 +1.5VS_VGA VSS VSSQ U1
1.33K_0402_1%
+1.5VS_VGA VSS VSSQ VSSQ
FBx_CMD24 ABI#
U1 H2
2 VSSQ H2 G1 VSSQ K2 FBx_CMD25 A12_RFU
2

G1 VSSQ K2 L1 VDD VSSQ A3


L1 VDD VSSQ A3 G4 VDD VSSQ C3
VDD VSSQ VDD VSSQ
FBx_CMD26 A0_A10
G4 C3 L4 E3
L4 VDD VSSQ E3 C5 VDD VSSQ N3
B VDD VSSQ VDD VSSQ FBx_CMD27 A1_A9 B
C5 N3 R5 R3
R5 VDD VSSQ R3 C10 VDD VSSQ U3
VDD VSSQ VDD VSSQ
FBx_CMD28 RAS#
C10 U3 R10 C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.5VS_VGA VDD VSSQ VDD VSSQ
FBx_CMD29 RST#
D11 R4 G11 F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
VDD VSSQ VDD VSSQ
FBx_CMD30 CKE#
L11 M5 P11 F10
VDD VSSQ VDD VSSQ
1

P11 F10 G14 M10 FBx_CMD31 CAS#


RV145 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV215 VSSQ VSSQ
A12 C12
2

1 2 +FBA_VREFD_H VSSQ C12 VSSQ E12


931_0402_1% VSSQ E12 VSSQ N12
820P_0402_25V7
1

VSSQ N12 VSSQ R12


CV60

1 VSSQ VSSQ
RV146 R12 170-BALL U12
VSSQ VSSQ
1

D 1.33K_0402_1% 170-BALL U12 H13


2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<23,28,30,31> MEM_VREF G 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
2

QV11 VSSQ A14 VSSQ C14


S
3

2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ E14


VSSQ E14 VSSQ N14
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ X76@
X76@
+1.5VS_VGA UV5 SIDE H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV6 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV84

CV81

CV82

CV83
CV179

CV138

CV142

CV137

2 1 1 1 1 1 1 1
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV187

CV87

CV88

CV85

CV86

CV145

CV143

CV144
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_GDDR5_A Upper


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 29 of 69

5 4 3 2 1
5 4 3 2 1

Memory Partition C - Lower 32 bits


UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBC_D0 A4 FBC_D24
FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1 FBC_EDC3 C2 DQ24 DQ0 A2 FBC_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D26
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D27
<27> FBC_D[0..31] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE0 R2 EDC2 EDC1 DQ27 DQ3 E4
FBC_D4 FBC_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 EDC3 EDC0 DQ28 DQ4 E2 FBC_D29
DQ29 DQ5 F4 FBC_D6 DQ29 DQ5 F4 FBC_D30
<27> FBC_EDC[3..0] FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7 FBC_DBI3# D2 DQ30 DQ6 F2 FBC_D31
D <27> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <27> FBC_DBI3# DBI0# DBI3# DQ31 DQ7 D
D13 A11 D13 A11
FBC_DBI2# P13 DBI1# DBI2# DQ16 DQ8 A13 FBC_DBI1# P13 DBI1# DBI2# DQ16 DQ8 A13
<27> FBC_DBI2# P2 DBI2# DBI1# DQ17 DQ9 B11 <27> FBC_DBI1# P2 DBI2# DBI1# DQ17 DQ9 B11
DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_CLK0 J12 DQ19 DQ11 E11
<27> FBC_CLK0 FBC_CLK0# J11 CK DQ20 DQ12 E13 FBC_CLK0# J11 CK DQ20 DQ12 E13
<27>
<27>
FBC_CLK0#
FBC_CKE_L
FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 FBC_CKE_L J3 CK#
CKE#
DQ21
DQ22
DQ13
DQ14
F11 GDDR5
F13 F13

FBC_MA2_BA0_L H11
DQ23
DQ8
DQ15
DQ16
U11
U13
FBC_D16
FBC_D17 FBC_MA4_BA2_L H11
DQ23
DQ8
DQ15
DQ16
U11
U13
FBC_D8
FBC_D9
Mode H - Mirror Mode Mapping
<27> FBC_MA2_BA0_L FBC_MA5_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D18 FBC_MA3_BA3_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D10
<27> FBC_MA5_BA1_L FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 FBC_MA2_BA0_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D11
<27> FBC_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 BA2/A4 BA0/A2 DQ11 DQ19 BYTE1 DATA Bus
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 FBC_MA5_BA1_L H10 N11 FBC_D12
<27> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D21 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D13
DQ13 DQ21 DQ13 DQ21
Address 0..31 32..63
M11 FBC_D22 M11 FBC_D14
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23 FBC_MA0_MA10_L K4 DQ14 DQ22 M13 FBC_D15
<27> FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD0 CS#
FBC_MA1_MA9_L H5 U4 FBC_MA6_MA11_L H5 U4
<27> FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA7_MA8_L H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD1 A3_BA3
FBC_MA6_MA11_L K5 T4 FBC_MA1_MA9_L K5 T4
<27> FBC_MA6_MA11_L FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA12_RFU_L J5 A11/A6 A9/A1 DQ2 DQ26 T2
<27> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27 FBx_CMD2 A2_BA0
N4 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
VPP/NC DQ5 DQ29 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD3 A4_BA2
U5 M4 U5 M4
2 RV147 1 VPP/NC DQ6 DQ30 M2 2 RV148 1 VPP/NC DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31 FBx_CMD4 A5_BA1
1K_0402_1% 1K_0402_1%
J1 +1.5VS_VGA J1 +1.5VS_VGA FBx_CMD5 WE#
2 RV149 1 J10 MF 2 RV150 1 J10 MF
2 RV151 1 J13 SEN B1 2 RV152 1 J13 SEN B1
1K_0402_1%
ZQ VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD6 A7_A8
121_0402_1% D1 121_0402_1% D1
VDDQ F1 VDDQ F1
VDDQ VDDQ FBx_CMD7 A6_A11
Follow DG FBC_ABI#_L J4 M1 FBC_ABI#_L J4 M1
<27> FBC_ABI#_L FBC_RAS#_L G3 ABI# VDDQ P1 FBC_CAS#_L G3 ABI# VDDQ P1
<27> FBC_RAS#_L RAS# CAS# VDDQ RAS# CAS# VDDQ FBx_CMD8 ABI#
FBC_CS#_L G12 T1 FBC_WE#_L G12 T1
FBC_CLK0 1 2 <27> FBC_CS#_L FBC_CAS#_L L3 CS# WE# VDDQ G2 FBC_RAS#_L L3 CS# WE# VDDQ G2
<27> FBC_CAS#_L CAS# RAS# VDDQ CAS# RAS# VDDQ FBx_CMD9 A12_RFU
RV37 40.2_0402_1% FBC_WE#_L L12 L2 FBC_CS#_L L12 L2
<27> FBC_WE#_L WE# CS# VDDQ B3 WE# CS# VDDQ B3
VDDQ VDDQ FBx_CMD10 A0_A10
2

C
D3 D3 C
VDDQ F3 VDDQ F3
RV155
VDDQ VDDQ FBx_CMD11 A1_A9
160_0402_1% FBC_WCK0_N D5 H3 FBC_WCK1_N D5 H3
<27> FBC_WCK0_N FBC_WCK0 D4 WCK01# WCK23# VDDQ K3 FBC_WCK1 D4 WCK01# WCK23# VDDQ K3
@
<27> FBC_WCK0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ FBx_CMD12 RAS#
M3 M3
1

FBC_CLK0# 1 2 FBC_WCK1_N P5 VDDQ P3 FBC_WCK0_N P5 VDDQ P3


<27> FBC_WCK1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ FBx_CMD13 RST#
RV39 40.2_0402_1% FBC_WCK1 P4 T3 FBC_WCK0 P4 T3
<27> FBC_WCK1 WCK23 WCK01 VDDQ E5 WCK23 WCK01 VDDQ E5
VDDQ VDDQ FBx_CMD14 CKE#
N5 N5
VDDQ VDDQ
CV195
0.01U_0402_25V7K

1 +FBC_VREFD_L A10 E10 +FBC_VREFD_L A10 E10 FBx_CMD15 CAS#


U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBC_VREFC0 J14 VREFD VDDQ B12 +FBC_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ VREFC VDDQ FBx_CMD16 CS#
D12 D12
2 VDDQ F12 VDDQ F12
VDDQ VDDQ FBx_CMD17 A3_BA3
H12 H12
FBC_RST#_L J2 VDDQ K12 FBC_RST#_L J2 VDDQ K12
<27> FBC_RST#_L RESET# VDDQ RESET# VDDQ FBx_CMD18 A2_BA0
M12 M12
VDDQ P12 VDDQ P12
VDDQ VDDQ FBx_CMD19 A4_BA2
T12 T12
+1.5VS_VGA VDDQ G13 VDDQ G13
VDDQ VDDQ FBx_CMD20 A5_BA1
H1 L13 H1 L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
VSS VDDQ VSS VDDQ FBx_CMD21 WE#
1

B5 D14 B5 D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
RV159
VSS VDDQ VSS VDDQ FBx_CMD22 A7_A8
549_0402_1% L5 M14 L5 M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
RV216 VSS VDDQ VSS VDDQ FBx_CMD23 A6_A11
B10 T14 B10 T14
2

1 2 +FBC_VREFC0 D10 VSS VDDQ D10 VSS VDDQ


VSS VSS FBx_CMD24 ABI#
820P_0402_25V7

931_0402_1% G10 G10


VSS VSS
1

CV61

1 L10 A1 L10 A1 FBx_CMD25 A12_RFU


RV160 P10 VSS VSSQ C1 P10 VSS VSSQ C1
T10 VSS VSSQ E1 T10 VSS VSSQ E1
1.33K_0402_1%
VSS VSSQ VSS VSSQ FBx_CMD26 A0_A10
H14 N1 H14 N1
2 K14 VSS VSSQ R1 K14 VSS VSSQ R1 FBx_CMD27 A1_A9
2

+1.5VS_VGA VSS VSSQ U1 +1.5VS_VGA VSS VSSQ U1


VSSQ H2 VSSQ H2
VSSQ VSSQ FBx_CMD28 RAS#
G1 K2 G1 K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
B VDD VSSQ VDD VSSQ FBx_CMD29 RST# B
G4 C3 G4 C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
VDD VSSQ VDD VSSQ FBx_CMD30 CKE#
C5 N3 C5 N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
+1.5VS_VGA VDD VSSQ VDD VSSQ FBx_CMD31 CAS#
C10 U3 C10 U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
VDD VSSQ VDD VSSQ
1

G11 F5 G11 F5
RV161 L11 VDD VSSQ M5 L11 VDD VSSQ M5
549_0402_1% P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
RV217 L14 VDD VSSQ C11 L14 VDD VSSQ C11
2

1 2 +FBC_VREFD_L VDD VSSQ R11 VDD VSSQ R11


VSSQ VSSQ
820P_0402_25V7

931_0402_1% A12 A12


VSSQ VSSQ
1

CV62

1 C12 C12
RV162 VSSQ E12 VSSQ E12
1.33K_0402_1% VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
VSSQ VSSQ
1

D 2 170-BALL U12 170-BALL U12


2

2 VSSQ H13 VSSQ H13


<23,28,29,31> MEM_VREF G SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
QV13 VSSQ A14 VSSQ A14
S
3

2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ C14


VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 +1.5VS_VGA VSSQ U14
VSSQ UV8 SIDE VSSQ
X76@ X76@
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.5VS_VGA UV7 SIDE
CV207

CV95

CV96

CV93

CV94

CV163

CV161

CV162
H5GQ1H24AFR-T2L_BGA170 2 1 1 1 1 1 1 1 H5GQ1H24AFR-T2L_BGA170
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV199

CV91

CV92

CV89

CV90

CV160

CV157

CV159

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

A A
1 2 2 2 2 2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_GDDR5_C Lower


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 30 of 69

5 4 3 2 1
5 4 3 2 1

Memory Partition C - Upper 32 bits


UV9

MF=0 MF=1 MF=1 MF=0 UV10

A4 FBC_D32 MF=0 MF=1 MF=1 MF=0


FBC_EDC4 C2 DQ24 DQ0 A2 FBC_D33
C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D34 A4 FBC_D56
FBC_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D35 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<27> FBC_D[63..32] R2 EDC2 EDC1 DQ27 DQ3 E4
BYTE4 C13 EDC0 EDC3 DQ25 DQ1 B4
FBC_D36 FBC_D58
EDC3 EDC0 DQ28 DQ4 E2 FBC_D37 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
DQ29 DQ5 F4 FBC_D38 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D60
<27> FBC_EDC[7..4] D2 DQ30 DQ6 F2 EDC3 EDC0 DQ28 DQ4 E2
BYTE7
FBC_DBI4# FBC_D39 FBC_D61
<27> FBC_DBI4# D13 DBI0# DBI3# DQ31 DQ7 A11 DQ29 DQ5 F4 FBC_D62
D DBI1# DBI2# DQ16 DQ8 DQ30 DQ6 D
FBC_DBI6# P13 A13 FBC_DBI7# D2 F2 FBC_D63
<27> FBC_DBI6# P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11 <27> FBC_DBI7# D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11 GDDR5
B13 FBC_DBI5# P13 A13
<27> FBC_CLK1
FBC_CLK1
FBC_CLK1#
J12
J11 CK
DQ19
DQ20
DQ11
DQ12
E11
E13
<27> FBC_DBI5# P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11
B13
Mode H - Mirror Mode Mapping
<27> FBC_CLK1# FBC_CKE_H J3 CK# DQ21 DQ13 F11 FBC_CLK1 J12 DQ19 DQ11 E11
<27> FBC_CKE_H CKE# DQ22 DQ14 F13 FBC_CLK1# J11 CK DQ20 DQ12 E13
DQ23 DQ15 CK# DQ21 DQ13 DATA Bus
U11 FBC_D48 FBC_CKE_H J3 F11
FBC_MA2_BA0_H H11 DQ8 DQ16 U13 FBC_D49 CKE# DQ22 DQ14 F13
<27> FBC_MA2_BA0_H BA0/A2 BA2/A4 DQ9 DQ17 DQ23 DQ15
Address 0..31 32..63
FBC_MA5_BA1_H K10 T11 FBC_D50 U11 FBC_D40
<27> FBC_MA5_BA1_H FBC_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D51 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
<27> FBC_MA4_BA2_H BA2/A4 BA0/A2 DQ11 DQ19 BA0/A2 BA2/A4 DQ9 DQ17 FBx_CMD0 CS#
FBC_MA3_BA3_H H10 N11 FBC_D52 BYTE6 FBC_MA3_BA3_H K10 T11 FBC_D42
<27> FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D53 FBC_MA2_BA0_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D43
DQ13 DQ21 BA2/A4 BA0/A2 DQ11 DQ19 BYTE5 FBx_CMD1 A3_BA3
M11 FBC_D54 FBC_MA5_BA1_H H10 N11 FBC_D44
FBC_MA7_MA8_H K4 DQ14 DQ22 M13 FBC_D55 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D45
<27> FBC_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 DQ13 DQ21 FBx_CMD2 A2_BA0
FBC_MA1_MA9_H H5 U4 M11 FBC_D46
<27> FBC_MA1_MA9_H FBC_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
<27> FBC_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25 A8/A7 A10/A0 DQ15 DQ23 FBx_CMD3 A4_BA2
FBC_MA6_MA11_H K5 T4 FBC_MA6_MA11_H H5 U4
<27> FBC_MA6_MA11_H FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_MA7_MA8_H H4 A9/A1 A11/A6 DQ0 DQ24 U2
<27> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 A10/A0 A8/A7 DQ1 DQ25 FBx_CMD4 A5_BA1
N4 FBC_MA1_MA9_H K5 T4
A5 DQ4 DQ28 N2 FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2
VPP/NC DQ5 DQ29 A12/RFU/NC DQ3 DQ27 FBx_CMD5 WE#
U5 M4 N4
2 RV163 1 VPP/NC DQ6 DQ30 M2 A5 DQ4 DQ28 N2
DQ7 DQ31 +1.5VS_VGA VPP/NC DQ5 DQ29 FBx_CMD6 A7_A8
1K_0402_1% U5 M4
J1 +1.5VS_VGA 2 RV164 1 VPP/NC DQ6 DQ30 M2
MF DQ7 DQ31 FBx_CMD7 A6_A11
2 RV165 1 J10 1K_0402_1%
2 RV167 1 J13 SEN B1 J1 +1.5VS_VGA
1K_0402_1%
ZQ VDDQ MF FBx_CMD8 ABI#
121_0402_1% D1 2 RV166 1 J10
VDDQ F1 2 RV168 1 J13 SEN B1
VDDQ
1K_0402_1%
ZQ VDDQ FBx_CMD9 A12_RFU
Follow DG FBC_ABI#_H J4 M1 121_0402_1% D1
<27> FBC_ABI#_H FBC_RAS#_H G3 ABI# VDDQ P1 VDDQ F1
<27> FBC_RAS#_H RAS# CAS# VDDQ VDDQ FBx_CMD10 A0_A10
FBC_CS#_H G12 T1 FBC_ABI#_H J4 M1
FBC_CLK1 1 2 <27> FBC_CS#_H FBC_CAS#_H L3 CS# WE# VDDQ G2 FBC_CAS#_H G3 ABI# VDDQ P1
<27> FBC_CAS#_H CAS# RAS# VDDQ RAS# CAS# VDDQ FBx_CMD11 A1_A9
RV41 40.2_0402_1% FBC_WE#_H L12 L2 FBC_WE#_H G12 T1
<27> FBC_WE#_H WE# CS# VDDQ B3 FBC_RAS#_H L3 CS# WE# VDDQ G2
VDDQ CAS# RAS# VDDQ FBx_CMD12 RAS#
2

D3 FBC_CS#_H L12 L2
VDDQ F3 WE# CS# VDDQ B3
C RV171
VDDQ VDDQ FBx_CMD13 RST# C
160_0402_1% FBC_WCK2_N D5 H3 D3
<27> FBC_WCK2_N FBC_WCK2 D4 WCK01# WCK23# VDDQ K3 VDDQ F3
@
<27> FBC_WCK2 WCK01 WCK23 VDDQ VDDQ FBx_CMD14 CKE#
M3 FBC_WCK3_N D5 H3
1

FBC_CLK1# 1 2 FBC_WCK3_N P5 VDDQ P3 FBC_WCK3 D4 WCK01# WCK23# VDDQ K3


<27> FBC_WCK3_N WCK23# WCK01# VDDQ WCK01 WCK23 VDDQ FBx_CMD15 CAS#
RV48 40.2_0402_1% FBC_WCK3 P4 T3 M3
<27> FBC_WCK3 WCK23 WCK01 VDDQ E5 FBC_WCK2_N P5 VDDQ P3
VDDQ WCK23# WCK01# VDDQ FBx_CMD16 CS#
N5 FBC_WCK2 P4 T3
VDDQ WCK23 WCK01 VDDQ
CV215
0.01U_0402_25V7K

1 +FBC_VREFD_H A10 E10 E5 FBx_CMD17 A3_BA3


U10 VREFD VDDQ N10 VDDQ N5
+FBC_VREFC1 J14 VREFD VDDQ B12 +FBC_VREFD_H A10 VDDQ E10
VREFC VDDQ VREFD VDDQ FBx_CMD18 A2_BA0
D12 U10 N10
2 VDDQ F12 +FBC_VREFC1 J14 VREFD VDDQ B12
VDDQ VREFC VDDQ FBx_CMD19 A4_BA2
H12 D12
FBC_RST#_H J2 VDDQ K12 VDDQ F12
<27> FBC_RST#_H RESET# VDDQ VDDQ FBx_CMD20 A5_BA1
M12 H12
VDDQ P12 FBC_RST#_H J2 VDDQ K12
VDDQ RESET# VDDQ FBx_CMD21 WE#
T12 M12
+1.5VS_VGA VDDQ G13 VDDQ P12
VDDQ VDDQ FBx_CMD22 A7_A8
H1 L13 T12
K1 VSS VDDQ B14 VDDQ G13
VSS VDDQ VDDQ FBx_CMD23 A6_A11
1

B5 D14 H1 L13
G5 VSS VDDQ F14 K1 VSS VDDQ B14
RV175
VSS VDDQ VSS VDDQ FBx_CMD24 ABI#
549_0402_1% L5 M14 B5 D14
T5 VSS VDDQ P14 G5 VSS VDDQ F14
RV218 VSS VDDQ VSS VDDQ FBx_CMD25 A12_RFU
B10 T14 L5 M14
2

1 2 +FBC_VREFC1 D10 VSS VDDQ T5 VSS VDDQ P14


VSS VSS VDDQ FBx_CMD26 A0_A10
820P_0402_25V7

931_0402_1% G10 B10 T14


VSS VSS VDDQ
1

CV63

1 L10 A1 D10 FBx_CMD27 A1_A9


RV176 P10 VSS VSSQ C1 G10 VSS
T10 VSS VSSQ E1 L10 VSS A1
1.33K_0402_1%
VSS VSSQ VSS VSSQ FBx_CMD28 RAS#
H14 N1 P10 C1
2 K14 VSS VSSQ R1 T10 VSS VSSQ E1 FBx_CMD29 RST#
2

+1.5VS_VGA VSS VSSQ U1 H14 VSS VSSQ N1


VSSQ H2 K14 VSS VSSQ R1
VSSQ +1.5VS_VGA VSS VSSQ FBx_CMD30 CKE#
G1 K2 U1
L1 VDD VSSQ A3 VSSQ H2
VDD VSSQ VSSQ FBx_CMD31 CAS#
B
G4 C3 G1 K2 B
L4 VDD VSSQ E3 L1 VDD VSSQ A3
C5 VDD VSSQ N3 G4 VDD VSSQ C3
+1.5VS_VGA R5 VDD VSSQ R3 L4 VDD VSSQ E3
C10 VDD VSSQ U3 C5 VDD VSSQ N3
R10 VDD VSSQ C4 R5 VDD VSSQ R3
VDD VSSQ VDD VSSQ
1

D11 R4 C10 U3
RV177 G11 VDD VSSQ F5 R10 VDD VSSQ C4
549_0402_1% L11 VDD VSSQ M5 D11 VDD VSSQ R4
P11 VDD VSSQ F10 G11 VDD VSSQ F5
RV219 G14 VDD VSSQ M10 L11 VDD VSSQ M5
2

1 2 +FBC_VREFD_H L14 VDD VSSQ C11 P11 VDD VSSQ F10


VDD VSSQ VDD VSSQ
820P_0402_25V7

931_0402_1% R11 G14 M10


VSSQ VDD VSSQ
1

CV64

1 A12 L14 C11


RV178 VSSQ C12 VDD VSSQ R11
1.33K_0402_1% VSSQ E12 VSSQ A12
VSSQ N12 VSSQ C12
VSSQ VSSQ
1

D 2 R12 E12
2

2 170-BALL VSSQ U12 VSSQ N12


<23,28,29,30> MEM_VREF G VSSQ H13 VSSQ R12
QV15 SGRAM GDDR5 VSSQ K13 170-BALL VSSQ U12
S
3

2N7002W-T/R7_SOT323-3 VSSQ A14 VSSQ H13


VSSQ C14 SGRAM GDDR5 VSSQ K13
VSSQ E14 VSSQ A14
VSSQ N14 VSSQ C14
VSSQ R14 VSSQ E14
VSSQ U14 VSSQ N14
VSSQ +1.5VS_VGA VSSQ R14
UV10 SIDE VSSQ U14
X76@
+1.5VS_VGA VSSQ
UV9 SIDE
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
H5GQ1H24AFR-T2L_BGA170 X76@
CV227

CV103

CV104

CV101

CV102

CV170

CV168

CV169
2 1 1 1 1 1 1 1
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

H5GQ1H24AFR-T2L_BGA170
CV245

CV99

CV100

CV97

CV98

CV167

CV164

CV165

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

1 2 2 2 2 2 2 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_GDDR5_C Upper


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 31 of 69

5 4 3 2 1
5 4 3 2 1

B+_SLI
follow MXM 3.0 spec

JSLI1
D D
1 2
3 GND GND 4
5 NC GND 6
7 NC GND 8
9 NC GND 10
11 NC +19V 12
13 NC +19V 14
15 NC +19V 16
17 NC +19V 18
PCIE_CTX_C_GRX_N15 19 GND +19V 20
PCIE_CTX_C_GRX_P15 21 PEG_RX_N7 +19V 22
PEG_RX_P7 +19V
23 24
PCIE_CTX_C_GRX_N14 25 GND +19V 26
PCIE_CTX_C_GRX_P14 27 PEG_RX_N6 GND 28 +5VS_SLI
29 PEG_RX_P6 GND 30
31 GND GND 32
PCIE_CTX_C_GRX_N13 33 GND GND 34
PCIE_CTX_C_GRX_P13 35 PEG_RX_N5 GND 36
37 PEG_RX_P5 GND 38
PCIE_CTX_C_GRX_N12 39 GND +5V 40
PCIE_CTX_C_GRX_P12 41 PEG_RX_N4 +5V 42
43 PEG_RX_P4 +5V 44
PCIE_CTX_C_GRX_N11 45 GND +5V 46
PCIE_CTX_C_GRX_P11 47 PEG_RX_N3 +5V 48
49 PEG_RX_P3 GND 50
PCIE_CTX_C_GRX_N10 51 GND GND 52
PCIE_CTX_C_GRX_P10 53 PEG_RX_N2 GND +3VS_SLI +3VS
PEG_RX_P2
55 54
PCIE_CTX_C_GRX_N9 57 GND NC 56
C PCIE_CTX_C_GRX_P9 59 PEG_RX_N1 +3V 58 C
61 PEG_RX_P1 +3V 60
PCIE_CTX_C_GRX_N8 63 GND GND 62
PCIE_CTX_C_GRX_P8 65 PEG_RX_N0 NC 64
67 PEG_RX_P0 NC 66 SLI_B+_ON#
GND NC SLI_B+_ON# <56>
69 68 SLI_5V_ON#
GND NC SLI_5V_ON# <56>
PCIE_CRX_GTX_N15 0.22U_0402_10V6K 2 1 CV20 PCIE_CRX_C_GTX_N15 71 70 SUSP#
PEG_TX_N7 NC SUSP# <46,55,60,61,62>
PCIE_CRX_GTX_P15 0.22U_0402_10V6K 2 1 CV22 PCIE_CRX_C_GTX_P15 73 72
75 PEG_TX_P7 NC 74 SLI_FAN_SPEED
GND TH_TACH SLI_FAN_SPEED <44,46>
PCIE_CRX_GTX_N14 0.22U_0402_10V6K 2 1 CV16 PCIE_CRX_C_GTX_N14 77 76 SLI_FAN_PWM
PEG_TX_N6 TH_PWN SLI_FAN_PWM <44,46>
PCIE_CRX_GTX_P14 0.22U_0402_10V6K 2 1 CV18 PCIE_CRX_C_GTX_P14 79 78
81 PEG_TX_P6 NC 80
PCIE_CRX_GTX_N13 0.22U_0402_10V6K 2 1 CV19 PCIE_CRX_C_GTX_N13 83 GND PEX_STD_SW# 82 VGA_AC_DET_R
PEG_TX_N5 AC_DC VGA_AC_DET_R <23>
PCIE_CRX_GTX_P13 0.22U_0402_10V6K 2 1 CV14 PCIE_CRX_C_GTX_P13 85 84 S_DGPU_PWROK
PEG_TX_P5 PWR_GOOD S_DGPU_PWROK <16,54>
87 86 S_DGPU_PWR_EN#
GND PWR_EN S_DGPU_PWR_EN# <55>
PCIE_CRX_GTX_N12 0.22U_0402_10V6K 2 1 CV15 PCIE_CRX_C_GTX_N12 89 88 CLK2_REQ_GPU#_R
PEG_TX_N4 CLK_REQ# CLK2_REQ_GPU#_R <16>
PCIE_CRX_GTX_P12 0.22U_0402_10V6K 2 1 CV17 PCIE_CRX_C_GTX_P12 91 90 S_NVDD_PWR_EN
PEG_TX_P4 RSVD S_NVDD_PWR_EN <19,54>
93 92 S_DGPU_RST S_DGPU_RST <16,54>
PCIE_CRX_GTX_N11 0.22U_0402_10V6K 2 1 CV12 PCIE_CRX_C_GTX_N11 95 GND RSVD 94
PEG_TX_N3 NC SLAVE_PRESENT# <19>
PCIE_CRX_GTX_P11 0.22U_0402_10V6K 2 1 CV13 PCIE_CRX_C_GTX_P11 97 96 PCH_THRMTRIP#_R
PEG_TX_P3 TH_OVERT# PCH_THRMTRIP#_R <19,23>
99 98 PLT_RST# PLT_RST# <14,23,40,41,46>
PCIE_CRX_GTX_N10 0.22U_0402_10V6K 2 1 CV10 PCIE_CRX_C_GTX_N10 101 GND NC 100 GC6_EVENT_SLI# RV158 1 @ 2 0_0402_5%
PEG_TX_N2 RSVD S_GC6_EVENT# <54>
PCIE_CRX_GTX_P10 0.22U_0402_10V6K 2 1 CV11 PCIE_CRX_C_GTX_P10 103 102 EC_SMB_DA2
PEG_TX_P2 SMB_DAT EC_SMB_DA2 <17,23,34,36,43,46>
105 104 EC_SMB_CK2
GND SMB_CLK EC_SMB_CK2 <17,23,34,36,43,46>
PCIE_CRX_GTX_N9 0.22U_0402_10V6K 2 1 CV8 PCIE_CRX_C_GTX_N9 107 106
PCIE_CRX_GTX_P9 0.22U_0402_10V6K 2 1 CV9 PCIE_CRX_C_GTX_P9 109 PEG_TX_N1 WAKE# 108 GC6_SLI_EN
111 PEG_TX_P1 RSVD 110 S_DGPU_PWR_EN
GND RSVD S_DGPU_PWR_EN <19,54,55>
PCIE_CRX_GTX_N8 0.22U_0402_10V6K 2 1 CV6 PCIE_CRX_C_GTX_N8 113 112
PCIE_CRX_GTX_P8 0.22U_0402_10V6K 2 1 CV7 PCIE_CRX_C_GTX_P8 115 PEG_TX_N0 GND 114 CLK_PCIE_2VGA#
PEG_TX_P0 CLK_PCIE_N CLK_PCIE_2VGA# <16>
117 116 CLK_PCIE_2VGA
GND CLK_PCIE_P CLK_PCIE_2VGA <16>
118
GND
B 119 120 B
121 GND GND 122 RV234 1 2 0_0402_5% RV173 1 @ 2 0_0402_5%
GND GND S_GC6_EN <27,54>
@

TE_2199022-1_118P-T ME@

PCIE_CTX_C_GRX_N[0..15]
<23,5> PCIE_CTX_C_GRX_N[0..15]
11/11 for 2nd VGA fan PCIE_CTX_C_GRX_P[0..15]
need to notic EC <23,5> PCIE_CTX_C_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
<23,5> PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
<23,5> PCIE_CRX_GTX_P[0..15]

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 VGA MXM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 32 of 69

5 4 3 2 1
5 4 3 2 1

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE

2
RV92 RV93 RV94 RV121 RV122 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
45.3K_0402_1% @ 4.99K_0402_1% 30K_0402_1% 4.99K_0402_1% 20K_0402_1%
GT1@ @ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
D D

1
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP4
<24> STRAP4 CHANGE_GEN3
2

2
@ Pull-up to
@ RV95 RV96 RV97 RV124 RV125 Resistor Values Pull-down to Gnd
SLOT_CLK_CFG
45.3K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1%
+3VS_VGA
45.3K_0402_1%
GT@ 5K 1000 0000 0 GPU and MCH don't share a common reference clock
1

1
10K 1001 0001
1 GPU and MCH share a common reference clock (Default)
15K 1010 0010
20K 1011 0011
25K 1100 0100 SUB_VENDOR
30K 1101 0101
0 No VBIOS ROM (Default)
35K 1110 0110
+3VS_VGA 45K 1
C 1111 0111 BIOS ROM is present C

3GIO_PADCFG XCLK_417 USER Straps


2

RV98 RV99 RV100 3GIO_PADCFG[3:0] 0 277MHz (Default) User[3:0]


4.99K_0402_1% 10K_0402_1% 4.99K_0402_1%
@
@ 2012-0418--> Set BOM 0000 Notebook Default 1 Reserved 1000-1100 Customer defined
1

structure as Stuff for ALL SKU

<24> ROM_SI ROM_SI PEX_PLL_EN_TERM PCIE_MAX_SPEED FB_0_BAR_SIZE


<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK 0 Disable (Default) 0 Limit to PCIE Gen1 0 Reserved
2

1 Enable 1 PCIE Gen 2/3 Capable 1 Reserved


2

RV101 RV103
X76 20K_0402_1% RV102 RV103
X76@ 2 256MB (Default)
30K_0402_1%
@
4.99K_0402_1% SMBUS_ALT_ADDR VGA_DEVICE
1

GT1@
1

GT@ 0 0x9E (Default) 0 3D Device (Class Code 302h) 3 Reserved


15K_0402_1%
B B
1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

X76

GPU FB Memory (GDDR5) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 VRAM X76 VRAM P/N

K4G20325FD-FC04 2G 64Mx32 PD 30K X76409JVL01 (2G 64Mx32) SA00005B70J


Samsung Samsung
PD 15K
K4G10325FG-HC04 1G 32Mx32 PD 45K (ROM not present) X76409JVL51 (1G 32Mx16) SA00003RS0J
N13P-GT1 PU 10K PU 45K PD 5K PD 25K PU 5K PD 45K
28nm EOL PD 35K
H5GQ2H24MFR-T2C 2G 64Mx32 PD 25K (ROM present) X76409JVL02 (2G 64Mx32) SA00004GD0J EOL

Hynix H5GQ1H24BFR-T2C 1G 32Mx32 PD 20K Hynix X76409JVL02 (2G 64Mx32) SA00004GD1J


A A
H5GQ2H24AFR-T2C 2G 64Mx32 PD 25K X76409JVL52 (1G 32Mx16) SA00003WL1J

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 N13P_MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 33 of 69

5 4 3 2 1
5 4 3 2 1

Use BLM18KG331SN1 Use BLM18KG331SN1 Use BLM18KG331SN1


Close Pin14
+3VS +3.3VS_DTL +3.3VS_DTL
LT4 BLM18PG331SN1D_2P LT1 BLM18PG331SN1D_2P LT3 BLM18PG331SN1D_2P
LT2
2 1 1 2 VDDIO_DTL 1 2 VDDIOX_DTL SW_OUT 1 2 VDD12_DTL1 2 VDDRX_DTL 1.2V
RT1270 0_0402_5%
2.2UH_HPC252012F-2R2M_1.3A_20%
1 1 1 1 1 1
Use 2.2uH 800mA
CT5 CT6 CT10 CT4 CT2 CT9
D 0.47U_0402_6.3V6K 1U_0402_6.3V6K 0.47U_0402_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 1U_0402_6.3V6K D
2 2 2 2 2 2
GND of 4.7uF capacitor
Close Pin12,13 behind Inductor.

CT12 0.1U_0402_10V7K UT3


2 1 VDDRX_DTL 53 LVDS_A0_NVS
VDDRX_DTL 6 TA0p 54 LVDS_A0#_NVS LVDS_A0_NVS <35>
13 VDDRX TA0n LVDS_A0#_NVS <35>
2 1 VDDIOX_DTL
VDDIOX_DTL 14 VDDIOX 51 LVDS_A1_NVS
Close Pin6 VDDIOX TB0p LVDS_A1_NVS <35>
CT11 0.01U_0402_16V7K VDD12_DTL 19 52 LVDS_A1#_NVS

38
VDD12 PS8625 TB0n
48
LVDS_A1#_NVS <35>
VDDIO_DTL LVDS_A2_NVS 0.1U_0402_10V7K CT30
VDDIO_DTL 50 VDDIO TC0p 49 LVDS_A2#_NVS LVDS_A2_NVS <35> EDP_AUX#_C 1 2 EDP@ EDP_AUX#_CON
CT22 0.1U_0402_10V7K LVDS_A2#_NVS <35> EDP_AUX#_CON <35>
2 1 VDDIO TC0n
VDD12_DTL
46 LVDS_ACLK_NVS LVDS_ACLK_NVS <35> 0.1U_0402_10V7K CT31
EDP_AUX# 1 TCK0p 47 LVDS_ACLK#_NVS EDP_AUX_C 1 2 EDP@ EDP_AUX_CON
2 1 Close Pin19 LVDS_ACLK#_NVS <35>
2 DAUXn TCK0n EDP_AUX_CON <35>
EDP_AUX
DAUXp 43 0.1U_0402_10V7K CT32
CT13 0.01U_0402_16V7K
EDP_TX0+ 4 TD0p 44 EDP_TX0+_C 1 2 EDP@ EDP_TX0+_CON
EDP_TX0- 5 DRX0p TD0n EDP_TX0+_CON <35>
DRX0n 41 LVDS_B0_NVS 0.1U_0402_10V7K CT33
EDP_TX1+ 7 TA1p 42 LVDS_B0#_NVS LVDS_B0_NVS <35> EDP_TX0-_C 1 2 EDP@ EDP_TX0-_CON
EDP_TX1- 8 DRX1p TA1n LVDS_B0#_NVS <35> EDP_TX0-_CON <35>
DRX1n 39 LVDS_B1_NVS 0.1U_0402_10V7K CT34
CT8 0.1U_0402_10V7K LVDS_B1_NVS <35>
2 1 VDDIO_DTL EDP_HPD 11 TB1p 40 LVDS_B1#_NVS EDP_TX1+_C 1 2 EDP@ EDP_TX1+_CON
<38> EDP_HPD HPD TB1n LVDS_B1#_NVS <35> EDP_TX1+_CON <35>
2 1 VDDIO_DTL INVT_PWM 45 36 LVDS_B2_NVS 0.1U_0402_10V7K CT35
<35> INVT_PWM DTL_RST# 9 PWMI TC1p 37 LVDS_B2#_NVS LVDS_B2_NVS <35> EDP_TX1-_C 1 2 EDP@ EDP_TX1-_CON
10 RST# TC1n LVDS_B2#_NVS <35> EDP_TX1-_CON <35>
CT7 0.1U_0402_10V7K Close Pin38,50 DTL_PD#
PD# 34 LVDS_BCLK_NVS
C TL_INVPWM 12
PWMO
TCK1p
TCK1n
35 LVDS_BCLK#_NVS
LVDS_BCLK_NVS
LVDS_BCLK#_NVS
<35>
<35>
Close to JLVDS1 C
Noe: ENPVCC_I2C_ADDR 33
GPIO0 21 ENPVCC 31
LVDS output swing control
RLV_CFG 22 RLV_LNK/GPIO0 TD1p 32
4.99K for default swing, change the value for
RT2 10K_0402_5% EN_BACKLIGHT 23 RLV_CFG TD1n
swing adjust ENBLT
CT3 1 2 VDDIO_DTL 30 EDID_DAT_CON
2 1 DTL_PD# RT14 4.99K_0402_1% DDC_SDA 29 EDID_CLK_CON
2 1 REXT 26 DDC_SCL 24 CSDA/MSDA
1U_0402_6.3V6K 2 1 RLV_AMP 27 REXT CSDA/MSDA 25 CSCL/MSCL
20 RLV_AMP CSCL/MSCL
RT1 10K_0402_5% RT9 4.99K_0402_1% TESTMODE 17
CT1 1 2 VDDIO_DTL SW_OUT 15 GNDX 18 +3.3VS_DTL
2 1 DTL_RST# SW_OUT 16 SW_OUT GNDX 28
SW_OUT GND 3
2.2U_0402_6.3V6M 55 GND
NC

1
56
NC RT12 RT13
CT17 0.1U_0402_10V7K 57 2K_0402_5% 2K_0402_5%
EDP_AUX#_C 2 1 EDP_AUX# Epad
<38> EDP_AUX#_C
PS8625QFN56GTR-A0_QFN56_7X7

2
CT18 0.1U_0402_10V7K
EDP_AUX_C 2 1 EDP_AUX
<38> EDP_AUX_C
EDID_DAT_CON
EDID_CLK_CON EDID_DAT_CON <35>
CT19 0.1U_0402_10V7K
EDP_TX0+_C 2 1 EDP_TX0+ EDID_CLK_CON <35>
<38> EDP_TX0+_C To LVDS
ENPVCC_I2C_ADDR
ENPVCC_I2C_ADDR <35> panel
CT16 0.1U_0402_10V7K
EDP_TX0-_C 2 1 EDP_TX0- EDP_HPD RT1268 1 EDP@ 2 0_0402_5% EDP_HPD_CON EN_BACKLIGHT
<38> EDP_TX0-_C EDP_HPD_CON <35> EN_BACKLIGHT <35>
CT15 0.1U_0402_10V7K
EDP_TX1+_C 2 1 EDP_TX1+ TL_INVPWM
<38> EDP_TX1+_C TL_INVPWM <35>
CT14 0.1U_0402_10V7K
EDP_TX1-_C 2 1 EDP_TX1-
B <38> EDP_TX1-_C B

Power On Configuration
Close to UT3
Initial Code EEPROM
VDDIO_DTL
1

+3.3VS_DTL
RT6 VDDIO_DTL VDDIO_DTL RT8 @ 4.7K_0402_5%
RA 4.7K_0402_5% 1 2 CSCL/MSCL
1

@ RT3 DAUL@ RT10 RT7 @ 4.7K_0402_5%


2

RLV_CFG RC 4.7K_0402_5% RD 4.7K_0402_5% 1 2 CSDA/MSDA


1

RT15 ENPVCC_I2C_ADDR GPIO0


RB 4.7K_0402_5%
@
GPIO0: LVDS single link or dual link selection, internal pull-down ~80K
2

+3.3VS_DTL
@ UT2
8 1
Default ENPVCC_I2C_ADDR RC Default GPIO0 RD GPIO0 7 VCC A0 2
Default RLV_CFG RA RB NA EC_SMB_CK2 RT1272 1 2 0_0402_5% CSCL/MSCL 6 WP A1 3
H:0x90h~0x9Fh Stuff * Single channel <17,23,32,36,43,46> EC_SMB_CK2 SCL A2
H:6-bit both VESA NA EC_SMB_DA2 RT1271 1 2 0_0402_5% CSDA/MSDA 5 4
* and JEIDA mapping
Stuff
NA Stuff <17,23,32,36,43,46> EC_SMB_DA2 SDA GND
* L:0x10h~0x1Fh Daul channel
M:8-bit JEIDA mapping NA Stuff M24C08-WMN6TP_SO8

L:8-bit VESA mapping NA NA I2C_CFG = "H"


EEPROM for Initial Code
RLV_CFG: LVDS color depth and data I2C_ADDR: I2C Slave address selection, internal pull-down ~80K I2C Address: 0xA0
A mapping selection, internal pull-down ~80K A
Suggest minimum 8Kbit

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 LVDS/ CMOS/ USB-ReDriver


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 34 of 69
5 4 3 2 1
5 4 3 2 1

JLVDS1 ME@
EDID_CLK_CON 1 2 EDP_AUX#_CON +CMOS_PW
<34>
<34>
EDID_CLK_CON
EDID_DAT_CON EDID_DAT_CON 3
5
1
3
2
4
4
6
EDP_AUX_CON
EDP_AUX#_CON
EDP_AUX_CON
<34>
<34>
CMOS Camera
<34> TL_INVPWM 7 5 6 8 Q94 AO3413_SOT23-3 R432
LVDS_BCLK_NVS EDP_TX0+_CON W=40mils
<34> LVDS_BCLK_NVS 9 7 8 10 EDP_TX0+_CON <34> (40 MIL) 0_0603_5%
LVDS_BCLK#_NVS EDP_TX0-_CON
<34> LVDS_BCLK#_NVS EDP_TX0-_CON <34> 3 1 1 2

D
LVDS_B2_NVS 11 9 10 12 +3VS +CMOS_PW_R
<34> LVDS_B2_NVS LVDS_B2#_NVS 13 11 12 14 EDP_TX1+_CON 1 CMOS@ 1

10U_0603_6.3V6M
C519
<34> LVDS_B2#_NVS 15 13 14 16 EDP_TX1+_CON <34> CMOS@ CMOS@
LVDS_B1_NVS EDP_TX1-_CON
<34> LVDS_B1_NVS 15 16 EDP_TX1-_CON <34> C518

G
LVDS_B1#_NVS 17 18 EDP_HPD_CON

2
<34> LVDS_B1#_NVS 17 18 EDP_HPD_CON <34> 1 1 0.1U_0402_16V4Z
<34> LVDS_B0_NVS LVDS_B0_NVS 19 20 C1051 @ C1052 @ 2 2 @
LVDS_B0#_NVS 21 19 20 22 0.1U_0402_16V4Z
<34> LVDS_B0#_NVS 23 21 22 24 @
R822 2 1 4.7K_0402_5%
+3VS 0.01U_0402_16V7K
LVDS_ACLK_NVS 25 23 24 26 2 2
<34> LVDS_ACLK_NVS 25 26
<34> LVDS_ACLK#_NVS LVDS_ACLK#_NVS 27 28 DISPOFF# 2 1 BKOFF# CMOS@
29 27 28 30 BKOFF# <46> 1 R435 2
LVDS_A2_NVS +3VS 0_0402_5% R891
<34> LVDS_A2_NVS 31 29 30 32 <19> CMOS_ON#
LVDS_A2#_NVS W=60mils
<34> LVDS_A2#_NVS 33 31 32 34 100K_0402_5% 1
D LVDS_A1_NVS +LCDVDD_CON 1 D
<34> LVDS_A1_NVS 33 34

680P_0402_50V7K
LVDS_A1#_NVS 35 36 C529 2 1 C520
<34> LVDS_A1#_NVS 37 35 36 38 EN_BACKLIGHT <34>
LVDS_A0_NVS 0_0402_5% R823 0.1U_0402_16V4Z
<34> LVDS_A0_NVS 39 37 38 40 @
<34> LVDS_A0#_NVS LVDS_A0#_NVS +LEDVDD @ 2 CMOS@
41 39 40 42 2
GND1GND2
(60 MIL)

ACES_87142-4041-BS
+LEDVDD B+
2A 80 mil 2A 80 mil
1 R813 2
1 1 R_short 0_0805_5%
C523 C58
470P_0603_50V8J C524 @
4.7U_0805_25V6-K 2 1
2 2
0.047U_0402_16V4Z
9/23 EMI Request
W=40mils JCMOS1
+CMOS_PW 1
USB20_N0_CMOS 2 1
USB20_N0 R1166 1 2 0_0402_5% USB20_N0_CMOS USB20_P0_CMOS 3 2
<18> USB20_N0 3
<18> USB20_P0 USB20_P0 R1167 1 2 0_0402_5% USB20_P0_CMOS +3VS
4
5 4
<45> DMIC_CLK 5
<45> DMIC_DATA
6
L74 7 6
USB20_N0 2 1 USB20_N0_CMOS 8 7
2 1 8
9
USB20_P0 3 4 USB20_P0_CMOS 10 GND
3 4 GND
WCM-2012-900T_4P
ME@
@

C C

LCDVDD
+3VS +LCDVDD_CON
U76
5 1
IN VOUT

1U_0402_6.3V6K

150_0603_1%
2
GND

4.7U_0603_6.3V6K

CV283
R818
1 1
C291 4 3
DIS EN

2 NCT3521U 2

eDP to LVDS
R1202 1 2 0_0402_5%
<34> ENPVCC_I2C_ADDR

R1198 1 2 0_0402_5%
GPU <23> VGA_ENVDD
@
D61 @
2
1
R1196 1 2 0_0402_5% 3
PCH <14> PCH_ENVDD
@

2
DAN202UT106_SC70-3 R828
B 100K_0402_5% B

1
R1515
TL_INVPWM 1 2

@
0_0402_5%
R826 1 2
<23> VGA_BL_PWM
0_0402_5%

D60
2
1 INVT_PWM
INVT_PWM <34>
R1197 1 2 3
<14> PCH_EDP_PWM
0_0402_5%
2

DAN202UT106_SC70-3 R829
100K_0402_5%
1

EMI request ESD request


D59 @
DMIC_CLK TL_INVPWM USB20_P0_CMOS 4 1 DMIC_DATA
R834 1 2 I/O3 I/O1
470P_0402_50V7K

470P_0402_50V7K
<23> VGA_ENBKL
0_0402_5% DISPOFF#
100P_0402_50V8J

1 C525
5 2
C934

D62 1@ 1@ +3VS
2 C527 VDD GND
A
1 ENBKL A
1 2 3 ENBKL <46> 2
<14> PCH_ENBKL 2 2 6 3
R1212 0_0402_5% USB20_N0_CMOS DMIC_CLK
I/O4 I/O2
DAN202UT106_SC70-3
2

AZC099-04S.R7G_SOT23-6
R827
100K_0402_5%
1

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 LVDS/ CMOS/ USB-ReDriver


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LVDS LOAD SWITCH
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.9mS Typical Rise time ,Rds_on 80m ohm MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 35 of 69
5 4 3 2 1
A B C D E

CRT Connector
+CRT_VCC
+5VS +CRT_VCC_CON
D36
F1
2 1 1 2 +CRT_VCC_CON
1
RB491D_SC59-3 0.5A_8V_KMC3S050RY
C536

1
W=40mils 2
0.1U_0402_16V4Z
1

<14> CRT_DET#

JCRT1
6
CRT_DET# 11
L16 1 2 NBQ100505T-800Y_0402 CRT_R_CON 1
<37> DAC_RED_1
7
From CRT SW CRT_DDC_DAT_CON 12
L17 1 2 NBQ100505T-800Y_0402 CRT_G_CON 2
<37> DAC_GRN_1
8
HSYNC_CON 13
L18 1 2 NBQ100505T-800Y_0402 CRT_B_CON 3
<37> DAC_BLU_1
9

1
1 1 1 1 1 1 VSYNC_CON 14
4
R830 R831 R832 C537 C538 C539 C540 C542 C541 10 G 16
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J CRT_DDC_CLK_CON 15 G 17
2 2 2 2 2 2 5

2
1
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J C543 SUYIN_070546HR015M22BZR
CLOSE TO CONN
100P_0402_50V8J ME@
2

2 2
+CRT_VCC
R833
1 2
1
C544 OE# 1K_0402_5%
0.1U_0402_16V4Z
2

1
R840 NBQ100505T-800Y_0402

OE#
P
2 4 CRT_HSYNC_1 1 2 CRT_HSYNC_2 1 2 HSYNC_CON
<37> HSYNC_G A Y
33_0603_5% L19

G
U24
SN74AHCT1G125DCKR_SC70-5 1

3
@ D7 @
C545 CRT_R_CON 3 6 CRT_G_CON
10P_0402_50V8J I/O2 I/O4
+CRT_VCC 2
From CRT SW
2 5 +CRT_VCC_CON
GND VDD
1
C546 OE#
0.1U_0402_16V4Z CRT_DET# 1 4 CRT_B_CON
2 I/O1 I/O3
5

1
AZC099-04S.R7G_SOT23-6
R839 NBQ100505T-800Y_0402

OE#
P
2 4 CRT_VSYNC_1 1 2 CRT_VSYNC_2 1 2 VSYNC_CON
3 <37> VSYNC_G A Y 3
33_0603_5% L20
G

U25 1 D31 @
SN74AHCT1G125DCKR_SC70-5 VSYNC_CON 3 6 HSYNC_CON
3

+3VS @ C547 I/O2 I/O4


10P_0402_50V8J
+CRT_VCC 2
2 5 +CRT_VCC_CON
GND VDD
1

1
2.2K_0402_5%

CRT_DDC_CLK_CON 1 4 CRT_DDC_DAT_CON
5

I/O1 I/O3
G

R837 R838
2.2K_0402_5%
AZC099-04S.R7G_SOT23-6
2

<37> CRT_DDC_DATA_R CRT_DDC_DATA_R R1189 1 2 0_0402_5% DDC_DAT_R 4 3 CRT_DDC_DAT_CON


D
S
2
G

From SW Q73B
CRT_DDC_CLK_R R1190 1 2 0_0402_5% 2N7002KDW H_SOT363-6
<37> CRT_DDC_CLK_R
DDC_CLK_R 1 6 CRT_DDC_CLK_CON
D
S

<17,23,32,34,43,46> EC_SMB_DA2 EC_SMB_DA2 R1191 1 2 0_0402_5% Q73A 1 1


@ 2N7002KDW H_SOT363-6 @ @
C548 C549
100P_0402_50V8J 68P_0402_50V8K
EC_SMB_CK2 R1192 1 2 0_0402_5% 2 2
<17,23,32,34,43,46> EC_SMB_CK2
4
@ 4

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 36 of 69

A B C D E
2 1

+3VS +3VS_HDSW +3VS_HDSW RA RB +3VS_HDSW RC RD +3VS_HDSW RE RF


0_0402_5% CM2 4.7U_0603_6.3V6K RM13 @ RM14 @ RM15 @ RM16 @ RM18 @ RM17 @
2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2
RM25
CM3 0.01U_0402_16V7K 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
1 2
DDC_BUF IN1_PEQ IN2_PEQ

SEL DDC_BUF RA RB SEL IN1_PEQ/IN2_PEQ RC RD RE RF


UHM1 +3VS_HDSW H:Active DDC buffer H: High level receiving
enable, setting 1 Stuff NA equalization selection Stuff NA Stuff NA

6 M:Active DDC buffer M: Low level receiving


VDD 31 NA Stuff NA Stuff NA Stuff
VDD enable, setting 2 equalization selection

L: No DDC active L: Middle level


PWDN_ASQ
25 PWDN_ASQ * buffer, passive NA NA * receiving equalization NA NA NA NA
CM4 1 2 0.1U_0402_10V6K CPU_HDMI_TX0-_C 44 DDC level shifting selection
<8> CPU_HDMI_TX0- IN1_D1n
CM5 1 2 0.1U_0402_10V6K CPU_HDMI_TX0+_C 45 28 CFG_HPD
<8> CPU_HDMI_TX0+ IN1_D1p CFG_HPD
CM6 1 2 0.1U_0402_10V6K CPU_HDMI_TX1-_C 47 DDCBUF DDC_BUF_EN = L: No DDC active IN1_PEQ/IN2_PEQ: Rx Equalization Setting for
<8> CPU_HDMI_TX1- IN1_D2n
CM7 1 2 0.1U_0402_10V6K CPU_HDMI_TX1+_C 48 40 DDC_BUF buffer, passive DDC level shifting port1/port2.Internal pull-down ~500K ohm
<8> CPU_HDMI_TX1+ IN1_D2p DDCBUF
CM8 1 2 0.1U_0402_10V6K CPU_HDMI_TX2-_C 1 34 PRE_EMI
<8> CPU_HDMI_TX2- IN1_D3n PRE_EMI
CM9 1 2 0.1U_0402_10V6K CPU_HDMI_TX2+_C 2 7
<8> CPU_HDMI_TX2+ IN1_D3p RTERM
CM10 1 2 0.1U_0402_10V6K CPU_HDMI_CLK-_C 4 +3VS_HDSW RG RH +3VS_HDSW RI RJ
<8> CPU_HDMI_CLK- IN1_D4n
CM11 1 2 0.1U_0402_10V6K CPU_HDMI_CLK+_C 5
<8> CPU_HDMI_CLK+ IN1_D4p RM19 @ RM20 @ RM21 @ RM22 @
1 2 1 2 1 2 1 2

B 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% B

CM12 1 2 0.1U_0402_10V6K GPU_HDMI_TX0-_C 8 PRE_EMI CFG_HPD


<24> GPU_HDMI_TX0- IN2_D1n
CM13 1 2 0.1U_0402_10V6K GPU_HDMI_TX0+_C 9
<24> GPU_HDMI_TX0+ IN2_D1p
CM14 1 2 0.1U_0402_10V6K GPU_HDMI_TX1-_C 11 SEL PRE_EMI RG RH SEL CFG_HPD RI RJ
<24> GPU_HDMI_TX1- IN2_D2n
CM15 1 2 0.1U_0402_10V6K GPU_HDMI_TX1+_C 12 36 VGA_HDMI_TX0- VGA_HDMI_TX0- <39> H: Pre-emphasis H: IN1_HPD=OUT_HPD SW_DDC=L/
<24> GPU_HDMI_TX1+ IN2_D2p OUT_D1n
CM16 1 2 0.1U_0402_10V6K GPU_HDMI_TX2-_C 13 35 VGA_HDMI_TX0+ VGA_HDMI_TX0+ <39> added, no EMI control Stuff NA IN2_HPD=OUT_HPD SW_DDC=H Stuff NA
<24> GPU_HDMI_TX2- IN2_D3n OUT_D1p
CM17 1 2 0.1U_0402_10V6K GPU_HDMI_TX2+_C 14 33 VGA_HDMI_TX1- VGA_HDMI_TX1- <39> IN1_HPD=LOW otherwise /
<24> GPU_HDMI_TX2+ IN2_D3p OUT_D2n IN2_HPD=LOW otherwise
CM18 1 2 0.1U_0402_10V6K GPU_HDMI_CLK-_C 16 32 VGA_HDMI_TX1+ VGA_HDMI_TX1+ <39> M: No pre-emphasis,
<24> GPU_HDMI_CLK- IN2_D4n OUT_D2p
CM19 1 2 0.1U_0402_10V6K GPU_HDMI_CLK+_C 17 30 VGA_HDMI_TX2- VGA_HDMI_TX2- <39> EMI control selected NA Stuff
<24> GPU_HDMI_CLK+ IN2_D4p OUT_D3n 29 VGA_HDMI_TX2+ VGA_HDMI_TX2+ <39> M: IN1_HPD=OUT_HPD when SW_DDC=L or SW_MAIN=L /
OUT_D3p 27 VGA_HDMI_CLK- IN2_HPD=OUT_HPD when SW_DDC=H or SW_MAIN=H NA Stuff
OUT_D4n VGA_HDMI_CLK- <39> L: No pre-emphasis,
OUT_D4p
26 VGA_HDMI_CLK+ VGA_HDMI_CLK+ *
<39> no EMI control NA NA IN1_HPD=LOW otherwise / IN2_HPD=LOW otherwise

L: IN1_HPD=OUT_HPD when SW_MAIN=L /


46 PRE_EMI: TMDS output drive pre-emphasis and IN2_HPD=OUT_HPD when SW_MAIN=H NA NA
<14> TMDS_B_HPD 10 IN1_HPD
<23,39> DGPU_HDMI_HPD IN2_HPD
EMI setting, Internal pull-down ~500K ohm * IN1_HPD=LOW
IN2_HPD=LOW
otherwise /
otherwise
DDPB_CLK 41
<14> DDPB_CLK IN1_SCL
DDPB_DATA 42
<14> DDPB_DATA IN1_SDA
19 CFG_HPD: HPD switching configuration.
<24> GPU_HDMI_CLK 20 IN2_SCL
<24> GPU_HDMI_DATA Internal pull-down ~500K
IN2_SDA
HDSW_DDC 22 39 HDMI_CONN_HPD
<19> HDSW_DDC SW_DDC OUT_HPD HDMI_CONN_HPD <39>
HDSW_MAIN 21 38 VGA_HDMI_CLK +3VS_HDSW RK RL
<19> HDSW_MAIN SW_MAIN OUT_SCL VGA_HDMI_CLK <39>
37 VGA_HDMI_DATA
OUT_SDA VGA_HDMI_DATA <39>
RM23 @ RM24 @
IN1_PEQ 3 1 2 1 2
IN2_PEQ 15 IN1_PEQ
IN2_PEQ 4.7K_0402_5% 4.7K_0402_5%

23 PWDN_ASQ
24 CEXT
REXT +3VS SEL PWDN_ASQ RG RH
1

1 H: power down
CM1 RM26 Stuff NA

1
2.2U_0603_6.3V6K 430_0402_1% 18
43 GND RM1
2 49 GND L: Normal operation NA NA
0_0402_5% *
2

PAD
PS8271QFN48GTR-A1_QFN48_7X7 PWDN_ASQ: Power down control. Internal pull-down

2
~500K

1U_0603_10V6K
1 UM1

CM1183
HDSW_MAIN 1 2 HDSW_DDC
+3VS_HDSW RM33 0_0402_5% 4 1
16 VDD A0 2 DAC_RED_1 <36>
2 23 VDD A1 5 DAC_GRN_1 <36>
RM27 4.7K_0402_5%
1 2 29 VDD A2 6 DAC_BLU_1 <36>
HDSW_DDC For PS8271: R35/R36 NC
For PS8272: R35/R36 NC, pin21/pin22 NC or SW_MAIN/SW_DDC driven to LOW 32 VDD A3 7 CRT_DDC_CLK_R <36>
For PS8273: R35/R36 stuff or SW_MAIN/SW_DDC driven to HIGH VDD A4 CRT_DDC_DATA_R <36>
RM28 4.7K_0402_5%
1 2 HDSW_MAIN 27 8 CRT_SWITCH_1
<23> VGA_CRT_R 25 0B1 SEL1 CRT_SWITCH_1 <13>
<23> VGA_CRT_G 22 1B1
RM29 2.2K_0402_5%
1 2 <23> VGA_CRT_B 20 2B1 9
DDPB_CLK <23> VGA_CRT_CLK
18 3B1 A5 10 HSYNC_G <36>
RM30 2.2K_0402_5% Channel A --> GPU <23>
<23>
VGA_CRT_DATA
VGA_CRT_HSYNC
12 4B1
5B1
A6 VSYNC_G <36>
1 2 DDPB_DATA 14 30 CRT_SWITCH_1
<23> VGA_CRT_VSYNC 6B1 SEL2 For reserved CRT SW
26
<14> PCH_CRT_R 24 0B2
SW Input Output <14> PCH_CRT_G 21 1B2 3
<14> PCH_CRT_B 19 2B2 GND 11
<14> PCH_CRT_DDC_CLK 3B2 GND
A 17 28 A

SW_DDC IN1---CPU L=IN1 Channel B --> PCH <14>


<14>
PCH_CRT_DDC_DAT
PCH_CRT_HSYNC
13 4B2
5B2
GND
GND
31
15 33
<14> PCH_CRT_VSYNC 6B2 GPAD
IN2---GPU H=IN2
PI3V712-AZLEX_TQFN32_6X3
SW_MAIN IN1---CPU L=IN1
IN2---GPU H=IN2
Input SELx Input/Output An Function

L nB1--GPU An=nB1

H nB2---PCH An=nB2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDMI and CRT SW


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 37 of 69
2 1
5 4 3 2 1

D D

+3VS

1
RM2
0_0402_5%

2
U79

1U_0603_10V6K
CPU_EDP_TX0+ 31 3 1
<8> CPU_EDP_TX0+ D0+A VDD

CM1184
CPU_EDP_TX0- 30 9
<8> CPU_EDP_TX0- CPU_EDP_TX1+ 27 D0-A VDD 12
<8> CPU_EDP_TX1+ CPU_EDP_TX1- 26 D1+A VDD 16
<8> CPU_EDP_TX1- D1-A VDD 20 2
CPU_EDP_AUX 19 VDD 29
<8> CPU_EDP_AUX 18 AUX+A VDD
CPU_EDP_AUX#
<8> CPU_EDP_AUX# 17 AUX-A
C <8> CPU_EDP_HPD HPD_A 1 C
25 D0+ 2 EDP_TX0+_C <34>
<24> VGA_EDP_TX0+ 24 D0+B D0- 4 EDP_TX0-_C <34>
<24> VGA_EDP_TX0- 23 D0-B D1+ 5 EDP_TX1+_C <34>
<24> VGA_EDP_TX1+ 22 D1+B D1- EDP_TX1-_C <34>
<24> VGA_EDP_TX1- D1-B 6
15 AUX+ 7 EDP_AUX_C <34>
<24> VGA_EDP_AUX 14 AUX+B AUX- 8 EDP_AUX#_C <34>
<24> VGA_EDP_AUX# 13 AUX-B HPD EDP_HPD <34>
<23> VGA_EDP_HPD HPD_B 10
21 SEL 11 EDP_SEL <15>
28 GND OE# 32
33 GND AUX_SEL EDP_AUX_SEL <16>
GPAD

PI3VDP3212ZLEX_TQFN32_6X3

OE# SEL AUX_SEL FUNCTION


L L L PORT A
L L H PORT A-HS, PORT B-HPD/AUX
L H L PORT B-HS, PORT A-HPD/AUX
L H H PORT B
B H X X IC POWER DOWN B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 LVDS/ CMOS/ USB-ReDriver


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 38 of 69
5 4 3 2 1
5 4 3 2 1

W CM2012F2SF-900T04_4P
HDMI_CLK+_R 4 3 HDMI_CLK+_CON 1 2
4 3 C1016 3.3P_0402_50V8C
@
HDMI_CLK-_R 1 2 HDMI_CLK-_CON 1 2
1 2 C1015 3.3P_0402_50V8C
L23
@
L24
+5VS
HDMI_TX0+_R 1 2 HDMI_TX0+_CON 1 2
1 2 C1018 3.3P_0402_50V8C VGA_HDMI_CLK
<37> VGA_HDMI_CLK
D @ D
HDMI_TX0-_R 4 3 HDMI_TX0-_CON 1 2
4 3 C1017 3.3P_0402_50V8C
W CM2012F2SF-900T04_4P @ VGA_HDMI_DATA
<37> VGA_HDMI_DATA
W CM2012F2SF-900T04_4P
HDMI_TX1+_R 4 3 HDMI_TX1+_CON 1 2
4 3 C1020 3.3P_0402_50V8C
@

0.1U_0402_16V4Z
HDMI_TX1-_R 1 2 HDMI_TX1-_CON 1 2 C659 1 1 C562
1 2 C1019 3.3P_0402_50V8C
L26
@ 2200P_0402_50V7K
2 2
L27 +3VS
HDMI_TX2+_R 1 2 HDMI_TX2+_CON 1 2 U78
1 2

1
C1022 3.3P_0402_50V8C

VIN

APL3517AI-TRG_SOT23-3
@
HDMI_TX2-_R 4 3 HDMI_TX2-_CON 1 2

2
4 3 C1021 3.3P_0402_50V8C
W CM2012F2SF-900T04_4P R862 +5VS
@ 1M_0402_5%
SA00004ZB0J

2
G
Q85

VOUT
1

GND
R1486 1 2 3 1
<37> HDMI_CONN_HPD
0_0402_5%

3
2N7002_SOT23

2
20120829 VA1
Change net name for add HDMI MUX R885 @

1
20K_0402_5% D38
C BAT54S-7-F_SOT23-3 C
R320

1
499_0402_1% +CRT_VCC_CON
R1505

2
HDMI_CLK+_CON 1 2
@ R1499 +CRT_VCC_CON 2 1 +5VS_HDMI
HDMI_CLK-_CON 1 2 @ 0_0402_5%
R321 @ 499_0402_1%
0_0402_5% 1 C561
HDMI_TX0+_CON 1 2 0.1U_0402_16V4Z
for NV recommend

2
R322 @ 499_0402_1% @
HDMI_TX0-_CON 1 2 L67
R323 @ 499_0402_1% R860 R861 2
BLM18PG181SN1D_0603
HDMI_TX1+_CON 1 2 R859 2 @ 1 HDMI_DET_R 2 1 2.2K_0402_5% 2.2K_0402_5%
R324 @ 499_0402_1% <23,37> DGPU_HDMI_HPD @

1
HDMI_TX1-_CON 1 2 1K_0402_5%

1
R325 @ 499_0402_1%

R864
100K_0402_5%
HDMI_TX2+_CON 1 2 1
R326 @ 499_0402_1% @ C59
HDMI_TX2-_CON 1 2
@
220P_0402_25V8J JHDMI1
R327 @ 499_0402_1% D 2 HDMI_DET 19
1

2
18 HP_DET
2 Q114 17 +5V
+3VS DDC/CEC_GND
G 2N7002H 1N_SOT23-3 VGA_HDMI_DATA 16
S@ VGA_HDMI_CLK 15 SDA
3

1 @ 2 14 SCL
R328 100K_0402_5% 13 Reserved
VGA_HDMI_CLK- R300 1 2 0_0402_5% HDMI_CLK-_R R866 1 @ 2 0_0402_5% HDMI_CLK-_CON 12 CEC 20
<37> VGA_HDMI_CLK- CK- GND
11 21
VGA_HDMI_CLK+ R301 1 2 0_0402_5% HDMI_CLK+_R R865 1 @ 2 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND 22
<37> VGA_HDMI_CLK+ CK+ GND
<37> VGA_HDMI_TX0- VGA_HDMI_TX0- R302 1 2 0_0402_5% HDMI_TX0-_R R868 1 @ 2 0_0402_5% HDMI_TX0-_CON 9 23
B 8 D0- GND B
VGA_HDMI_TX0+ R303 1 2 0_0402_5% HDMI_TX0+_R R867 1 @ 2 0_0402_5% HDMI_TX0+_CON 7 D0_shield
<37> VGA_HDMI_TX0+ D0+
<37> VGA_HDMI_TX1- VGA_HDMI_TX1- R304 1 2 0_0402_5% HDMI_TX1-_R R870 1 @ 2 0_0402_5% HDMI_TX1-_CON 6
5 D1-
VGA_HDMI_TX1+ R305 1 2 0_0402_5% HDMI_TX1+_R R869 1 @ 2 0_0402_5% HDMI_TX1+_CON 4 D1_shield
<37> VGA_HDMI_TX1+ D1+
<37> VGA_HDMI_TX2- VGA_HDMI_TX2- R306 1 2 0_0402_5% HDMI_TX2-_R R872 1 @ 2 0_0402_5% HDMI_TX2-_CON 3
2 D2-
VGA_HDMI_TX2+ R307 1 2 0_0402_5% HDMI_TX2+_R R871 1 @ 2 0_0402_5% HDMI_TX2+_CON 1 D2_shield
<37> VGA_HDMI_TX2+ D2+
TAITW _PDVBR0-19FLBS4NN4N0
ME@
Close to JHDMI1
D57 @ D32 @ D33 @
VGA_HDMI_CLK 3 6 HDMI_DET HDMI_CLK+_CON 1 1 10 9HDMI_CLK+_CON HDMI_TX2-_CON 1 1 10 9HDMI_TX2-_CON
I/O2 I/O4
HDMI_CLK-_CON 2 2 9 8HDMI_CLK-_CON HDMI_TX2+_CON 2 2 9 8HDMI_TX2+_CON

2 5 HDMI_TX0-_CON 4 4 7 7HDMI_TX0-_CON HDMI_TX1+_CON 4 4 7 7HDMI_TX1+_CON


GND VDD
HDMI_TX0+_CON 5 5 6 6HDMI_TX0+_CON HDMI_TX1-_CON 5 5 6 6HDMI_TX1-_CON 46@

VGA_HDMI_DATA 1 4 +5VS_HDMI 3 3 3 3
I/O1 I/O3
AZC099-04S.R7G_SOT23-6 8 8

A HDMI+HDCP A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 39 of 69

5 4 3 2 1
A B C D E

Mini-Express Card(WLAN/WiMAX) 9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
+3VS_WLAN LPC_FRAME#_R R873 1 @ 2 0_0402_5% LPC_FRAME#
1 2 LPC_FRAME# <17,46>
LPC_AD3_R R874 @ 0_0402_5% LPC_AD3
LPC_AD3 <17,46>
LPC_AD2_R R875 1 @ 2 0_0402_5% LPC_AD2
1 2 LPC_AD2 <17,46>
LPC_AD1_R R876 @ 0_0402_5% LPC_AD1

For RF request
+1.5VS LPC_AD1 <17,46>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <17,46>
PCI_RST#_R R879 1 @ 2 0_0402_5% PLT_RST#

0.047U_0402_16V4Z
+1.5VS CLK_PCI_DB
1 CLK_PCI_DB <16>

C57

1
@ R400 1 1
1 2 1
0_0603_5% @ @
C564 C565
<41,46,55> LAN_WAKE# R1620 1 @ 2 0_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
JWLN1 2 2
COMBT@ <15,19,41> PCIE_WAKE# PCIE_WAKE# 1 2
3 WAKE# 3.3V 4
BT_CTRL R897 1 2 0_0402_5% BT_CTRL_R 5 NC GND 6 +1.5VS_WLAN
WLAN_CLKREQ1# 7 NC 1.5V 8 LPC_FRAME#_R
<16> WLAN_CLKREQ1# CLKREQ# NC
9 10 LPC_AD3_R
1 2 BT_DISABLE# 11 GND NC 12 LPC_AD2_R
<16> CLK_PCIE_WLAN# REFCLK- NC
13 14 LPC_AD1_R +3VS +3VS_WLAN
R1556 <16> CLK_PCIE_WLAN 15 REFCLK+ NC 16 LPC_AD0_R
1K_0402_5% PCI_RST#_R 17 GND NC 18 J8

@
CLK_PCI_DB 19 NC GND 20 WL_OFF# R880 1 2 0_0402_5%
COMBT@ NC NC PCH_WL_OFF# <14> 1 2
21 22 PLT_RST# 1 2
GND PERST# PLT_RST# <14,23,32,41,46>
For isolate Intel Rainbow Peak and <18> PCIE_PRX_DTX_N5
23
PERn0 +3.3Vaux
24 R881 1 2 @ 0_0402_5%
+3VALW
25 26 R882 1 2 R_short 0_0402_5% JUMP_43X79
Compal debug card. <18> PCIE_PRX_DTX_P5 PERp0 GND +3VS_WLAN
27 28 +3VALW
29 GND +1.5V 30 SMB_CLK_S3_R R883 1 2 @ 0_0402_5% Q104
GND SMB_CLK SMB_CLK_S3 <11,12,17,47>
31 32 SMB_DATA_S3_R R884 1 2 @ 0_0402_5% SMB_DATA_S3 <11,12,17,47> AO3413_SOT23-3
<18> PCIE_PTX_C_DRX_N5 PETn0 SMB_DATA
33 34

D
<18> PCIE_PTX_C_DRX_P5 PETp0 GND 3 1 1
For EMI 35 36
+3VS_WLAN GND USB_D- USB20_N10 <18> AOAC@
R125 10_0402_5% 37 38
1 2 39 NC USB_D+ 40 USB20_P10 <18> 1 C533
CLK_PCI_DB @ AOAC@ 1
NC GND 0.1U_0402_16V4Z

G
@ 41 42

2
1 NC LED_WWAN# C526 2
43 44 0.1U_0402_16V4Z C1048
@ C199 100_0402_1% 45 NC LED_WLAN# 46 2 0.01U_0402_25V7K
@
R887 47 NC LED_WPAN# 48 AOAC@ 2
2 EC_TX 1 2 49 NC +1.5V 50 1 R436 2 1
<46> EC_TX NC GND <46> AOAC_ON#
EC_RX 1 2 BT_DISABLE# 51 52
10P_0402_50V8J
<46> EC_RX
R888 NC +3.3V WLAN&BT Combo module circuits 100K_0402_5%
C1055
100_0402_1% 53 54 BT on module BT on module 0.1U_0402_16V4Z
GND GND 2
Enable Disable
R1557 COMBT@
<19> PCH_BT_DISABLE# 1 2 BT_CTRL TAITW_PFPET0-AFGLBG1ZZ4N0
softstart (RC) will check on EVT PCB

2
0_0402_5%
R889 ME@ * BT_CRTL (GPIO22) H L
6

2
D D 100K_0402_5% 2
<19> PCH_BT_ON# 2 5 SUSP <10,55,61>
Q157A

Q157B

G G PCH_BT_ON#
2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

For EC to detect L H

1
S S
debug card insert.
1

@ @ 9/18 Increase for Intel AOAC function

NGFF(SSD) SATA_PTX_DRX_P0
C574
1 2
0.01U_0402_16V7K
SATA_PTX_C_DRX_P0_R
R898
1
0_0402_5%
2 SATA_ITX_DRX_P0_R
<13> SATA_PTX_DRX_P0
C575 0.01U_0402_16V7K R899 0_0402_5%
<13> SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 1 2 SATA_PTX_C_DRX_N0_R 1 2 SATA_ITX_DRX_N0_R
+3VS_SSD
R903 0_0402_5% C571 0.01U_0402_16V7K
0.1U_0402_16V4Z 10U_0805_10V6K SATA_PRX_DTX_P0 1 2 SATA_PRX_DTX_P0_R 1 2 SATA_DTX_IRX_P0_R

1 1 1 1
SSD Active:4.5W(1.5A) R904 0_0402_5% C570 0.01U_0402_16V7K
@ SATA_PRX_DTX_N0 1 2 SATA_PRX_DTX_N0_R 1 2 SATA_DTX_IRX_N0_R
C566 C567 C568 C569
+3VS +3VS_SSD
2 2 2 2
J5
0.01U_0402_25V7K 10U_0805_10V6K 1 2
1 2

JUMP_43X79
ME@ @
JSSD1
1 2
3
3 CONFIG_3 3.3VAUX1 4 3
5 GND1 3.3VAUX2 6
7 GND2 FULL_CARD_POWER_OFF# 8
9 USB_D+ W_DISABLE#1 10 +3VS
11 USBD- LED#1/DAS/DSS#
GND3 NC 12
13 NC NC 14
15 NC NC 16
17 NC NC 18
@ 20
19 NC GPIO_5
1

2 R906 1 21 22
0_0402_5% 23 CONFIG_0 GPIO_6 24 RR6 +3VS
WAKE_ON_WWAN# GPIO_7
1

25 26 4.7K_0402_5%
DPR W_DISABLE#2

CR1

CR2
27 28 RR4 RR5
GND4 UIM-RFU

1
29 30 @ 4.7K_0402_5% @ 4.7K_0402_5% 1 1

0.1U_0402_16V4Z
2

USB3.0-TX-(Device) UIM-RESET

0.01U_0402_16V7K
31 32 @ RR1 @ @ RR2 RR3
33 USB3.0-TX+(Device) UIM-CLK 34 @ 4.7K_0402_5%
4.7K_0402_5% 4.7K_0402_5%
2

35 GND5 UIM-DATA 36 R907


37 USB3.0-RX-(Device) UIM-PWR 38 1 2 UR1 @ 2 2 @ @

2
39 USB3.0-RX+(Device) DEVSLP 40 0_0402_5% 7 10
SATA_DTX_IRX_P0_R 41 GND6 GPIO_0 42 @ EN VDD1 20
SATA_DTX_IRX_N0_R 43 PERN0/SATA-B+ GPIO_1 44 SATA_PTX_C_DRX_P0 1 VDD2
PERP0/SATA-B- GPIO_2 <13> SATA_PTX_C_DRX_P0 A_INp
45 46 SATA_PTX_C_DRX_N0 2 6
GND7 GPIO_3 <13> SATA_PTX_C_DRX_N0 A_INn NC1
SATA_ITX_DRX_N0_R 47 48 0.01U_0402_16V7K 16
SATA_ITX_DRX_P0_R 49 PETN0/SATA-A- GPIO_4 50 SATA_PRX_DTX_P0 2 @ C572 SATA_DTX_IRX_P0
@1 5 NC2
51 PETP0/SATA-A+ PERST# 52 <13> SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 2 1 C573 SATA_DTX_IRX_N0 4 B_OUTp 9
53 GND8 CLKREQ# 54 <13> SATA_PRX_DTX_N0 @ B_OUTn A_PRE0 8
55 REFCLKN PEWAKE# 56 0.01U_0402_16V7K 19 B_PRE0 @
57 REFCLKP NC1 58 17 A_PRE1 15 SATA_ITX_DRX_P0_C CR3 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P0_R
59 GND9 NC2 60 B_PRE1 A_OUTp 14 SATA_ITX_DRX_N0_C CR4 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N0_R
61 ANTCTL0 COEX3 62 18 A_OUTn @ @
63 ANTCTL1 COEX2 64 3 TEST 11 SATA_DTX_IRX_P0_C CR5 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P0_R
65 ANTCTL2 COEX1 66 13 GND1 B_INp 12 SATA_DTX_IRX_N0_C CR6 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0_R
67 ANTCTL3 SIM_DETECT 68 21 GND2 B_INn @
SATA_DET# 1 2 69 RESET# SUSCLK 70 EPAD
<13> SATA_DET# R896 0_0402_5% 71 CONFIG_1 3.3VAUX3 72 PS8520CTQFN20GTR2A0_TQFN20_4X4
73 GND10 3.3VAUX4 74
For SSD use: @
GND11 3.3VAUX5
75
CONFIG_2
4 4
76 77
PEG1 PEG2

TYCO_2199230-3

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Mini-Card


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 40 of 69

A B C D E
5 4 3 2 1

+3VALW +3VALW_LAN
J16
1 2
1 2

@
+LX
JUMP_43X79 Close together
QL1
3 1 RL2 0_0603_5% LL1 SH00000GT0J

D
+1.1_DVDDL 1 2 +LX_R 1 2 +LX SH00000JM0J

1000P_0402_50V7K

10U_0805_10V4Z
0.1U_0402_16V4Z
4.7UH +-20% PCAA041B-4R7M 1.1A
1 1

@ CL36

CL37

CL38
@ LP2301ALT1G_SOT-23 @

G
1 1

2
CL34 CL35
D D
0.1U_0402_16V4Z 0.01U_0402_25V7K Note: Place Close to LAN chip LL2 LL3
2 2 LL1 DCR< 0.15 ohm
RL3 2 2 FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
LAN_PWR_ON# 2 1
<46> LAN_PWR_ON# Rate current > 1A +1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +1.1_DVDDL
100K_0402_5%

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
1

CL40

CL41

CL42
1 1 1
CL39
0.1U_0402_16V4Z
2
2 2 2
Close to
Pin40

Vendor recommand reserve the


PU resistor close LAN chip Place close to Pin34

@
RL4 1 2 4.7K_0402_5%
+3VALW_LAN

PLT_RST#
<14,23,32,40,46> PLT_RST#

H --> Overclocking mode


UL1
L --> Not overclocking mode
Place Close to Chip
C CL43 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N4 29 38 LAN_ACTIVITY# C
<18> PCIE_PRX_DTX_N4 TX_N LED_0 LAN_ACTIVITY# <42>
39 LAN_LINK#
CL44 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P4 30
Atheros LED_1 23 LAN_CLK_SEL
LAN_LINK# <42>
<18> PCIE_PRX_DTX_P4 TX_P LED_2
QCA8171 RL5 2 1 10K_0402_5%
36 @
<18> PCIE_PTX_C_DRX_N4 RX_N 12 LAN_MDI0-
35 TRXN0 11 LAN_MDI0+ LAN_MDI0- <42>
<18> PCIE_PTX_C_DRX_P4 RX_P TRXP0 LAN_MDI0+ <42>
RL5
15 LAN_MDI1- NC = 25MHz
32 TRXN1 14 LAN_MDI1- <42>
LAN_MDI1+ Pull-Down = 48MHz
<16> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 LAN_MDI2- LAN_MDI1+ <42>
<16> CLK_PCIE_LAN REFCLK_P TRXN2 17 LAN_MDI2+ LAN_MDI2- <42>
2 TRXP2 21 LAN_MDI2+ <42>
PLT_RST# LAN_MDI3-
PERST# TRXN3 20 LAN_MDI3- <42>
LAN_MDI3+
RL6 1 2 0_0402_5% PCIE_WAKE#_R 3 TRXP3 LAN_MDI3+ <42> Place Close to PIN1
<15,19,40> PCIE_WAKE# 1 2 0_0402_5% WAKE#
<40,46,55> LAN_WAKE# RL7
@ 25 10 LAN_RBIAS 1 2 +3VALW_LAN
26 TESTMODE_0 RBIAS
RL8 2.37K_0402_1%
1 2 4.7K_0402_5% 27 TESTMODE_1
+3VALW_LAN RL16 Place Close to PIN10
TESTMODE_2 1
@ +3VALW_LAN
VDD33

1000P_0402_50V7K

10U_0805_10V4Z

10U_0805_10V4Z
28

0.1U_0402_16V4Z

1U_0402_6.3V4Z
NC 1 1 1 1

@
@ Optional @
40 +LX RL9 1 2 30K_0402_5%
LX +LX +3VS

CL45

CL46

CL47

CL48

CL49
LAN_XTALO 7
XTLO

1
LAN_XTALI 8 2 2 2 2
1 2 4.7K_0402_5% XTLI 5
+3VALW_LAN RL17 @ DEBUGMODE RL10 1 2 30K_0402_5%
DEBUGMODE +3VALW_LAN
4
<16> CLKREQ_LAN# CLKREQ# 24
PPS 37 +1.1_DVDDL
+1.1_AVDDL 13 DVDDL_REG
+1.1_AVDDL 19 AVDDL
31 AVDDL 16
+1.1_AVDDL +AVDD3.3
B +1.1_AVDDL_L 34 AVDDL AVDD33 22 +2.7_AVDDH B
+1.1_AVDDL 6 AVDDL AVDDH 9
AVDDL_REG AVDDH_REG
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
CL50

CL51

CL52

CL53

CL54
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1

CL58

CL59
41 1 1
GND
RL11 0_0603_5%
1 2
0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
+AVDD3.3
2 2 2 2 2 QCA8171-BL3A-R_QFN40_5X5 +3VALW_LAN
2 2
CL55

CL56

CL57
1 1 1

0.1U_0402_16V4Z

1U_0402_6.3V4Z
CL60

CL61
2 2 2 1 1
UL1
Near
Near Near Near Near Pin37 2 2
Pin13 Pin19 Pin31 Pin6
@ Near Near
SA00006540J Pin9 Pin22
LAN_XTALI QCA8172-AL3A-R_QFN40_5X5 Place close to Pin16
YL7
LAN_XTALO
1 3
QCA8171/72 Pin defination difference.
1 3
GND GND
Pin17 Pin18 Pin19 Pin20 Pin21
1 2 4 1
CL63
CL62 25MHZ_10PF_7V25000014 15P_0402_50V8J
15P_0402_50V8J
2 2 QCA8171 LAN_MDI2+ LAN_MDI2- +1.1_AVDDL LAN_MDI3+ LAN_MDI3-
A A

QCA8172 NC NC NC NC NC

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 LAN_QCA8171


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 41 of 69

5 4 3 2 1
5 4 3 2 1

LAN_LINK#
<41> LAN_LINK#
LAN_ACTIVITY#
<41> LAN_ACTIVITY#

JRJ45
CL73 0.1U_0402_16V4Z TL1 LAN_LINK# 9
2 1 1 24 1 RL12 2 Green LED-
TCT MCT0
D
2
TCT1 MCT1
23 R_short 0_0805_5% +3VALW_LAN RL13 1 2 220_0402_5% 10
Green LED+
placement D
LAN_MDI0+ 1:1 RJ45_MIDI0+ 1
<41> LAN_MDI0+ TD1+ MX1+ RJ45_MIDI0+ 1
@
CL64 PR1+
470P_0402_50V7K RJ45_MIDI0- 2
2 PR1-
LAN_MDI0- 3 22 RJ45_MIDI0- RJ45_MIDI1+ 3
<41> LAN_MDI0- TD1- MX1- PR2+
CL74 0.1U_0402_16V4Z
2 1 4 21 MCT1 1 RL18 2 RJ45_MIDI2+ 4
TCT2 MCT2 PR3+
LAN_MDI1+ 5 1:1 20 RJ45_MIDI1+ R_short 0_0805_5% RJ45_MIDI2- 5
<41> LAN_MDI1+ TD2+ MX2+ PR3-
RJ45_MIDI1- 6
PR2-
RJ45_MIDI3+ 7 14
LAN_MDI1- 6 19 RJ45_MIDI1- PR4+ G2
<41> LAN_MDI1- TD2- MX2- RJ45_MIDI3- 8 13
CL75 0.1U_0402_16V4Z
2 1 7 18 MCT2 1 RL19 2 PR4- G1
TCT3 MCT3 LAN_ACTIVITY# 11
LAN_MDI2+ 8 1:1 17 RJ45_MIDI2+ R_short 0_0805_5% Yellow LED-
<41> LAN_MDI2+ TD3+ MX3+
1 +3VALW_LAN RL14 1 2 220_0402_5% 12
@ Yellow LED+
CL65 SANTA_130456-111
470P_0402_50V7K
LAN_MDI2- 9 16 RJ45_MIDI2- 2
<41> LAN_MDI2- TD3- MX3- ME@
10 15 MCT3 1 RL20 2
TCT4 MCT4
LAN_MDI3+ 11 1:1 14 RJ45_MIDI3+ R_short 0_0805_5%
<41> LAN_MDI3+ TD4+ MX4+

BS401N 1206
RL15
C C
75_0402_1%

2
LAN_MDI3- 12 13 RJ45_MIDI3-
<41> LAN_MDI3- TD4- MX4-

FL5
2
350UH_NS892407

1
SURGE@

1
1 1 TL1 CL66
@ CL69 CL33 10P_1206_2KV7K
0.1U_0402_16V4Z 1U_0402_10V6K 2

2 2 JP/N
@ SP05000650J
350UH_NS892405
CL69 reserved for EMI, Place CL33 close to TL1
place close to TL1

B B

Place Close to TL1


MCT3

MCT2

MCT1

BS4200N-C-LV_SMB-F2
MCT0
DL3 DL4

BS401N 1206

BS401N 1206

BS401N 1206
@ @
LAN_MDI0- 1 10 LAN_MDI2- 1 10
2 1 10 9 LAN_MDI1+ 2 1 10 9 LAN_MDI3+
2 9 2 9

2
LAN_MDI0+ 3 8 LAN_MDI2+ 3 8
3 8 3 8

FL1

FL2

FL3

FL4
4 7 LAN_MDI1- 4 7 LAN_MDI3-
GND

GND

2
5 4 7 6 5 4 7 6
5 6 5 6

1
TCLAMP3302N.TCT_SLP2626P10-10 TCLAMP3302N.TCT_SLP2626P10-10
11

11

SURGE@ SURGE@ SURGE@

1
A A
FL1 ~ FL4 Reserve for Serge Line to GND
DL3, DL4 Reserve for Surge
FL3 change to BS4200N for ESD request

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 LAN Transformer


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 42 of 69

5 4 3 2 1
5 4 3 2 1

D Close U29 SMSC thermal sensor D

REMOTE1+
1
+3VS placed near by VRAM REMOTE1+
Under VRAM
C449 1

1
2200P_0402_50V7K U29 @ C
2 REMOTE1- C982 2 Q137
Remove +VDD netname B
100P_0402_50V8J MMST3904-7-F_SOT323-3
1 10 EC_SMB_CK2 2 E
EC_SMB_CK2 <17,23,32,34,36,46>

3
VDD SMCLK REMOTE1-
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <17,23,32,34,36,46>
REMOTE2+ 2
1 REMOTE1- 3 8
DN1 ALERT# R624
C443
C658 0.1U_0402_16V4Z REMOTE2+ 4 7 2 1
2200P_0402_50V7K 1 DP2 THERM# +3VS Close to SSD side
2 REMOTE2- REMOTE2- 5 6 REMOTE2+
DN2 GND 10K_0402_5%
1

1
@ @ C
C984 2 Q138
EMC1403-2-AIZL-TR_MSOP10 100P_0402_50V8J B MMST3904-7-F_SOT323-3
FAN_PWM & TACH 2 E

3
for PWM FAN Address 1001_101xb REMOTE2-

REMOTE2+/-:
internal pull up 1.2K to 1.5V
C
Trace width/space:10/10 mil C
R for initial thermal
Trace length:<8"
shutdown temp

B B

FAN1 Conn
+5VS

JFAN1
1
2 1
2 1 <46> EC_FAN_SPEED 2
<46> EC_FAN_PW M 3
C986 C49 @ 4 3
10U_0805_10V6K 0.1U_0402_10V7K 5 4
1 2 6 G5
G6
ACES_85205-04001
ME@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 VGA Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 43 of 69

5 4 3 2 1
A B C D E F G H

1
SATA HDD Conn. SATA ODD Conn. 1

JHDD1 JODD2 ME@

1 HDD_PWR_DET# 1
SATA_PTX_C_DRX_P1 2 GND SATA_PTX_C_DRX_P2 2 GND
<13> SATA_PTX_C_DRX_P1 A+ <13> SATA_PTX_C_DRX_P2 A+
SATA_PTX_C_DRX_N1 3 SATA_PTX_C_DRX_N2 3
<13> SATA_PTX_C_DRX_N1 A- <13> SATA_PTX_C_DRX_N2 A-
4 4
SATA_PRX_DTX_N1 C627 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND SATA_PRX_DTX_N2 C629 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N2 5 GND
<13> SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C628 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6 B- <13> SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 C630 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2 6 B-
<13> SATA_PRX_DTX_P1 7 B+ <13> SATA_PRX_DTX_P2 7 B+
GND R1479 1 2 R_short 0_0402_5% GND
<32,46> SLI_FAN_SPEED
<19> ODD_DETECT# R1476 1 @2 0_0402_5%
8 R710 1 @2 0_0402_5% 8
9 V33 9 DP
10 V33 10 +5V
11 V33 +5VS_ODD 11 +5V
12 GND 12 MD 15
@J12
@ J12 13 GND R921 1 2 10K_0402_5% ODD_DA# 13 GND GND 14
GND +3VS GND GND
1 2 +5VS_HDD 14
+5VS 1 2 15 V5 R1497 1 @ 2 0_0402_5%
JUMP_43X79 16 V5 <14> ODD_DA#_R R1494 1 2 R_short 0_0402_5% SANTA_202404-1
17 V5 <32,46> SLI_FAN_PWM
18 GND
19 Reserved
20 GND
+5VS 21 V12 24
22 V12 GND 23
V12 GND
2 2
1 1 1 1 1
SANTA_191201-1
C631 C632 C633 C634 C635
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M
2 2 2 2 2 ME@

ODD Power Control


@ J6
1 2
1 2
JUMP_43X79
+5VALW +5VS +5VS_ODD +5VS_ODD
Q88 AO3413_SOT23-3 AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
3 1

1
1

1
R923 R1496 R1477 @

G
1 2 1 1

2
3 100K_0402_5% @ 100K_0402_5% C1049 C638 C639 C637 470_0603_5% 3
0.1U_0402_16V4Z @ @ 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z

2
2

2
2 1 2 2
2 R1110 1 ODD_EN#
Q90
100K_0402_5%

1
D
2
Q89 C1057 ODD_EN# 2 @
1

D 0.01U_0402_16V7K G
2 2N7002KW_SOT323-3 S
<19> ODD_EN

3
G 2N7002KW_SOT323-3 1
1

S
3

R1478
100K_0402_5%
R1504 0_0402_5%
2

HDD_PWR_DET# 1 2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 HDD/ODD CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 44 of 69

A B C D E F G H
5 4 3 2 1

1 @ 2 +1.5VS
RA1648 0_0402_5%

RA1649 1 2 +3.3VD

2 1 R_short 0_0402_5%

10U_0805_10V4Z

0.1U_0402_16V4Z
CA1377 CA1378

Place close 1 2

D to pin 9 D

+5VD

0.1U_0402_16V4Z
10U_0805_10V4Z
2 1
CA1380
CA1379
Place close to Pin 26 1 2 Place close to pin 1 UA1
+3.3VD 1 16

0.1U_0402_16V4Z
9 DVDD MONO-OUT 29
1 1

10U_0603_6.3V6M
0.1U_0402_16V4Z CA1382 DVDD-IO MIC2-VREFO 30

CA1381
+5VA 26 MIC1-VREFO-R 31
2 1 CA1383 +AVDD2 40 AVDD1 MIC1-VREFO-L +MIC1_VREFO_L Ext. MIC
1 2 2 2 10U_0805_10V4Z AVDD2 15 RA1650 2 1 20K_0402_1% 10 mils
CA1384 CA1385 41 JDREF
PVDD1 Place close to Pin 28
+5VD 46 28

0.1U_0402_16V4Z
2 1 PVDD2 VREF

10U_0805_10V4Z
2 1 +CPVDD 36
10U_0805_10V4Z CA1387 CPVDD 32 HPOUTL_R R5 2 1 60.4_0402_1% HP_OUTL
HPOUT-L(PORT-I-L) HP_OUTL <50>
CA1386 DMIC_DATA_R 2 33 HPOUTR_R R10 2 1 60.4_0402_1% HP_OUTR 1 1
3 GPIO0/DMIC-DATA HPOUT-R(PORT-I-R) HP_OUTR <50>
DMIC_CLK_R CA1388 CA1390
1 2 GPIO1/DMIC-CLK 35 Place close to Pin 34/35/36
HDA_SDIN0_R 8 CBN 37 2 1 0.1U_0402_16V4Z
1 2 HDA_SDOUT_AUDIO_R 5 SDATA-IN CBP 10 mils 2 2
<13> HDA_SDOUT_AUDIO RA1651 CA1389 2.2U_0603_10V6K
SDATA-OUT 2.2U_0603_10V6K
10_0402_5% 34 CA1391 2 1 2.2U_0603_10V6K
1
RA1652 2 HDA_BITCLK_AUDIO_R 6 CPVEE
<13> HDA_BITCLK_AUDIO 10_0402_5% BCLK 27 CA1392 1 2 10U_0805_10V4Z
1
RA1653 2 HDA_SYNC_AUDIO_R 10 LDO1-CAP 39 CA1393 1 2 10U_0805_10V4Z
<13> HDA_SYNC_AUDIO 10_0402_5% SYNC LDO2-CAP 7 CA1394 1 2 10U_0805_10V4Z
PC_BEEP 12 LDO3-CAP
1 2 PCBEEP 43 SPKOUT_L2- 30 mils
<50> PLUG_IN SPK-OUT-L-
39.2K_0402_1% RA1654 13 42 SPKOUT_L1+
1 2 14 Sense A SPK-OUT-L+ 44 SPKOUT_R2-
<50> MIC_JD Sense B SPK-OUT-R-
20K_0402_1% RA1656 45 SPKOUT_R1+
MIC1_L 2.2U_0603_6.3V6K 1 2 CA1280 C_MIC1_L 19 SPK-OUT-R+
C place close to pin 13 <50> MIC1_L MIC1-L(PORT-B-L)
C
MIC1_R 2.2U_0603_6.3V6K 1 2 CA1279 C_MIC1_R 20 48 R946 1 2 SPDIF_OUT
<50> MIC1_R MIC1-R(PORT-B-R) SPDIF-OUT/GPIO2 SPDIF_OUT <50>
17 FBMA-10-100505-301T_2P
18 MIC2-L(PORT-F-L)
MIC2-R(PORT-F-R) 4
DVSS R438
P/N chang to 0 ohm to B phase 22 25
21 LINE1-L(PORT-C-L) AVSS1 38 1 2 A_PDB
LINE1-R(PORT-C-R) AVSS2 <46> EC_MUTE#

1
10 mils 24 49
LINE2-L(PORT-E-L) Thermal Pad

1
RA1657 23
DMIC_CLK 1 2 DMIC_CLK_R LINE2-R(PORT-E-R) 100K_0402_5% R437
<35> DMIC_CLK 33_0402_5%
R956 0_0402_5% 11 100K_0402_5%
<13> HDA_RST_AUDIO# RESETB @

2
<35> DMIC_DATA DMIC_DATA 1 2 DMIC_DATA_R A_PDB 47

2
R957 0_0402_5% PDB

CA13951
HDA_SDIN0 ALC282-CG_MQFN48_6X6
<13> HDA_SDIN0
10U_0805_10V4Z
2

2
@
CA1396 Place close to Pin 34/35/36
10P_0402_50V8J
HDA_SDOUT_AUDIO 1

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO

SPK_R1 @ CA9 1 2 1000P_0402_50V7K~N


2 2
SPK_R2 @ CA10 1 2 1000P_0402_50V7K~N
2 CA1397 CA1398
SPK_L1 @ CA11 1 2 1000P_0402_50V7K~N
B CA1399 1 1 PC Beep B
10P_0402_50V8J 10P_0402_50V8J
1 SPK_L2 @ CA12 1 2 1000P_0402_50V7K~N
10P_0402_50V8J
<46> BEEP# 1 2
EC Beep CA24 0.1U_0402_16V4Z 2009/11/02 Modify
RA4
1 2 PC_BEEP1 1 2 PC_BEEP
<13> HDA_SPKR
PCH Beep CA23 0.1U_0402_16V4Z 33_0402_5%
1

@ RA3
FBMA-10-100505-301T_2P 10K_0402_5% 30 mils JSPK1
+3.3VD +3.3VD 1 2 +3VS
2

LA62 SPKOUT_L1+ RA56 1 2 0_0603_5% SPK_L1 1


SPKOUT_L2- RA58 1 2 0_0603_5% SPK_L2 2 1
+CPVDD 1 2 SPKOUT_R1+ RA60 1 2 0_0603_5% SPK_R1 3 2
LA63 SPKOUT_R2- RA61 1 2 0_0603_5% SPK_R2 4 3
FBMA-10-100505-301T_2P 5 4
6 G5
FBMA-10-100505-301T_2P G6
+5VA 1 2 ACES_85205-04001
+5VS
LA64 ME@
ALC282 Configuation - example

2
+5VD 1 2
LA65
FBMA-10-100505-301T_2P
4 external jacks: Line-in / Mic-in / Hp-out / SPDIF-OUT DA1 @ DA2 @

+AVDD2 1 2 1 2
Internal speaker AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3
+1.5VS
LA66 RA1658 0_0402_5% Internal Stereo DMIC
FBMA-10-100505-301T_2P For EMI
1 @ 2 R126 10_0402_5%
+3VS
RA1659 0_0402_5% HDA_BITCLK_AUDIO_R 1 2

1
If AVDD2 is design to 1.5V, you will get better @ 1
power consumption. @ C200
RA1660
1 2 10P_0402_50V8J
2
0_0402_5%
A Pin Assignment Location Function Reserve for ESD request. A
DGND AGND
SPEAKER-OUT (pin-43/44/45/46_Port D) Internal Internal Speaker
Cap-Saving HP-OUT (pin-32/33_Port I) External Headphone out
Tied at one point only under
the codec or near the codec LINE1 (pin-21/22_Port C) External Line in
MIC1 (pin-19/20_Port B) External Mic in
MONO-OUT (pin-16) NC Title
Security Classification LC Future Center Secret Data
MIC2 (pin-17/18_Port F) NC Issued Date 2012/05/02 Deciphered Date 2012/5/02 Audio Codec
DMIC1/2 (pin-2/3) Internal Internal Mic ( Digital MIC )
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 45 of 69
5 4 3 2 1
5 4 3 2 1

For EMI 1 2
For ESD RE125 10_0402_5% RE5 0_0603_5%
+3VL
CLK_PCI_EC 1 2
PLT_RST# @ 1
1 2
@ CE204 Close EC RE1 @ 0_0603_5%
+3VALW

1 CE1
2 2 1 VCOREVCC
@ +3VALW_EC
CE63 +3VALW_R +3VALW_R
220P_0402_25V8J 10P_0402_50V8J .1U_0402_16V7K LE1
2 +3VALW_R All capacitors close to EC 1 2 +3VALW_R
BLM18PG181SN1D_0603

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
CE4
CE3 1000P_0402_50V7K

1
+3VS +3VALW_EC LE2 0.1U_0402_16V4Z

2
CE10

CE9

CE8

CE7

CE6

CE5
+RTCBATT RE2 1 @ 2 0_0402_5% 1 2 EC_AGND RE4
D 10K_0402_5% D
BLM18PG181SN1D_0603 @

2
RE3 1 2 R_short 0_0402_5%

2
LAN_WAKE#
LAN_WAKE# <40,41,55>
AC_PRESENT_R RE38 1 2 0_0402_5% AC_PRESENT
minimum trace width 12 mil AC_PRESENT <15>

114
121
127

1
12

11

26
50
92

74
3
UE1 RE43 0_0402_5% RE32
AC_PRESENT_R 2 1 VGA_AC_DET 10K_0402_5%

VCC

AVCC
VBAT

VSTBY(PLL)
VCORE

VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VGA_AC_DET <23>
RE44 0_0402_5%
EC_GPO7 2 @ 1

2
RE45 0_0402_5%
EC_GPO7 2 1 SUS_VCCP
SUS_VCCP <62>
KBRST# 4 24 PWR_LED# +3VALW_R
<19> KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# <51,52>
SERIRQ BATT_CHG_LED#
<17> SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# <51>
LPC_FRAME# 6 28 BATT_LOW_LED#
<54> WRST# <17,40> LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# <51>
LPC_AD3 LED_KB_PWM
<17,40> LPC_AD3 LAD3/GPM3 PWM3/GPA3 LED_KB_PWM <47>

1
LPC_AD2 8 PWM 30 SLI_FAN_PWM
<17,40> LPC_AD2 LAD2/GPM2 PWM4/GPA4 SLI_FAN_PWM <32,44>
LPC_AD1 9 31 EC_FAN_PWM RE8
+3VALW_R <17,40> LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM <43> 10K_0402_5%
LPC_AD0 BEEP# @
RE6 <17,40> LPC_AD0 LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# <45>
CLK_PCI_EC 13 LPC 34 EC_GPO7 +3VS
1 2 <16> CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120
WRST# BATT_LEN#
BATT_LEN# <57>

2
EC_SMI# 15 WRST# TMRI0/GPC4 124 SUSP#
<19> EC_SMI# ECSMI#/GPD4 TMRI1/GPC6 SUSP# <32,55,60,61,62>
100K_0402_5% EC_RX 16
1 <40> EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7

1
EC_TX 17 66 NTC_V NTC_V <57>
<40> EC_TX LPCPD#/GPE6 ADC0/GPI0
PLT_RST# 22 67 TURBO_V TURBO_V <57> DRAMRST_CNTRL_EC CE2
<14,23,32,40,41> PLT_RST# 23 LPCRST#/GPD2 ADC1/GPI1 68
CE11 EC_SCI# BATT_TEMP 0.1U_0402_16V4Z
<19> EC_SCI# BATT_TEMP <57>

2
2 GATEA20 126 ECSCI#/GPD3 ADC2/GPI2 69 IMVP_IMON
1U_0402_6.3V6K <19> GATEA20 GA20/GPB5 ADC ADC3/GPI3 IMVP_IMON <64>
70 EC_ON
<47> KSO[0..17]
KSO[0..17]

KSI[0..7]
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
AD_ID
EC_ON
ADP_I
<52,59>
<57,58>
+3VS
ADC6/DSR1#/GPI6 AD_ID <57>
<47> KSI[0..7]
KSI0
KSI1
58
59 KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73

78
VDDQ_PGOOD

SUSWARN#
VDDQ_PGOOD <60>
EC_FAN_SPEED 10K_0402_5% 2 1 RE9

60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 SUSWARN# <15>


KSI2 MAINPWON_EC RE39 1 2 0_0402_5% SLI_FAN_SPEED 10K_0402_5% 2 1 RE16
C
Need to check which SMBus can be use for debug KSI3 61 KSI2/INIT#
DAC
DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC RE17 1 2 0_0402_5%
MAINPWON <57,59>
C
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 PROCHOT# <57> +3VS
KSI4 ENBKL ENBKL <35>
+3VALW_R KSI5 63 KSI4 DAC5/RIG0#/GPJ5
KSI6 64 KSI5 85 USB_CH TP_CLK 4.7K_0402_5% 1 2 RE11
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 USB_CH <50>
EC_SMB_CK1 PAD IT0 KSI7 PBTN_OUT#
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# <15>
1

EC_SMB_DA1 PAD IT1 KSO0 36 87 PM_SLP_SUS#


37 KSO0/PD0 GPF2 88 PM_SLP_SUS# <15,55> 1 2 RE12
RE22 PAD IT2 KSO1 Int. K/B PS2 SUSACK# TP_DATA 4.7K_0402_5%
KSO1/PD1 GPF3 SUSACK# <15>
0_0603_5% PAD IT3 KSO2 38 89 TP_CLK
PAD IT4 KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA
TP_CLK <47>
40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA <47>
KSO4 +5VALW
2

KSO5 41 KSO4/PD4 96 CAPS_LED#


KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 CAPS_LED# <51>
1 RE23 2 2.2K_0402_5% EC_SMB_CK1 KSO6 42 97 PCH_PWR_EN USB_CH 10K_0402_5% 1 RE18 2
KSO6/PD6 GPH4/ID4 PCH_PWR_EN <55,57>
KSI7 PAD IT5 KSO7 43 98 ACOFF
KSO7/PD7 GPH5/ID5 ACOFF <58>
KSI6 PAD IT6 KSO8 44 99 PCH_PWROK
1 RE24 2 2.2K_0402_5% EC_SMB_DA1 45 KSO8/ACK# GPH6/ID6 PCH_PWROK <15>
WRST# PAD IT7 KSO9 USB_ON# 10K_0402_5% 1 RE19 2
KSO10 46 KSO9/BUSY 101 EC_SPI_CS1#
KSO11 51 KSO10/PE NC 102 EC_SPI_SI
52 KSO11/ERR# NC 103
For factory EC flash KSO12
KSO12/SLCT SPI Flash ROM NC
EC_SPI_SO_L
+3VS
KSO13 53 105 EC_SPI_CLK
KSO14 54 KSO13 NC
KSO15 55 KSO14 EC_FAN_PWM10K_0402_5% 1 RE20 2
KSO16 56 KSO15 108 ACPRN
KSO16/SMOSI/GPC3 AC_IN# ACPRN <58>
KSO17 57 UART 109 LID_SW# @
KSO17/SMISO/GPC5 LID_SW# LID_SW# <47>
+3VS
<52> ON/OFF 110 82 EXIO_DATA
111 PWRSW# EGAD/GPE1 83 EXIO_DATA <54>
SM Bus EXIO_CS
XLP_OUT EGCS#/GPE2 EXIO_CS <54>
EC_SMB_CK1 115 84 EXIO_CLK LPC_FRAME# 10K_0402_5% 1 RE21 2
<57,58> EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 EXIO_CLK <54>
EC_SMB_DA1 116
<57,58> EC_SMB_DA1 SMDAT1/GPC2
<6> H_PECI RE37 1 2 43_0402_5% PECI_EC 117 GPIO 77 EC_MUTE#
SMCLK2/PECI/GPF6 GPJ1 EC_MUTE# <45>
LAN_PWR_ON# 118 100 LAN_WAKE#
<41> LAN_PWR_ON# 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 +3VLP
EC_SMB_CK2 DRAMRST_CNTRL_EC DRAMRST_CNTRL_EC <6>
<17,23,32,34,36,43> EC_SMB_CK2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0
EC_SMB_DA2 95 104 ME_FLASH RE28 10K_0402_5%
<17,23,32,34,36,43> EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH <13>
107 SYSON ACPRN 1 2
DTR1#/SBUSY/GPG1/ID7 119 SYSON <60>
BKOFF#
+3VLP CRX0/GPC0 BKOFF# <35>
123 AOAC_ON#
CTX0/TMA0/GPB2 AOAC_ON# <40>
RE34 1 2 0_0402_5% 112 18 PM_SLP_S3#
VSTBY0 RI1#/GPD0 PM_SLP_S3# <15>
VR_ON 125 21 PM_SLP_S4# PM_SLP_S4# <15>
B +3VS <64> VR_ON GPE4 RI2#/GPD1 +3VS B
WAKE UP 76 NOVO#
TACH2/GPJ0 48 SLI_FAN_SPEED NOVO# <52>
TACH1A/TMA1/GPD7 SLI_FAN_SPEED <32,44> RE7
47 EC_FAN_SPEED
1 RE29 2 2.2K_0402_5% EC_SMB_CK2 USB_ON# 33 TACH0A/GPD6 19 TP_LED# EC_FAN_SPEED <43> ENBKL 1 2
<49> USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 TP_LED# <51>
DPWROK_EC 35 GPIO 20 NUM_LED# @
<15> DPWROK_EC RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# <51>
EC_RSMRST# 93 20120730 VA
1 RE30 2 2.2K_0402_5% <15> EC_RSMRST# CLKRUN#/GPH0/ID0 100K_0402_5%
EC_SMB_DA2 Reserved hardware
strapping for Auto load
EC_LID_OUT# 2 code
<19> EC_LID_OUT# CK32KE/GPJ7
AC_PRESENT_R 128 Clock
CK32K/GPJ6
RE41 1 2 H_PROCHOT# <57,6>
<64> VR_HOT#
R_short 0_0402_5%

1
D CE14

1
AVSS

H_PROCHOT#_EC 2 47P_0402_50V8J
VSS

VSS
VSS
VSS
VSS
VSS

G @
QE1 S

2
IT8586E-FX_LQFP128_14X14 2N7002H_SOT23-3
1

27
49
91
113
122

75

+3VL
EC_AGND +3VALW_R
S IC IT8586E/EX LQFP 128P KB CONTROLLER
RE10 @ 10K_0402_5%
1 2 ON/OFF
EMC Request

1
SYSON
RE13 10K_0402_5% BATT_TEMP CE16 1 2 100P_0402_50V8J RE31
1 2 BKOFF# @ SYSON

1
EC_GPO7 2 @ 1 RE40 ACPRN CE17 1 2 100P_0402_50V8J 100K_0402_5% RE27
CPU1.5V_S3_GATE <10>
RE14 @ 10K_0402_5% 0_0402_5%

CE15
2
100K_0402_5%

0.1U_0402_10V6K
1 2 ACPRN
SUSP#
1

RE25
1
RE15 10K_0402_5% @

2
100K_0402_5%

1
1 2 LID_SW# @
A RE26 A
RE33 10K_0402_5% 2
2

1 2 EXIO_CS 100K_0402_5%
@

2
EC_SPI_CS1# RE1524 1 2 SPI_CS1#_R
0_0402_5% SPI_CS1#_R <17>
@
EC_SPI_SI RE1525 1 2 SPI_SI_R1
0_0402_5% SPI_SI_R1 <17>
@
EC_SPI_SO_L RE1526 1 2 SPI_SO_L1 Title
0_0402_5% SPI_SO_L1 <17> Security Classification LC Future Center Secret Data
@
EC_SPI_CLK RE1527 1 2 SPI_CLK_PCH_1
Issued Date 2012/05/02 Deciphered Date 2012/5/02 EC ITE8586LQFP
0_0402_5% SPI_CLK_PCH_1 <17>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 46 of 69
5 4 3 2 1
5 4 3 2 1

15" INT_KBD Conn.


KSI[0..7]
KSI[0..7] <46> JKB1 KB Lighting CONN.4pin
KSO[0..17] 1
KSO[0..17] <46> 2 1
3 2
D 3 JKBL1 D
4 +VCC_KB_LED
5 4 1
KSO17 1
5 2
KSO16 C794 1 2 @ 100P_0402_50V8J KSO16 6 2
KSO15 7 6 3
3

0.1U_0402_10V6K
KSO17 C795 1 2 @ 100P_0402_50V8J KSO10 8 7 4
4

C905
KSO11 9 8 2 5
KSO2 C734 1 2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J 9 6 G1
KSO14 10 G2
KSO13 11 10
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSO12 12 11 @ E&T_6906-Q04N-00R
12 1 ME@
KSO3 13
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSO6 14 13
KSO8 15 14
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSO7 16 15
KSO4 17 16
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSO2 18 17
KSI0 19 18
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J
KSO1 20 19
KSO5 21 20
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSI3 22 21
KSI2 23 22
KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J 23 +5VS
KSO0 24 AO3413
KSI5 25 24
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J 25 VGS= -4.5V, Id=-3A, Rds<97m ohm
KSI4 26
26 +VCC_KB_LED
KSO9 27
KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J KSI6 28 27 Q121 AO3413_SOT23-3

1
KSI7 29 28 31 KBL@
C754 1 2 @ 100P_0402_50V8J C755 1 2 @ 100P_0402_50V8J 3 1

D
KSI0 KSO9 KSI1 30 29 G1 32
30 G2 R1229
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J 10K_0402_5%
ACES_85202-3005N @
KBL@

G
2

2
ME@ C908
C
CONN PIN define need double check R1232 0.1U_0402_16V4Z C
1 2 KBL_DET 1

0_0402_5% 1
C907
Q163 @
0.01U_0402_16V7K

1
D
2
2
<46> LED_KB_PWM
G

1
S 2N7002KW_SOT323-3

3
R1480 +3VS
100K_0402_5%
R1230
KBL@

2
1 @ 2 KBL_DET#
KBL_DET# <54>

10K_0402_5%

To TP/B Conn. 1
R1231
@ 2 KBL_DET#

10K_0402_5%

JTP1 ME@
SMB_DATA_S3 1
<11,12,17,40> SMB_DATA_S3 SMB_CLK_S3 2 1
<11,12,17,40> SMB_CLK_S3 3 2
TP_DATA 4 3
<46> TP_DATA 5 4
TP_CLK
B <46> TP_CLK
1
@
1
@
+3VS
6 5
6 Lid Switch B

C761 C762 C760 7


100P_0402_50V8J 100P_0402_50V8J 8 GND
2 2 0.1U_0402_16V4Z GND
ACES_88514-00601-071
+3VL R1002 1 2 +VCC_LID R1003 1 2 100K_0402_5%

R_short 0_0402_5%

2
5711ACDL-M3T1S SOT-23
D58

VDD
4 1
I/O3 I/O1 1
+3VALW 3
OUTPUT LID_SW# <46>
C758
0.1U_0402_16V4Z 2

GND
5 2 2
VDD GND C553

1
C759
U37 10P_0402_50V8J 330P_0402_50V8J

1
1
6 3

2
I/O4 I/O2

AZC099-04S.R7G_SOT23-6
@
For ESD request

For ESD Request


A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 KB/ KB-LIGHT/ LID IC


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 47 of 69

5 4 3 2 1
5 4 3 2 1

CW3
1 2

UW1 4.7U_0603_10V6K

2 RW1 1 12 23
+3VS +3VS_CARD +DV12 DVDD12 PMOS +CRD_POWER
R_short 0_0603_5% 13
+3V3_AUX V33IN
AC Coupling close to 25
AVDD33 +3VS_CARD
pin1 and pin2 of Chip
.1U_0402_16V7K 22
RW10 1 2 R_short 0_0402_5% 2 1 CW1 USB30_RX_N6_C 1 DVDD33
+3V3_AUX +3VS_CARD <18> USB30_RX_N6 TXN
.1U_0402_16V7K
D 2 1 CW2 USB30_RX_P6_C 2 D
<18> USB30_RX_P6 TXP
1.2V Power Source Selection: CW4
.1U_0402_16V7K 21 1 2
(Optional) 2 1 CW8 USB30_TX_N6_C 4 VUHSI
Close to chip
<18> USB30_TX_N6 RXN 1U_0402_10V6K
2 1 CW9 USB30_TX_P6_C 5
<18> USB30_TX_P6 RXP 20
.1U_0402_16V7K SD_DATA2_MS_CLK_R RW3 1 2 0_0402_5% SD_DATA2_MS_CLK
SB6
6 19 SD_MS_DATA3_R RW4 1 2 0_0402_5% SD_MS_DATA3
X1 SB5
1 RW2 2 7 18 SD_CMD_MS_DATA2_R RW5 1 2 0_0402_5% SD_CMD_MS_DATA2
X2 SB4
1M_0402_5% 17 SD_CLK_MS_DATA0_R RW6 1 2 0_0402_5% SD_CLK_MS_DATA0
YW1 3 SB3
+DV12 AVDD12 16 SD_DATA0_MS_DATA1_R RW7 1 2 0_0402_5% SD_DATA0_MS_DATA1
1 3 28 SB2
1 3 AVDD12 15 SD_DATA1_MS_BS_R RW8 1 2 0_0402_5% SD_DATA1_MS_BS
GND GND SB1
1 1
CW25 CW26 26
2 4 <18> USB20_P4 DP
15P_0402_50V8J 15P_0402_50V8J
25MHZ_10PF_7V25000014 27 10 SD_WP
2 2 <18> USB20_N4 DM SD_WP
CW5 11 SD_CD#
1 2 +3VS_CARD 8 SD_CDZ
Vendor recommend to reserve 0.1U_0402_16V4Z AVDD33
1 RW9 2 9 14 MS_INS#
680_0402_1% RTERM MS_INS

CW6
1 2 24 29
0.1U_0402_16V4Z RSTZ G1

C C
GL3213-OHY03_QFN28_5X5

< 4 in 1 Card Reader Connector > +CRD_POWER

(40mil)
+CRD_POWER
800mA
JREAD2 (40mil)
22 11
XD-VCC SD4-VDD 18
+DV12 30 MS9-VCC
20 mils XD10-D0 (40mil)
29 9 SD_CLK_MS_DATA0
28 XD11-D1 SD5-CLK 4 SD_DATA0_MS_DATA1

0.1U_0402_16V4Z
27 XD12-D2 SD7-DAT0 3 SD_DATA1_MS_BS

10U_0805_10V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 26 XD13-D3 SD8-DAT1 21 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2.2U_0603_6.3V6K

SD_DATA2_MS_CLK

CW15
XD14-D4 SD9-DAT2
1U_0402_10V6K

1 1 1 1 @ 25 19 SD_MS_DATA3

CW16

CW17

CW18
24 XD15-D5 SD1-DAT3 16 SD_CMD_MS_DATA2
XD16-D6 SD2-CMD
CW19

CW20

CW21

23 1
CW7

2 SD_CD# 2 2 2
XD17-D7 SD-CD 2 SD_WP
2 2 2 2 33 SD-WP
32 XD07-WE 6
34 XD08-WP SD6-VSS 13
Close to Pin12 Close to Pin3 Close to Pin28 Colse to Conn. 39 XD06-ALE SD3-VSS
B 38 XD01-CD Colse to Conn. Colse to Socket Pin11. B
37 XD02-R/B
36 XD03-RE 17 SD_DATA2_MS_CLK
35 XD04-CE MS8-SCLK 10 SD_CLK_MS_DATA0 SD_CLK_MS_DATA0 SD_DATA2_MS_CLK
XD05-CLE MS4-DATA0 8 SD_DATA0_MS_DATA1
All of cap. close to chip 31 MS3-DATA1 12 SD_CMD_MS_DATA2
XD GND MS5-DATA2

2
40 15 SD_MS_DATA3
XD GND MS7-DATA3 14 MS_INS# RW11 RW12
MS6-INS 7 SD_DATA1_MS_BS 10_0402_5% 10_0402_5%
+3VS_CARD +3V3_AUX MS2-BS 5
40 mils 40 mils MS1-VSS @ @
41 20

1
42 SD CD/WP GND MS10-VSS
SD CD/WP GND
1 1
4.7U_0603_10V6K

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

T-SOL_144-1313002600_40P_NR-T CW550 CW551


1U_0402_10V6K

1 1 1 1 10P_0402_50V8J 10P_0402_50V8J
CW22

CW10

ME@ @ @
2 2
CW23

CW24

2 2 2 2
For EMI

SD_DATA2_MS_CLK SD_CLK_MS_DATA0
Close to Pin22 Close to Pin25 Close to Pin13

2
RW13 RW14
10_0402_5% 10_0402_5%
@ @

1
1 1
CW552 CW553
10P_0402_50V8J 10P_0402_50V8J
A @ @ A
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Card reader GL3213


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 48 of 69
5 4 3 2 1
A B C D E

LEFT SIDE USB3.0 PORT X1


+5VALW +USB_VCCA
U39
1 8
C767 0.1U_0402_16V4Z 2 GND VOUT 7 +USB_VCCA
2 1 3 VIN VOUT 6 C814 220U_6.3V_M
USB_ON# 4 VIN VOUT 5 USB_OC1# 1 2
<46> USB_ON# EN FLG USB_OC1# <18>

+
G547I2P81U_MSOP8 1
1 C904 1 2 1
Low Active 2A @ 1000P_0402_50V7K C816 470P_0402_50V7K
2
For EMI request
1 2 C819
USB2.0 choke --> SM070001S0J For ESD request
0.1U_0402_16V4Z
USB3.0 Choke --> SM070001S0J
JUSB1
1
USB20_N2 R1162 1 2 0_0402_5% USB20_N2_R 2 VBUS
<18> USB20_N2 D-
L68 USB20_P2 R1163 1 2 0_0402_5% USB20_P2_R 3
<18> USB20_P2 D+
USB30_RX_N2 2 1 USB30_RX_R_N2 @ 4
2 1 USB30_RX_N2 R1154 1 @ 2 0_0402_5% USB30_RX_R_N2 5 GND_1
<18> USB30_RX_N2 SSRX-
USB30_RX_P2 R1155 1 2 0_0402_5% USB30_RX_R_P2 6 13
<18> USB30_RX_P2 SSRX+ GND_6
USB30_RX_P2 3 4 USB30_RX_R_P2 @ 7 12
3 4 USB30_TX_N2 C300 1 2 0.1U_0402_10V6K USB30_TX_C_N2 R1156 1 @ 2 0_0402_5% USB30_TX_R_N2 8 GND_2 GND_5 11
<18> USB30_TX_N2 SSTX- GND_4
WCM-2012-900T_4P USB30_TX_P2 C299 1 2 0.1U_0402_10V6K USB30_TX_C_P2 R1157 1 2 0_0402_5% USB30_TX_R_P2 9 10
<18> USB30_TX_P2 SSTX+ GND_3
@
L70 @ SANTA_370300-1
USB30_TX_C_N2 2 1 USB30_TX_R_N2
2 1
ME@
USB30_TX_C_P2 3 4 USB30_TX_R_P2
3 4
2 WCM-2012-900T_4P 2

L72 For ESD request


USB20_N2 2 1 USB20_N2_R
2 1 D24
@
@ D27 USB20_N2_R 3 6
USB20_P2 3 4 USB20_P2_R USB30_RX_R_N2 9 10 1USB30_RX_R_N2 I/O2 I/O4
1
3 4
WCM-2012-900T_4P USB30_RX_R_P2 8 9 2 2 USB30_RX_R_P2
2 5 +5VALW
USB30_TX_R_N2 7 4 USB30_TX_R_N2 GND VDD
7 4

USB30_TX_R_P2 6 6 5 5 USB30_TX_R_P2
1 4 USB20_P2_R
3 I/O1 I/O3
3
8 AZC099-04S.R7G_SOT23-6

YSCLAMP0524P_SLP2510P8-10-9 +USB_VCCA
C815 220U_6.3V_M For EMI request
For ESD request 1 2
@ USB2.0 choke --> SM070000I00

+
@ D29
USB30_RX_R_N5 9 10 1 1USB30_RX_R_N5 1 2 USB3.0 Choke --> SM070001U00
C817 470P_0402_50V7K
USB30_RX_R_P5 8 9 2 2 USB30_RX_R_P5
C818 For ESD request
3 USB30_TX_R_N5 7 7 4 4 USB30_TX_R_N5 3
1 2 L69
USB30_TX_R_P5 6 6 5 5 USB30_TX_R_P5 USB30_RX_N5 2 1 USB30_RX_R_N5
0.1U_0402_16V4Z 2 1
3 3
USB30_RX_P5 3 4 USB30_RX_R_P5
8 JUSB2 3 4
1 WCM-2012-900T_4P
USB20_N3 R1165 1 @ 2 0_0402_5% USB20_N3_R 2 VBUS
<18> USB20_N3 D-
YSCLAMP0524P_SLP2510P8-10-9 USB20_P3 R1164 1 2 0_0402_5% USB20_P3_R 3 L71
<18> USB20_P3 D+
@ 4 USB30_TX_C_N5 2 1 USB30_TX_R_N5
USB30_RX_N5 R1161 1 @ 2 0_0402_5% USB30_RX_R_N5 5 GND_1 2 1
<18> USB30_RX_N5 SSRX-
USB30_RX_P5 R1160 1 2 0_0402_5% USB30_RX_R_P5 6 13
<18> USB30_RX_P5 SSRX+ GND_6
@ 7 12 USB30_TX_C_P5 3 4 USB30_TX_R_P5
USB30_TX_N5 C302 1 2 0.1U_0402_10V6K USB30_TX_C_N5 R1159 1 @ 2 0_0402_5% USB30_TX_R_N5 8 GND_2 GND_5 11 3 4
<18> USB30_TX_N5 SSTX- GND_4
USB30_TX_P5 C301 1 2 0.1U_0402_10V6K USB30_TX_C_P5 R1158 1 2 0_0402_5% USB30_TX_R_P5 9 10 WCM-2012-900T_4P
<18> USB30_TX_P5 SSTX+ GND_3
@
SANTA_370300-1 L73
USB20_N3 2 1 USB20_N3_R
2 1
D25 ME@
@
USB20_N3_R 3 6 USB20_P3 3 4 USB20_P3_R
I/O2 I/O4 3 4
WCM-2012-900T_4P

2 5 +5VALW
GND VDD
4 4

1 4 USB20_P3_R
I/O1 I/O3

AZC099-04S.R7G_SOT23-6 Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 USB 3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 49 of 69

A B C D E
5 4 3 2 1

+5VS
+5V_CHGUSB

JSB1
Touch panel 1 ME@
2 1
JTHP ME@ 3 2
R2 2 1 0_0603_5% 1 4 3
+5VS 1 4
2 5
USB20_N8_THP 3 2 6 5
USB20_P8_THP 4 3 7 6
5 4 0.1U_0402_16V4Z 1 USB20_P1_C 8 7
USB20_N8 R1168 1 2 0_0402_5% USB20_N8_THP 6 5 @ C1099 USB20_N1_C 9 8
<18> USB20_N8 6 9
D USB20_P8 R1169 1 2 0_0402_5% USB20_P8_THP 7 10 D
<18> USB20_P8 G7 10
8 11
G8 2 EXT_MIC_L 12 11
L75 ACES_85205-06001 EXT_MIC_R 13 12
USB20_N8 2 1 USB20_N8_THP MIC_JD 14 13
2 1 <45> MIC_JD 14
HP_OUTR 15
<45> HP_OUTR HP_OUTL 16 15
USB20_P8 3 4 USB20_P8_THP <45> HP_OUTL SPDIF_OUT 17 16 19
3 4 <45> SPDIF_OUT PLUG_IN 18 17 G1 20
<45> PLUG_IN 18 G2
WCM-2012-900T_4P
1 ACES_50505-0184N-001
@
C1100
220P_0402_25V8J
2

For ESD

Sleep & Charge


Right side USB Charger Port (USB_Port5, near JMIC1)
+5VALW
Genesys GL887 Genesys GL887T
1 1 CHG_MOD2 CHG_MOD1 CHG_MOD0 Charge Mode CHG_MOD2 CHG_MOD1 CHG_MOD0 Charge Mode
10U_0603_6.3V6M

0.01U_0402_16V7K
C1096

C1097

C C
Close to U8 Pin 1 0 0 0 Charge Disable 0 0 0 Power down mode
2 2

+5VALW
+5VALW +5V_CHGUSB * 0

0
1

1
0

1
CDP mode

DCP mode
0

X
0

1
1

0
Auto 2A mode without wake up function

BC1.2 SDP mode

50 mil
1
U8

P5V
887T@

VBUS_OUT
50 mil
12
1

1
0

0
0

1
Apple 1A mode

Apple 2A mode
* 0

1
1

0
1

0
Auto 2A mode with wake up function

BC1.2 DCP mode

1 1 0 Auto mode (DCP and Apple 1A) 1 0 1 Apple 2A mode


2

R1553 USB20_P1 3
<18> USB20_P1 DP_UP 10 USB20_P1_C BC1.2 CDP mode with Smart CDP
10K_0402_5%
<18> USB20_N1
USB20_N1 2
DM_UP
DP_DOWN

DM_DOWN
11 USB20_N1_C * 1 1 1 Auto mode (DCP and Apple 2A)

TI TPS2543
* 1 1 1
1

R1555 R1558 USB_CH 5 @ 20120902 VA2


CHG_MOD1 2 1 2 <46>
1 USB_CH CHG_MOD2 6 PSW_EN 9 Change to OC0#
PAD T182
0_0402_5% 887@ 0_0402_5% CHG_MOD1 7 CHG_MOD2 BC_CON MODE
CHG_MOD2 CHG_MOD1 CHG_MOD0 ILIM_SEL2
CHG_MOD0 8 CHG_MOD1 13
CHG_MOD0 ALARM USB_OC0# <18>
For TI charger DCH OUT held low /Data lines disconnected
+5VALW 0 0 0 X

Mode S0 S3 ILIM_SEL2
ILIM_SEL1
4
16 NC2
NC1
GND
14
* 1 1 1 1 CDP Data connected and Load detect active
SDP2 Data connected
2

R1559 ILIM_SEL0 15 17 1 1 1 0
NC0 GND_PAD
CHG_MOD 1 0 SDP1 Data connected
10K_0402_5% 1 1 0 X
@ GL887-OCGC_QFN16_3X3
0 1 0 X SDP1 Data connected
1

R1560 1 2 0_0402_5% CHG_MOD2


1 0
B U8 0 X DCP_Short Stay in DCP BC1.2 Charging mode B
1

D
1
R1561 1 210K_0402_5%
2
<54> CHG_MOD 1 0 1 X DCP_Divider Stay in DCP Divider1 Charging mode
@ G Q122 C1098
S 2N7002KW_SOT323-3 0.1U_0402_16V4Z TI@
3

@ 2

Close to U8
TPS2546RTER_QFN16_4X4
* 0

0
1 1

1
X

X
DCP_Auto Data disconnected and Load detect active

DCP_Auto Data disconnected and Load detect active


0

@
R1551 1 TI@ 2 ILIM_SEL2 R1584 1 2
+5VALW
10K_0402_5% 10K_0402_5%
TI@
R1585 1 @ 2 ILIM_SEL1 R1552 1 2
10K_0402_5% 20K_0402_5%

R1586 1 @ 2 ILIM_SEL0 R1554 1 @ 2


10K_0402_5% 20K_0402_5%

Ext. MIC +MIC1_VREFO_L

A A

Remove Diode (DA1, DA2)


2

RA1622 RA1623
2.2K_0402_5% 2.2K_0402_5% Title
Security Classification LC Future Center Secret Data
Issued Date 2012/07/01 Deciphered Date 2014/07/01 AUDIO-B CONN/ USB CHARGER
1

RA1634 2 1 1K_0402_5% EXT_MIC_R


<45> MIC1_R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RA1633 2 1 1K_0402_5% EXT_MIC_L DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
<45> MIC1_L
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 50 of 69

5 4 3 2 1
BATT CHARGE/LOW LED
White
Amber LED2

BATT_LOW_LED# 2 R1012 1 3
<46> BATT_LOW_LED#
470_0402_5% 1
White +5VALW
BATT_CHG_LED# 2 R1014 1 2
<46> BATT_CHG_LED#
LION LED SC500007F0J
470_0402_5%
12-22-S2ST3D-C30-2C_WHI-ORG

White LION LED:SC500004Y0J


PWR LED HDD LED CapsLK LED LED5
1 2 2 1
<46> NUM_LED# +5VS
300_0402_5% R1563
12-21SYGCS530-E1S155TR8_W

LED3
1 2 2 R1013 1
<46,52> PWR_LED# +5VALW
300_0402_5%
12-21SYGCS530-E1S155TR8_W

TouchPad_LED 2012-0507 --> Change LED1 to T/P LED


LED1
R1322 1
<46> TP_LED# R1621 1 2 HDD_LED#_R 1 2 2
+5VS
0_0402_5%
300_0402_5%
12-21SYGCS530-E1S155TR8_W
<13> HDD_LED# R1622 1 @ 2 HDD_LED#_R
0_0402_5%
LED4
1 2 2 R1323 1
<46> CAPS_LED# +5VS
300_0402_5%
12-21SYGCS530-E1S155TR8_W
LED3 LED2 LED1 LED4

POWER BATTERY T/P CapsLK

Screw Hole

CPU and GPU: H_3P8X 6 MIN PCIE: H_3P3 X 1


C: H_3P8X 3 B: H_3P8X 3 E: H_3P3X 1
H13 H10 H12 H11 H14 H15
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
1
CPU GPU

ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1


A: H_2P8X 8
H30 H31 H32 H33
HOLEA HOLEA HOLEA HOLEA

1
1

1
H_3P0X9
E: H_3P3X 3 H_2P8X4P0NX1
H23 H24 H25 H28 H29 H34 H35 H36 H37 H20 H21
H16 H26 HOLEA HOLEAHOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEAHOLEA
HOLEA HOLEA

1
1
1

PCB Fedical Mark PAD Title


Security Classification LC Future Center Secret Data
FD1 FD2 FD3 FD4 Issued Date 2012/07/01 Deciphered Date 2014/07/01 LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 51 of 69
ON/OFF switch Power Button/B link
SW 2 @ +3VALW +3VL to Function/B Conn. 10pin
1 3
Power Button

2
TOP Side 2 4
R1116 R1117
SMT1-05_4P 100K_0402_5% 100K_0402_5%

6
5
NO51ON@
J7

1
Bottom Side 1 2 1 2 For S3.5
R1531 0_0603_5%
SHORT PADS
@ D72 NO51ON@ JPW R1 ME@
8
3 ON/OFF
ON/OFF <46> 7 GND
ON/OFFBTN# 1 GND
2 51_ON# 6
51_ON# <56> +5VALW 6
5
DAN202UT106_SC70-3 NOVO_BTN# 4 5
4

1
D 3
<46,51> PW R_LED# 3
EC_ON 2 ON/OFFBTN# 2
<46,59> EC_ON 1 2
G
1
2

S Q153

3
R1523 2N7002_SOT23-3 1 C551 ACES_88514-00601-071

1
10K_0402_5% C552
330P_0402_50V8J @ 100P_0402_50V8J
1

2
2

For ESD Request


+3VALW +3VL For S3.5

EMI REQUEST 1ST = SCA00000E00

2
2

R1119
NO51ON@ R1118 100K_0402_5% 2ST = SCA00000R00
100K_0402_5%

1
@
1

1 2
R1532 0_0603_5%

D56
NOVO# 2
<46> NOVO#
NO51ON@ 1 NOVO_BTN#
51_ON# R19 1 2 0_0402_5% 3

ON/OFF R28 1 2 0_0402_5% DAN202UT106_SC70-3


NO51ON@ default reserved
For S3.5

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 ONOFF SW/ PWR-B CONN/ ISPD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 52 of 69
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data


Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NVSR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Y501 NM-A032
Date: Wednesday, March 27, 2013 Sheet 53 of 69
5 4 3 2 1
1 @ 2
+3VALW_R
RXE1 0_0603_5%

EXIO_DATA
<46> EXIO_DATA
FB_CLAMP2 GC6@ 1

12
<23,27,54> FB_CLAMP U80

1
0_0402_5% RXE3 @
CHG_MOD 2 1

VSS1
VSS2
<50,54> CHG_MOD 2
0_0402_5% RE46
EXIO_CLK 4 GPIO_DATA
<46> EXIO_CLK EXIO_CS 3 GPIO_CLK 24
<46> EXIO_CS GC6_EVENT# 2 GC6@ 1 5 CYCLE_START VSTBY2 13
<19,23,54> GC6_EVENT# RESET# VSTBY1
RXE2 0_0402_5% WRST#
<46> WRST# 6 23 SLI_FB_Clamp
<23,27,54> FB_CLAMP GPIO4 GPIO35 S_GC6_EN <27,32>
7 21 FB_clamp_req
<19,23,54> GC6_EVENT# 8 GPIO5 GPIO33 22 S_GC6_EVENT# <32> GPU_PWR_GOOD
<19,27,62,63> DGPU_PWROK 9 GPIO7 GPIO31 20 S_DGPU_PWROK <16,32> GPU_PWR_EN
<14,23,55> DGPU_PWR_EN 10 GPIO9 GPIO29 19 S_DGPU_PWR_EN <19,32,55> PEX REST
<14,23> DGPU_HOLD_RST# 11 GPIO11 GPIO27 18 S_DGPU_RST <16,32> DGPU_HOLD_RST#
PAD T178 @
<14,27> DGPU_GC6_EN 14 GPIO13 GPIO26 17
<14,63> NVDD_PWR_EN KBL_DET# 15 GPIO18 GPIO24 16 CHG_MOD S_NVDD_PWR_EN <19,32>
<47> KBL_DET# GPIO20 GPIO22 CHG_MOD <50,54>

GND
For USB charge

25
IT8302FN
IT7230BFN-BX-0001_QFN24_4X4

GC6_EVENT# RXE141 2 0_0402_5% S_GC6_EVENT#


@

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 EX IO


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 54 of 69
A B C D E

+5VALW to +5VS +3VALW to +3VS

AP4800BGM AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V VGS=+-25V

+5VALW +5VS +3VALW +3VS

U46 U47
8 1 8 1
1 7 2 1 1 1 7 2 1 1
1 C836 6 3 6 3 1
@ 5 C837 C838 5 C840 C841
10U_0603_6.3V6M 1U_0603_10V4Z @ C839 10U_0603_6.3V6M 1U_0603_10V4Z

1
2 AP4800BGM-HF 2 2 2 10U_0805_10V6K AP4800BGM-HF 2 2
4

4
R1474
10U_0805_10V6K R1475 @
@ For ESD request 470_0603_5%
470_0603_5%

2
R1089
5VS_GATE_R 1 R1088 2 5VS_GATE R1085 3VS_GATE_R1 2 3VS_GATE 2 R1086 1
+VSB +VSB
82K_0402_5% 150K_0402_5% 470K_0402_5%
1 1 R_short 0_0402_5%

1
C842 D D @ C843 D D @
0.01U_0402_25V7K 2 SUSP 2 0.01U_0402_25V7K 2 SUSP 2
R1484 R1483
@ G G Q101 @ G G Q102
2 820K_0402_5% 2 820K_0402_5%
S Q99 S 2N7002KW_SOT323-3 S Q100 S 2N7002KW_SOT323-3

3
2N7002KW_SOT323-3 2N7002KW_SOT323-3
2

2
+5VALW +3VALW to +3V_PCH
+5VALW +0.675VS
1

+3VALW +3V_PCH
J11 @

1
R1120 1 2
DS3@
100K_0402_5% 1 2 R1097 R1094
2 100K_0402_5% 22_0603_5% 2
JUMP_43X79
2

PCH_PWR_EN#_R R60 1 DS3@ 2 PCH_PWR_EN#

2
100K_0402_5% SUSP
D DS3@ <10,40,61> SUSP
1

PCH_PWR_EN 1 R117 2 2
<46,57> PCH_PWR_EN Q118 Q148

3
G 2N7002_SOT23 AO3413_SOT23 D D
R_short 0_0402_5% 2 5 SUSP
S <32,46,60,61,62> SUSP#
3
1

PM_SLP_SUS# R1448 2 1 3 1

D
@ G G
<15,46> PM_SLP_SUS#
0_0402_5% Id=3.2A Q107B
R1121 DS3@ 1 1 Q107A S S 2N7002KDWH_SOT363-6

4
100K_0402_5% 2N7002KDWH_SOT363-6

G
C1065

2
@ @ C1066
0.1U_0402_16V4Z
2

0.01U_0402_25V7K For Intel S3 Power Reduction.


2 2

PCH_PWR_EN#_R

1
R1453 C39 @

通通Power 修修58頁, 反反
LAN_WAKE# 2 @ 1 PCH_PWR_EN#_R 0.1U_0402_16V4Z +3VS +3VS_VGA
40,41,46> LAN_WAKE#
0_0402_5%
2
Q145
AO3413_SOT23
+5VALW
3 1

D
+3VS to +3VS_VGA 1 1

1
C1058 C1059

1
+5VALW +5VS +3VALW +3VS +3VL @ @

G
R1449 0.1U_0402_16V4Z 0.01U_0402_25V7K 1

2
47K_0402_5% 2 2 R1450 @ C37
470_0603_5% 10U_0603_6.3V6M

2
3 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 2 3
1
1 R1451

2
C44 C43 C42 C45 C40 C41 C46 DGPU_PWR_EN# 2
10K_0402_5%
1

1
2 2 2 2 2 2 2 R1452 D C1011 D @
1 2 2 0.1U_0402_10V7K DGPU_PWR_EN# 2
<14,23,54> DGPU_PWR_EN
G G Q149
R_short 0_0402_5% Q146 S 2 S

3
1
2N7002KW_SOT323-3 2N7002KW_SOT323-3
R1454
100K_0402_5%

For ESD request

2
+3VS +3VS_SLI
+3VS to +3VS_SLI
2012-0419 --> modify +3VS_SLI BOM structure to "SLI@" Q147
AO3413_SOT23
+5VALW 3 1
S

1 1
@ @
C1062 C1063
1

1
G

0.1U_0402_16V4Z 0.01U_0402_25V7K 2
2

R1502 2 2 R1500 @ C48


47K_0402_5%
470_0603_5% 10U_0603_6.3V6M
4 1 4
1 R1513
2

2
<32> S_DGPU_PWR_EN#
10K_0402_5%
1
1

D C1012 D @
2 R1503 1 2 0.1U_0402_10V7K S_DGPU_PWR_EN# 2
<19,32,54> S_DGPU_PWR_EN
G G Q151 Title
R_short 0_0402_5% Q150 S 2 S
Security Classification LC Future Center Secret Data
3

3
1

2N7002KW_SOT323-3 2N7002KW_SOT323-3 DC V TO VS INTERFACE


Issued Date 2012/07/01 Deciphered Date 2014/07/01
R1501
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y501 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 55 of 69

A B C D E
5 4 3 2 1

DC030006J00 VIN

PF101 PL101
12A_65V_451012MRL SMB3025500YA_2P
4
4 APDIN 1 2 APDIN1 1 2
B+ B+_SLI
3
3
PQ102
SLI@ +5VS to +5VS_SLI

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2 AON7403L_DFN8-5 JUMP_43X79
2 +5VS +5VS_SLI
1
PJ102

1
D 1 2 5 @ D
1

0.1U_0603_25V7K
3 1 2
1 2

PC110
2

2
@ 4602-Q04C-09R 4P P2.5

PC101

PC102

PC103

PC104
SLI@
JDCIN1 PQ103 AO6409L_TSOP6

0.22U_0603_25V7K

2
SLI@

D
6

S
2

PC109
SLI@ 4 5
PR110 2

0.01U_0402_16V7K
1

0.1U_0402_16V4Z
200K_0402_1% 1 1

G
1
SLI@ PR111 SLI@ PC113

PC112
200K_0402_1% 10U_0603_6.3V6M
SLI@ 2 2

PC111
2 SLI@

1
SLI@

2
PR113
47K_0402_1% PR112 SLI@
SLI@ 47K_0402_1%

1
VIN
<32> SLI_B+_ON# <32> SLI_5V_ON#

LL4148_LL34-2
2
@

PD101
@
PD102

1
C LL4148_LL34-2 PJ101 51ON-1 C

BATT+ 2 1 @ JUMP_43X39

1
68_1206_5%

68_1206_5%
1 2 @ @
1 2

PR101

PR102
@ PQ101
PR103 @ TP0610K-T1-E3_SOT23-3

2
200_0402_1%
1 2 51ON-2 3 1
VS
0.22U_0603_25V7K

@ @
1

100K_0402_1%

0.1U_0603_25V7K
2

1
PR104

PC105

PC106
1

@ PR105 2 @
2

22K_0402_1%
1 2 51ON-3

+3VLP
<53> 51_ON#
- JRTC1 + PR106
560_0603_5%
PR107
560_0603_5%
PD103
2 1 1 2 1 2 2 1
+RTCBATT

RB751V-40_SOD323-2
2

0_0402_5%

@ MAXEL_ML1220T10 1 2 +CHGRTC
+CHGRTC
PR108

PD104
@ PU101 PR109 RB751V-40_SOD323-2
@ 200_0603_5%
RTC Battery
1

APL5156-33DI-TRL_SOT89-3
3.3V
2

3 2 CHGRTCIN
B VOUT VIN B
1

GND PC108
PC107 1U_0805_25V6K
10U_0603_6.3V6M 1
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Vin Detector


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 56 of 69
5 4 3 2 1
5 4 3 2 1

VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5

1
D 6 D
6

1
7 PC201 PC202
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND 9
GND PR201

PR202
TYCO_1775789-1
2

2
@
For KB930 --> Keep PU1 circuit
PH1 under CPU botten side :
(Vth = 0.825V)
CPU thermal protection at 92+-3 degree C
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
Recovery at 56 +-3 degree C
PH201, PR205,PR211,PQ201,PR208,PR212
EC_SMB_CK1 < 34,47,51,59>

EC_SMB_DA1 < 34,47,51,59>

1 2
+3VALW
VL
PR203 +3VLP

0.1U_0603_25V7K
6.49K_0402_1%
<47,59> ADP_I PR222

2
4.42K_0402_1%

13.7K_0402_1%

21.5K_0402_1%
PC207
4.42K:90W

1
1 2
BATT_TEMP <47>
9.1K:120W

PR222

PR225

PR226
PR204

2
10K_0402_5% @
+3VS 16.5K:170W

1
PU201 @

2
1 8 NTC_V_1
VCC TMSNS1

100K_0402_1%
C 2 7 OTP_N_002 2 1 C
@ GND RHYST1

100K_0402_1%_NCP15WF104F03RC
1
0_0402_5%
PR218

PH201
3 6 TURBO_V_1 PR224
<6,47> H_PROCHOT# OT1 TMSNS2

2
10K_0402_1%

10K_0402_1%

PR230
4 5 ADP_OCP_2 1 2
@

1
@ OT2 RHYST2

0_0402_5%
PR221

2
D G718TM1U_SOT23-8 @ 57.6K_0402_1%

2
PR231

PR223
PQ201 @ 2 ADP_OCP_1

1
OTP_N_003
2N7002KW_SOT323-3 G
S

1
PR219 @ @
0_0402_5% PR220
+3VALW <47> PROCHOT#

NTC_V
3V--- 90W 1 2 2 1
MAINPWON <47,60>
1.5V--- 120W 0_0402_5%
0V--- 170W PR221

TURBO_V
<47>
PR227
2 1
57.6K:90W
100K_0402_5%
AD_ID <47>
82.5K:120W <47>
76.8K:170W
2 1

PR228
47W@ 100K_0402_5%

B B

P2
PQ202
+3VALW +3VALW
0.01U_0402_25V7K

TP0610K-T1-E3_SOT23-3
1

100K_0402_1%

100K_0402_1%
PC203

3 1
B+ +VSBP
2

VMB2

100K_0402_1%
PR210

PR211

0.22U_0603_25V7K
2

1
PR217

PC205
PR205 PR209
2

255K_0402_1% 10M_0402_5% PC206


1

1 2 0.1U_0603_25V7K
BATT_OUT <59>

2
PR229 PQ203

2
10K_0402_1% 2N7002KW_SOT323-3 PR216
8

1 2 +3VL 22K_0402_1%
1

3 D 1 2
P

+ 1 2
O
2

PR206 2 G
-
G
2

150K_0402_1% PU202A S @ PR214


3

AS393MTR-E1 SO 8P OP 200K_0402_1%
4

+3VALW @PR215
@ PR215 PR233 PQ204
1

0_0402_5% 1K_0402_1% D PJ201


1

1 2 1 2 2 2N7002KW_SOT323-3 @ JUMP_43X39
<60> SPOK
100K_0402_1%

2 1 G 1 2
+CHGRTC +VSBP 1 2 +VSB
2

S
3
1
PR212

PR207 PR232 PC204


10K_0402_1% 0_0402_5% 1U_0402_6.3V6K
1 2
<47,56> PCH_PWR_EN
2
1

A PQ205 A
PR213
1

D 2N7002KW_SOT323-3
2 1 2
<47> BATT_LEN#
G
10K_0402_1% S
3

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 BATTERY CONN/OTP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 57 of 69
5 4 3 2 1
5 4 3 2 1

Charge Option() bit[8]=1

P3
B+
P2

PQ301 PQ302
AO4423L 1P SO8 AO4423L 1P SO8
8 1 1 8
VIN 7 2 2 7 0.01_2512_1% PR327 PL302 CHG_B+
6 3 3 6 1UH_PCMB061H-1R0MS_7A_20%
5 5 1 4 1 2 PQ310
AO4423L 1P SO8
2 3 1 8

@ 10U_0805_25V6K

@ 10U_0805_25V6K
4

4
D D
2 7

2
PC302 3 6

2200P_0402_50V7K
PQ303 2200P_0402_50V7K 5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 2

PC323

PC322
1

1
1

2
200K_0402_1%
0.1U_0603_25V7K

PC318

4
1

PC321

PC320

PC319
PR301 DTA144EUA_SC70-3 DISCHG_G
3

PC301

PR302
200K_0402_5% 1 2

1
PR325
PC303 @ 47K_0402_1%
2

2
2 0.1U_0603_25V7K 1 2

2
VIN

2ACOFF-1

1SS355_SOD323-2
2
ACP ACN
1

PR326

1DISCHG_G-1
10K_0402_1%
1

2
PD303
P2-1 PR324

0.1U_0603_25V7K

1
2 200K_0402_1%
PQ304 PQ309

1
PC313 PC312 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3 +3VALW P
PR303 <60> 1 2 2 1 PD302
3

ACPRN 1SS355_SOD323-2
20K_0402_1%
0.1U_0603_25V7K 2 1 2

100K_0402_1%
6 2
6

@ 10K_0603_1%
1

1
PR315 @
PQ307A PC311

2
PR304

PR317
PQ305A 2N7002KDW -2N_SOT363-6
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K

6
2 PQ308A

0.1U_0603_25V7K
BATT_OUT <58> 2 1
150K_0402_1% 2N7002KDW -2N_SOT363-6
1

1
PC317
VIN PR314 @ PR316 @
1

1
C 2 1 1 2 2 PACIN C
2N7002KDW-2N_SOT363-6

4.7M_0603_1% P2 PQ311
390K_0603_1%

2
1

5
P2-2

39.2K_0402_1% AON7408L_DFN8-5

1
PR308

1
PQ305B

PR321
3

10_1206_5%

ACOK

CMPIN

CMPOUT

ACP

ACN
PR305 PR309 <47,59> ADP_I 1 2
2

47K_0402_1% 64.9K_0603_1% 21 4
PACIN 1 2 5 1 2 6 TP
ACDET PC310
PC304 .1U_0603_25V7K PC305 20 1 2
4

2 1 1 2 7 VCC PL301

3
2
1
PR310 IOUT PR332
1U_0603_25V6
1

PQ306 0_0402_5% 100P_0603_50V8 19 4.7UH_PCMB104E-4R7MS_10A_20% 0.01_2512_1%


PHASE
DTC115EUA_SC70-3 EC_SMB_DA1
<41,47,51,58>
1 2 8
SDA
PU301
1 2 1 4
BATT+
PR311 BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG CHG
PR306 0_0402_5% 18 DH_CHG
HIDRV

5
1 2ACOFF-12 EC_SMB_CK1 1 2 9 2 3
<47> ACOFF SCL

1
10K_0402_5% <41,47,51,58> PR322 PC309 PQ312
PR312 2.2_0603_5% 0.047U_0603_16V7K

4.7_1206_5%
AON7702L_DFN8-5
1

1 2 10 17 BST_CHG 1 2 2 1

10U_0805_25V6K

10U_0805_25V6K
+3VALW P ILIM BTST
1

PR323
16251_SN
PR307 147K_0402_1% PD301
3

RB751V-40_SOD323-2 4

LODRV
0_0402_5%

1
16 2 1

PC315

PC316
PR313

GND
SRN

SRP
REGN
BM
100K_0402_1%
2

2
680P_0603_50V7K
BQ24737_VDD
BM# 11

1 12

13

14

15

3
2
1
3

PC314
10_0603_5%
6.8_0603_5%

2
1
PR320
PR318 PR319
18K_0402_1% PC308
BATT_OUT 5 2 1 1U_0603_25V6

2
B B
2

PQ307B
4

2N7002KDW -2N_SOT363-6 PC307 DL_CHG


0.1U_0603_25V7K
2 1
0.1U_0603_25V7K
1

0.1U_0603_25V7K
1
PC306

PC324
2

BQ24737_VDD
@
PR330
10K_0402_1%
1

1
1 2
ACIN <47>
PR329
PR328 10K_0402_1%
47K_0402_1%
2

2
PACIN
2N7002KDW-2N_SOT363-6

1
3
PQ308B

PR331

ACPRN 5 12K_0402_1%
2
4

A A

For disable pre-charge circuit.

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 CHARGER


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 58 of 69
5 4 3 2 1
5 4 3 2 1

PJ401
PR401 +3VALW P 2 1 +3VALW
13K_0402_1% 2 1
1 2 @ JUMP_43X118
@
PC410 +3VL PC422
0.1U_0402_25V6 0.1U_0402_25V6
@
1 2 1 2 PJ402
+5VALW P 2 1 +5VALW
2 1

1U_0603_10V6K
D D

2
PR411 @ JUMP_43X118

0_0603_5%~D

1
30K_0402_1%

PR406

PC418
1 2

2
PR403 PR408

1
20K_0402_1% 20K_0402_1%
1 2 1 2

+3VLP

2
B++

2
PR405 PR407
B++ 130K_0402_1% 56K_0402_1%
FB_3V FB_5V

1
1
PJ403

2 1 PU401
B+

2200P_0402_50V7K
2 1

1
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
0.1U_0603_25V7K

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

1
@ JUMP_43X118

PC419

PC420

PC417
CS2

VFB2

VREG3

VFB1

CS1
21
PC405

PC401

PC414
PAD
1

3V_EN 6
PC402

PC403

PC404

2
EN2
8
7
6
5
14 @
VO1

5
6
7
8
<58>
2

PQ401 7 PQ402
AO4466L_SO8 SPOK PGOOD 19 AO4406AL_SO8
C VCLK C
4 UG_3V 10 TPS51225CRUKR_QFN20_3X3
PC413 PR402 DRVH2 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR410 PC415
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2
1
2
3

VBST1

3
2
1
SW 2_3V 8
SW2 18 SW 1_5V

VREG5
DRVL2

DRVL1
+3VALWP PL402 SW1 PL401
+5VALWP

EN1
VIN
3.3UH +-20% PCMB063T-3R3MS 6.5A 4.7UH_VMPI1004AR-4R7M-Z01_10A_20%
2 1 1 2

11

12

13

5V_EN 20

15
1

8
7
6
5

5
6
7
8

1
LG_3V LG_5V
4.7_1206_5%

4.7_1206_5%
330U_D2E_6.3VM_R25M

PQ403 PQ404
PR409

PR412
1
AO4712_SO8

330U_D2E_6.3VM_R25M
+
PC409

1
1 SNUB_3V 2

2
4 4 +

PC408
2

1SNUB_5V
2

1U_0603_10V5K
0.1U_0603_25V7K

2
AO4456_SO8

0_0603_5%~D
680P_0603_50V7K

680P_0603_50V7K
1
2
3

3
2
1
1

1
PC411

PC421

PR404
PC412

PC416
2

2
2

2
B B
3V_EN 1 2
B++ VL
PR414 0_0402_5%

5V_EN 1 2

PR415 0_0402_5%
PR413
2.2K_0402_5%
<47,53> 1 2
EC_ON

PD401
LL4148_LL34-2
<47,58> 1 2
MAINPW ON
1 2
@ PR420
D 3VALWP 5VALWP
1

330_0402_5%
PR419 @
100K_0402_5%
2
G
Imax=7.5A Imax=10A
S PQ405 @ OCP current 8.6A~13.92A OCP current 11.5~19.5A
3

2N7002KW _SOT323-3
TYP MAX TYP MAX
2

H/S Rds(on): 22mohm , 30mohm H/S Rds(on):22mohm , 30mohm


@ PD402 @ PR416 L/S Rds(on):10.8mohm ,13.6mohm L/S Rds(on):10.8mohm , 13.6mohm
A A
LL4148_LL34-2 1M_0402_1%
2 1 1 2
VL
402K_0402_1%

4.7U_0603_6.3V6K
1
PR417

PR418
PC423

Security Classification LC Future Center Secret Data Title


316K_0402_1%
1 2
VS Issued Date 2012/07/01 Deciphered Date 2014/07/01 3VALWP/5VALWP
2
2

@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 59 of 69
5 4 3 2 1
A B C D

PL501
HCB1608KF-121T30_0603 PC510 PR504
B+ 1 2 B+_1.35V 0.22U_0402_10V6K 2.2_0603_5%
1 2 1 2

2200P_0402_50V7K
68P_0402_50V8J

10U_0805_25V6K
0.1U_0402_25V6

4.7U_0805_25V6-K
PR505

1
PC501

PC502

PC503

PC504

PC505
0_0402_5%
1 2
+1.35VP

2
+0.675VSP

VIN_0.675V
BST_1.35V

VIN_1.35V
DH_1.35V
LX_1.35V
5

10U_0805_6.3VAM

10U_0805_6.3VAM
1
PJ501 1

1 1

PC514

PC515
2 1
+1.35VP +1.35V

16

17

18

19

20
4 PU501 2 2 JUMP_43X118

PHASE

UGATE

BOOT

VLDOIN

VTT
PQ501 21
PAD PJ502
PL502 SIS472DN-T1-GE3
2.2UH_VMPI0703AR-2R2M-Z01_8A_20% DL_1.35V 15 1 2 1

1
2
3
LGATE VTTGND
+0.675VSP 2 1
+0.675VS
1 2
+1.35VP 14
PGND VTTSNS
2 VTTSNS_0.675V JUMP_43X39

5
PR503
20.5K_0402_1%
PR501 1 2 CS_1.35V 13 3
4.7_1206_5% CS RT8207MZQW _W QFN20_3X3 GND
330U_D2_2.5VY_R15M

1
+5VALW
2
4 VDDP_1.35V 12 4 VTTREF_0.675V
+ VDDP VTTREF
PC506

PR502
1SNB_1.35V 5.1_0603_5%
2
+5VALW 1 2 VDD_1.35V 11
VDD VDDQ
5 VDDQ_1.35V +1.35VP

PGOOD
PQ502
680P_0603_50V7K

1
2
3

1
SISA12DN-T1-GE3

TON
PC507

PC508 PC509 PC513

FB
S5

S3
1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K

2
2

10

6
PR531

FB_1.35V
S5_1.35V

S3_1.35V
0_0402_5%

TON_1.35V
<47> VDDQ_PGOOD 2 1
2
PR532 PR507 2

10K_0402_5% 8.06K_0402_1%
+3VS
2 1 1 2 +1.35VP
PR506 PC525
887K_0402_1% 100P_0402_50V8J
B+_1.35V1 2 1 2

1
PR510
10K_0402_1%
1

2
PR519 PR514
PR516 0_0402_5% 0_0402_5%
100K +-1% 0402 1 2
<32,47,56,62,63> SUSP#
2

PR540 @
1

1
0_0402_5%
@ PC518 1 2 @ PC517
<61,62> SUSP#_PWR
0.1U_0402_10V7K 0.1U_0402_10V7K
2

2
<47>
3
SYSON 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 1.35VP/0.675VSP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 60 of 69
A B C D
A B C D

PJ503
JUMP_43X118 B+
2 1
2 1
@

470P_0603_50V7K
10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.1U_0402_25V6
5

1
PC528

PC536

PC537

PC538

PC539
PQ504

2
PD502
RB751V-40_SOD323-2 4
1 1 2 1
<27> FBVDDQ_PW R_EN
PR533 PR529 PC529
0_0402_5% PU502 2.2_0603_5% 0.22U_0603_16V7K MDV1525URH_PDFN33-8-5

3
2
1
1 2 1 10 1 2BST_1.5VSP_VGA-1
1 2
PGOOD VBST PL503
PR524 2 9 1UH_PCMB063T-1R0MS_12A_20%
0_0402_5% TRIP DRVH
1 2 3 8 1 2 +1.5VSP_VGA
<32,47,57,61,62,63> SUSP# EN SW

1
4 7

4.7_1206_5%
VFB V5IN +5VALW

PR521
1M_0402_1%

220U_B2_6.3VM_R15M
1
5 6

PR523

.1U_0402_16V7K
RF DRVL 1

PC530 @

@
PC542

0.1U_0402_10V7K
1

2
11 1U_0603_10V6K +

PC56
2

1SNUB_1.5V2
TP PQ505

75K_0402_1%

470K_0402_1%
1

1 PR527 2
TPS51212DSCR_SON10_3X3

PC58
2

1
2

PR526

680P_0603_50V7K
4

PC526
2

@
2
AON6504_POW ERDFN56-8-5

3
2
1
PR525
0_0402_5%
1 2 PR518 1 2 VDDQ_SENSE <25>
11.5K_0402_1%

1
2 2

PR517 +1.5VSP_VGA PJ504 +1.5VS_VGA


10K_0402_1% 2 1
2 1

2
@ JUMP_43X118

+3VL +5VS +3VALW


1

1
PR537 @
100K_0402_5% PR534 PJ508

1
0_0402_5% JUMP_43X79
@
2

2
3 <60,62> 3

2
SUSP#_PW R +5VS +1.5VSP PJ505 +1.5VS
SUSP#_PW R

2
2 1
D 2 1
1

1
PC549
2 PQ503 @ 1U_0402_6.3V6K @ JUMP_43X118
<34> SUSP
G 2N7002KW _SOT323-3
@
2
1

S
3

1
PR536 PC546
0_0402_5% 4.7U_0805_6.3V6K

6
PU504

2
@ PR538 5
VCNTL
2

1 2 7 VIN
<60,61,62> SUSP#_PWR POK 4 +1.5VSP
0_0402_5% VOUT
3
<32,47,56,61,62,63> VOUT

1
PR535

22U_0805_6.3V6M
1 2 EN_1.5VSP 8 2

PC547
SUSP# EN FB
2

PR522
GND

2
0_0402_5% PR520 9 39.2K_0402_1%
.1U_0603_25V7K

VIN
1
PC545

20K_0402_1%

2
APL5912-KAC-TRL_SO8
1
2

PC548

1
0.01U_0402_25V7K

PR539
VFB=0.8V 44.2K_0402_1%

2
Vo=VFB*(1+PR522/PR539)
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 +1.5VS_VGA/+1.5VS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 61 of 69
A B C D
5 4 3 2 1

+3VS

2
PR703
10K_0402_5%

1
PR715
0_0402_5%
2 1
D D
PJ702 PC702
@ JUMP_43X118 PC717 22U_0805_6.3V6M PU701 PL701

4
22U_0805_6.3V6M S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
+5VALW 1 2 10 2 1 2 +1.05VS_VCCPP

PG
1 2 PVIN LX

1
9 3
PVIN LX

4.7_1206_5%
2

1
2 1 8
@ PR701 SVIN

PR704

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
0_0402_5% PR716 6 +1.05VS_VCCPP PJ701 +1.05VS
1 2 10_0402_5% 5 FB 2 1

PC705

PC706

PC707

PC708
<32,47,56,61,62,63> SUSP# EN 2 1

SS
TP

LX

2
@ PR717 SY8036LDBC_DFN10_3X3 @ JUMP_43X118

2
0_0402_5%

1U_0402_16V6K

680P_0603_50V7K
11

1
1
@
1 2

PC718
<60,61> SUSP#_PWR

1
PR702 @ PC701

PC704
1
PR718 47K_0402_5% .1U_0402_16V7K

2
0_0402_5% PC703

2
1 2 .1U_0402_16V7K
<47> SUS_VCCP

2
PR706
2 1
VFB=0.6V

1
75K_0402_1%
Vo=VFB*(1+PR706/PR705) PR705
100K_0402_1%
2 1
C C

2
PC709
22P_0402_50V8J

+3VS
2

PR713
10K_0402_5%

PR714
1

0_0402_5%
2 1
PU702 PL702
PJ703 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.05VMP_VIN 4 3 1.05VMP_LX 1 2
+3VALW 2 1 IN LX +1.05VSP_VGA
5 2

68P_0402_50V8J
JUMP_43X39 PG GND
1

1
PC710
680P_0603_50V7K 4.7_1206_5%

1
B @ PC716 22U_0805_6.3VAM 6 1 PR708 B

PC711
22U_0805_6.3VAM FB EN 75K_0402_1%
PR707
2

PJ704

2
SY8032ABC_SOT23-6 +1.05VSP_VGA 2 1 +1.05VS_VGA

22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

2
2 1

1
FB=0.6Volt
@ JUMP_43X79

PC713

PC714
PD701
PC712

2
2

RB751V-40_SOD323-2
1 2

PR709
1 2 EN_1.05VMP 1.05VMP_FB
<19,27,55,64> DGPU_PW ROK
1

0_0402_5%
0.1U_0402_10V7K
2

PC715 @

PR711
1

PR710 100K_0402_1%
1M_0402_5%
PR712
2

1 2
<32,47,56,61,62,63> SUSP#
1
@

0_0402_5%

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01 +1.05VS/+1.05VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 62 of 69
5 4 3 2 1
A B C D

+VGA_CORE Under VGA Core GB4-128 package

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1

1
+VGA_B+
PC801

PC802

PC803

PC804

PC805

PC806

PC807

PC808

PC809

PC810

PC811

PC812

PC813

PC814
+3VS PL801
HCB2012KF-121T50_0805
2

2
1 2 B+

2
1 PL802 1

@ @ @ @ PR831 HCB2012KF-121T50_0805

2200P_0402_50V7K
10K_0402_5% 1 2
<23> <23>

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_25V6
PD801

1
1

1
DPRSLPVR_VGA
PC815

PC816

PC817

PC818

PC831

PC832

PC833

PC834
RB751V-40_SOD323-2

NVVDD PWM_VID
2 1 <14>
NVDD_PWR_EN
2

2
1
PR803
30K_0402_1% PR832
1 2 100K_0402_5% 4
@
PC855

2
+3VS_VGA
+VGA_CORE Near VGA Core .1U_0402_16V7K
1 2
PR821
0_0603_5%
PC838
0.22U_0603_10V7K PQ801

3
2
1
2 1BOOT1_2_VGA 1 2 PR822 FDMS7698
0_0402_5%

10K_0402_5%
2 1 UGATE1_2_VGA PL803
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
+VGA_CORE

0_0402_5%

0_0402_5%
22U_0805_6.3V6M

47U_0805_6.3V6M

1 0.24UH_FDUE0630J-H-R24M-P3_22A_20%
1

1
PC829

PC830

PC819

PC820

PC821

PC822

PC823

PC824

PC825

PC826

PC827

PC828
1 2

BOOT1_VGA
2

5
2

1
2

PR801

PR804

PR802
@ @ @ @ @ @ PR820
PC858 4.7_1206_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1

1
PR830 0_0402_5% 10P_0402_50V8J LGATE1_VGA 4 4

1SNUB1_VGA 2
+ +

PC836

PC837
2 1 2 1
PR827
2 100K_0402_1% PR824 PR823 GPU_VID 2

1
2 2

PSI_VGA
2 1 20K_0402_1% 20K_0402_1% UGATE1_VGA PQ802 PQ806

EN_VGA

3
2
1

3
2
1
VREF 2 1 2 1VIDBUF PR834 @ FDMC0310AS FDMC0310AS
2
G

PQ805 PR828 2.2_0402_5%

1
2N7002KW_SOT323-3 5.1K_0402_1% @ PC859 @ PC835

PHASE1_VGA
3 1 2 1 2700P_0402_50V7-K PR829 680P_0402_50V7K

2
@
S

2K_0402_1%

2
6

1
PR825 PR826

2
0_0402_5% 18K_0402_1%

VIDBUF

VID

EN
PSI

HG1

BST1
2
2 1 2 1

2 1 PC856 7 24
REFIN PH1
PR805 = 34K ==>Fsw = 450KHz PC854 2200P_0402_50V7K PC839
1 2 VREF 8 PU801 23 4.7U_0603_10V6K
0.01U_0603_50V7K PR805 VREF LG1
2 1 FS 9 NCP81172MNTWG_QFN24_4X4 22 1 2
PR806 0_0402_5% 34K_0402_1% FS PGND

<24> VSSSENSE_VGA 1 2 VSS_SEN 10 21 PVCC_VGA 1 2 +5VS


FBRTN PVCC PR811 0_0402_5%
PC852 PR809 FB_VGA 11 20
FB LG2
1

PC853 47P_0402_50V8J 51_0402_1% PC850 10P_0402_50V8J +VGA_B+


1000P_0402_50V7K 1 2FB1_VGA1 2 1 2 COMP_VGA 12 19

TALERT#
PR808 COMP PH2

PGOOD
2

10K_0402_1%

TSNS

BST2
GND

VCC

HG2

2200P_0402_50V7K
<24> VCCSENSE_VGA 1 2 VCC_SEN 1<BOM Structure>
2 1 2FB2_VGA1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
5
PR807 0_0402_5% PC851 PR810
25

13

14

15

16

17

18

1
PC840

PC841

PC842

PC843
100P_0402_50V8J 82K_0402_1%

3 BOOT2_VGA PR818 3

VCC_VGA

2
0_0402_5%
UGATE2_VGA 2 1 UGATE2_2_VGA 4
<19,27,55,63>
100K_0402_1%_NCP15WF104F03RC

DGPU_PWROK
1

5.9K_0402_1%

PR816 10K_0402_5% PR817 PC847 PQ803

3
2
1
PC849 2 1 +3VS 0_0603_5% 0.22U_0603_10V7K FDMS7698
PH801

.1U_0402_16V7K 2 1 BOOT2_2_VGA 1 2
2

PR815 2.2_0402_5% PL804 +VGA_CORE


2 1 +5VS 0.24UH_FDUE0630J-H-R24M-P3_22A_20%
2

PHASE2_VGA 1 2
2

1U_0402_10V6K

5
PR812
2

1
PC848

Thermistor near MOSFET


1

@
trigger point 97 degree C. PR819
4.7_1206_5%

330U_D2_2V_Y

330U_D2_2V_Y
1 1
VREF

LGATE2_VGA 4 4

1SNUB2_VGA 2
+ +

PC845

PC846
PR814 0_0402_5%

1
2 1
N14P-GT 35W N14P-GS 25W PR833 @ PQ804 PQ807 2 2

3
2
1

3
2
1
PR813 10K_0402_5% 2.2_0402_5% FDMC0310AS FDMC0310AS
Ipeak=50A Ipeak=36A 2 1 +3VS
PC844
Imax=35A Imax=25A

2
@ 680P_0402_50V7K

2
4
Iocp=64.8A Iocp=64.8A 4

Fsw=450KHz Fsw=450KHz
bulk cap 330uF 9m *5 bulk cap 330uF 9m *3
Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01


VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 63 of 69
A B C D
5 4 3 2 1

D D

PR903
121K +-1% 0603
1 2 SWN3

PR902 PR904

220K_0402_5%_ERTJ0EV224J
165K_0402_1% 47W@ 121K +-1% 0603
1 2 1 2 SWN2 NA for 37W

0.047U_0402_16V7K
CSREF

1000P_0402_50V7K

680P_0402_50V7K
75K_0402_1%

20K_0402_1%
PR905

2
121K +-1% 0603

1
PH901

PR901

PC901

PC902

PC904

@ PR907
1 2 SWN1

PR910

2
5.76K_0402_1%
2

1
CSP3 2 1
SWN3 <66>

Place close to

1000P_0402_50V7K

0.047U_0402_16V7K
CSREF
phase 1 inductir

20K_0402_1%
2

2
PC903

PC905

@ PR908
47W@

1
PR911

2
5.76K_0402_1%
CSREF <66>

1
C C
CSP2 2 1 NA for 37W
SWN2 <66>
CSP3 47W@

0.047U_0402_16V7K
PR906 CSREF

20K_0402_1%
CSP2

2
<47>

PC906

@ PR909
CSP1

CSSUM
CPU_B+

IMVP_IMON
PR919 PR913
DRON <66>

2
PR917 43K_0402_1% 5.76K_0402_1%

1
PR906 37W@ CSP1 2 1
SWN1 <66>
66.5K_0402_1%
2

CSCOMP 1 2 37W=43K
PR918 47W@
10K_0402_1% 1K_0402_1% 37W=10K 47W=66.5K
37W@ 10K_0402_1% +5VALW
37W@ 47W=15.4K 81103_PWM <66>
1

0_0402_5%
0.01U_0402_25V7K

PR914
PC914 PC913

1
390P_0402_50V7K 10P_0402_50V8J PR917
1 2 1 2 1 2 PR912 15.4K_0402_1% 37W@
1
PC912

PR920 24.3K_0402_1% 47W@ PU901 PR915 PC907

27
26
25
24
23
22
21
20
19
49.9_0402_1% 1 2 NCP81103MNTWG_QFN36_5X5 2.2_0603_5% 0.22U_0402_10V6K
1

37W=10K 1 2 1 2

CSSUM
CSREF
CSCOMP

PWM2/IMAX
DRON
CSP3
CSP2
CSP1

BST3
2

2
PC911
47W=7.5K 470P_0402_50V8-J CSP2 Mount for 37W
1 2 1 2 2 1 28 18
ILIM HG3 HG3 <66>
PR921 PR919 29 17
IOUT SW3 SW3 <66>
1K_0402_1% 7.5K_0402_1% 30 16 PC908
VRMP LG3 LG3 <66>
47W@ 31 15 1 2 PR951
32 COMP PVCC 14 0_0402_5%
33 FB PGND 13 2.2U_0603_10V7K 1 2
1 2 VSN_1 1 2 VSN_2 34 DIFFOUT LG1 12
LG1 <66> +5VALW
VSN SW1 SW1 <66>
PR922 PR924 35 11
VSP HG1 HG1 <66>
B 0_0402_5% 1K_0402_5% 36 10 B
<9> VSSSENSE VCC BST1
1

VR_RDY
VRHOT#

INT_SEL
TSENSE

1 2
ALERT#

PC915 PR916 PC909


ROSC

37
SCLK

1000P_0402_50V7K 2.2_0603_5% 0.22U_0402_10V6K


SDIO

<9> VCCSENSE GND


PC916 1 2 1 2
EN
2

1 2 VSP 2200P_0402_50V7K
PR923
1
2
3
4
5
6
7
8
9

0_0402_5% PR928
1 2 45.3K_0402_1%
VR_HOT#_1

+5VALW 1 2
TSENSE
VR_SVID_ALRT#_1
2.2U_0603_10V7K

PR925 PR926
VR_SVID_DAT_1

VR_SVID_CLK_1

2_0603_5% 0_0402_5%
VR_RDY
2
PC917

1 2
<47> VR_ON
TSENSE
2

1 2
1

<47> VR_HOT# PR927 PC910


0_0402_5% .1U_0402_16V7K
1
2

PR929

100K_0402_1%_TSM0B104F4251RZ
34.8K_0402_1%
1

+VCCIO_OUT 13K_0402_1%
2

2
PR938

PH902
0_0402_5%

1.91K +-1% 0402


1

1
130_0402_1%

75_0402_1%

54.9_0402_1%
2

PR931

PR930

1
PR934

PR933

PR932

Place close to
2

phase 2 MOSFET
2

PC918
1

.1U_0402_16V7K
1

A A

<9> 1 2 VR_SVID_DAT_1
VR_SVID_DAT
+3VS

PR935
0_0402_5%
VGATE

<9> 1 2 VR_SVID_ALRT#_1
VR_SVID_ALRT#
PR936
0_0402_5%
<9> 1 2 VR_SVID_CLK_1 <6,15>
VR_SVID_CLK
PR937 Title
0_0402_5% Security Classification LC Future Center Secret Data
Issued Date 2012/07/01 Deciphered Date 2014/07/01
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 64 of 69
5 4 3 2 1
5 4 3 2 1

D D

CPU_B+ PL901
FBMA-L11-453215-800LMA90T_1812
1 2
B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.1U_0402_25V6K
5
1 1

68U_25V_M_R0.36

68U_25V_M_R0.36
1

1
+ +

PC920

PC921

PC922

PC923

PC924

PC933

PC934
PR939
2.2_0603_1% PQ901

2
2 1 4 AON6428L_DFN8-5 2 2
<65> HG1

+VCC_CORE
3
2
1
PL902
0.22UH +-20% PCMB104T-R22MS 35A
1 4
<65> SW1

1
2 3

4.7_1206_5%

68P_0402_50V8J

220P_0402_50V7K
5

@ PC926

@ PC925
<65> LG1

1
PR940
V1N_CPU
CPU_B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
0.1U_0402_25V6K
5
4 2 1
CSREF <65>
1SNUB_CPU1

1
PQ902 PR941

PC927

PC928

PC929

PC930

PC931
AON6504_POWERDFN56-8-5 10_0402_1% PR942

680P_0402_50V7K
2.2_0603_1%
SWN1 <65>
3
2
1

2
2 1 4
<65> HG3
PC919

C C
2

PQ903
+VCC_CORE

3
2
1
AON6428L_DFN8-5 PL903
0.22UH +-20% PCMB104T-R22MS 35A
1 4
<65> SW3

1
2 3

4.7_1206_5%
5

PR943
<65> LG3

2
PR944
4 V3N_CPU 2 1 CSREF

SNUB_CPU3
PQ904 10_0402_1%
AON6504_POWERDFN56-8-5
SWN3 <65>

3
2
1

680P_0402_50V7K
1

PC935
2
CPU_B+
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K

2200P_0402_50V7K
PR946 47W@
1

1
2.2_0603_5%
PC939

PC940

PC941

PC942

PC943
B B
BSTA2 1 2 BSTA2_1
2

2
5
1

PC936 47W@ PQ905 47W@


0.22U_0402_10V6K AON6428L_DFN8-5 47W@ 47W@ 47W@ 47W@ 47W@
4
2

Mount for 47W


1 9 47W@ PR947
BST FLAG 2.2_0603_1% PL904 +VCC_CORE
3
2
1

2 8 HG2 2 1 0.22UH +-20% PCMB104T-R22MS 35A


<65> 81103_PWM PWM DRVH
47W@
2 PR945 1EN_VCORE2 3 7 SW2 1 4
<65> DRON EN SW
2K_0402_1%
1

+5VALW 2 1 VCC_VCORE2 4 6 2 3
VCC GND
5

5 LG2 PR949
DRVL 4.7_1206_5% 47W@
1

47W@ PR948 PU902 47W@


2

0_0402_5% PC937 47W@ NCP81151MNTBG_DFN8_2X2


2.2U_0603_10V7K 47W@ 4
2

SNUB_CPU2

47W@ PQ906 PR950


AON6504_POWERDFN56-8-5 10_0402_1%
V2N_CPU 2 1 CSREF
3
2
1

47W@
1

PC938
680P_0402_50V7K
SWN2 <65>
47W@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01


CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 65 of 69
5 4 3 2 1
5 4 3 2 1

Based on PDDG rev 0.7 Table 5-1.


+VCC_CORE

1 1 1 1
+VCC_CORE + PC1030 + PC1031 + PC1032 + PC1033

470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D 470U_D2_2VM_R4.5M~D


2 2 2 2
D 1 1 1 1 1 D
PC1001 PC1002 PC1003 PC1004 PC1005 @ @ @

10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM


2 2 2 2 2

1 1
+ + PC1035
1 1 1 1 1 1 PC1034 470U_D2_2VM_R4.5M~D
PC1011 PC1010 PC1009 PC1008 PC1007 PC1006 470U_D2_2VM_R4.5M~D
2 2
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 @

+VCC_CORE
1 1 1 1 1
PC1016 PC1015 PC1014 PC1013 PC1012
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

C 1 1 1 1 1 C

PC1017 PC1018 PC1019 PC1020 PC1021


22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1 1
PC1026 PC1025 PC1024 PC1023 PC1022
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1
PC1027 PC1028 PC1029 PC1036
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2012/07/01 Deciphered Date 2014/07/01
PROCESSOR DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 66 of 69
5 4 3 2 1
5 4 3 2 1

D D
2-A
PCH_PWR_EN#
Q148,+3VALW_PCH

V
AC A1
MODE VIN Q149,+5VALW_PCH

V V
A2 A3 B5
B+

VV
PU301 PU401 A5 2

V
+3VALW_PCH
+3VALW B7 2 3
BATT B2 V +5VALW_PCH
BATT
MODE
B1 BATT+ VS B4
PCH_DPWROK_R
2 V SYS_PWROK
V

V
V
V
PQ101 EC PCH_RSMRST#
4
PM_DRAM_PWRGD_CPU
10-A

V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
51ON# EC_ON
15
PM_SLP_S3# PLT_RST#
C PM_SLP_S4# C

PM_SLP_S5#
A4 B6 PM_SLP_A# 6

V
V
ON/OFFBTN# V
ON/OFF
SYSON 7 PU501

V
+1.35V, +0.675VS
DGPU_PWR_EN (GPU) 8-A
NVDD_PWR_EN (PCH) (DIS) Q145, Q147

V
+3VS_VGA
11
8 +3VS_SLI
SUSP#,SUSP U46

V
VGATE
+5VS
U3

V
+1.35V_CPU_VDDQ

V
U47
PU502, PU702
+3VS +1.5VS_VGA
+1.05VS_VGA
B
V B

V
PU503
+1.8VS 8-B
(DIS)
SUSP#,SUSP

DGPU_PWROK (PWR IC)

V
PU504

V
+1.5VS PU801
+VGA_CORE

V
PU701 PU701
V

+1.05VS_VCCP
+1.05VS +1.05VS 9
VDDQ_PWRGOOD
V

VR_ON 10
PU901

V
V

+VCC_CORE
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Power Sequence


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 67 of 69
5 4 3 2 1
5 4 3 2 1

HW PIR (Product Improve Record)


QIQY5 LA-8691P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/03/09

D
NO DATE PAGE MODIFICATION LIST PURPOSE D
---------------------------------------------------------------------------------------------------------------------
01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 HW PIR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 68 of 69
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1


for PWR
Item Reason for change PG# Modify List Date Phase

1
D D

7
8

C C
9

10

11

12

13

14

B B

15

16

17
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 PWR PIR


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Y510 NM-A032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, March 27, 2013 Sheet 69 of 69
5 4 3 2 1
www.s-manuals.com

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