Influence of gate geometry in integrated MOS

varactors on accumulation mode for RF

E. Amselem, B. Gonzalez, J. Garcia, I. Aldea, M. Marrero, A.G. Iturri, J. del Pino,
S.L. Khemchandani, and A. Hernaindez
Institute for Applied Microelectronics, and Departamento de Ingenieria Electronica y Automaitica,
Universidad de Las Palmas de Gran Canaria, Campus Universitario de Tafira,
35017, Las Palmas de Gran Canaria, Spain ([email protected]).

Abstract- Driven by the many applications that varactors II. FABRICATION, MEASUREMENT AND SIMULATION
have in RF integrated blocks, this work analyzes the influence of
gate geometry (width and length) on integrated accumulation A. Fabrication
MOS varactors. For this purpose, a number of varactors have
been designed and fabricated on a 0.8 ,Im CMOS standard Our varactors have been designed interconnecting basic
technology. The most relevant parameters: quality factor, tuning cells in 0.8 ptm CMOS standard technology. Figure 1 shows
range, and capacitance, are simulated and compared against the layout of a basic cell. It is a symmetric set of six
measurements. Some design considerations are reported. MOSFETs, having all drain/source terminals interconnected to
ground: six single accumulation mode varactors in parallel.
Index Terms- integrated circuit, MOS, RF, varactor. The resulting structure is surrounded by a contact metal that
connects a buried layer under it to the drain/source terminals.
I. INTRODUCTION
Table I shows the gate geometry and number of basic cells
N OWADAYS silicon integrated circuits find many used for all fabricated varactors. In order to consider the
applications in the gigahertz range of frequencies, influence of the gate geometry on the most relevant
particularly at the standards GPS, UMTS, Bluetooth and LAN, characteristic parameters (capacitance, C, quality factor, Q,
where varactors are needed. In some RF integrated blocks, and tuning range, TR), the gate width, w, is scaled in M2
such us tunable filters or LC tanks for voltage controlled
oscillators (VCOs), varactors are essential [1, 2]. They can
also be used as simple capacitors in others RF blocks such as
low noise amplifiers, mixers, or for impedance matching
networks [3].
The studied MOS varactors operate in accumulation mode.
The drain and source terminals are connected, Vd5= 0, and the
gate to drain/source voltage, Vgs, set the required capacitance.
By changing the operation mode from depletion to
accumulation, the capacitance rises from a minimum to a
maximum value. When a negative voltage is applied between
the gate and drain/source contacts, Vg, < 0, the total
capacitance is the series connection of the oxide capacitance,
COX, and the depletion capacitance, Cj. When the applied
voltage is reversed, Vg, > 0, electrons coming from the two n+
diffusion regions and the n-well accumulate under the oxide.
In this case the gate capacitance reaches its maximum value,
Cox. Fig. 1. Layout of the MI basic cell.
In section II the classical design flow used so far is
TABLE I
reviewed. The practical considerations assumed to develop the GEOMETRICAL PARAMETERS OF THE MOS VARACTORS
work are explained in Section III, together with the simulated
and measured results when varying the gate geometry. Finally, Varactor varactorwvw (jm)
(m) /Z (~tm)
(m) ~~~~~~basiccells
Number of

some conclusions about this work are reported in Section IV. Ml 10 0.8 40
M2 20 0.8 24
M3 30 0.8 16
M4 10 1.6 35
M5 10 2.4 30

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 frequency.
C. Simulation
Three dimensional numerical simulations have been carried
out for every basic cell with Taurus Device [6]. The simulated
results for their capacitance, quality factor and tuning range
are compared with measurements.
Due to symmetry, it is only necessary to simulate half of a
basic cell, as figure 3 shows for varactor MI. As the buried
layer, connected to ground, electrically de-couples the
substrate from the n-well, the structure has been simulated
replacing all layers beneath the n-well by a grounded ohmic
Fig. 2. Microphotograph of the integrated MOS varactor MI with the guard- contact (p-substrate influence is neglected). Thus CPU time is
ring.
reduced and more precise simulations are performed (a higher
(double) and M3 (triple), and the gate length, 1, is scaled in M4 number of nodes, limited to 40.000, can be used in half a basic
(double) and M3 (triple) than that for Ml. cell).
B. Measurement Obviously, the resistance and capacitance of a basic cell
Varactors characterization has been carried out with a
simulated will be the half and double of the simulated values,
measurement system based on the Agilent 8720ES Vector
respectively.
Network Analyzer. The calibration was performed following
the Short-Open-Load-Through (SOLT) method. As figure 2
III. RESULTS
shows, the varactors have been designed and fabricated
surrounded by guard rings, in order to use the Cascade ACP40 A. Preliminary considerations
GSG microprobes. The de-embedding method determinates
Parasitic capacitance, mainly due to interconnections, is not
the parasitic elements that appear in the measurement structure taken into account in simulations. Figure 4 shows the
of the device under test. We have selected a de-embedding
method [4], based on the four-step de-embedding technique characteristic curve, capacitance versus frequency, measured
and simulated for the basic cell of MI. Notice how the
[5], to extract the guard-ring influence. Thus, resistance and simulated curve is vertically down displaced by parasitic
reactance of every varactor are measured from S-parameters.
As far as our varactors have a different number of cells, it is
capacitances: Cparai in inversion mode and Cpara2 in
accumulation mode. However, for simplicity, the same
necessary to normalize the measurements to just one basic cell
in order to compare them. As all cells are shunt-connected, the
parasitic capacitance, Cpara. is assumed for all operation
regions, equal to the average value of Cparal and Cpara2:
value of the resistance of one basic cell, Rcell is calculated by
multiplying the number of cells, n, of the corresponding
varactor, by the total resistance, R. Therefore: C para - Cparal +
2 Cpara2 (5)
Rcell = n R (1)
which is added to the simulated capacitance of the basic cell,
The basic cell capacitance, Cce,11 is obtained by dividing the Csim, as they are considered shunt-connected. Thus, the
total capacitance, C, among the number of cells, as equation simulated capacitance to be compared with the measured in
(2) shows: the characteristic curve of a basic cell is:

Ccell-_Cn (2)
Besides, following equations (3) and (4) the tuning range,
TRcell and the quality factor Qcell, for a basic cell, do not
depend on the number of cells:
rDoping
Log xl ({em-3)
TRcell =TR Cmax Cmin .100(%) (3) -X
5
max + min
19
Qcell = Q = 2 RC (4) 1 8.-

where Cmax and Cmin are the respective maximum and 1 6.5l
1 6.4-5=l
minimum capacitance of the varactor, R and C, are the Fig. 3. 3D dimensional structure of half a MI basic cell. The meshing grid is
resistance and capacitance respectively, and f is the operating including; w 10,um, / =0.8 ,m.
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 Then, the parasitic inductance of a basic cell, Lcell, can be
approximated from the mesured C-f curves as:

(7)
(2jfr) n Clf

Table 2 includes f, and L,e11 from (7) for every varactor. With
equation (7) the frequency dependence can be now considered
ct
in the constant simulated capacitance of a basic cell, to be
ct
compared with Cce,. For that purpose, an effective
capacitance, Cejsim, is defined as:

Csim (8)
Cef sim - 1
-5 -4 -3 -2 -1 0 1 2 3 4 5 6 (2rf )2 Lg nf
Gate Voltage (V)

Fig. 4 Measured and simulated capacitance vesus gate voltage for a MI basic
Finally, as interconnections are excluded from simulations, the
cell, including the parasitic capacitances;f= 2.1 GHz. difference between the measured resistance of a basic cell,
Rcell and the corresponding simulated one is considerable.
Thus, for the simulated quality factor of a basic cell, in order
Csim = Csim + Cpara (6) to achieve proper relative errors, Rcell is used. The effective
simulated quality factor in a basic cell is then given by:
Particularly, the basic cell of MI Cparal and Cpara2 are 35.78
fF and 36.46 fF respectively. From (5) Cpara is 36.12 fF, which 1
(9)
is considered in figure 4 to representCs,i. Notice how the Qjsm2FTf -RcelliCef im
relative errors with Ccell are drastically reduced: 1.63 %0 for the
capacitance in inversion mode and 0.32 °0 in accumulation B. When varying the gate width
mode. The resulting relative error for the tuning range is only The influence of the gate width is studied increasing the gate
1.5 00. length of varactor MI, w = 10 gim, to 20 gm and 30 gm in
The parasitic inductance of interconnections is not either varactors M2 and M3 respectively. The gate length in all cases
considered in our simulations, but is critical at high is set to I = 0.8 gm.
frequencies. Figures 5 show the frequency dependence of capacitance (a)
From measured S-parameters all varactor reactance is and quality factor (b) of a basic cell in Ml, M2 and M3
considered capacitive in C. Thus, when the gate voltage is set, varactors. Note how simulations qualitatively predict the
C is nearly constant at low frequencies, C Cl>f and increases ;
measured results: the capacitance increases with the gate
drastically for frequencies close to the resonance frequency, fr.

-E-MI simulated -E-Ml simulated

2,0 * MI measured 120 * Ml measured
-o-M2 simulated -0-M2 simulated
* M2 measured * M2 measured
-A-M3 simulated -,-M3 simulated
A M3 measured 100 A M3 measured
1,5 k
80 kE
0
C.)
a)
c.) 1,0 _ d 60

ct ct
Qcz ak 1.
40 F_
V
A .
0,5 _ I
4 4 8Z- 20 _
4- -o-
-U
F
U U U
.
A o
0-
m I
UL 0 I -ii--.
-~~
v

1 2 3 4 1 2 3 4
Frequency (GHz) Frequency (GHz)
(a) (b)
Fig. 5. (a) Measured and simulated C-f curves for a basic cell in MI, M2 and M3 varactors; Vg = OV.
(b) Measured and simulated Q-fcurves for a basic cell in MI, M2 and M3 varactors; Vg = OV

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 -E-MI simulated -E-Ml simulated
* MI measured 120 * Ml measured
2,0 -o-M4 simulated -O-M4 simulated
* M4 measured m
* M4 measured
-A-M5 simulated _-A-Ms simulated
A M5 measured 100 A M5 measured
1 ,5
80 kE
0
C.)
ofD. 1,0 d 60 _
.
S
ct Ct
a 40
V
0,5 _ \ I
20 a
~~0----
A A I
E is
i i 2 2
A1
-

A11
0,0 0 I -e~ V \- lw ALA

1 2 3 4 1 2 3 4 5
Frequency (GHz) Frequency (GHz)

(a) (b)

Fig. 6. (a) Measured and simulated C-f curves for a basic cell in MI, M4 and M5 varactors; Vg = 0V.
(b) Measured and simulated Q-f curves for a basic cell in MI, M4 and M5 varactors; Vg = 0V
Simulated dependences of capacitances and quality factors
width, and the quality factor diminishes. But the relative error with gate voltage and operating frequency are qualitatively
is quite considerable. predicted. However, in order to reduce their relative errors,
not only a better simulation of the basic cell is necessary
C. When varying the gate length
(realistic diffusion profiles, precise physical parameters, etc.),
Figures 6 show the frequency response of capacitance (a) but also the parasitic elements due to interconnections should
and quality factor (b) of a basic cell in varactors MI, M4 and be simulated and better modelled.
M5. The influence of the gate length is analyzed increasing the
gate length of varactor MI, = 0.8 gim, to 1.6 gm and 2.4 tm ACKNOWLEDGEMENTS
in varactors M4 and M5 respectively. The gate width in all
This reported work is supported in part by the Spanish MEC
cases is set to w =10Inm.
under projects TEC-2005-08091 -C03-02 and TEC-2005-
Once again simulations qualitatively predict the measured 06784-C02-02.
results in figures 6: the capacitance increases with the gate
width, and the quality factor diminishes. REFERENCES
[1] P. Andreani et al. "On the use of MOS varactors in RF VCOs". IEEE J.
IV. CONCLUSIONS of Solid-State circuits, vol. 35, pp 905-910, June 2000.
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VCO's", IEEE Journal of Solid-State Circuits, vol. 35, pp. 905-910,
capacitance and area in our structures, but as compared with June 2000.
measurements this is not precise. It is true when the area [3] R. Aparicio and A. Hajimiri, "Capacity limits and matching properties of
increases due to increase in gate width, but not when the gate integrated capacitors", IEEE Journal of Solid-State Circuits, vol. 37, pp.
length increases (the measured capacitance becomes smaller). 384-393, March 2002.
[4] T. E. Kolding, "A four-step method for de-embedding gigahertz on
On the other hand, the tuning range and quality factor wafer CMOS measurement", IEEE Trans. on Electronic Devices, vol.
increases more with the gate length than with the gate width, 47, pp. 734-740, April 2000.
[5] I. Gutierrez, J. Garcia, N. Sainz, J.R. Sendra, J. de No and A. Hernandez,
whereas the resonance frequency remains nearly constant. "PN Juction Integrated Varactors for RF Applications at Different
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[6] Synopsys, Taurus Device Manual, 2006.

TABLE II
DERIVED PARAMETERS FROM MEASUREMENTS OF THE MOS VARACTORS
Varactor f (GHz) Lce,i (nH) TR (%)
Ml 6.20 7.07 37.23
M2 5.73 4.04 47.09
M3 5.58 2.84 47.75
M4 6.39 5.59 60.31
M5 4.82 5.07 70.12

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