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Sequencer 110

The document describes the design and implementation of a sequence detector to recognize the 3-bit sequence "110" using a Mealy machine approach. It includes: 1) A state diagram and state table for the Mealy machine detector. 2) K-maps and equations to implement the detector with D-type flip-flops. 3) A Verilog implementation of the detector using the D-type flip-flop equations. 4) A request to rework the problem as the equivalent Moore machine.

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2K views

Sequencer 110

The document describes the design and implementation of a sequence detector to recognize the 3-bit sequence "110" using a Mealy machine approach. It includes: 1) A state diagram and state table for the Mealy machine detector. 2) K-maps and equations to implement the detector with D-type flip-flops. 3) A Verilog implementation of the detector using the D-type flip-flop equations. 4) A request to rework the problem as the equivalent Moore machine.

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maha8 bala
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EE 254 March 12, 2012

Sequence Detector for 110

Design and implement a sequence detector which will recognize the three-bit sequence
110. Your detector should output a 1 each time the sequence 110 comes in. The input is
a clocked serial bit stream.

Mealy Machine
Figure 1 shows a state diagram for a Mealy machine version of the detector.

Figure 1
A Mealy machine version of the sequence detector for the sequence 110.

The corresponding state table is shown in Figure 2.


n n+1
Din A B A B Dout
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 x x x
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 0 0
1 1 1 x x x
Figure 2
State table for the sequence detector.

Figure 3 shows the K-maps corresponding to the state table with the equations for the D-
type flip-flops.

D A = Din ( A + B) DB = Din ⋅ A ⋅ B Dout = Din A


Figure 3
K-maps and equations for implemenation with D-type flip-flops
Figure 4
Implementation with D-type flip-flops.

//Sequence110.v
//Recognizes the sequence 110
module sequence110(clk, dIn, dOut);
input clk;
input dIn;
output dOut;
reg Qa, Qb;
wire dA, dB, dOut;
assign dA = dIn & (Qa | Qb);
assign dB = dIn & ~Qa & ~Qb;
assign dOut = ~dIn & Qa;
always@(posedge clk)
begin
Qa <= dA;
Qb <= dB;
end
endmodule
Figure 5
Verilog implemenatation. Note that DB is implemented as Din ⋅ A ⋅ B = Din ⋅ ( A + B ) .

Figure 6
Simulation results from Verilog code.

Rework this problem as the equivalent Moore machine.

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