Operating Systems

Memory Management

Matti Juutilainen
Mikpoli MB317
[email protected]

8.11.2010
 Computer Storage Hierarchy
 Computers use a variety of
memory types, organized in a
storage hierarchy around the
CPU, as a trade-off between
performance and cost
 The lower a storage is in the
hierarchy,
 the lesser its bandwidth
 the greater its access
latency is from the CPU
 the lower its cost

 Now we concentrate on
the main memory (RAM)
2

8.11.2010 Matti Juutilainen

 Primary Memory: RAM vs. Cache

 RAM and cache both store "active" data in (volatile) electronic circuitry
 Cache uses faster, more expensive SRAM technology
 Level-1 cache is stored directly on the CPU chip (runs at speeds
comparable to processor speed, ~10x RAM access speed common)
 Level-2 cache is stored on the CPU chip or nearby chip
 Common approach:
 When data from RAM is needed by CPU, first copy into cache
 CPU then accesses cache directly
 Cache retains recently used (most active?) data, fast access if needed
again

Note: cache is to RAM as RAM is to secondary memory (RAM to cache

usually handled by hardware; disk to RAM usually handled by OS)

8.11.2010 Matti Juutilainen

 Memory Management

 Memory management and CPU scheduling are perhaps the two

most central tasks of an OS
 Memory consists of a large array of words, each with its
own address
 Both program and data are stored in memory
 Recall: CPU fetch-execute cycle
1. fetch next instruction from memory (based on program counter)
2. decode the instruction
3. possibly fetch operands from memory
4. execute the instruction
5. store the result in memory

 Note: memory is given an address and it returns a value

 it does not distinguish between instructions and data
 it does not care how the address was arrived at
4

8.11.2010 Matti Juutilainen

 Address Binding
 Users do not (cannot?) think about real addresses
 User processes go through several steps before
execution (e.g., compilation, loading, linking, …)
 Addresses may be represented in different ways
during these steps (symbol, relocatable addr, …)
 Instructions/data may be bound to real addresses:
at compile time:
 compiler substitutes actual addresses in executable
 used in MS-DOS (why?)
at load time:
 compiler generates relocatable code, final binding
is delayed until load time
 once loaded in memory and process starts,
bindings are locked in
 not generally used (why?)
at execution time:
 if process can be moved during its execution, then
binding must be delayed until run time
 requires special hardware support
 used in most general-purpose OS's (why?) 5

8.11.2010 Matti Juutilainen

 Logical vs. Physical Addresses
 The concept of a logical address space that is mapped to a
physical address space is central to memory management
 CPU works in a logical (virtual) address space
 Users, processes, instruction operands, program counter refer
to logical addresses
 Memory chips are physical address space
 Real memory accesses require real addresses
 Memory Management Unit
(MMU) maps logical addresses
to physical addresses
 Implemented in hardware
 For example, might have a
relocation register that
provides the base address
for a process' block of
physical memory
6

8.11.2010 Matti Juutilainen

 Swapping

 A process needs to be in memory to be executed

 However, it may be temporarily swapped out of memory
into a backing store
 The process can later be restarted by swapping it back into
memory
 Backing store is generally a fast disk – speed is important!

8.11.2010 Matti Juutilainen

 Swapping Example

 When a process blocks or

timeouts,
 swap it out to disk
 swap in a new (ready)
process from disk to memory
 dispatch the new process

 Another example: roll out, roll in

 in a priority-based system,
lower-priority process may
be swapped out so higher-
priority process can be
loaded and executed

8.11.2010 Matti Juutilainen

 To Swap Or Not To Swap

 Few operating systems use standard swapping

 The context-switch time is generally too costly
 Special care must be taken
 For example, can't swap out a process waiting on I/O
 Some operating systems use variations on swapping
 Windows 3.1: if new process is loaded but insufficient
memory, swap out old
 However, user decides when to swap out & swap in processes
 Some versions of UNIX will use paging if system load is
very high
 Swapping may be used in combination with other approaches
(for example segmentation)

8.11.2010 Matti Juutilainen

 Contiguous Memory Allocation

 Main memory must accommodate both

the OS and user processes
 Usually divided into two partitions:
 OS & interrupt vector in low memory
 User processes in high memory
 Contiguous memory allocation places
each process in a single, contiguous
section of memory
 Any process can be loaded into the
memory if there is a free section
(partition) that is large enough
 There can be one or several partitions
 The partitions may be sized equally or
unequally
10

8.11.2010 Matti Juutilainen

 Contiguous Memory Allocation
 OPTION 1: single partition
(all processes share same memory space)
 Relocation-register scheme used to protect user processes
from each other, and from changing OS code and data
 Relocation register contains smallest physical address;
limit register contains range of logical addresses – each
logical address must be less than the limit register

11

8.11.2010 Matti Juutilainen

 Contiguous Memory Allocation
 OPTION 2: multiple partitions
(each process has its own partition)
 A hole is a block of available memory process memory
 When a process arrives, it is allocated P1 600K
P2 1000K
memory from a sufficiently large hole
P3 300K
 OS maintains info about allocated and P4 700K
free partitions (holes) P5 500K

0 0 0 0
OS OS OS OS
400K 400K 400K 400K
P1 P1 P1
1000K 1000K 1000K

P2
P4 …
1700K
2000K 2000K 2000K
P3 P3 P3
2300K 2300K 2300K

2560K 2560K 2560K 2560K 12

8.11.2010 Matti Juutilainen

 Dynamic Storage Allocation
Problem
 As processes free up holes in memory and new processes request memory,
how do you allocate partitions?
 first-fit: - allocate the first hole that is big enough
 best-fit: - allocate the smallest hole that is big enough
- must search the entire list of holes unless ordered by size
- produces the smallest leftover hole
 worst-fit: - allocate the largest hole available
- also must search the entire list of holes
- produces the largest leftover hole

0
OS
400K
P1
process memory
1000K
first-fit is fast
P1 600K
P2 1000K best-fit tends to
P3 300K 2000K work better w.r.t.
P4 200K
2300K
P3 storage utilization
P5 100K
2560K 13

8.11.2010 Matti Juutilainen

 External Fragmentation

 With dynamic storage allocation, external fragmentation can

be a problem
 There may be many small holes, none big enough to fit a
process
 50% rule: in practice, given N allocated blocks, expect N/2
blocks lost to fragmentation

8.11.2010 Matti Juutilainen / MAMK 14

14

8.11.2010 Matti Juutilainen

 External Fragmentation

 Compaction is needed to merge holes

(similar to defragging a hard drive)

0 0
OS OS
400K 400K
P1 P1
process memory
1000K 1000K
P1 600K compaction P3
P2 1000K 1300K

P3 300K 2000K
P4 1200K P3
2300K

2560K 2560K

15

8.11.2010 Matti Juutilainen

 Internal Fragmentation

 Internal fragmentation can occur as well

 Memory is allocated in blocks
 Allocated memory may be slightly larger than requested
memory
 Internal fragmentation is the space wasted inside of
allocated memory blocks because of restriction on the
allowed sizes of allocated blocks
 For example, suppose
memory is allocated in
blocks of 4 kB
 a 1 kB process will waste
3 kB of space in its partition,
as will a 5 kB process

16

8.11.2010 Matti Juutilainen

 Paging

 Paging is one solution to the external fragmentation problem

 Noncontiguous storage allocation: a process is allocated
physical memory wherever it is available
 Divide the physical memory into fixed-size blocks called frames
(size is a power of 2, generally between 512 and 8K bytes)
 Divide the logical memory into blocks of the same size called pages
 To run a process of size n pages, need to find n free frames and load

 Every logical address generated

by the CPU is divided into:
 page number (p):
used as an index into a page
table containing the base
address of each page in
physical memory
 page offset (d):
combined with base address to
determine the physical memory
address
17

8.11.2010 Matti Juutilainen

 Paging Examples

Abstract example: Tiny (but concrete) example:

 4 pages in logical address space  Page size = 4 bytes
 Page table maps to physical frames  Physical memory = 32 bytes

18

8.11.2010 Matti Juutilainen

 Paging Examples

Page table contents at (f):

8.11.2010 Matti Juutilainen / MAMK

 Hardware Defines
Page/Frame Size
 EXAMPLE: logical address is 32 bits (address space 232 = 4 GB)
 10 bits are used for page number  210 = 1024 pages
 22 bits are used for offset  222 = 4 MB of addresses per page

0010001001 0000110110011001110111
p d

 More, smaller pages are obtained by increasing p & decreasing d

 12 bits are used for page number  212 = 4096 pages
 20 bits are used for offset  220 = 1 MB of addresses per page

001000100111 00001101100110011101
p d
20

8.11.2010 Matti Juutilainen

 Advantages of Paging

 There is no external fragmentation

 Internal fragmentation is minimized
 All but the last frame allocated to a process will be full
(on average, will waste ½ a frame)
 The page table is used to dynamically convert logical
addresses (pages) into physical addresses (frames)
 Small frames reduce internal fragmentation, but increase
the size of the page table

21

8.11.2010 Matti Juutilainen

 Frame Table

 OS needs to keep track of allocated and free frames in memory

 System-wide frame table keeps this information
 When a new process arrives, it is allocated frames that are
free (if there are not enough then the process must wait)

Frame number Alloc/free Owner Page in process

0 alloc 6 23
1 free - -
2 free - -
3 alloc 3 6

22

8.11.2010 Matti Juutilainen

 Structure of A Page Table
 Each process has its own page table, stored in main memory
(PCB)
 Page Table Base Register (PTBR) points to the page table for
that process
 PTBR is changed by the OS whenever a process is dispatched,
or context-switch
 Note: every data/instruction
access requires 2 memory
accesses
 One access to get the
page table entry,
so can construct
physical address
 One more to get the
data/instruction stored
at that address
23

8.11.2010 Matti Juutilainen

 Translation Look-aside Buffer

 Can reduce to a single memory access using an associative array

 Translation Look-aside Buffer (TLB) provides constant-time
access to frame number given page number (using a parallel
search)
 TLB retains the most recent
references to the page table
 MMU first checks to see if the
page in the logical address is
in the TLB, if not then must
access page table
 Note similarity to caching
 Suppose
memory access = 100ns,
TLB access = 10 ns
 If 80% of references are
in TLB, then effective
memory reference time is
(210 * 0.20 + 110 * 0.80)
= 130 ns (would be 200 ns without TLB)
24

8.11.2010 Matti Juutilainen

 Memory Protection With Paging

 Can associate a protection bit with each frame

 Valid indicates that the page in that frame is in the process'
logical address space
 Legal to access
 Invalid indicates that the
page is not in the
process' logical address
space
 Not legal to access

25

8.11.2010 Matti Juutilainen

 Shared Pages

 Pages can be shared

among processes
 Read-only reentrant
code can be shared
without fear of
interference
 A frame in main
memory can be
referenced by several
different page tables
 OS must ensure that a
frame cannot be
removed from memory
if any active processes
are referencing it
26

8.11.2010 Matti Juutilainen

 Handling Large Address Spaces
 Suppose page size is 4 kB
 Address space uses 32 bits (references 232 = 4 GB of memory)
 Requires a page table with 1 M entries,
each entry is 4 kilobytes
 1024*1024*4096 B =
4 GB of main memory
 Large page tables are slow to handle
 Multi-level paging: break the table
into pieces, have another table tell
where the pieces are
page number(s) page offset

p1 p2 d

 p1 is an index into the outer page table

 p2 is the displacement within the
page of the outer page table 27

8.11.2010 Matti Juutilainen

 Multi-Level Paging Example
Physical
Virtual address memory
10 bit 10 bit 12 bit
Page
table Offset
Outer Outer page
entry Frame
page table number
Page table
table
entry
number

Page Frame number

table
number

Page table

28

8.11.2010 Matti Juutilainen

 Segmentation

 Segmentation is similar
to paging, except that
partitioning is based on
the user's view of
memory
 User sees a program
as a collection of
segments
 For example
 main program,
 function,
 object,
 global variables,
 stack,
 symbol table,
 …
29

8.11.2010 Matti Juutilainen

 Advantages of Segmentation

 View of memory is the user's view

 Segments are protected from one another
 Each segment contains one type of information
(for example instructions, stack, …)
 Sharing segments is logical and easy
 If all the instructions are in one segment and all data in
another, the instruction segment can be shared freely by
different processes (each with own data)
 As with paging, can implement protection using a valid/invalid
bit

 DISADVANTAGE: unlike paging, external fragmentation can

be a problem

30

8.11.2010 Matti Juutilainen

 Segmentation With Paging

 Modern computers use a combination of segmentation and

paging
 Solve the external fragmentation problem by paging the
segments
 Segment-table entry contains not the base address of the
segment, but rather the base address of a page table for
the segment

31

8.11.2010 Matti Juutilainen

 Segmentation With Paging
Example: Intel Pentium
 Utilizes both pure segmentation and segmentation with
paging
 The segmentation and paging units act in sequence to map a
logical address to physical memory

32

8.11.2010 Matti Juutilainen

 Segmentation With Paging
Example: Intel Pentium
 Segmentation
 Max segment size = 4 GB
 Max # of segments per process = 16 KB
 Logical address is 48 bits long
 16-bit selector identifies the segment
 32-bit offset specifies location in segment

33

8.11.2010 Matti Juutilainen

 Segmentation With Paging
Example: Intel Pentium
 Paging
 Page size = 4 kB or 4MB
 Utilizes 2-level paging
scheme
 First 10 bits index a
page directory
 Next 10 bits index
corresponding page
table
 Remaining 12 bits
specify offset in page

34

8.11.2010 Matti Juutilainen

 Memory Management in Linux

 Linux’s physical memory-management system deals with

allocating and freeing pages, groups of pages, and small
blocks of memory
 Additional mechanisms for handling virtual memory, memory
mapped into the address space of running processes
 Splits memory into 3 different zones due to hardware
characteristics, for example in 80x86:

35

8.11.2010 Matti Juutilainen

 Linux on Pentium Systems

 Linux is designed to work on a variety of processors

 Since some processors don't support segmentation, Linux doesn't
rely on it
 On the Pentium, Linux uses only 6 segments: kernel code, kernel
data, user code, user data, task-state, local-descriptor table

 Since some processors

support 64-bit addresses,
2-level paging is not
sufficient
 In general, Linux uses
3-level paging
 But uses 0 bits for
middle table if only
32-bits are supported
(as with Pentium)
36

8.11.2010 Matti Juutilainen