RESUME

OBJECTIVE:
Intend to build a career with a leading corporate of hi-tech environment with
committed & dedicated people, which will help me to explore myself fully and
realize my potential. Willing to work as a key player in a challenging & creative
environment
ABHINAV ARORA INNOVATIONS:
❖ Published Paper in IP.COM:
Permanent Address: • A Novel Startup circuit for voltage and current references in analog systems.
• IP.COM DISCLOSURE NUMBER: IPCOM000251681D, PUBLICATION DATE: 2017-Nov-23
H.NO.:1/1150, GOPAL NAGAR, ACHIEVEMENTS:
GANGOH ROAD, OLD SUGAR ❖ MANAGER CHOICE AWARD:
MILL NEAR CIRCUIT HOUSE,
• Two time got Manager Choice Award in 14nm & 7nm for test chip and Methodology
SAHARANPUR (U.P.)
development.
PINCODE:- 247001
PROFESSIONAL SUMMARY:
❖ Carrier Summary:
Present Address:
• Approximately, 1 Years of Industrial Experience in Physical Design (RLM) in IBM.
H.no.: 21, 2nd Cross, Mallappa • Approximately, 8 Years of Industrial Experience in full custom & semi-custom
Layout, Babusapalya near memory and analog layout/compilers and basic knowledge of analog and memories
BESCOM OFFICE, NAGA design
PALACE BANGALORE (K.A.) • Presently, I am working in IBM INDIA PVT. LTD. As a TEAM LEADER (Handling 12
PINCODE: - 560043 member team) since Feb 2015.Till Now.
• Worked as Engineer -I at SMARTPLAY TECHNOLOGY PVT. Ltd. BANGALORE (K.A.)
Contact Numbers: • Worked in MEMORIES as Engineer-I in QUALCOMM, BANGALORE through SMARTPLAY
Mob. No.: +91-8826459888 TECHNOLOGY, BANGALORE from Sept 2013- Jan 2015
:+91-8892213332 • Worked in STMicroelectronics. G. Noida & Synopsys, Noida through MASAMB
ELECTRONICS from Mar 2011-Sept 2013
E-Mail Address: • Worked in RF silicon, Noida from Nov 2011-Feb 2011
G-mail:
• Did 3 months summer internships each in Synopsys and Virage Logic as part of B.Tech.
[email protected]
Curriculum.
❖ Working Summary:
LINKED-IN:
• Worked on various technologies ranging from 0.18u to 28nm FD-SOI & 16nm &14 nm
http://in.linkedin.com/Pub/
FINFETS (SOI-FINFETS & BULK FINFETS) & 7nm BULK FINFETS TECNOLOGY.
Abhinavarora/9/99b/953
• Proficient in handling complete backend activities for memory compilers.
Personal Dossier:
TECHNICAL SKILLS:
Date of Birth :12 July
th ✓ Different types of MEMORY and ANALOG ARCHITECTURE (SRAM, RF, CHACHE, CAM).
1988 ✓ Custom & Compiler Based Memory Validations and checks.
Languages: English and ✓ Parasitic Extraction, Floor-planning, Power-planning, Clock Tree Synthesis, Static Timing
Hindi, Punjabi Analysis, Timing Optimization, Crosstalk Analysis and Fixing
Gender: Male ✓ Familiar with lower nodes challenges (7nm & 14nm: BULK & SOI).
Marital Status: ✓ IR Drop and Electro migration Analysis.
married
✓ Shielding of sensitive signals. Crosstalk Effect, Antenna Effect
Nationality: Indian
Interests: Watching TV, Net
TOOLS EXPERIENCE:
Surfing
➢ EDA Tools : Spice ,Tanner, Cadence design tools Synopsys
design tools Mentor’s Calibre for DRC/LVS and
PLSextract.
➢ Hardware Languages : Verilog.
➢ Algorithmic Analysis : MATLAB.
➢ Programming Language : C, C++, SKILL(cadence language)
➢ Operating Systems : Solaris, Linux & Windows
STRENGTHS:
o Demonstrated ability to work in a demanding team-oriented environment
o Good understanding of CMOS Device Cross section.
o Good understanding of the concepts used in analog layout and Memory Layout.
WORK EXPERIENCE:

IBM INDIA PVT. LTD, Bangalore since FEB 2015 – TILL NOW:

Handling and Leading Z series PROCESSOR: - Leading Z-register file MACRO/CUTS LAYOUTS in
INDIA. Near about 12 Macro/Cuts at a one time and handle 12 member team.

At IBM, (PHYSICAL DESIGN(PD) GROUP) I am involving on 14nm & 7nm Physical Design,
analysis and verifications work.
Primary Roles:
• Perform design partitioning, floor-planning, and power-planning for both flat and
hierarchical low Power designs.
• Perform clock tree building with both conventional and clock mesh technique.
• Perform DRV and timing analysis, timing optimization, ECO generation and
implementation.
• Perform cross-talk analysis and Fixing.
• Perform static voltage drop analysis.
• Perform physical signoff including DRC, LVS, ANTENNA, ERC, EM.

Challenges/Responsibilities:

• Highly congested design and Large no. of cross talks.

• Performed PnR of six such blocks.
• Performed Netlist Synthesis, floor planning, macro placement, place and route, timing
analysis and optimization, timing and functional ECO implementation, cross talk analysis and
bump fixing, DRC, LVS, EM checks

At IBM, (MEMORY GROUP) I am working in 14nm SOI-FINFETS, and 7nm BULK-FINFETS. I am

involving and responsibilities in RF, CACHE & CAM MACROS (memory-cuts). Reduce the area of
custom cuts. Solving Extraction Issues at 14nm & 7nm; EM & IR drop analysis, making single port
to dual port custom memory and done all the verifications. LIKE timing, slew, slack & hot-electron
analysis at lower nodes

At IBM, (ANALOG GROUP): Involving on 14nm IOT projects.

QUALCOMM Bangalore through SMARTPLAY TECHNOLOGY since SEPT 2013 – JAN 2015:
At Qualcomm, I am worked in 14nm FINFETS, 16nm FINFETS & 20nm BULK & 28nm BULK. I am
involving on Single & dual port (HPSP, LLPDP, LLSP, and STDSP) & ROM full custom or semi-custom
memories Development projects & making “level shifter block” , “LDP(local data path) Block ”, “LBC
(local control) Block“ CLK near , CLK far , and CLK edge blocks” LWBL (local word bit line booster)
block , GBC(Global control + Pre decoder block) & LEF GENERATION , Reduce the area of custom
cuts (Zero padding) , Extraction at 14nm & 16nm & 20nm ; EM & IR drop analysis , making single
port to dual port custom memory and done all the verifications ..

SYNOPSYS Noida through MASAMB Electronics, Noida since JUL 2013 – AUG 2013:
At Synopsys, I Worked in Memory group, I was involved in 14nm FINFETS & Making some part of
Control blocks (BSEN, BSEN_MUX, BSEN_BUF) .

STMicroelectronics Noida through MASAMB Electronics, Noida since MAR, 2011 – JUNE,
2013:
At STMicroelectronics, I worked in TRnD group (MEMORIES). I was involved in Single port &
Double port (LVT, RVT, HVT, MVT, HS, LP, HD) & ROM memory Development projects & making I/O,
Rowdec, scan-chain & scan buffer blocks. New Bit cell library plugging, Design change & Via-bar
implementation, Extraction & Verification at 28nm & 32nm & 28_FDSOI ; EM & IR drop analysis,
CDM update, Check LFD , SRD, DFM , Adding new features in many compilers, Product verification
and submission.
*LVT - low vt (high speed, less delay & more leakage)
*MVT - mixed vt (rvt + hvt/lvt) use for better performance.
*RVTor SVT - regular vt (standard vt) use for normal behavior
*HVT - high vt (low speed, more delay, & less leakage)
RF-Silicon Noida from Nov,2010 to Feb 2011
At RF-Silicon, I worked in memory development group. I was involved on design of memory cells,
SRAM-256x8, (Single port and Double port) layout, successfully running DRC, LVS, PEX, pre and
post-layout simulations of the instances designed. The main concern in design was technology
migration from 0.18u to 0.12u.

Summer Training in Synopsys (EDA) India Pvt. Ltd., Noida from July 2009-Oct, 2009
At Synopsys, I learned the full custom design flow using Synopsys tools. It involved schematic
entry, simulation, layout, RC extraction, post-layout simulations and DRC/LVS leading to GDSII.
Analog design labs from Synopsys University Program were done successfully. As a training project,
I did Differential Amplifier design from schematic entry to GDSII. In addition, the complete
documentation of the work during the training was done.

Summer Training in Virage Logic International, Noida from Aug 2008-Sep, 2008
At Virage, my internship involved understanding of Standard Cell Library Development Flow. I got
to work on standard cell circuit design and layout activities. I have successfully completed circuit
design and layout of basic blocks like Inverter, NAND, NOR, etc. I have also prepared a basic tutorial
on circuit design and full custom layout (DRC, LVS and parasitic extraction, transistor matching
considerations), for which my guide there has applauded me.

ACADEMIC HISTORY:

YEAR DEGREE INSTITUTE / UNIVERSITY

2015-17 M.TECH. Birla Institute of Technology and Science, Pilani
(MICROELECTONICS) (BITS)

2006-10 B.Tech. (Electronics and Institute of Engineering and Technology,

Communication Engg.) (Dr. RML Avadh University, Faizabad)

2004-05 12th Standard G.T.B. Public School, Saharanpur (C.B.S.E.)

2002-03 10th Standard G.T.B. Public School, Saharanpur (C.B.S.E.)

EXTRA-CURRICULAR ACTIVITIES:
➢ Event organizer & IBM CLUB MEMBER

DECLARATION:
If given a chance, I assure you that I shall work with all dedication, devotion and sincerity to your
full satisfaction. I am looking forward to building a career with you. I hereby declare that all
information furnished above is true & correct to the best of my knowledge and belief.
Thanks for your consideration; I look forward to hearing from you soon.

DATE: -
PLACE: - Bangalore (K.A.) INDIA
(ABHINAV ARORA)