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Experiment Topic: FM Demodulator

8-1: Curriculum Objectives

1. To understand the operation theory of phase-locked loop.

2. To understand the basic characteristics of MC4046 phase-locked loop.

3. To understand the basic characteristics of LM565 phase-locked loop.

4. To design and implement the FM demodulator by using MC4046.

5. To design and implement the FM demodulator by using LM565.

8-2: Curriculum Theory

Frequency demodulator is also called frequency discriminator, which can convert

the variation of frequency to the variation of linear voltage. Normally we use FM to AM
conversion circuit, balanced discriminator circuit, phase-shift discriminator circuit and
PLL synthesizer for the FM demodulator. In this chapter, we will introduce the phase-
locked loop frequency demodulator and FM to AM conversion discriminator.

8-1: The Operation Theory of Phase-Locked Loop

Phase-locked loop or PLL is a feedback circuit. In the feedback loop, the

feedback signal will lock the output signal frequency and the phase with the same
frequency and phase of the input signal. So, for wireless communication, if the frequency
of the carrier signal deviates during transmission, the PLL in the receiver will operate and
lock the carrier signal. In this experiment, there are two types of using PLL, and the first
type is demodulator, which is used for demodulation by following the variation of phase
and frequency. The second is the carrier frequency tracking which is used to track the
changes of the frequency of the carrier signal and synchronize the oscillation.
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Normally, phase-locked loop can divided into 3 sections, there are

1. Phase detector (PD)

2. Low-pass filter (LPF)
3. Voltage-controlled oscillator (VCO)
From figure 8-1, the function of phase detector is to receive input signal and
VCO signal then compare the two signals by phase detector and provides an output
signal, which is a pulse signal. After that, this signal sent to a low-pass filter to remove
the unwanted signal and left the DC voltage.

Figure 8-1 Block diagram of phase-locked loop.

This DC voltage can used to control the output signal frequency of VCO. Figure
8-1 is the block diagram of phase-locked loop, where

Kd = The gain of phase detector (Volts/Radian).

Ka = The gain of amplifier (Volt/Volt).

Ko = The gain of VCO (kHz/Volt).

KL = Kd Ka Ko =The gain of closed loop (kHz/Radian).

We use a simple circuit to explain the basic concept of phase detector. Figure 8-
2(a) shows that the phase difference between two input signals is the smallest, so
the output signal pulse width is the narrowest. Figure 8-2(b) shows the phase
difference between two input signals is larger than figure 8-2(a), so the output
signal pulse width is wider than figure 8-2(a). Figure 8-2(c) shows the phase
difference between two input signals is the largest and therefore the output signal
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pulse width is the widest. If these three output signals pass through the low-pass
filter to remove the AC signal, the magnitude of DC voltage in figure 8-2 is as
follow: 1. figure 8-2(c) has the highest DC voltage, 2.figure 8-2(b) is the second
higher, and 3. Figure 8-2(a) is the lowest. The relation of DC voltage and the
phase difference of A, B input signals show in figure 8-2(d).

Figure 8-2 Theory of phase detector.

From figure 8-3, assume that the free-running frequency of a VCO is set to 1 kHz
(assume the bias voltage is 2V). If inputting a signal A is below 1 kHz and a signal B is
higher than 1 kHz. From figure 8-3, we found that, when input signal A frequency is
lower than the free-running frequency of VCO, then the output of low-pass filter will
receive a lower voltage level (assume is 1V). This lower voltage level will adjust the
oscillation frequency of VCO, so that the oscillation frequency will decrease until the
frequency of output signal of VCO and the frequency of signal A equal to each other.
When input signal B frequency is higher than the basic frequency of VCO, the output
terminal of low-pass filter will receive a higher voltage (assume is 3 V), so that the
oscillation frequency of VCO will increase until the frequency of output signal of VCO
and the frequency of signal B equal to each other. Normally the time needed for VCO
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locked frequency is very short. The aforementioned discussion is only the description of
concept, however, practically; the circuit of phase detector is quite difficult and
complicated.

Figure 8-3 Theory of locked frequency.

8-2: The Basic Characteristics of PLL LM565

(1) Free-running frequency

Figure 8-4 is a LM565 phase-locked loop circuit diagram, from figure 8-4, when
input terminal does not input any signal, the output signal frequency of VCO is called
free-running frequency. Where C2 is timing capacitor, VR1 is timing variable resistor, the
free-running frequency (fo) of LM565 is decided by C2 and VR1.

1
Free-running frequency: fo = (8-1)
3.7VR1C2

33.6 f o
Close loop gain: KL = Kd Ka Ko = (8-2)
VC

Where Vc = Total voltage supply = Vcc- (-Vcc) = 5-(-5) = 10V

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Figure 8-4 LM565 phase-locked loop.

(2) Locked Range

When phase-locked loop circuit is at already-locked situation, assume the input
signal frequency (fi) slowly moves away from fo, when fi reaches at a certain frequency,
the PLL will leave the locked situation. At this moment, the maximum

frequency difference for frequency fi and fo is called locked-range (refer to figure 8-5).

The locked-range of LM565 is

8 fo
fL = (8-3)
VC

(3) Captured Range

At the beginning, PLL is at not-locked situation, and then let the input signal
frequency fi slowly move close to fo, when fi reaches at a certain frequency, PLL will be
at already-locked situation. Then at this moment, the frequency difference between fi and
fo is called captured range (refer to Figure 8-5). LM565 captured range is

 1  2  f L
fc =   (8-4)
 2  3.6  10  C2
3
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Figure 8-5 Lock range and capture range diagram.

8-3: Implementation of FM demodulator by Using LM565 PLL

Figure 8-4 is the circuit diagram of LM565 phase-locked loop, we can use this
circuit as a FM demodulator. When the input signal frequency increases, then the output
signal voltage decrease.

However, when the input signal frequency decreases, the output signal voltage
will increase, therefore, we can utilize the relationship between the voltage of PLL and
frequency to design the FM demodulator.

LM565 phase detector and VCO are designed in the IC package. This VCO and
LM566 are the same. The free-running frequency fo of VCO is decided by the external C2
and VR1. The low-pass filter is comprised of the internal resistor R3 at pin 7 and external
capacitor C3. The objective of capacitor C4, which is connected between pins 7 and 8, is
to reduce the parasitic oscillation.

Figure 8-6 Block diagram of FM to AM frequency discriminator.

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8-4: Basic Characteristics of PLL MC4046

(1) Free-running frequency

Figure 8-6 is a MC4046 phase-locked loop circuit diagram. From figure 8-6,
when input terminal does not input any signal, the output signal frequency of VCO is
called

free-running frequency. Where C2 is timing capacitor, VR1 is timing variable resistor, the
free-running frequency (fo) of MC4046 is decided by C2 and VR1.

1
Free-running frequency: fo = (8-5)
VR1C2

(2) Locked Range

When phase-locked loop circuit is at already-locked situation, assume the input
signal frequency (fi) slowly moves away from fo, when fi reaches at a certain frequency,
the PLL will leave the locked situation. At this moment, the maximum frequency
difference for frequency fi and fo is called locked-range (refer to figure 8-5). The locked-
range of MC4046 is

2fL = fmax - fmin (8-6)

(3) Captured Range

At the beginning, PLL is at not-locked situation, and then let the input signal
frequency fi slowly move close to fo, when fi reaches at a certain frequency, PLL will be
at already-locked situation. Then at this moment, the frequency difference between fi and
fo is called captured range (refer to Figure 8-5). The captured range of MC4046 is

 1  2  f L
2fc =   (8-7)
   R1 R2  C1 
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Figure 8-6 Circuit diagram of MC4046 PLL.

8-5 Implementation of FM demodulator by Using MC4046

PLL

Figure 8-6 is the circuit diagram of MC4046 phase-locked loop, which its
functions are similar to LM565, we can use this circuit as a FM demodulator. When the
input signal frequency increases, the output signal voltage decreases. However, when the
input signal frequency decreases, the output signal voltage will increase, therefore, we
can utilize the relationship between the voltage of PLL and frequency to design the FM
demodulator.

Since the demodulated audio signal consists of noise signal, therefore, we utilize
the low-pass filter in figure 8-7 to remove all the unwanted signal. Capacitors C1, C2,

resistors R1, R2, R3, R4 and uA741 comprise an active low-pass filter. This structure is a
voltage-controlled voltage-source (VCVS) low-pass filter.

The expression of the gain is

R4
AV = 1+ (8-8)
R1

Cutoff frequency is
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1
fo = (8-9)
2 R2 R3C1C2

If R2 = R3 = R and C1 = C2 = C, then

1
fo = (8-10)
2RC

Figure 8-7 Circuit diagram of second order active low-pass filter.

8-3 : Experimental Procedures

Experiment 1 : LM565 FM demodulator

1. Refer to the circuit diagram in figure 7-6 or figure ACS7-2 on ETEK ACS-
3000-04 module to produce the demodulated FM signal as the signal source.
Let J1 be short circuit, i.e. the circuit is the FM modulator. J3 be short
circuit and J2 be opened circuit, i.e. the selected capacitor is C 4 = 10 nF.
Adjust variable resistor VR1 so that the frequency at the modulated FM
output port (FM O/P) is 20 kHz square wave.
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2. Refer to the circuit diagram in figure 8-4 or figure ACS8-1 on ETEK ACS-
3000-04 module. Let J3 be short circuit, J1 and J2 be opened circuit, i.e.
C5 = 10 nF. Adjust the variable resistor VR1, so that the Free-running
frequency (fo) of the VCO O/P is 20 kHz.
3. Connect the output port (FM O/P) of the VCO LM566 to the input port (FM
I/P) of the PLL LM565.
4. At the audio input port (Audio I/P) of the VCO LM566, input 250 mV
amplitude and 1kHz sine wave frequency. By using oscilloscope, observe
on the output signal waveforms of the demodulated FM signal (Audio O/P)
at PLL LM565.Then record the measured results in table 8-4.
5. According to the input signals in table 8-5, repeat step 4 and record the
measured results in table 8-5

Experiment 2: MC4046 FM demodulator

1. Refer to the circuit diagram in figure 7-5 or figure ACS7-1 on ETEK ACS-
3000-04 module to produce the demodulated FM signal as the signal source.
Adjust variable resistor VR1 so that the frequency at the modulated FM
output port (FM O/P) is 20 kHz square wave.
2. Refer to the circuit diagram in figure 8-6 or figure ACS8-2 on ETEK ACS-
3000-04 module. Adjust the free-running frequency (fo) of the VCO output
port (TP1) be 20 kHz.
3. Connect the output port (FM O/P) of the VCO MC4046 to the input port
(FM I/P) of the PLL MC4046.
4. At the audio input port (Audio I/P) of the VCO MC4046, input 250 mV
amplitude and 1kHz sine wave frequency. By using oscilloscope, observe
on the output signal waveforms of the demodulated FM signal (Audio O/P)
at PLL MC4046. Then record the measured results in table 8-6.

5. According to the input signals in table 8-7, repeat step 4 and record the
measured results in table 8-7.
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8-4: Measured Results

Table 8-4 Measured results of the input and output signal waveforms of PLL frequency
demodulator. (Vm = 250 mV, fo = 20 kHz)

Audio signal
FM I/P Audio O/P
frequencies

1 kHz

2 kHz

Table 8-5 Measured results of the input and output signal waveforms of PLL frequency
demodulator.(Vm = 500 mV, fo = 20 kHz)

Audio signal
FM I/P Audio O/P
frequencies

1 kHz

2 kHz
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Table 8-6 Measured results of the input and output signal waveforms of FM to AM
conversion frequency demodulator. (Vm 250 mV, fo = 20 kHz)

Audio signal
1 kHz 2 kHz
frequencies

FM I/P

TP2

LPF IN

Audio O/P

Table 8-7 Measured results of the input and output signal waveforms of FM to AM
conversion frequency demodulator. (Vm = 500mV, fo = 20 kHz)

Audio signal
1 kHz 2 kHz
frequencies

FM I/P

TP2

LPF IN

Audio O/P
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8-5: Discussion Questions

1. From the measured results of the basic characteristics experiment of LM565

PLL, when the input signal frequency moves away from the frequency locked
range, what is the oscillation frequency of the VCO?
2. For LM565 PLL, compare the locked range and the captured range.
3. In figure 8-4, what are the functions for capacitor C3? If let C3 charge from
0.1 uF to 0.01 uF, what are the charges of the pin 7 of LM565?
4. In the LM565 frequency demodulator experiment, if the output signal passes
through the first order low-pass filter, then is the output signal flatter than the
previous one? Try to design the low-pass filter.
5. How to use the PLL circuit and the logic circuit to comprise a doubler
frequency circuit?