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A 0.9-V Input Discontinuous-Conduction-Mode Boost Converter With

CMOS-Control Rectifier

Article  in  IEEE Journal of Solid-State Circuits · October 2008

DOI: 10.1109/JSSC.2008.2001933 · Source: IEEE Xplore

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 2036 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

A 0.9-V Input Discontinuous-Conduction-Mode

Boost Converter With CMOS-Control Rectifier
Tsz Yin Man, Student Member, IEEE, Philip K. T. Mok, Senior Member, IEEE, and
Mansun J. Chan, Senior Member, IEEE

Abstract—A 0.9-V input discontinuous-conduction-mode swing and hence forces the use of sophisticated low-voltage
(DCM) boost converter delivering 2.5-V and 100-mA output is analog circuits [3], which normally consumes more power and
presented. A novel low-voltage pulse-width modulator is pro- chip area. Even though the modulator can be powered from the
posed. The modulator can be directly powered from the 0.9-V
input instead of using the 2.5-V output as in general modulator boost converter output [3], [4], the modulator, especially the
designs. Sophisticated low-voltage analog blocks, which normally analog blocks, become highly sensitive to the ripple and the
consume a large amount of power and chip area, are not required transient-induced perturbation at the converter output. Start-up
in the modulator. The impact of output-voltage ripple and tran- circuits and carefully designed start-up sequence are also re-
sient-induced output-voltage perturbation on the operation of quired as the modulator cannot be operated until the converter
analog blocks inside the modulator is eliminated. Boost converter
start-up sequence is also greatly simplified. A CMOS-control output is ready. Another design difficulty is the strong tradeoff
rectifier (CCR) is also proposed to improve converter power between the power efficiency and the size of off-chip compo-
efficiency. The CCR is used to replace the conventional rec- nents. Inductor is normally the one consuming the most board
tifying switch to provide adaptive dead-time, which helps to space. Its size can be reduced by the use of small-value inductor.
minimize charge-sharing loss and body-diode conduction loss. However, this makes the continuous-conduction-mode (CCM)
Corresponding thermal stress on the rectifying switch is hence
minimized. The CCR also enables the use of small off-chip in- converter operate at several MHz [5], [6] or even at tens to
ductor and capacitor at sub-MHz switching frequency to improve thousands MHz [7]–[9], which increases the switching loss and
light-load efficiency. This converter has been implemented in a hence inevitably degrades the converter light-load efficiency.
0.35- m CMOS process. It is designed to operate at 667 kHz In this work, as illustrated in Fig. 1, both a novel sub-1V
with a 1 H inductor and 4.7 F output capacitor to reduce pulse-width modulator and a CMOS-control rectifier (CCR)
both switching loss and form factor. Experimental results prove
that the converter can be directly powered from 0.9-V input with [10] are proposed to enable a 0.9-V input discontinuous-con-
85% efficiency at 100-mA output. duction-mode (DCM) boost converter with small off-chip
Index Terms—Sub-1V, boost converter, discontinuous-conduc-
components and high power efficiency. The proposed modu-
tion mode, adaptive dead-time. lator can be directly powered from the 0.9-V input without the
use of sophisticated low-voltage analog circuits. The problems
associated with modulator powered from the converter output
I. INTRODUCTION no longer exist. The proposed CCR helps to improve converter
efficiency in different ways. It replaces the conventional recti-
fying switch to provide an adaptive dead-time, which reduces
C OMPACT size and long battery life are both required in
today’s battery-powered mobile systems. One of the ef-
fective solutions to reduce their size is the use of single-cell
the charge-sharing loss and the body-diode conduction loss.
The reduced body-diode loss helps to minimize the power dis-
battery in which the commonly used nickel-based battery (e.g., sipation and the corresponding thermal stress on the rectifying
NiMH) has minimum output voltage equal to V. As most switch. Its diode-like characteristic facilitates the converter
analog circuits are still operated at a supply voltage much larger operate in DCM, which enables the use of small value inductor
than 1 V, for example audio amplifiers [1], [2], a boost converter at moderate switching frequency (e.g., hundreds of kHz) such
is required to step up this sub-1V battery voltage to higher level. that switching loss is reduced.
However, designing a sub-1V input boost converter with high This paper is organized as follows. Operation and de-
power efficiency and small off-chip components is not trivial. sign of the proposed modulator are thoroughly discussed in
One of the difficulties is the design of pulse-width modulator Section II. In Section III, relationship between dead-time and
in which the sub-1V input voltage limits the available voltage charge-sharing and body-diode conduction loss is first intro-
duced. Then, design of CCR to provide an adaptive dead-time
is presented in detail. Experimental results and discussions
Manuscript received October 11, 2007; revised May 30, 2008. Current version
published September 10, 2008. This work was supported in part by the Research are shown in Section IV. Finally, conclusions are given in
Grant Council of Hong Kong SAR Government under Project 617705. Section V.
T. Y. Man was with the Department of Electronic and Computer Engi-
neering, The Hong Kong University of Science and Technology, Clear Water II. PROPOSED LOW-VOLTAGE PULSE-WIDTH MODULATOR
Bay, Hong Kong, and is now with Marvell Hong Kong Ltd., Hong Kong
(e-mail: [email protected]). The ability of proposed modulator to directly operate at 0.9-V
P. K. T. Mok and M. J. Chan are with the Department of Electronic and Com- input comes from the method to generate the pulse-width-mod-
puter Engineering, The Hong Kong University of Science and Technology, Clear
Water Bay, Hong Kong (e-mail: [email protected]; [email protected]). ulation (PWM) signal. Before introducing the proposed modu-
Digital Object Identifier 10.1109/JSSC.2008.2001933 lator, limitation of conventional modulator to operate at sub-1V
0018-9200/$25.00 © 2008 IEEE

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 MAN et al.: A 0.9-V INPUT DISCONTINUOUS-CONDUCTION-MODE BOOST CONVERTER WITH CMOS-CONTROL RECTIFIER 2037

Fig. 1. Simplified schematic and timing diagram of a boost converter with both the proposed CMOS-control rectifier and the proposed sub-1V pulse-width mod-
ulator.

Fig. 2. Block-level schematic and timing diagram of conventional pulse-width modulator.

input is first described. Fig. 2 shows the block-level schematic threshold voltages of the nMOS and pMOS transistor, respec-
and the timing diagram of conventional modulator. The PWM tively. It is found that the is 50 mV at 0.9-V when
signal is generated by a comparator that compares the comparator is designed in a 0.35- m CMOS process where
the error amplifier output with a fixed amplitude ramp is 550 mV, is 700 mV, and , and
. Duty cycle of the is controlled by the , are designed to 50 mV. As a ramp signal with 50
voltage level of as illustrated in Fig. 2. In order for the mV amplitude is relatively difficult to produce and sensitive to
comparator to generate the with wide range of duty cycle noise, sophisticated comparator with wide or even rail-to-rail
(e.g., 1% to 99%), the comparator is required to have proper is required.
operation at different input voltage such as different values of In contrast to the conventional modulator, the in the
. In other words, the comparator used in the conventional proposed sub-1V modulator is generated by a comparator that
modulator must have its common-mode-input voltage compares a fixed DC voltage , which is generated by
equal to at least the amplitude of . However, the is on-chip circuit that is powered from 0.9-V , to a ramp with
greatly reduced when the supply voltage is scaled down. variable amplitude . As illustrated in Fig. 3, duty cycle
Assuming the comparator is implemented with a simple nMOS of the is now controlled by the amplitude of . The
input stage. The can be expressed by (1) comparator in the proposed modulator is therefore able to pro-
duce the with wide range of duty cycle at fixed input
voltage that is defined by the . Significance of the proposed
modulator is that once the is designed within the common-
(1) mode-input-voltage range of a comparator, very simple com-
parator design can be used at 0.9-V to produce the
where and are the overdrive voltage of the with wide range of duty cycle without encountering any prob-
nMOS input transistor and the nMOS tail-current transistor lems. Moreover, as compared to the conventional modulator, op-
of the nMOS input stage, correspondingly. is the over- eration of the proposed modulator is no longer affected by the
drive voltage of the pMOS transistor. and are the amplitude of the ramp signal such as the amplitude of .

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 2038 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

Fig. 3. Block-level schematic and timing diagram of the proposed sub-1V pulse-width modulator.

The is generated by a voltage-to-current (V-I) converter, current to the timing capacitor , which is imple-
a timing capacitor and a reset transistor . The mented by on-chip PIP (polysilicon–insulator–polysilicon) ca-
is used to fully discharge the at the beginning of pacitor. Transistors and operate as conventional
each switching cycle. The switching period is defined by common-source differential pair that is used to control the cur-
the periodic clock signal with very small pulse-width rent going into based on the input-voltage difference (
. The amplitude of is controlled by the such - ) where is generated by on-chip circuit that is
that duty cycle of can be adjusted by negative feedback powered from 0.9-V . A current mirror formed by transistors
to regulate the output voltage of the boost converter . and is used to mirror the current of to the
In the following subsections, design of different blocks inside output of V-I converter. The relationship between the V-I con-
the proposed modulator is discussed. Start-up of sub-1V input verter output current and the input voltage difference is the
boost converter with the proposed modulator is also presented. same as the conventional common-source pair [14]. Transistor
is used to make the drain-to-source voltage of both
A. Design of Error Amplifier and Comparator and into very close proximity so that the offset voltage
of V-I converter can be reduced. The voltage should be
Design of both the error amplifier and the comparator is based designed according to (1) to make sure all transistors are in sat-
on the NMOS-input current-mirror amplifier topology. The only uration region. Overdrive voltage of transistor and
difference between them is that inverter chain is used in the should be designed to a small value such that the differential pair
comparator as output buffer. To make sure both of them are can be properly operated at sub-1V supply. Simplicity of pro-
operated in the high-gain region, the and the reference posed V-I converter also eliminates the need of on-chip com-
voltage applied to their inverting-input terminals are de- pensation capacitor required in [3], tradeoff between stability
signed according to (1). The required under sub-1V input and response time is hence no longer existed in the proposed
can be generated by different bandgap circuits [11]–[13]. Once design.
the is defined, ratio between feedback resistors ( and The aspect ratio of reset transistor should be de-
) can be designed with (2): signed to a large value to make sure that the timing capacitor
can be fully discharged within the turn-on time of
(2) (e.g., ), which is very short in time compared to the
whole switching period . The value of timing capacitor
To minimize the finite-gain offset, gain of the error amplifier should be designed to a value much larger than the parasitic
and the comparator can be improved by using transistors with capacitance at the node, which is mainly contributed by
channel length larger than the minimum feature size of a given the drain capacitance of , the input capacitance of the
CMOS technology. comparator, and the output capacitance of the V-I converter.
The value of is 2.5 pF in this design. The ramp rate of
can hence be controlled by adjusting the mag-
B. Design of V-I Converter, Timing Capacitor and Reset
nitude of . On-time of nMOS power transistor (DT) can be
Transistor
well approximated by using the fact that is much shorter
Fig. 4 shows the transistor-level schematic and the timing in time than the switching period . With the help of Fig. 3,
diagram of the proposed V-I converter that is constructed by expression of DT can be easily derived and is shown in (3)
one current source and five MOS transistors ( to
). The current source defines the maximum charging (3)

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 MAN et al.: A 0.9-V INPUT DISCONTINUOUS-CONDUCTION-MODE BOOST CONVERTER WITH CMOS-CONTROL RECTIFIER 2039

Fig. 4. Transistor-level schematic and timing diagram of the proposed V-I converter.

Fig. 5. Transistor-level schematic and timing diagram of clock signal generator.

As the nMOS power transistor of the boost converter , as mentioned before, is the pulse-width of the clock signal
cannot be turned on for the whole switching period , there that is defined by both the response time of the com-
should be a maximum on time, or in other words, a maximum parator and the propagation delay of the buffer. As is usu-
duty cycle . It can be obtained by designing the tail ally much smaller than the switching period , the aspect ratio
current of the V-I converter. The required for of pull-down transistor should be large enough to make
a given can be calculated by sure the timing capacitor is fully discharged within the pe-
riod of . Moreover, the switching period can be approx-
(4) imated to the time and expressed as

Dependence of the duty cycle variation on the change (6)

of error amplifier output voltage can be expressed by
The threshold voltage should be designed according
(5) to (1) to make sure all transistors of the comparator operating in
saturation region.
where is the transconductance of transistor of
the V-I converter. It can be observed that the maximum value of D. Design of Supply-Voltage Multiplexer, Level Shifter and
is occurred at zero duty cycle. Tapered Buffer
To improve power efficiency and reduce chip area of the
C. Design of Clock Signal Generator converter, the tapered buffer used to drive the nMOS power
Fig. 5 shows the transistor-level schematic and the timing di- transistor is preferred to be powered from the 2.5-V boost
agram of the clock signal generator, which consists of a current converter output rather than its 0.9-V input such that the size
source , another timing capacitor , a pull-down tran- and the conduction loss of nMOS power transistor are reduced.
sistor , a current-mirror comparator with NMOS-input When 2.5 V instead of 0.9 V is used to drive the nMOS power
stage and a buffer. The switching period of comprises transistor, under the same conduction loss, transistor size can be
two periods of time ( and ). The first period of time reduced by almost 6X in this design. This transistor size reduc-
is the time required to charge the timing capacitor from tion not only significantly reduces the size of entire converter
zero volt to the threshold . The second period of time but also helps to reduce the power loss and the gate-drive delay

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 2040 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

Fig. 6. Transistor-level schematic of the proposed supply-voltage multiplexer, and the conventional level shifter and tapered buffer.

caused by parasitic elements associated with the metal used

by such large-size power transistor. Even this scheme gives
1.3X increase in switching loss, almost 6X power transistor
size reduction is the key to reduce chip area such that the size
of entire boost converter can be small enough to fit into the
recent size-constrained mobile systems. This can be achieved
by using a conventional level shifter to shift the logic-one level
of PWM signal from 0.9 V to 2.5 V. As the converter
output is not ready during start-up, a supply-voltage multiplexer
(SVMUX) is introduced here to make sure the level shifter
and the tapered buffer can be supplied from the 0.9-V input at
start-up. Fig. 6 shows the transistor-level schematic of the pro-
posed SVMUX, and the conventional level shifter and tapered
buffer. The SVMUX consists of two comparators, where each
of them is constructed by two constant current sources and two
matched pMOS transistors, and , and and ,
acted as current mirrors. Outputs of these two comparators
are buffered to drive the transistors and , which are Fig. 7. Simulated start-up response of a sub-1V boost converter with the pro-
used to connect either the input or the output of converter to posed modulator.
the supply-rail of both the level shifter and the tapered buffer.
When the converter output is not ready (e.g., -V
input), transistor is on and transistor is off so that E. Start-Up of Sub-1V Modulator
both the level shifter and the tapered buffer are powered from The proposed modulator eliminates the need of special
the 0.9-V input. Once the converter output is close to 0.9 V start-up circuits and sequence that are required in existing
during start-up, both transistors and are on. Both sub-1V boost converter designs [3], [4]. This is because all
the converter input and output are hence connected through the building blocks inside the proposed modulator can directly
small transistor-turn-on resistance to the supply-rail of the level operate at sub-1V input. As a result, start-up circuit such
shifter and tapered buffer. When the converter is ready (e.g., as low-voltage oscillator used to firstly boost the converter
V), transistor is off and is on. The level output voltage in open-loop manner is not required. Moreover,
shifter and tapered buffer are then powered from the 2.5-V decision circuit, which is used to switch the modulator from
output. To prevent the input and the output of the converter open-loop to closed-loop operation when the converter output
connecting through the body diodes of transistors and is larger than certain predefined value, is no longer required.
, both the converter input terminal and the output Soft-start to reduce converter output voltage overshoot during
terminal are connected to the drain terminals but not start-up is also implemented in the proposed modulator. It is
the source terminals of transistors and as shown in achieved by the error amplifier and the compensation capacitor.
Fig. 6. Moreover, size of transistors and are designed As the error amplifier output is loaded by a relatively large value
to make their turn-on resistance small enough such that enough compensation capacitor, the error amplifier output cannot sud-
current can be sourced by the tapered buffer to drive the nMOS denly jump to a near-supply-rail voltage even a large voltage dif-
power transistor. ference is existed between its inputs at the beginning of start-up.

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 MAN et al.: A 0.9-V INPUT DISCONTINUOUS-CONDUCTION-MODE BOOST CONVERTER WITH CMOS-CONTROL RECTIFIER 2041

Fig. 8. Illustration of body-diode conduction loss of a boost converter.

As a result, duty cycle of the PWM signal is initially close of the pMOS rectifying switch is turned on and carries
to zero from which the converter output capacitor is charged inductor current in the remaining period of dead-time .
through the proposed CCR (discussed in Section III) or body- As the voltage drop of the body-diode is normally much larger
diode of pMOS transistor if conventional rectifying switch is than the drain-to-source voltage of a fully turn-on rectifying
used. As the compensation capacitor is continuously charged by switch , large amount of power is wasted in the form of
the error amplifier, duty cycle is slowly increased from zero to body-diode conduction loss. As this amount of power is dissi-
steady-state value. It also means that the inductor current and the pated on the rectifying switch, its thermal stress is inevitably in-
converter output voltage can gradually increase to the steady- creased. In case the load current and hence the is small,
state values. Fig. 7 shows the simulation result of a sub-1V fixed dead-time becomes too short compared to the optimum
boost converter start-up with the proposed modulator. Same as dead-time . As illustrated in Fig. 9, charge stored at the
aforementioned, output of error amplifier is gradually in- output capacitor of the converter is shared by the para-
creased from zero volt to the steady-state value. Duty cycle of sitic capacitor when the rectifying switching is on
the signal applied to the gate of nMOS power transistor at the end of dead-time . In other words, energy stored at the
of the boost converter is steadily increased so that the converter for the load is wasted in the form of charge-sharing loss.
output is gradually increased without any undershoot or
overshoot. With the proposed SVMUX, the peak voltage of
follows the converter output once it is larger than its input B. Design of Proposed CMOS-Control Rectifier
. As shown by the block diagram in Fig. 10, the proposed CCR
consists of a pMOS power transistor , buffers, and two
III. PROPOSED CMOS-CONTROL RECTIFIER specially designed comparators ( and ) in cross-coupled
connection with a coupling capacitor ). The body ter-
To understand and appreciate how the adaptive dead-time in-
minal of is connected to the converter output to eliminate
troduced by the proposed CCR improving the converter power
unwanted current flowing from the node through the body
efficiency, the relationships between dead-time, charge-sharing
diode to the node. The CCR conducts when the node
loss and body-diode conduction loss are first briefly introduced.
voltage is larger than the converter output . Otherwise, it is
Design of the proposed CCR is then thoroughly discussed.
off. This diode-like characteristic enables the CCR to adaptively
A. Relationships between Dead-Time, Charge-Sharing Loss adjust the dead-time close to the optimum value without the use
and Body-Diode Conduction Loss of sophisticated circuits to acquire the inductor-current level and
the parasitic capacitance at the node. It also enables
To prevent shoot-through current from appearing in any syn- DCM operation by eliminating the inductor current flowing in
chronous switching converters, dead-time is commonly used. negative direction. Therefore, negative-inductor current sensor
However, a fixed dead-time introduces extra power losses such and dead-time circuit are no longer required in the boost con-
as the charge-sharing loss and the body-diode conduction loss. verter with the proposed CCR. The corresponding controller de-
This is because the fixed dead-time is either too long or too sign is also greatly simplified as only one gate signal is required
short compared to the optimum dead-time as shown to drive the nMOS power transistor.
in (7) However, design of the comparator used in the proposed
CCR is very challenging. It is obvious that classical design
(7) with common-source-differential input and current-tail bias can
not be used. The common-source-differential input imposes a
where is the parasitic capacitor at the switching node common-mode-voltage limit that disables the classical com-
of the boost converter, and is the peak inductor parator used in the proposed CCR. The current-tail structure
current. When the load current and hence the is large, introduces a very strong tradeoff between response time and
fixed dead-time normally becomes too long compared to the quiescent-current consumption. It is important to note that the
optimum value . As illustrated in Fig. 8, the body-diode longer the response time means the longer the actual dead-time

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 2042 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

Fig. 9. Illustration of charge sharing loss of a boost converter.

Fig. 10. Block-level schematic of the proposed CMOS-control rectifier.

compared to the optimum one, from which more power is lost

as body-diode of is forced to conduct.
To overcome the aforementioned challenge, specially Fig. 11. Transistor-level schematic of the proposed CMOS-control rectifier.
designed comparator is proposed. Fig. 11 shows the tran-
sistor-level schematic of the proposed CCR in which the
comparators and are constructed by constant current negative direction. This is done by connecting two proposed
source and transistors to , and transistors comparators in cross-coupled connection with the help of a
to and constant current source , respectively. 0.1 pF on-chip PIP coupling capacitor . Regardless of
The use of source terminal of transistors , whether the node voltage is smaller or larger than the con-
and as inputs of comparators solve the problem of verter output , either the drain current of transistor
common-mode-voltage limit existed in conventional design. or transistor , which is much larger than the constant
Tradeoff between response time and quiescent-current con- current source and , can be provided to speed up the
sumption existed in conventional design is also released due comparator response. High slew-rate in positive direction is
to the fact that slew-rate of the proposed comparator is no achieved by the large drain current of . The large drain
longer constrained by the constant current bias. This is easily current of also quickly turns on transistor , which
understood by considering a case that the node voltage provides large discharging current to enable high slew-rate in
is higher than the converter output voltage , in which negative direction. With the help of coupling capacitor ,
overdrive voltage of transistor is larger than that of response time of the proposed CCR is further improved as this
. As a result, current of delivered to the comparator capacitor virtually latches these two cross-coupled comparators
output becomes much larger than the one defined by , and during transient response. Moreover, this capacitor also pro-
more importantly, it is no longer limited by the constant current vides DC-isolation between the output of comparator and
source of the comparator. one of the inputs of comparator . Together with transistors
To enable the proposed CCR with fast on and off time, the and , which provide DC bias to that input of com-
comparator should have high slew-rate in both positive and parator , stable steady-state operation can be guaranteed.

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 MAN et al.: A 0.9-V INPUT DISCONTINUOUS-CONDUCTION-MODE BOOST CONVERTER WITH CMOS-CONTROL RECTIFIER 2043

Fig. 13. Chip micrograph of the proposed boost converter.

Fig. 12. Measured on and off characteristics of the proposed CMOS-control

rectifier.

Fig. 14. Measured steady-state operation of the proposed boost converter at

IV. EXPERIMENTAL RESULTS AND DISCUSSIONS 100-mA output current and 1.2-V input voltage.
To facilitate characterization of the proposed CCR, a stand-
alone CCR has been fabricated in Austria Micro Systems
(AMS) 0.35- m 2-poly 4-metal CMOS technology. Fig. 12 CCR is small in magnitude and has a slow rate of change.
shows the measured on and off characteristics of the CCR and At the instant where the current carried by the CCR is just
the corresponding measurement setup. Two voltage sources, changed from positive to negative direction, only very small
and , are set to 0.9 V and 2.5 V, respectively. Inductor voltage different is appeared at the inputs of comparator inside
with H is used. The measurement is done by applying the CCR, and this voltage takes a relatively longer time to be
a periodic voltage pulse to the gate of the nMOS increased. Therefore, the CCR takes a longer time to be turned
power transistor. The period of is adjusted to ensure off compared to the turn-on case. It is important to note that the
that the inductor current is around zero ampere at the beginning measured on and off time shown above is not just the response
of each cycle. Peak inductor current can hence be adjusted by time of the comparator but including the propagation delay of
controlling the pulse-width of . Once the nMOS power the buffer inside the CCR.
transistor is off, potential of node is increased until the CCR The boost converter with both the proposed sub-1V pulse-
is conducted. The CCR is off when the inductor current flow is width modulator and the proposed CCR has also been imple-
changed from positive to negative direction. The measured on mented in AMS 0.35- m 2-poly 4-metal CMOS technology.
and off time of the CCR are 20 ns and 60 ns, respectively. The chip area is about 3 mm , and the chip micrograph is shown
This response time difference is caused by the different rate of in Fig. 13. The converter is able to provide a regulated 2.5-V
change of -node voltage. It is observed in Fig. 12 that the output voltage and maximum load current of 100 mA at an
-node voltage is quickly increased from zero volt to a level input voltage ranged from 0.9 V to 1.2 V. A 1 H off-chip in-
higher than the converter output when the nMOS power ductor and a 4.7 F output filtering capacitor are used to facili-
transistor is off. A large voltage difference is hence instantly tate the proposed converter used in today’s pocket-size or even
appeared at the inputs of the comparator of the CCR, from thumb-size mobile systems. To minimize the switching loss and
which the CCR is driven to turn on quickly. When the CCR hence improve the light-load efficiency, switching frequency
is conducted, the voltage dropped across the CCR depends on of the proposed converter is designed at the sub-MHz range,
the inductor current and the on-resistance of the pMOS power which is around 667 kHz in the proposed design. Figs. 14 and
transistor inside the CCR. As on-resistance of power transistor 15 show the measured steady-state operation of the proposed
is normally minimized to reduce conduction loss, the voltage converter at 100-mA output, and 1.2-V and 0.9-V input, respec-
dropped across the CCR is relatively small. Moreover, as tively. When the input is 1.2 V, the converter is operated in DCM
shown in Fig. 12, current flowing through the CCR is decreased where ringing is appeared at the node when both the nMOS
relatively slow. As a result, the voltage dropped across the power transistor and the CCR are off. This unique characteristic

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 2044 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

Fig. 15. Measured steady-state operation of the proposed boost converter at

100-mA output current and 0.9-V input voltage. Fig. 18. Measured power efficiency of the proposed boost converter.

Fig. 16. Measured transient response of the output voltage and the inductor
current of the proposed converter with 100-mA load current at 1.2-V input.

Fig. 19. Estimated power loss distribution as percentage of load power dissi-
pation.

load step (e.g., from 0 mA to 100 mA and vice versa) at 1.2-V

and 0.9-V input, respectively. It is shown that the proposed con-
verter has stable operation under wide range of output current
and input voltage. Efficiency of the proposed converter is mea-
sured and shown in Fig. 18. An estimation of power loss distri-
bution as percentage of load power dissipation is also done ac-
cording to the measured efficiency and is shown in Fig. 19. Max-
imum efficiency of 87% is achieved at 1.2-V input voltage
Fig. 17. Measured transient response of the output voltage and the inductor and 100-mA output current. Even the input voltage is reduced
current of the proposed converter with 100-mA load current at 0.9-V input. to 0.9 V, 85% efficiency is still obtained at 100-mA output
current. Finally, performance of the proposed boost converter is
of DCM can be easily suppressed with a freewheel switch [15]. summarized in Table I.
As shown in Fig. 15, the proposed converter is able to be directly
powered from 0.9-V input, in which the converter is operated V. CONCLUSION
very close to the DCM/CCM boundary due to the fact that longer In this work, a 0.9-V input DCM boost converter delivering
time is required to store energy in the inductor. Figs. 16 and 2.5-V and 100-mA output is successfully achieved with both
17 show the measured transient responses of the output voltage the proposed low-voltage pulse-width modulator and the pro-
and the inductor current of the proposed converter with 100-mA posed CCR. The modulator enables the converter to be directly

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 MAN et al.: A 0.9-V INPUT DISCONTINUOUS-CONDUCTION-MODE BOOST CONVERTER WITH CMOS-CONTROL RECTIFIER 2045

TABLE I [7] S. K. Reynolds, “A dc-dc converter for short-channel CMOS technolo-

SUMMARIZED PERFORMANCE OF THE PROPOSED BOOST CONVERTER gies,” IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 111–113, Jan.
1997.
[8] P. Hazucha, G. Schorm, J. Hahn, B. A. Bloechel, P. Hack, G. E.
Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borkar,
“A 233-MHz 80%–87% efficient four-phase dc-dc converter utilizing
air-core inductors on package,” IEEE J. Solid-State Circuits, vol. 40,
no. 4, pp. 838–845, Apr. 2005.
[9] M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, and P. Palmer,
“A 3 GHz switching dc-dc converter using clock-tree charge-recycling
in 90nm CMOS with integrated output filter,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb.
11–15, 2007, pp. 532–33.
[10] T. Y. Man, P. K. T. Mok, and M. Chan, “A CMOS-control rectifier for
discontinuous conduction mode switching dc-dc converters,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Fran-
cisco, CA, Feb. 5–9, 2006, pp. 1408–1417.
[11] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi,
and K. Sakui, “A CMOS bandgap reference circuit with sub-1-V oper-
ation,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670–674, May
1999.
[12] K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/ C CMOS
bandgap voltage reference without requiring low threshold voltage
device,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 526–530, Apr.
2002.
[13] H. Lin and C. J. Liang, “A sub-1V bandgap reference circuit using
powered from a 0.9-V input and therefore fully utilize the ca- subthreshold current,” in Proc. IEEE Int. Symp. Circuits and Systems
(ISCAS’05), Kobe, Japan, May 23–26, 2005, pp. 4253–4256.
pacity of a single-cell NiMH battery and thus operation time of [14] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
single-cell battery operated system is greatly extended. Oper- Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001.
ation of the modulator is no longer affected by the ripple and [15] D. Ma, W.-H. Ki, and C.-Y. Tsui, “A pseudo-CCM/DCM SIMO
switching converter with freewheel switching,” IEEE J. Solid-State
transient-induced perturbation of the converter output. Start-up Circuits, vol. 38, no. 6, pp. 1007–1014, Jun. 2003.
design is greatly simplified compared to the designs where the
modulator is powered from the boost converter output. The CCR
enables adaptive dead-time to minimize the body-diode conduc-
tion loss and the charge-sharing loss such that the boost con-
verter in this design is able to achieve 85% peak efficiency at
0.9-V input and almost 3x step-up ratio. Moreover, the CCR Tsz Yin Man (S’01) received the B.Eng. (highest
honors), M.Phil., and Ph.D. degrees in electrical
enables the use of microfarad range off-chip capacitor and mi- and electronic engineering from the Hong Kong
crohenry range off-chip inductor at submegahertz switching fre- University of Science and Technology, Hong Kong,
quency. The size of the entire boost converter can thus be greatly in 2001, 2003, and 2008, respectively.
He is now with Marvell Hong Kong Ltd., Hong
reduced. Light-load efficiency is also improved. More impor- Kong.
tantly, the proposed CCR is applicable in other switching con- Dr. Man received the first prize in the 2001 IEEE
verters such as buck and non-inverting buck-boost converter to Hong Kong student paper contest.
provide adaptive dead-time and minimize thermal stress of rec-
tifying switch.

REFERENCES Philip K. T. Mok (S’86–M’95–SM’02) received the

B.A.Sc., M.A.Sc., and Ph.D. degrees in electrical
[1] J. Varona, A. A. Hamoui, and K. Martin, “A low-voltage fully-mono- and computer engineering from the University of
lithic 16 -based class-D audio amplifier,” in Proc. 29th European Toronto, Toronto, ON, Canada, in 1986, 1989, and
Solid-State Circuits Conf. (ESSCIRC’03), Estoril, Portugal, Sep. 1995, respectively.
16–18, 2003, pp. 545–548. In January 1995, he joined the Department of
[2] S. C. Li, V. C. C. Lin, K. Nandhasri, and J. Hgarmnil, “New high- Electronic and Computer Engineering, The Hong
efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for portable Kong University of Science and Technology, Hong
consumer electronics,” IEEE Trans. Circuits Syst. I, vol. 52, no. 9, pp. Kong, China, where he is currently an Associate Pro-
1767–1774, Sep. 2005. fessor. His research interests include semiconductor
[3] C. Y. Leung, P. K. T. Mok, and K. N. Leung, “A 1-V integrated current- devices, processing technologies and circuit designs
mode boost converter in standard 3.3/5-V CMOS technologies,” IEEE for power electronics and telecommunications applications, with current
J. Solid-State Circuits, vol. 40, no. 11, pp. 2265–2274, Nov. 2005. emphasis on power management integrated circuits, low-voltage analogue
[4] H. Deng, X. Duan, N. Sun, Y. Ma, A. Q. Huang, and D. Chen, “Mono- integrated circuits and RF integrated circuits design.
lithically integrated boost converter based on 0.5-m CMOS process,” Dr. Mok received the Henry G. Acres Medal, the W. S. Wilson Medal and a
IEEE Trans. Power Electron., vol. 20, no. 3, pp. 628–638, May 2005. Teaching Assistant Award from the University of Toronto, and the Teaching Ex-
[5] D. Ma, W.-H. Ki, and C.-Y. Tsui, “An integrated one-cycle control cellence Appreciation Award twice from The Hong Kong University of Science
buck converter with adaptive output and dual-loop output error correc- and Technology. He is also a co-recipient of the Best Student Paper Award in the
tion,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 140–149, Jan. 2002 IEEE Custom Integrated Circuits Conference. In addition, he has been a
2004. member of the International Technical Program Committees of the IEEE Inter-
[6] E. Bonizzoni, F. Borghetti, P. Malcovati, F. Maloberti, and B. Niessen, national Solid-State Circuits Conference (ISSCC) since 2005 and he has served
“A 200 mA 93% peak efficiency single-inductor dual-output dc-dc as an associate editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS
buck converter,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. PART II from 2005–2007, IEEE JOURNAL OF SOLID-STATE CIRCUITS since 2006,
Tech. Papers, San Francisco, CA, Feb. 11–15, 2007, pp. 526–527. and IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I since 2007.

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 2046 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

Mansun J. Chan (S’92–M’95–SM’01) received SPICE, which has been accepted by most U.S. companies and the Compact
the B.S. degree in electrical engineering (highest Model Council (CMC) as the first industrial standard MOSFET model. In Jan-
honors) and the B.S. degree in computer sciences uary 1996, he joined the EEE faculty at Hong Kong University of Science and
(highest honors) in 1990 and 1991, respectively, Technology. His research interests include nanodevice technologies, image sen-
both from the University of California at San Diego. sors, SOI technologies, high-performance ICs, 3-D Circuit Technology, device
He received the M.S. degree in 1994 and the Ph.D. modeling and Nano BioNEMS technology. Between July 2001 and December
degree in 1995 from the University of California 2002, he was a Visiting Professor at University of California at Berkeley and
at Berkeley. During his undergraduate study, he the Co-director of the BSIM program. He is currently still consulting on the de-
worked with Rockwell International Laboratory on velopment of the next-generation compact models.
heterojunction bipolar transistor (HBT) modeling, Dr. Chan is a recipient of the UC Regents Fellowship, Golden Keys Schol-
where he developed the self-heating SPICE model arship for Academic Excellence, SRC Inventor Recognition Award, Rockwell
for HBT. His research at Berkeley covered a broad area in silicon devices Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Ex-
ranging from process development to device design, characterization, and cellence Appreciation award (1999), Distinguished Teaching Award (2004) and
modeling. A major part of his work was on the development of record-breaking other awards. He is a Distinguished Lecturer of IEEE.
silicon-on-insulator (SOI) technologies.
He has also maintained a strong interest in device modeling and circuit sim-
ulation. He is one of the major contributors to the unified BSIM model for

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