STA516B

65 V, 7.5 A quad power half bridge

Datasheet - production data

Description
STA516B is a monolithic quad half-bridge stage in
multipower BCD technology. The device can be
used as dual bridge or reconfigured, by
connecting pin CONFIG to pins VDD, as a single
bridge with double-current capability or as a half
bridge (binary mode) with half current capability.
The device is designed, particularly, to be the
output stage of a stereo all digital high efficiency
PowerSO36 package amplifier. It is capable of delivering 200 W +
with exposed pad up 200 W into 6  loads with THD = 10% at
VCC = 51 V or, in single BTL configuration, 400 W
into a 3 load with THD = 10% at VCC = 52 V.

Features The input pins have a threshold proportional to

the voltage on pin VL.
 Low input/output pulse width distortion
The STA516B is aimed at audio amplifiers in hi-fi
 200 m RdsON complementary DMOS output applications, such as home theatre systems,
stage active speakers and docking stations.
 CMOS compatible logic inputs It comes in a 36 pin PowerSO package with
 Thermal protection exposed pad up (EPU).
 Thermal warning output
 Undervoltage protection

Table 1. Device summary

Order code Temperature range Package Packaging

STA516B13TR 0 to 90 °C PowerSO36 EPU Tape and reel

February 2014 DocID13183 Rev 6 1/18

This is information on a product in full production. www.st.com
Introduction STA516B

1 Introduction

Figure 1. Application circuit (dual BTL)

VCC1A +VCC

15
IN1A 29 M3 C30 C55
IN1A 1 F 1000 F
17 L18 22 H
VL 23
+3.3V OUT1A
CONFIG 24 16 C20
100nF
OUT1A
PWRDN PWRDN 25 M2 C52
14 GND1A 330pF R98 C99
PROTECTIONS 6 100nF
R57 R59 FAULT 27 & C23 8
10K 10K LOGIC
26 12 VCC1B 470nF
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1 F
C21
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22 H
IN1B
M4
VDD 21 13 GND1B
VDD 22
VSS 33 REGULATORS
7 VCC2A
VSS 34
M17 C32
C58 C53 1 F
100nF 100nF VCCSIGN 8 L113 22 H
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1 F
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22 H
GNDSUB M14
1 5 GND2B

D00AU1148B

2/18 DocID13183 Rev 6

STA516B Pin description

2 Pin description

Figure 2. Pin out

VCC_SIGN 36 1 SUB_GND
VCC_SIGN 35 2 OUT2B
VSS 34 3 OUT2B
VSS 33 4 VCC2B
IN2B 32 5 GND2B
IN2A 31 6 GND2A
IN1B 30 7 VCC2A
IN1A 29 8 OUT2A
STA516B OUT2A
TH_WARN 28 9
FAULT 27 10 OUT1B
TRISTATE 26 11 OUT1B
PWRDN 25 12 VCC1B
CONFIG 24 13 GND1B
VL 23 14 GND1A
VDD 22 15 VCC1A
VDD 21 16 OUT1A
GND_REG 20 17 OUT1A
GND_CLEAN 19 18 N.C.

Table 2. Pin function

Pin Name Type Description

1 GND_SUB PWR Substrate ground

2, 3 OUT2B O Output half bridge 2B
4 VCC2B PWR Positive supply
5 GND2B PWR Negative supply
6 GND2A PWR Negative supply
7 VCC2A PWR Positive supply
8, 9 OUT2A O Output half bridge 2A
10, 11 OUT1B O Output half bridge 1B
12 VCC1B PWR Positive supply
13 GND1B PWR Negative supply
14 GND1A PWR Negative supply
15 VCC1A PWR Positive supply
16, 17 OUT1A O Output half bridge 1A
18 N.C. - No internal connection
19 GND_CLEAN PWR Logical ground
20 GND_REG PWR Ground for regulator VDD
21, 22 VDD PWR 5-V regulator referred to ground
23 VL PWR High logical state setting voltage, VL

DocID13183 Rev 6 3/18

18
Pin description STA516B

Table 2. Pin function (continued)

Pin Name Type Description

Configuration pin:
0: normal operation
24 CONFIG I
1: bridges in parallel (OUT1A = OUT1B, OUT2A = OUT2B (If
IN1A = IN1B, IN2A = IN2B))
Standby pin:
25 PWRDN I 0: low-power mode
1: normal operation
Hi-Z pin:
26 TRISTATE I 0: all power amplifier outputs in high impedance state
1: normal operation
Fault pin advisor (open-drain device, needs pull-up resistor):
27 FAULT O 0: fault detected (short circuit or thermal, for example)
1: normal operation
Thermal warning advisor (open-drain device, needs pull-up
resistor):
28 TH_WARN O
0: temperature of the IC >130 °C
1: normal operation
29 IN1A I Input of half bridge 1A
30 IN1B I Input of half bridge 1B
31 IN2A I Input of half bridge 2A
32 IN2B I Input of half bridge 2B
33, 34 VSS PWR 5-V regulator referred to +VCC
35, 36 VCC_SIGN PWR Signal positive supply

4/18 DocID13183 Rev 6

STA516B Electrical characteristics

3 Electrical characteristics

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC_MAX DC supply voltage (pins 4, 7, 12, 15) 65 V

Vmax Maximum voltage on pins 23 to 32 5.5 V
Tj_MAX Operating junction temperature 0 to 150 °C
Tstg Storage temperature -40 to 150 °C

Warning: Stresses beyond those listed under “Absolute maximum

ratings” make cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated
under “Recommended operating condition” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, power supply with nominal value rated inside
recommended operating conditions, may experience some
rising beyond the maximum operating condition for short
time when no or very low current is sinked (amplifier in mute
state). In this case the reliability of the device is guaranteed,
provided that the absolute maximum rating is not exceeded.

Table 4. Thermal data

Symbol Parameter Min. Typ. Max. Unit

Tj-case Thermal resistance junction to case (thermal pad) - 1 2.5 °C/W

Twarn Thermal warning temperature - 130 - °C
TjSD Thermal shut-down junction temperature - 150 - °C
thSD Thermal shut-down hysteresis - 25 - °C

Table 5. Recommended operating conditions

Symbol Parameter Min. Typ. Max. Unit

VCC Supply voltage for pins PVCCA, PVCCB 10 - 58 V

Tamb Ambient operating temperature 0 - 90 °C

DocID13183 Rev 6 5/18

18
Electrical characteristics STA516B

Unless otherwise stated, the test conditions for Table 6 below are VL = 3.3 V, VCC = 50 V
and Tamb = 25 °C

Table 6. Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Power P-channel/N-channel
RdsON Idd = 1 A - 200 240 m
MOSFET RdsON
Power P-channel/N-channel
Idss - - - 50 µA
leakage Idss
Power P-channel RdsON
gN Idd = 1 A 95 - - %
matching
Power N-channel RdsON
gP Idd = 1 A 95 - - %
matching
Dt_s Low current dead time (static) see Figure 3 - 10 20 ns
L = 22 µH, C = 470 nF
High current dead time
Dt_d RL = 8 , Idd = 4.5 A - - 50 ns
(dynamic)
see Figure 4
td ON Turn-on delay time Resistive load - - 100 ns
td OFF Turn-off delay time Resistive load - - 100 ns
Resistive load
tr Rise time - - 25 ns
see Figure 3
Resistive load
tf Fall time - - 25 ns
see Figure 3
VL / 2 +
VIN-High High level input voltage - - - V
300 mV
VL / 2 -
VIN-Low Low level input voltage - - - V
300 mV
IIN-H High level input current VIN = VL - 1 - µA
IIN-L Low level input current VIN = 0.3 V - 1 - µA
High level PWRDN pin input
IPWRDN-H VL = 3.3 V - 35 - µA
current
Low logical state voltage
VLow (pins PWRDN, TRISTATE) VL = 3.3 V 0.8 - V
(seeTable 7)
High logical state voltage
VHigh (pins PWRDN, TRISTATE) VL = 3.3 V - 1.7 V
(seeTable 7)
IVCC- Supply current from VCC in
VPWRDN = 0 V - - 2.4 mA
PWRDN power down
Output current on pins
IFAULT FAULT, TH_WARN with fault Vpin = 3.3 V - 1 - mA
condition
Supply current from VCC in
IVCC-HiZ VTRISTATE = 0 V - 22 - mA
tristate

6/18 DocID13183 Rev 6

STA516B Electrical characteristics

Table 6. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Input pulse width

Supply current from VCC in = 50% duty,
IVCC operation, both channels switching frequency - 70 - mA
switching) = 384 kHz,
no LC filters
Overcurrent protection
IOCP threshold Isc (short-circuit - 7.5 8.5 10 A
current limit) (1)
Undervoltage protection
VUVP - - 7 - V
threshold
Overvoltage protection
VOVP - 61 62.5 V
threshold
tpw_min Output minimum pulse width No load 50 - 110 ns
1. See specific application note number: AN1994

Table 7. Threshold switching voltage variation with voltage on pin VL

Voltage on pin VL, VL VLOW max. VHIGH min. Unit

2.7 1.05 1.65 V

3.3 1.4 1.95 V
5.0 2.2 2.8 V

Table 8. Logic truth table

Inputs as per Figure 4 Transistors as per Figure 4
Pin
Output mode
TRISTATE
INxA INxB Q1 Q2 Q3 Q4

0 x x Off Off Off Off Hi Z

1 0 0 Off Off On On Dump
1 0 1 Off On On Off Negative
1 1 0 On Off Off On Positive
1 1 1 On On Off Off Not used

DocID13183 Rev 6 7/18

18
Electrical characteristics STA516B

3.1 Test circuits

Figure 3. Test circuit
OUTxY
Vcc

(3/4)Vcc
Low current dead time = MAX(DTr,DTf )
(1/2)Vcc

(1/4)Vcc
+Vcc

t
Duty cycle = 50% DTr DTf
M58
OUTxY R8
INxY

M57 +
-
V67 =
vdc = Vcc/2
gnd
D03AU1458

Figure 4. Current dead-time test circuit

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+VCC

Duty cycle=A Duty cycle=B

DTout(A)

M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTxA Rload=8 OUTxB
INxA INxB
L67 22 L68 22
Iout=4.5A Iout=4.5A
M57 Q3 C69 C70 Q4 M63
470nF C71 470nF 470nF

Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D00AU1162

8/18 DocID13183 Rev 6

STA516B Power supply and control sequencing

4 Power supply and control sequencing

To guarantee correct operation and reliability, the recommended power-on sequence as

given below should be followed:
 Apply VCC and VL, in any order, keeping PWRDN low in this phase
 Release PWRDN from low to high, keeping TRISTATE low (until VDD and VSS are
stable)
 Release TRISTATE from low to high
Always maintain PWM inputs INxy < VL.

Figure 5. Power-ON sequence

Power-OFF sequence:
– When TRISTATE or PWRDN go low, the outputs go into HiZ state
– Inputs INxy are removed before VL is removed
– VL can be removed before or after VCC

DocID13183 Rev 6 9/18

18
Power supply and control sequencing STA516B

Figure 6. Power-OFF sequence

10/18 DocID13183 Rev 6

STA516B Technical information

5 Technical information

The STA516B is a dual channel H-bridge that is able to deliver 200 W per channel (into
RL = 6  with THD = 10% and VCC = 51 V) of audio output power very efficiently. It operates
in conjunction with a pulse-width modulator driver such as the STA321 or STA309A.
The STA516B converts ternary, phase-shift or binary-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.
In differential mode (ternary, phase-shift or binary differential), two logic level signals per
channel are used to control high-speed MOSFET switches to connect the speaker load to
the input supply or to ground in a bridge configuration, according to the damped ternary
modulation operation.
In binary mode, both full bridge and half bridge modes are supported. The STA516B
includes overcurrent and thermal protection as well as an undervoltage lockout with
automatic recovery. A thermal warning status is also provided.

Figure 7. Block diagram of full-bridge DDX® or binary mode

INL[1,2]
INR[1,2] Logic OUTPL
VL interface Left
PWRDN and H-bridge
decode OUTNL
TRISTATE

FAULT OUTPR
Protection Right
THWARN H-bridge
OUTNR

Regulators

Figure 8. Block diagram of binary half-bridge mode

INA(1,2) Logic Left A

INB(1,2) OUT 1A
interface 1/2-Bridge
VL
and
PWRDN Left A
TRISTATE decode OUT 1B
1/2-Bridge

Left A
FAULT OUT 2A
Protection 1/2-Bridge
THWARN
Left A
OUT 2B
Regulators 1/2-Bridge

5.1 Logic interface and decode

The STA516B power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, the VL input must operate at the same voltage as
the DDX control logic supply.

DocID13183 Rev 6 11/18

18
Technical information STA516B

5.2 Protection circuitry

The STA516B includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN, pin 28, open drain MOSFET) is activated low when the IC
temperature exceeds 130 °C, just in advance of thermal shutdown. When a fault condition is
detected an internal fault signal immediately disables the output power MOSFETs, placing
both H-bridges in a high-impedance state. At the same time the open-drain MOSFET of pin
FAULT (pin 27) is switched on.
There are two possible modes subsequent to activating a fault.
 Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE separate, an
activated fault disables the device, signaling a low at pin FAULT output.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low to high using an external logic signal.
 Automatic recovery mode: This is shown in the applications circuits below where pins
FAULT and TRISTATE are connected together to a time-constant circuit (R59 and
C58).
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition persists, the circuit operation repeats until the fault condition is
cleared.
An increase in the time constant of the circuit produces a longer recovery interval. Care
must be taken in the overall system design not to exceed the protection threshold
under normal operation.

5.3 Power outputs

The STA516B power and output pins are duplicated to provide a low-impedance path for the
device bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRISTATE pin should be used to set all power MOSFETs to the
high-impedance state during power-up until the logic power supply, VL, has settled.

5.4 Parallel output / high current operation

When using the DDX mode output, the STA516B outputs can be connected in parallel in
order to increase the output current capability to a load. In this configuration the STA516B
can provide up to 240 W into a 3  load.
This mode of operation is enabled with the pin CONFIG (pin 24) connected to pin VDD. The
inputs are joined so that IN1A = IN1B, IN2A = IN2B and similarly the outputs
OUT1A = OUT1B, OUT2A = OUT2B as shown in Figure 9 on page 13

5.5 Output filtering

A passive 2nd order filter is used on the STA516B power outputs to reconstruct the analog
audio signal. System performance can be significantly affected by the output filter design
and choice of passive components. A filter design for 6 or 8  loads is shown in the
application circuit of Figure 8, and for 3 or 4  loads in Figure 9 and Figure 10.

12/18 DocID13183 Rev 6

STA516B Applications

6 Applications

Figure 9 below shows a single-BLT configuration capable of giving 400 W into a 3  load at
10% THD with VCC = 52 V. This result was obtained using the STA30X+STA50X demo
board. Note that a PWM modulator as driver is required.

Figure 9. Typical single-BTL configuration for 400 W

VL
+3.3V 23 18 N.C.
100nF 12 H
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 680nF 4
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
12 H
10K FAULT
27 VCC1A
15 +36V
26
TRI-STATE 1 F 2200 F
100nF X7R 63V
IN1A VCC1B
29 12
IN1B
IN1A 30
IN2A VCC2A
31 7 +36V
IN2B
IN1B 32 1 F
X7R
VSS VCC2B
33 4
VSS
34 GND1A
100nF 14
X7R VCCSIGN GND1B
35 13

100nF VCCSIGN GND2A

X7R 36 6
Add. GNDSUB GND2B
1 5
D04AU1545

Figure 10. Typical quad half-bridge configuration

VCC1P +VCC

15
IN1A 29 M3 R61 C21
IN1A 5K C31 820 F 2200 F
17 L11 22 H
VL 23
+3.3V OUTPL
CONFIG 24 16 R41 C71
20 100nF
OUTPL C91 4
PWRDN PWRDN 25 M2 1 F
14 PGND1P R51 C81 R62
PROTECTIONS C41 100nF
6 5K
R57 R59 FAULT 27 & 330pF
10K 10K LOGIC
26 12 VCC1N
TRI-STATE
C58 M5 C51 C61
100nF 11 1 F 100nF
R63
TH_WAR 28 OUTNL 5K C32 820 F
TH_WAR 10 L12 22 H
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF
VDD 21 13 PGND1N C92 4
1 F
VDD 22 R52 C82 R64
C42 100nF
6 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34
M17 R65
C58 C53 C33 820 F
L13 22 H 5K
100nF 100nF VCCSIGN 8
35
OUTPR
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4
M15 1 F
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1 F 100nF
R67
OUTNR 5K C34 820 F
IN2B 2 L14 22 H
IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4
1 F
R54 C84 R68
C44 100nF
6 5K
330pF
D03AU1474

For more information, refer to the application note AN1994.

DocID13183 Rev 6 13/18

18
Package mechanical data STA516B

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark

14/18 DocID13183 Rev 6

 Figure 11. PowerSO36 exposed pad up outline drawing

STA516B
DocID13183 Rev 6

Package mechanical data

15/18
Package mechanical data STA516B

Table 9. PowerSO36 exposed pad up dimensions

mm. inch.
Symbol
Min. Typ. Max. Min. Typ. Max.

A 3.25 - 3.43 0.128 - 0.135

A2 3.10 - 3.20 0.122 - 0.126
A4 0.80 - 1.00 0.031 - 0.039
A5 - 0.20 - - 0.008 -
a1 0.03 - -0.04 0.001 - -0.002
b 0.22 - 0.38 0.009 - 0.015
c 0.23 - 0.32 0.009 - 0.013
D 15.80 - 16.00 0.622 - 0.630
D1 9.40 - 9.80 0.370 - 0.386
D2 - 1.00 - - 0.039 -
E 13.90 - 14.50 0.547 - 0.571
E1 10.90 - 11.10 0.429 - 0.437
E2 - - 2.90 - - 0.114
E3 5.80 - 6.20 0.228 - 0.244
E4 2.90 - 3.20 0.114 - 0.126
e - 0.65 - - 0.026 -
e3 - 11.05 - - 0.435 -
G 0 - 0.08 0 - 0.003
H 15.50 - 15.90 0.610 - 0.626
h - - 1.10 - - 0.043
L 0.80 - 1.10 0.031 - 0.043
M 2.25 - 2.60 0.089 - 0.102
N - - 10 degrees - - 10 degrees
R - 0.6 - - 0.024 -
s - - 8 degrees - - 8 degrees

16/18 DocID13183 Rev 6

STA516B Revision history

8 Revision history

Table 10. Document revision history

Date Revision Changes

01-Feb-2007 1 Initial release.

19-Mar-2007 2 Update to reflect product maturity.
11-Aug-2009 3 Updated section Description on cover page.
Modified presentation
16-Nov-2010 4 Updated Chapter 3: Electrical specifications on page 5
Added Chapter 5: Applications information on page 10
15-Jan-2014 5 Modified Section 4: Power supply and control sequencing on page 9
11-Feb-2014 6 Updated order code Table 1 on page 1

DocID13183 Rev 6 17/18

18
 STA516B

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18/18 DocID13183 Rev 6