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QB For Ec1404 Vlsi Lab

The document contains 45 questions related to designing basic digital logic circuits like half adder, full subtractor, multiplexers, decoders, counters, flip flops, and converters using Verilog and simulating them using the Xilinx-ISE simulator. The questions involve implementing various combinational and sequential logic circuits as well as converting between different binary codes.

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Chandramouleeswaran Sarma
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247 views

QB For Ec1404 Vlsi Lab

The document contains 45 questions related to designing basic digital logic circuits like half adder, full subtractor, multiplexers, decoders, counters, flip flops, and converters using Verilog and simulating them using the Xilinx-ISE simulator. The questions involve implementing various combinational and sequential logic circuits as well as converting between different binary codes.

Uploaded by

Chandramouleeswaran Sarma
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Questionbank for EC1404 VLSI lab

1. Design a half-adder and full-subtractor in verilog and also simulate the same
using Xilinx-ISE simulator.
2. Design a half-subtractor and full-adder in verilog and also simulate the same
using Xilinx-ISE simulator.
3. Implement an 8:1 MUX in verilog and also simulate the same using Xilinx-ISE
simulator.
4. Implement an 8:1 MUX using 4:1 MUX and also simulate the same using Xilinx-
ISE simulator.
5. Design 3 to 8 decoder in verilog and also simulate the same using Xilinx-ISE
simulator.
6. Design a 4 to 16 decoder in verilog and also simulate the same using Xilinx-ISE
simulator.
7. Design 1:4 DEMUX and 1:8 DEMUX using verilog.
8. Write a verilog program to convert a given BCD number to seven segment
display in common cathode and also simulate the same using Xilinx-ISE
simulator.
9. Write a verilog program to convert a given BCD number to seven segment
display in common anode mode and also simulate the same using Xilinx-ISE
simulator.
10. Write a verilog program to convert a given weighted-code to cyclic code and also
simulate the same using Xilinx.
11. Write a verilog program to convert a given cyclic code to weighted-code and also
simulate the same using Xilinx.
12. Write a verilog program to convert a given weighted-code to self-complementing
code and also simulate the same using Xilinx.
13. Write a verilog program to convert a given self-complementing code to weighted-
code and also simulate the same using Xilinx.
14. Write a verilog program to implement a Full adder using Half adder in verilog and
also simulate the same using Xilinx-ISE simulator.
15. Write a verilog program to design a 4-bit magnitude comparator using 2-bit
magnitude comparator and also simulate the same using Xilinx-ISE simulator.
16. Write a verilog program to design a 4 bit Ripple carry adder and also simulate the
same using Xilinx-ISE simulator.
17. Write a verilog program to design an 8:3 encoder and also simulate the same
using Xilinx-ISE simulator.
18. Design and simulate an asynchronous 4bit counter using JK Flip Flop with active
low CLEAR signal using Xilinx-ISE simulator.
19. Design and simulate a synchronous 4 bit counter using T Flip Flop with active
high CLEAR signal using Xilinx-ISE simulator.
20. Write a verilog program to convert JK flip flop into SR, T and D flip flop and also
simulate the same using Xilinx-ISE simulator.
21. Design a parallel-in-parallel-out shift register using verilog and also simulate the
same using Xilinx-ISE simulator.
22. Design a serial-in-serial-out shift register using verilog and also simulate the same
using Xilinx-ISE simulator.
23. Design a serial-in-parallel-out shift register using verilog and also simulate the
same using Xilinx-ISE simulator.
24. Write a verilog program to implement a Full subtractor using Half subtractor and also
simulate the same using Xilinx-ISE simulator.
25. Write a verilog program to implement a real time clock using FPGA.
26. Write a verilog program to implement a parallel adder. Add 8 nos. of 12 bit each
using FPGA.
27. Write a verilog program to implement a multiplier. Multiply 2 nos. of 8 bit each
using FPGA.
28. Design a 4 bit even parity checker including parity bit using verilog.
29. Design a 4 bit odd parity checker including parity bit using verilog.
30. Design a 4 bit odd parity generator using verilog.
31. Design a 4 bit even parity generator using verilog
32. Design a Jhonson counter using verilog.
33. Design a Ring counter using verilog.
34. Design a 3bit up/down counter using verilog.
35. Design a D Flip Flop using verilog.
36. Design a JK Flip Flop using verilog.
37. Design a MOD-7 counter using verilog.
38. Design a MOD-10 counter using verilog.
39. Design a BCD to Excess-3 code converter using verilog.
40. Design a Excess-3 code to BCD converter using verilog.
41. Design a 4 to 16 decoder using behavioral model in verilog.
42. Design a 3 bit magnitude comparator.
43. Design a T Flip Flop using verilog.
44. Design a 3bit up counter using verilog.
45. Design a 8 x 1 using behavioral model using verilog.

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