Scribd
Upload
88 views

Vlsi Lab Doc

VLSI lab, semester 07, Anna University

Uploaded by

Chandramouleeswaran Sarma
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
88 views

Vlsi Lab Doc

VLSI lab, semester 07, Anna University

Uploaded by

Chandramouleeswaran Sarma
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 5

3) 8x1 Mux using behavioral modelling

module mux(x,s,y);
input [7:0]x;
input [2:0]s;
output y;
reg y;
always@(x or s)
begin
if(s==0)
y=x[0];
else if(s==1)
y=x[1];
else if(s==2)
y=x[2];
else if(s==3)
y=x[3];
else if(s==4)
y=x[4];
else if(s==5)
y=x[5];
else if(s==6)
y=x[6];
else if(s==7)
y=x[7];
end
endmodule

module testbench();
reg [7:0]x;
reg [2:0]s;
wire y;
mux m1(x,s,y);
initial
begin
x=8'b00000001;s=3'd0;
#10 x=8'b00000010;s=3'd1;
#10 $finish;
end
endmodule
7) 1:8 Demux

module demux8(x,s,y);
input x;
input [2:0]s;
output [7:0]y;
reg [7:0]y;
always @ (x or s)
begin
y=8'd0;
case(s)
3'b000:y[0]=x;
3'b001:y[1]=x;
3'b010:y[2]=x;
3'b011:y[3]=x;
3'b100:y[4]=x;
3'b101:y[5]=x;
3'b110:y[6]=x;
3'b111:y[7]=x;
endcase
end
endmodule

module testbench();
reg x;
reg [2:0]s;
wire [7:0]y;
demux8 d1(x,s,y);
initial
begin
x=1;s=3'd0;
#10 x=1;s=3'd5;
#10 $finish;
end
endmodule

15) 4bit magnitude comparator using 2bit mag comp

module mag2(a1,b1,g,e,l);
input [1:0]a1,b1;
output g,e,l;
assign g=(a1>b1),
e=(a1==b1),
l=(a1<b1);
endmodule

module mag4(a,b,g,e,l);
input [3:0]a,b;
output g,e,l;
wire g1,e1,l1,g2,e2,l2;
mag2 m1(a[3:2],b[3:2],g1,e1,l1);
mag2 m2(a[1:0],b[1:0],g2,e2,l2);
assign g=(g1 | (g2&g1)),
l=(l1 | (l2&l1)),
e=(e1 & e2);
endmodule

module testbench();
reg [3:0]a,b;
wire g,e,l;
mag4 m(a,b,g,e,l);
initial
begin
a=4'b0010;b=4'b1001;
#10 a=4'b1100;b=4'b1100;
#10 a=4'b1100;b=4'b1011;
#10 $finish;
end
endmodule

16) 4bit Ripple carry adder

module fa(a1,b1,c1,s,c0);
input a1,b1,c1;
output s,c0;
assign {c0,s}=a1 + b1 + c1;
endmodule

module ra(a,b,c,s,c0);
input [3:0]a,b;
input c;
output [3:0]s;
output c0;
wire t1,t2,t3;
fa f1(a[0],b[0],c,s[0],t1);
fa f2(a[1],b[1],t1,s[1],t2);
fa f3(a[2],b[2],t2,s[2],t3);
fa f4(a[3],b[3],t3,s[3],c0);
endmodule
module testbench();
reg [3:0]a,b;
reg c;
wire [3:0]s;
wire c0;
ra r(a,b,c,s,c0);
initial
begin
a=4'b1000;b=4'b0101;c=0;
#10 a=4'b0101;b=4'b1000;c=1;
#10 a=4'b1001;b=4'b1000;c=0;
#10 $finish;
end
endmodule

8x1 Mux using 4x1 Mux

module mux4(i,s,y);
input [3:0]i;
input [1:0]s;
output y;
reg y;
always @(i or s)
case(s)
2'b00:y=i[0];
2'b01:y=i[1];
2'b10:y=i[2];
2'b11:y=i[3];
endcase
endmodule

module mux8(x,sel,y0);
input [7:0]x;
input [2:0]sel;
output y0;
wire y1,y2;
//reg y0;
//always@(x or sel)
mux4 m1(x[3:0],sel[1:0],y1);
mux4 m2(x[7:4],sel[1:0],y2);
assign y0=sel[2]?y2:y1;
endmodule

module testbench();
reg [7:0]x;
reg[2:0]sel;
wire y0;
mux8 m3(x,sel,y0);
initial
begin
x=8'b11111111;sel=3'd0;
#10 x=8'b00000000;sel=3'd0;
#10 $finish;
end
endmodule

You might also like