2019 TUGx Global Seminar Abstracts

Teradyne is presenting a series of TUGx Global Seminars that will provide you with the latest information
regarding the best test strategies and techniques to use for testing the latest generation of devices on
Teradyne’s products.
Each TUGx Global Seminar has content tailored to the interests of the customers in the local region presenting
a seminar. Seminars will describe test challenges and how Teradyne test systems and software addresses
those challenges. They will also describe the benefits users obtain to reduce cost of test and to develop test
programs with less effort meet production ramp requirements. Seminar topics include the following:

0. Teradyne SOC 18-Month Product Roadmap

Device and industry trends are presented as they are the key drivers to the development of new products. The
Teradyne roadmap for the key SOC semiconductor test products will be reviewed along with an overview of
key hardware and software products to be released in the next 18 months (mid 2019 to end 2020).

1. UltraFLEX family best practice programming for digital devices, UltraFLEX

Test program development is typically a multiple test engineer program development project so that
customers can meet time to market. Managing modularity among test engineers becomes an influencing
factor in development efficiency. Equally important is how to create an optimized test program. Most
semiconductor manufacturers have a digital component to their devices. In this presentation, we will
describe how optimized programming will yield improvement in workbook memory usage, load time,
validate or re-validate time and test time for digital devices. In parallel you gain efficiency, reuse and
shared learning among team members with managed modularity.

2. ISOSearch - A unique searching method for long pattern execution times, UltraFLEX

When creating a search test, test engineers typically go to traditional types of search algorithms - mainly
Binary and Linear searches. We have developed a better algorithm that takes into account the
architecture. In this presentation we will explore 1) a test case where the passing condition has a long
pattern execution time 2) the test system digital architecture and 3) how simple changes to code can
lead to near zero seconds of Per Site Overhead (PSO).

3. Technical skills and solutions for the test time optimization experienced in ETS800 test
program using AQtime, ETS800

Technical skills and solutions for the test time optimization experienced in ETS800 test program are
introduced. Knowing the details of each command activation time is the first step to make the strategy of
test time reduction. AQtime, the profiling toolkit, is one of the best solutions for measuring the health of
test programs with unrivaled accuracy, and finding out which test command is time-consuming. In my
presentation, an overview of AQtime application and brief explanations of its activation procedure will be
introduced. Then, the practical experiences with AQtime are explained by showing how to find the time-
consuming test command line and improve test time. Taking advantage of these techniques came out
around 34.5% of test time reduction from 31.99sec to 20.79sec, which results satisfied customer’s
requirements.

4. A new circuitry to test Gate to Emitter Pinch-off Voltage of High Power IGBT, ETS88/88TH IGBT
Pinch-off Voltage is an important DC parameter of IGBT. Usually, it's tested in fixed VCE to make ICE in
specific value, the corresponding VGE is the pinch off voltage (Vp). The conventional method to test Vp
is to force VCE directly by HPU, then run an AWG pattern on Gate to search the Vp at specific ICE. This
method works for lower ICE (less than 500 Amps). When ICE reach up to 500 Amps, it's hard to make
VCE keep the set value by HPU. This presentation will introduce a new circuitry. It take VCE and ICE as
input, use feedback of op amp to output Vp. The simulation and experimental results show the validity of
this circuitry, and it was verified in real project with ICE reach up to 800 Amps.

5. Probe Interface Solutions for 5G, UltraFLEX

Billions of 5G integrated circuits (ICs) are needed to not only interconnect and control machines, objects,
and devices but also deliver multi-Gbps peak rates, ultra-low latency, massive capacity, and a more
uniform user experience. Our customers are demanding higher quality levels of test cell and faster time
to volume production as products become more complex and for fulfilling the 5G wireless networks. As
greater percentages of RF and complex SOC transition more to probe test, deciding the precise test
interface solution for one’s device is the most critical factor to meet faster time to volume production in
wafer test environment. This presentation will introduce industry proven probe interface solutions for 5G
wafer testing followed by a look in detail of each probe interface solution’s connections, its signal
performance and probe card technologies.

6. UltraFLEX frequency measurement in automotive, UltraFLEX

In automotive test solutions, the PLL is part of IP block for series of frequency measurement tests.
To be consistent with the legacy J750 solution, a pattern-based test solution is required in UltraFLEX,
running pattern and open interval window by pattern trigger to start/stop counting events.
It's easy to calculate the frequency with the counts and window interval. The UP1600 can support this
pattern triggered with frequency counter after IG-XL V9.00. This presentation will introduce and
demonstrate UP1600 pattern triggered frequency measurement, and discuss the possible encountered
issues during automotive project development. Afterwards, the pattern triggered method can be
applicable to test a DUT output clock is nondurable, which means clock signal only appears for a while.

8. Topic Area of Interest: Artificial Intelligence device testing, General Topic

Among today’s most popular buzzwords are Artificial Intelligence (AI) and Machine Learning (ML).
Traditional programming applies an algorithm directly to a given problem. AI abstracts this one level; AI
algorithms are applied toward learning or discovering a process that will solve the problem. AI includes
everything from the classical troubleshooting flowcharts to genetic programming, and has been used for
everything from computer poker players to discovering new drugs.
Machine Learning is a branch of AI that uses statistics to drive the learning process. ML can be used for
linear or polynomial regression, classification, and grouping. There are dozens of ML models, such as
decision trees, support vector machines, neural networks, etc. ML has been applied to natural language
processing, handwriting recognition, photo and video tagging, facial recognition, and many of the sub-
tasks performed by robots and self-driving cars. Applications of ML to device testing is a new area of
research.
This presentation introduces the basic concepts of Machine Learning, and will prepare the reader for
understanding other papers that implement ML for various applications.
9. Wait Adjust Tool for test time reduction
It is very difficult to decide the minimum wait time from the beginning even if programming with efficient
code at the time of coding when thinking about the test time. For this reason, it is necessary to adjust the
length of several hundred to several thousand instances of wait time during Test Time Reduction (TTR).
This is extremely hard work. This presentation shows a tool to automatically adjust many wait times for
TTR. This tool adjusts all wait time to a minimum in the program while repeatedly executing the test
program. Each adjusted wait time’s validity is judged from the result of Pass / Fail or statistical
processing. The tool can be used for FLEX and UltraFLEX systems, and reports the result of TTR
achieved using the tool on each system.

10. Test System Architectural Strengths for Digital Devices, UltraFLEX

The rate of change in digital test is moving quickly and tester capability that keeps pace with these
changes that are coming is necessary to manage the complexity. The test system architecture has
strengths that allow us to extend the testability of Big-D and MAP devices. This presentation will discuss
how the tester capability provides solutions in testing these devices to meet future customer needs.
Over the years, market trends show that the number of devices our customers want to test in parallel
has increased; the pin count can increase with some market segments; the number of patterns used to
test silicon tends to change scan/functional; the clocking requirements change; the ability to move large
amounts of data increases; and, there is increased challenges on manufacturability of loadboards. We
will discuss how the tester capability provides strengths that pair with the growing demands of digital
device testing.

11. Flexible Memory Architecture on Digital Capability UltraFLEX

This presentation will demonstrate the improved flexibility of the digital instrument. It will first provide a
broad description of the system before focusing in on the specifics of the pattern generators (PatGens).
This presentation will describe the pattern memory architecture show the impact on SCAN chain depth
and width. In order to help users leverage this architecture, this presentation will explain how to use the
Pattern Data Explorer (PDX) tool and go through two use cases that combine the memory architecture
with PDX and some best practices.

12. Al chip final test design and challenge, UltraFLEX

Many companies are designing AI chips. These are big power consuming devices and the interface
board design is very important. The VSM is used to provide the supply power for these devices. Proper
PCB power design of the interface board with simulation (PI) will ensure the VSM is a very stable power
source. When the large SCAN patterns are used for test, the effect on the power supply current can be
very useful for debugging the device. The UltraFLEX’s multiple patterns’ real time current profile is a
valuable tool to see current changes.
Yield can also be improved based on ITC@2014 IEEE’s paper (mitigating voltage droop during scan
with variable shift frequency). The current profile can be used to find the beginning of a stable setup
current and a clock period setting. The clock period can be modified on the fly to shift frequency and
then see how the shmoo results change.
DUT temperature control is also another important parameter for these high performance devices.
Another important topic is protecting the DUT by having the ability to power down the VSM when the
DUT exceeds temperature limits.

13. New IGXL 10.10.00 integrated Spike Check Tool, UltraFLEX

Spike Check Tool provides a convenient way to check a test program for excessive voltage levels that
could potentially damage a DUT. Many companies require a test program to undergo a glitch check as
part of the release to production process. This typically involves connecting a scope probe to each pin of
the DUT one at a time and running the test program. A test engineer reviews the waveforms captured by
the scope and is responsible for ensuring that the levels do not exceed the device’s absolute maximum
ratings. SpikeCheck Tool is intended to provide a test engineer the capability to check a test program for
spikes on a daily basis without the need to use a scope. This will simplify the process of checking for
and catching most spikes, as well as allow them to be caught and fixed by the original authors of the test
code while it is still fresh in their mind. This presentation will describe what the Spike Check Tool is, how
it works, how to use it and what performance to expect.

14. Improve IQxstream-M Background Calculation with User-defined SCPI, J750

When we are using J750+IQxstream-M solution, we will use the background calculation of the IQM to
reduce the test time. Usually we put all the calculation SCPI commands before other non-RF tests, and
send all the fetch SCPI commands after non-RF tests, then the calculating time can be saved. But
sometimes we should get the previous result, then use it to do next calculation, that will cause the
background calculation interrupted (eg. we should get the peak power's frequency offset, then we use
the offset to calculate the SSB,LO,etc.). So, we should develop the user-defined SCPI which can merge
the two functions into the one new SPCI and then we can hide the calculation time

15. Tools to Debug Errors and Alarms during ETS800 Test Program Development, ETS800
When developing new test applications or converting applications to the ETS-800 platform, errors or
alarms in the test program may be identified by the system software because of the programming
techniques used. Searching for where the errors or alarms occur in the test program can consume a lot
of engineering time, but must be addressed in order to ensure test quality. Two similar tools are
available to provide an easier way to identify these fast and fix them. The tools print exactly where in the
C++ files the errors and alarms have occurred. Both tools come as .CPP / .H source code which can be
added to the applications project.

17. 5G NR 101-101-101..., UltraFLEX

The presentation reviews the basic aspects of the 5G NR, covering topics like the physical layer,
operating environment and how that ties to test. It will include a review of Source & Capture Signal files
used to configure your test along with tips on determining correct demodulation configurations. This
presentation concludes with test time reduction techniques for 5G NR.

21.DC instrument guide, UltraFLEX

With a variety of VS instruments and all of the features that come with these next generation
instruments, the distinction between VS and VI instruments is getting hard to distinguish. This
presentation describes the similarities/differences between all of the DC instruments, helps users
understand what capabilities are offered by each, and what makes them unique. The presentation will
show how different averaging methods (fixed vs moving) work on each instrument, how VS's and VI's
use the different methods of collecting data, as well as the benefits to using either method. When
looking at these instruments it is important to understand how they are programmed and what
differences exist when trying to force a current or take a measurement. The presentation will go into
detail of how to convert DCVI code to DCVS code and vice versa for both current forcing and MV/MI
capabilities. Finally, it is important to understand what sort of performance in terms of test time and
accuracy can be expected when making this generational leap. Factors that can have a large impact on
test time vs accuracy of measurements and what users should be aware of when using these new
instruments will also be discussed.

24. Optimized Sampling Rate for Eagle Platforms, ETS800/ETS88

Static voltage and current measurements are an essential part of every test application. An established
practice on Eagle Test System platforms is the usage of a 13 µs sampling delay to ensure an optimal
signal acquisition for highest test quality. The usage of a 13 µs delay can cause signal aliasing at low
frequencies that can severely distort the measurement, causing the test engineer to increase the
number of samples to get a better average. This results in a longer test time. This presentation
describes the best practice for DC voltage and current measurements on ETS Platforms. It illustrates the
effects of aliasing with floating instruments on the ETS800 and the ETS88 and quantifies the benefit of
an optimized sampling practice by analyzing test time savings with different devices. The analysis shows
potential test time savings ranging from 1 to 5 percent.

27. Optimizing Your UltraPAC80 Capture Settings, UltraFLEX

Selecting optimal range and bandwidth for greatest use of dynamic range

The UltraPAC80 is a precision analog measurement instrument. To get the best dynamic performance
for your measurements you need to align your signal measurement requirements with the optimal
instrument settings. This requires a good understanding of the instruments voltage ranging, input
compliance, connection options, sampling rates, bandwidth and noise. This presentation will provide
some detail around each of these subjects. In addition, there is a spreadsheet based tool available that
will allow the user to enter input conditions to determine the best input ranging as well as a tool to
calculate expected noise for the selected conditions.

28. Digital Tips and Tricks, ETS-88

“Digital Tips and Tricks for the ETS-364 & ETS-88” is a collection of best practices from the past few
years. Many of the “tips” include often forgotten basics through more advanced programming techniques
for the ETS platform. The “tricks” will cover common best practices specifically for the DPU-16, QTMU
and MCU-66 resources. Also included are frequently asked Device Interface Board (DIB) layout
considerations.

29. PTE improvement in trim searching for IoT products, UltraFLEX

Devices need to be more accurate than before while test programs need search trim code for different
value, bias voltage, current, frequency, etc. Test site count is greater than before, thus program site
efficiency is more important. Most of users implement the trim searching by serial_site loop since each
device’s trim data is different and causes the lower PTE. This presentation puts in DSSC and
Site_Disable methods to improve PTE for test time reduction and gets better trim efficiency.
• Simple search trim code by site serial and modify trim code by VBT
• Searching trim code by DSSC, DSP function and site disable
• Test time reduction rate

31. HDDPS/HDVIS Send and Trig Mode on J750 (HD) Platform, J750HD

In this presentation, we will introduce J750 HDDPS / HDVIS send and trigger test mode and usage.
Send and trigger mode is a very useful test method for power and analog pin's setting and
measurement. This method will make test point more accurate and less time than flag loop.
1. What is Send and Trigger in HDDPS and HDVIDS.
2. How to use Send and Trigger with HDDPS and HDVIS.
 1) Usage in HDDPS
* What is Setups and Sequences in HDDPS.
* How to set setups and sequence by VBT and how to control them by send signal.
2) Usage in HDVIS
* How to set ExSend and ExtTrig in HDVIS and how to control them.
3. Common application scenarios.
1) Dynamic current test.
2) IDDQ test.
3) Ramp Output(HDVIS)

36. UPD-64 DR Mode and Enhanced ADC Features, ETS-800

The UPD-64 (Universal Pin Digital) resource provides many new features and benefits compared to
existing solutions. This presentation will describe a few of the key features, including a unique signal
delivery methodology called DR (DRIVE/RETURN) mode. This feature provides the user with two
different paths to the DUT (Device Under Test). One path is optimized for higher current and analog
performance; the other is optimized for higher bandwidth digital signal delivery. DR mode also inherently
adds other new features to the UPD-64. These include per-pin kelvin measurement and the ability to
USE the VI, PPMU, and timestampers on either the force or the sense line. Another key feature is
improved pattern based ADC capabilities. These include a firmware based threshold search for faster
test time. These new features, combined with high voltage digital performance, make the UPD-64 a
powerful tool in automotive and linear power testing.

37. ETS800 with Strip Handler Low Cost Test Solution For Above 35V Rating Multi-Cell Battery
Gauge Devices, ETS800
Recent developments in battery-powered appliances and applications in industrial and consumer
markets require multi-cell battery gauge devices. Texas Instruments has developed multi-cell battery
gauge devices to meet the needs of the end user. Those multi-cell battery gauge devices are rated
above 35V and are cost competitive ones. ETS800 was selected as the platform that enables above
35V, 16-site solution on a strip handler. This solution on ETS800 is the best compared to possible
solutions on ETS-364, FLEX, and J750-EX in terms of cost, number of sites, and load board design
simplicity. The presentation will describe how stable yields above 97% and on-target test cost were
achieved with a test solution that enables 16-site, above 35V testing, and significantly reduced circuitry
on the application load board by utilizing the MST ETS800 technology, 80V range APU32, A/B buses on
the UPU64, SPU2112, internal ETS800 buses and relays matrices.

38. The Test Time Benefits of the new AutoStrobe Edge Find and Edge Offset Features,
UltraFLEX

AutoStrobe Edge Find and Edge Offset are two new digital functions supported by IG-XL 10.10 that can
dramatically speed up certain timing edge search measurements and timing overlays. Edge searches
can be slow because they are typically performed with multiple pattern bursts. The AutoStrobe Edge
Find capability allows edge searches on repetitive signals to be performed dramatically faster, in a single
pattern burst. Timing overlays can be inefficient because the tester executive has to propagate spec
changes through a timing context before applying the updated values to hardware. The Edge Offset
feature allows calculated edge offsets to be stored in a set of per pin registers, where they can be
reused on multiple tests and in multiple timing contexts, avoiding timing value recalculations and the re-
loading of tester hardware. This presentation will show practical examples of how to use these features
and demonstrate the test time savings.

39. Part Average Testing in general and within the test program, ETS800
Part Average Testing is a statistical method for recognizing and quarantining semiconductor die that
have a higher probability of reliability failures. This technique identifies characteristics that are within
specification but outside of a normal distribution for that population as at-risk outliers not suitable for high
reliability applications.

The method can help to achieve a “zero defects” production. But as it has different approaches and
requirements, it causes additional effort and often investments in additional equipment like database
servers etc. An alternative way to get some advantages of PAT with less effort is the use of the EVS
PAT-library which can be used within the test program. The presentation explains the basic functionality
of PAT, most common algorithms and a short introduction in PAT-lib usage.

40. ATE Thermal Protection, UltraFLEX

To safeguard probes, sockets, and DIBs from damage when a device enters a thermal-runaway
condition, a real-time interrupt solution is described. This protection in intended to add an additional
layer of protection to the capabilities that are already provided with the DCVS instruments (including the
VSM and HexVS). The DIB shutdown utilizes DIB circuitry consisting of an analog switch and a circuit
that’s monitoring the temperature (on or off chip) and providing a logic signal to the switch. Production
considerations such as site specific control are considered. Hardware was developed to monitor the
effects of breaking various kelvin and interlock connections on the VSM instrument. Some specific
components and why they were selected are provided.

41. Best Solution for MIPI D-PHY/C-PHY on IP750, J750

Recent CMOS Image Sensors (CIS), especially mobile phone’s image sensors, have higher speed data
rate, high count of pixel number, and low power consumption. The Mobile Industry Processor Interface
(MIPI) standard defines industry specifications for the design of mobile devices such as smartphones.
The MIPI standard defines some unique physical (PHY) layer specifications called as MIPI D-PHY and
C-PHY. MIPI D-PHY and C-PHY physical layers support camera and display applications. In this
presentation, MIPI D-PHY/C-PHY specification will be explained. An FPGA based BOST Solution for
MIPI D-PHY over 1.5Gbps and for MIPI C-PHY have been developed. The BOST solutions with actual
CIS DUT results will be covered in the presentation.

42. Twin Direct Docking for IP750Ex-HD, J750 IP

Multi-site testing of image sensors requires to expand illuminator area and more resources of test
system. Illuminator companies have been released products for wide lighting area. Normal direct
docking on IP750s, could built-in the (small lighting area) illuminator in the test head, however, as for
wide lighting area illuminator, normal direct docking could not be built-in them. And, IP750s resources
limited less than 16sites testing on ICUL1G/ICMD at 4 data lanes devices. In this presentation, Twin
Direct Docking (TDD) will be explained. TDD has many advantages against Normal direct docking or
Cable docking. Multi-sites testing over 16sites, using wide lighting area illuminator, good signal integrity,
measurable DUT signal by an oscilloscope or other equipment even if docked, and more. These kinds of
Device Interface Board (DIB) will also be covered in the session.

44. ETS-88TH Inductor Box Best Practices, ETS88/ETS88TH

An indispensable element in test circuits for IGBTs and power modules is the inductor. This element can
determine very important characteristics such as peak voltages and currents in tests as TRR and ILM.
Nevertheless, when it comes to applications design for these devices, some errors can be made when
making the necessary connections of the inductor. This could represent a risk not only to the integrity of
the hardware but also to the people that work with it.

For this reason, having an instrument that can easily provide a safe and versatile connection for the
inductor on ETS-88TH applications is vital. The presentation will introduce the Inductor Box, which is an
instrument of the ETS-88TH with these characteristics. The presentation will also detail best practices
when programming the instrument, which can give reduced test time, avoid hot switching and guarantee
hardware integrity when coding our test program.

47. Integration of LitePoint Instruments on the UltraFLEX Test System, UltraFLEX

Some RF device testing needs are outside the BW and/or Carrier Frequency of the UltraWave24.
There are emerging RF technologies that will latch with the market requiring higher BW’s (>1GHZ) and
higher carrier frequencies (>6GHZ) than what is currently supported with the MW24.
LitePoint has a variety of high BW, high frequency instruments that can address these testing needs.
Through UltraFLEX instrument extensions, we have added high BW, high frequency LitePoint
instruments to the UltraFLEX tester.
This presentation will describe the software instrument extension (IX) API IQUTIL and go through some
multisite programing examples. It will also describe the HW interface and calibration of these Litepoint
instrument extensions.

51. Got a DUT with many Serdes Rx ONLY pins? Here is a solution!, UltraFLEX

A DIB Module that can replicate one SerDes transmitter into many for higher throughput and lower test
cost will be presented.

SerDes is becoming more and more popular and widely adopted among consumer electronic devices.
The US10G can well handle the data rates. The challenge is the SerDes transmitters and receivers are
not paired like in HDMI and other MIPI applications. Benchtop signal generators can do the job but they
lack the density to do multisite testing.

This presentation will demonstrate a DIB module that can take one or more serial signal inputs and
replicate them to many more serial output ports… up to 12 per module. The module size is extremely
small so it enables using eight of them under the UltraFLEX’s DIB to test octal site. This creates 96
serial signals for testing all device sites serial receivers. For a typical DUT with 4 MIPI D-PHY, it means
quad site is possible with 24 serial receivers per DUT. The module is ready and the performance is
verified.

55. GuardBanding, All Devices

The global automotive semiconductor market is estimated to grow rapidly in the next 10 years. The
growth in the automotive sector will drive higher demand in manufacture quality, required to meet
customer expectations of “Zero Field Returns”.

Guard-banding is one quality technique used often in production testing when instruments are affected
by measurement error/uncertainty. Guard-band limits improve quality by reducing the risk of validating a
defective product as good and, as consequence, by reducing product returns.

The trade-off for implementing guard-banding is yield loss will increase; for automotive devices this
trade-off is justified because the cost impact of product returns is much higher than yield loss.
This presentation will describe when guard-band limits are needed and how to set them in order to help
users to meet their failure target rate.

59. Stray Inductance, ETS88/88TH IGBT

In power devices including IGBT and SiC, all manufacturers attempt to optimize the product design on
a common technical specification – low stray inductance. This is due to the overshoot voltage
generated by the stray inductance during AC switching which will lead to the risk of device breakdown,
and have an impact on the power conversion efficiency.
In today's world of energy-saving and low-carbon life, Power device development is moving to faster
switching speeds and higher conversion efficiencies. For example, SiC MOSFETs are used in more
products such as electric vehicles. Trends in power devices have become more demanding for low
stray inductance. This presentation describes the mechanism of stray inductance and its impacts on
power devices in switching circuit. Taking examples on the ETS-88TH test system, the method of stray
inductance evaluation is introduced by describing how to measure the stray inductance of the ESU-
1200 instrument and internal device inductance. Using an RC Snubber for dealing with stray inductance
is also explained. Finally stray inductance down to 20nH to the device without a Snubber demonstrates
excellent low stray inductance performance of the ETS-88TH test system.

60.GaN Power Transistor Test Solution, ETS88/88TH GaN

Gallium Nitride (GaN) power transistors have excellent electrical characteristics: high switching speed,
high breakdown voltage, low conduction resistance and low switching losses. More and more GaN
power devices are in mass production for a variety of power circuit instead of silicon power MOSFET’s.
However, there are still many technical difficulties in GaN power transistors manufacturing. Some
defects lead to device failure and need to be screened out in production through effective testing. An
example is the dynamic on-resistance effect (or current collapse). When the device is in the off state
with the reverse bias voltage applied to the drain source, the on-resistance of the GaN power transistor
increases as the voltage increases. This presentation will introduce two common normally-off GaN
power transistors: Cascode and E-mode, and the differences comparing with traditional silicon power
transistor parameters and tests, dynamic on-resistance test requirements and challenges and Teradyne
ETS88TM test solution, show some different devices dynamic on-resistance test plot under different
stress. The test results show Teradyne ETS88TM tester with standard floating source and proprietary test
circuit can not only complete the fast test of dynamic on-resistance, but also can meet other production
test and characteristic analysis of GaN power transistor.

61. IGBT module reuse , ETS88/88TH IGBT and HPM

The concept of reuse in test applications involves the standardization of test techniques and application
circuitry for the power discrete market. This presentation will explore the application of reuse on the ETS
88TH test system for power modules and Discrete IGBT's for both AC and DC testing.

By reusing application code and specific circuit blocks or modules a number of advantages become
clear. The use of standard test code and circuitry greatly simplifies each successive application. Use of
common components and circuit modules across all applications enhances reliability with proven
circuitry. Additionally documentation outlining PCB layout techniques allows for high quality testing by
ensuring parasitic effects such as stray inductance and capacitance are well understood before the
design is implemented. All of these methods come together to reduce both application development cost
and time to market and improves test application robustness.
An overview of existing reuse capabilities deployed today on the ETS 88TH will be outlined. Finally, the
ongoing extraction of IP from future designs to increase reuse will be addressed.

64. UltraSerial60G Under Sampling Capture, UltraFLEX

The UltraSerial60G is a Teradyne ultra high-speed serial instrument extension enabling automated
testing of serial NRZ and PAM4 interfaces. It’s receive lanes has choice of capturing either NRZ or
analog data. A high pass filter is used in every receive lane to suppress noise from the sampler but the
high pass filter requires sample and hold output signals are not static for a duration greater than τ/10
(15 µs). This requirement asks for method other than what we usually adopted, the coherent sampling
when implementing under sampling capture. This presentation introduces a solution of under sampling
capture accord with the demands mentioned above.

66. Automated Spike Checking for the ETS-800, ETS800

For many customers, spike checking a test program is a necessary, but time-consuming task required
during release to production. Brute force searching for spikes on an oscilloscope is labor intensive, and
must be repeated for every pin of the device. Automating this process can accelerate time to market,
and increase the quality of test. Utilizing appropriate bench test equipment, captures can be taken and
stored for each pin of a device. Through post processing, spike locations are found throughout a test
function. The timing information from scope captures can be aligned to sections of code in the test
program using the ETS MST Timelines profiling tool. By using Timelines, spikes can be quickly found
and debugged by test engineers. This presentation walks through the process using the ETS-800. It
discusses setup of instrumentation and demonstrates the interface with Timelines.

67. Real Time Correlation with ETS-800, ETS800

The correlation phase of test program development and release is often a time consuming process.
Debugging correlation mismatches often occurs several times during the development of a program and
during revision changes after release. One of the challenges around correlation is that seemingly minor
changes to a test program may cause issues later in the test flow, and these issues may not be detected
until a full study is done with post-processing of data via 3rd party tools. If correlation mismatches can be
detected in real time while still on the tester, it can prevent the need for additional unplanned debugging
sessions. This presentation will describe a method for detecting correlation failures in real time on the
ETS-800 tester platform.

68. Using TEMS and Kibana Suite Software, TEMS

The industry now uses an increasing number of software tools generating very large quantities of data.
TEMS is one example of an industry standard whose associated tools can report overwhelming sets of
information. The challenge thus becomes how to efficiently store, analyze, and display the data.

This presentation will describe the information gathered and generated by TEMS and the architecture
we put in place in order to monitor Teradyne testers activity. Big data manipulation can be achieved
using the Kibana suite. Kibana is a powerful visualization tool which can be used to solve our problem.
The objective of this presentation will be to demonstrate how it is possible to start from low-level,
unreadable, network json packet and finally provide useful charts, timeline graph for optimizing tester
usage as well as real-time tester state display.

73. Device testing of a 28GHz 5G Half-Duplex TRX 2x2 Phased-Array IC, UltraFLEX
The commercialization of silicon-based phased array antennas for the 5G frequency band has created
an immediate need for ATE millimeter wave production testing. The focus of this presentation is to
review the current production needs required for 5G millimeter wave ATE testing, as well as review the
application of a new Teradyne UltraFLEX mmWave capability on the target production device.

A 28GHz 5G half-duplex TRX 2x2 phased-array IC was chosen for the application, a complete
UltraFLEX IG-XL based test program was developed to measure all functional parameters associated
with the target device. The core of the presentation will review all measurements obtained using the
new mmWave capability as well as a review of hardware strategies and lessons learned used on the
project.

74. DevOps for test engineering, Test Engineering Development

The increased complexity of the new devices (SoC, PMIC, audio, etc.) pushes the complexity of the test
program source code to increase. A set of software development practices to support this demand is
widely used in the software industry (embedded development). Adopting similar flows and practices for
test program development helped to improve the quality of the developed software and reduces the risk
of fail.

This presentation covers the construction of an "end-to-end" system that does development, build, SCA,
delivery of a Test program, with strict product (software) quality gates in a fully automated environment.
As a future task, this automated system will provide the functionality of creating task tickets in the error
management system right from the automated build results that will highlight all the failures without any
manual intervention.

75. Library based modular TP development, Test Engineering Development

The increase of device complexity and the aggressive requirement for shorter development times is
forcing test engineering teams to be more innovative to increase the reuse level of the test program
source code. One of the possibilities to achieve this and reduce the development time is to provide
libraries which can be adjusted to the different project types.

This presentation will illustrate in a very abstract view some of the implemented techniques, which
helped to achieve a highly reusable and scalable library:

• High compliance to ISO software quality standards for achieving high maintainability, reliability -
and efficiency of the test program
• High testing performance (test-time, MSE and stability) by usage of POP
• Provide an abstraction layer for the Teradyne POP capabilities (Pattern generation and support
of the analog instruments DCVI, DCDiffMeter, DSSC Src and Cap)
• Centralized implementation and management of company standards

76. mmWave noise figure test solution, UltraFLEX

New mmWave test capability extends the capability of the UltraWave family of microwave instruments
on UltraFLEX. This extension expands the capabilities of the UltraWave24 instruments to test 5G
cellular device operating in the frequency range from 6GHz to 44GHz. This presentation will describe
the capability and the application to noise figure testing.

78. 5G mmWave test concept, UltraFLEX

This presentation introduces PHY to millimeter wave 5G, which is currently in the preparation stage for
commercialization and the method of trouble shooting accordingly. This presentation introduces broad
band signal integrity, hardware preparation and test items.

79. Addressing Growing Scan Volume for AI Devices with ATE, UltraFLEX

The fifth wave of computing, Deep Learning and AI devices for training and inference are driving an
increased interest in scan depth, scan speed and compression. These device specifiers are focused on
innovative device architectures and time to market, while minimizing effort on DFT and test economics.
As a result, we are seeing increased demands for greater than Giga-Vector scan depth per pin, with a
growth rate of 30% per generation. The UltraFLEX's UltraPin1600+ digital instrument has been designed
with width, depth, and speed for testing parts that require over 4GV of scan cycles, enabling the testing
of the next generation of AI devices.

81. Enhanced Device Clocking with MCG and New Free Running Clock Features on the New
Digital Instrument, UltraFLEX

This presentation will describe two powerful features for creating device clock signals on a new digital
instrument: the enhanced MultiClock Generation (MCG) and the new Free Running Clock
(FRC). Feature details and differences to previous generation instruments will be explained, along with
examples of use in device applications.

82. nWire PA Flag and Hold Bit Action TTR Best Practice

In traditional SPI bus application cases, it’s simpler to control the data timing and there seems nothing
too much to do but increase data rate to reduce test time. However, in situation of ESPI which contains
multiple DIO pins, the issue of synchronization comes with opportunity of test time reduction by parallel
data transition.

A project with ESPI bus, as an example, will be raised to illustrate how PA flag and hold bit action work
to reduce test time. Through hold bit action, the tester could capture valid data from DUT by
automatically matching sync bit rather than wait for fix number of cycles. Using PA flag could cater the
need of running PA modules which contain different PA ports as well. Finally, some practical skills of PA
will be shared

84. Implementation of the walking strobe feature to achieve frequency measurements with low
PPM rates for the UP1600 instrument in the UltraFLEX system UltraFLEX

Every digital electronic device requires a reference clock and oscillators are widely used to serve that
purpose. High-reliability MEMS oscillators used in automotive, medical and aerospace applications are
designed to solve unique timing problems; which brings new challenges for testing such as dynamic
stability, better resolution, accurate frequency measurement and less test time.

A particular application required UltraFLEX validation for the frequency measurements to meet their
standards. This presentation will show how to setup the walking strobe feature in the UP1600
instrument to achieve low PPM rates, as well as provide a comparison with the frequency counter
technique.

86. An Introduction to mmWAVE Test Capability, UltraFLEX

With all of the major wireless carriers working to upgrade their services to provide 5G network capability,
device manufacturers are already in the process to release and ramp their latest 5G components. To
help fulfill the promises of 5G, all of these new devices will require testing.

Testing 5G New Radio devices brings many new test challenges including, but not limited to:
Frequency Range: 24000 MHz ~ 44000 MHz
Modulation Bandwidth: Up to 100 MHz for carriers below 6 GHz and 400 MHz for carriers above 24 GHz
Millimeter Wave Ports: Per device port counts reaching up to and beyond 30. The typical 5G millimeter
wave device test list contains the following tests: Gain, IP3, EVM, ACPR and Phase Measurements.

This presentation provides an introduction to how the testing challenges of 5G can be addressed.

87. 5G mmWave DIB Design, UltraFLEX

As technology and testing evolves to cover 5G devices at millimeter wave (mmWave) frequencies, new
ATE DIB design challenges arise when transmitting these frequencies through the PCB. At mmWave
frequencies, wavelengths approximately between 1mm and 10mm, the transmission line dimensions of
significance become much smaller. Small discontinuities cause measureable influences along the signal
delivery path.
This presentation will review some of the characteristics of particular concern and some of the trade-offs
that may be necessary for mmWave DIB designs. These will include dielectric constant, dissipation
factor, dielectric thicknesses, metal surface smoothness and glass weave/trace angle. Other topics
reviewed:

• Grounded co-planar waveguide and

• Stripline traces with vias on the DIB
• Connector launch considerations and the associated trade-offs
• Common circuit topologies such as balun, Wilkinson power divider, DC block

88. Device Personalization at High Site Counts without impacting wafer test times, UltraFLEX

High density instruments today can easily support testing beyond 10,000 sites,
which is required for testing SmartCard Devices. One requirement of these secure Chip Cards is the
programming of encrypted customer data into each site. Since each device has its own encryption key,
the amount of data that needs to be uploaded at each touch down is getting a major impact of the wafer
test times. While 10kBytes of data at 4k sites are still only 41Mbytes of data, 2Mbytes at 10k sites end
up to be 20Gbytes of site unique data. It is clear that the classic pattern vector modify will not be able to
patch this data in a reasonable time. This presentation will show a feature called Personalization, which
uses the high speed upload to the tester in a way it will not impact the wafer test time. It will provide
some background of the implementation and also show a comparison to the classic method.

89. PortBridge - Bridging the ATE and Debug Tool Gap, UltraFLEX

PortBridge software enables designers and test engineers to work seamlessly together to debug their
chips at a high level of device abstraction. Especially in the age of increasing IP complexity, enabling
design tools to control the tester elevates and significantly speeds debug of IP which could not be
previously achieved through the lower level access typical of traditional test patterns. These tools have
knowledge of the chip architecture and were involved in the initial development and simulation of the
device. Other tools can assist in debugging code executing on the processor cores. Collaborating with
test engineers, designers with no ATE experience can now launch their native tools for a remote device
debug session anywhere in the world. The PortBridge software provides the communication and
translation between tools and Teradyne ATE.

90. ETS-88TH AC & DC Dual Sector Test for High Power Discrete, ETS88TH
In high-power discrete devices for automotive not only DC test but also AC (dynamic) test are applied,
because of high quality. Conventionally DC and AC tests are done on one socket sequentially.
The Eagle test systems have the floating-resource architecture that enables sector-sector isolation and
provides AC/DC dual-sector test environment. We could provide COT reduction. One big concern is that
high power discrete devices requires much high voltage/high current, which might cause any
interferences between sectors. We evaluated these interferences in high voltage/high current pulse AC
test, so that some limited time duration noises were observed. The noise duration was only about 500
uS. That means that there is no interference if this noise duration would be avoided.

We employed "SyncStation" utility, that enables an AC sector execution synchronizing a DC sector

execution, in Denso’s new generation IGBT module test program. With avoiding any interferences, AC
and DC dual sector test was achieved. Also times waiting for each stage handshake were optimized.
This will provide lower COT to the customer.

92. VSM Bulk Capacitance Alternatives, UltraFLEX

As device power goes to the hundreds of amps, supply ganging and the multiplying effect of the bulk
capacitors has become more space consuming on the DIB. Currently the VSM recommends 1000uF per
81A channels, using 10uF max value capacitors. This means 100 caps per channel, or 1000 caps per
site for an 800A device.

Several alternatives were tested and evaluated for droop and ESL spike performance. Physically smaller
capacitors, larger value capacitors, and mixes of 10uF and 100uF capacitors were tried. Results of
these experiments reinforce the need for massive parallelism to minimize the effective series resistance
and inductance between the capacitors and the device, and their effect on the device’s power. Some
general DIB layout considerations are discussed.

93. Using Kelvin Resistors on DIB, ETS-800

Trends in test are leading to ever-increasing quality. Customers are looking to reach single digit PPM
levels. This puts extra pressure on test engineers to design reliable test programs that do not
accidentally pass bad DUTs. This presentation will highlight a common practice of using resistors to
connect Force and Sense together on the DIB to prevent Kelvin Run-away conditions and why this
practice can lead to passing bad DUT’s and failing good DUT’s. Passing bad DUT’s is a quality escape
while failing good DUT’s leaves money on the table. This presentation will shed light on best practices
for using Kelvin Resistors on the DIB.

94. Introducing a New Paradigm in Connectivity will Save Time to Market, ETS-800
With the introduction of the ETS-800 introducing the Adaptive Pin Expansion (APEx) high site counts on
complex System on a Chip (SOC) devices has reached new heights. The APEx architecture has taken
what would normally be hardware designed on the DIB to expand site count and brought that into the
tester. In addition to expanding site counts, it has greatly simplified DIB designs. The down side to this is
that it has placed a larger onus on users to be more careful in their programs to avoid Hot Switching the
APEx relays. Teradyne has re-designed the APEx architecture from using all mechanical relays to a new
Hybrid Relay Module (HRM) architecture using Solid State Photo MOS switches to replace mechanical
relays in key places. In conjunction with the HRM, the system utilizes what is called the Automatic
Sequence Engine and placed all care of Hot Switch avoidance in the test system. The system now
manages hardware and software such that the user can now connect the core test instruments to any
live DUT voltage without risk of Hot Switching. Now the user can spend more time focusing on
debugging the test program without worry of the tester. This presentation will show how the HRM sets a
new paradigm in tester connectivity.

95. Closed Loop DC-DC converter testing in production, ETS-800

Quality of test requirements to reach lower PPM levels is driving more and more closed loop functional
testing of DC-DC converters prior to shipment. Test engineers no longer have the luxury of testing with
just open loop or test modes. Understanding the impediments to closed loop DC-DC converter testing is
imperative to getting the best performance for higher yields. This presentation will show best practices
for closed loop functional DC-DC converter testing.

97. Over the air test consideration and methodology, UltraFLEX

This presentation is about understanding the most difficult OTA test to implement among millimeter
wave tests, the signal transmission characteristics and the test bed construction. It also includes a
description of the optimal test environment implementation and how to do it.

98. Tool to Generate ETS-800 Pin Map from Spreadsheet Based Resource Assignment Sheet

The APex architecture of the ETS-800 allows test engineers to test complex, high pin count, SOC
devices with a small number of SPU-2112 and APU-32 resources. In order to ensure that they have full
test coverage, many engineers use a spreadsheet to visualize their resource assignments to their DUT
pins as well as to visualize APex connections of instruments such as the SPU-2112 and APU-32 to the
UPU-64 Busses, APU-32 Busses, SPMB Mux, and MCMUX. Once this task is completed, the engineer
then must enter the resource assignments to the Pin Map File (PMF) using the Pin Map Editor (PME).
Additionally, with the introduction of the Safe Connect Analyzer (SCA) and the Connections Editor in the
PME, the user must then also use the Connections Editor to add the Connections to the PMF. Teradyne
has developed a tool that will generate an Excel spreadsheet template based on the engineers
config.ets. The engineer then enters the resource assignments and APex connections into this
spreadsheet template. Then the tool automatically generates a PMF including the Connections. This will
help to reduce time to market, as well as help ensure that the Connections are entered accurately and
completely.

100. Thinking Beyond Binary Search – An Innovative Approach in Testing Overcurrent Protection
Trip Point in Class-D Audio Device
Overcurrent protection circuit is a mandatory requirement in any device that operates in the mid-power
range or higher. The conventional way of testing the trip point of this circuit usually employs the binary
search method. However, in audio devices with a reasonably higher current load, this method will constrain
the tester resources due to repeated overcurrent sourcing. Furthermore, as overcurrent protection trips,
the device-under-test shuts down and needs to power-up in each iteration thus increasing the test time
drastically.
With these challenges in mind, the authors have developed a method that involves only a single iteration
to save test time while providing a set-up that allows a more efficient utilization of tester resources.