Mentor Graphics ICStudio

Schematic Simulation Tutorial

VLSI EE IITK
 Table of Contents
Contents Slide No.
Schematic Simulation Tutorial 3

Appendix I (Information on simulation configuration) 120

Appendix II (Important points to remember) 122

Appendix III (Frequently faced problems) 127

Appendix IV (Understanding netlist and command file) 163

Appendix V (Plotting current, power and energy) 174

Appendix VI (Not able to edit the circuit) 186

Appendix VII (Too many logins) 191

To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)

Shows already saved

sessions in
MobaXterm. Double
click
vs5.vlsi.iitk.ac.in.
(Will be available MobaXterm window on opening.
only if you had
already saved.)
 To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)

If v5.vlsi.iitk.ac.in is not seen here, click Session, first option in Toolbar.

• “Session Settings” window opens. Click SSH option on the window.
• Type vs5.vlsi.iitk.ac.in in “Remote host” field.
• Tick the “Specify user name” checkbox and provide the username
(CC login id) in the corresponding field, and press OK.
To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)

Select SSH
To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)
To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)
 To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)

• Type the password and press enter.

• While typing password, you will not see anything typed on the screen.
However, without making mistake, just type the password and press enter.
To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)

• Select Yes/No depending upon your wish.

To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method I)

• Log in is complete. Can continue with steps in slide 14.

To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method II)

• Select plus button.

 To Start Mentor Graphics - From Your Personal
Computer in MobaXterm (Method II)

• Type “ssh -X <cc_login_id>@vs5.vlsi.iitk.ac.in” and press enter.

• Provide the password and enter. (While typing password, you will
not see anything typed on the screen. However, type the password
without making mistake.) Continue the steps from slide 14.
To Start Mentor Graphics - From Workstations
in VLSI Lab.

right click on desktop

click on open terminal
 To Start Mentor Graphics

csh
mkdir ~/mentor_designs

last command Required only for first time

 To use Mentor Graphics
csh
cd mentor_designs
source /cad/Mentor_tools/ICFlow/2008.csh
icstudio&
 Mentor Graphics icstudio GUI will open

initially the screen will look like

• Click on File
• Then New
• Then Project
• You will get following window
02
• Press Next button to continue
• Give appropriate name to your project
03
• Again press the Next button
• Now press ‘Open Library List Editor...’ button
04
• Then click ‘Edit Menu’ button
• Select ‘Add MGC Design Kit...’option
• There select ‘/cad/Mentor_tools/ADK_3.1’
Then a row named ‘MGC_DESIGN_KIT’ will be
added to the entries
• Now again press ‘Edit Menu’ button
• Then select ‘Add Standard MGC Libraries’ then
more 5 libraries would be added to entries
• Now press ‘New Row’ button thrice to add3
new rows & fill them as follows
• (you can add rows by browsing appropriate
location upto ‘mgc_icstd_lib’ & then write
name of perticular library)

MGC_IC_COMMLIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_commlib
MGC_IC_COMMLIB_QS /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_comm_qs
MGC_IC_COMMLIB_RF /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_comm_rf
There must be 9 entries asfollows
MGC_DESIGN_KIT /cad/Mentor_tools/ADK_3.1
MGC_IC_GENERIC_LIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/generic_lib
MGC_IC_DEVICE_LIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/device_lib
MGC_IC_SOURCES_LIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/sources_lib
MGC_IC_VERILOG_LIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_verilog
MGC_MACROLIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_macrolib
MGC_IC_COMMLIB /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_commlib
MGC_IC_COMMLIB_QS /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_comm_qs
MGC_IC_COMMLIB_RF /cad/Mentor_tools/ICFlow/2008.2o/2008.2o_linux_x86_64
/icflow_home/mgc_icstd_lib/mgc_ic_comm_rf
Press OK
 Press ‘Next’
Press ‘Open Settings Editor’
There you must fill the entries asfollows
Process File /cad/Mentor_tools/ADK_3.1/technology/ic/process/tsmc018

DRCRules File /cad/Mentor_tools/ADK_3.1/technology/ic/process/tsmc018.rules

LVSFile /cad/Mentor_tools/ADK_3.1/technology/ic/process/tsmc018.calibre.rules

PEXRules Files /cad/Mentor_tools/ADK_3.1/technology/ic/process/tsmc018.calibre.rules

*Leave ‘SDLrules file’ entry empty

• Press ‘OK’
• Then ‘Next’
• Then ‘Finish’
• Now including the libraries isover
• our screen will look like...
• Now we can built the circuit
• To do this we have to create newLibrary
• Right click within Library space & selectNew
Library
• Give appropriate name to the library & press
OK
• Select the created Library
• Right click within the Cellarea
• Select ‘New Cell View’
• Enter Appropriate cell name
• Tobuilt the circuit, select View Typeas
‘Schematic’
• View Name would automatically become
‘Schematic’
• Press ‘Finish’
• Toplace devices select ‘Library’ on sidepanel
• Then ‘Device Lib’
• Let us put 4-pin NMOS
• Now select the device and do one of the two.
• Right click over the device & click over word
‘Properties’ but not onarrow in front. Or
• Press ‘q’ on the keyboard. (Ensure caps lock is
off.)
• Select the entry ASIM_MODEL & changethe value NCH
to N
• Click apply
• As per requirement we can also modify other attributes
of NMOS like W, Letc.
• W>=270nm, L>=180nm
• We keep W=450nm, L=180nm
• Finally press ‘OK’
• Similarly place other devices like PMOS
• Also through its properties makeits
‘ASIM_MODEL’ as Pfrom PCH
• Place VDD, GND etc through Generic Lib inside
libraries on side panel
• Various sources can be placed through
Sources Lib
• The value of the source can be modified by
selecting it and done of the two.
• Right click on the source and click on
word ‘properties' (not on the arrow). Or
• Press ‘q’ on the keyboard. (Ensure
caps lock is off.)
• The small branch at the side of circuit isto
define VDD
 V1 is the name of voltage source

While giving value, ensure that there is no space

between number and unit .(i.e., 1.8V and not 1.8 V)
• Press ‘w’ to place the wire (Ensure caps
lock is off)
• Make appropriate connections.
• After making appropriate connections,
press ‘Esc’ on keyboard.
• Now we have to add ports
• Ports are of 3 types- portin, portout, portbi
• through ports only we can vary or sweepthe
signal
• Ports list available on left sidebar
• Place portin wherever we need to applyinput
signal
• Place portout wherever we need to take
output
• By default name of each port is NET
• Tochange the name of the port select the
port and press ‘q’ on the keyboard.
(Ensure caps lock is off.)
• Give appropriate name to the port at the
value field.
• Now our circuit is ready for simulation
 SIMULATION
• Click Simulation on right side panel.
 If you see this
If you now see the above window (not what you see in the next slide),
skip the next 3 slides and continue (from slide no. 70).
If you see this “Entering simulation mode” window.

If you see like this, continue to the next slide.

 • Press New Configuration
• Select AMS_Simulation,
provide a name in
“Configuration name” field &
press OK.
• Press OK

• The steps given above in this and next slide

might not necessarily be followed all the time.
• More explanation on this is given in the
Appendix - I at the end of this document.
Configuration name provided
 Including Library (Model)

• Library/model that defines the working of devices

such as MOSFETs has to defined.
• Can be done in two ways.
• Both methods are given in the following slides.
• Only one of the two methods must be followed.
• Method I is preferred.
 Including Library (Model) – Method I

• For this select Lib/Temp/Inc

• Select include files in the dropdown list
• Browse & select model file at the location
$MGC_DESIGN_KIT/technology/ic/models/tsmc018.mod
• Press OK

Must not be followed if steps in method II is

already followed.
Including Library (Model) – Method I

Must not be followed if steps in method II is

already followed.
Including Library (Model) – Method I

Must not be followed if steps in method II is

already followed.
Including Library (Model) – Method I

Must not be followed if steps in method II is

already followed.
 Including Library (Model) – Method I

Select this and

press OK.

Whatever present in this field should be replaced with this text and
press Enter. Continue following steps from slide 80.

Must not be followed if steps in method II is

already followed.
Including Library (Model) – Method II

• For this select ADK Sim Palette on right

sidebar
• Browse and select model file at the location
$MGC_DESIGN_KIT/technology/ic/models/tsmc018.mod
• Press OK
• Again press Default Sim Palette

Must not be followed if steps in method I is

already followed.
 Including Library (Model) – Method II

Must not be followed if steps in method I is already followed.

 Including Library (Model) – Method II

Must not be followed if steps in method I is already followed.

 Including Library (Model) – Method II

Select this and

press OK.

Whatever present in this field should be replaced with this text and
press Enter.
Must not be followed if steps in method I is already followed.
• Now we have to Force the Input ports
• Forcing means applying appropriate input
signal to input port
• Select ‘Forces’ from right sidebar & click
manager
• Now select the name of port which you want
to force i.e. the ports to which we are applying
input signals & select appropriate input signal
• set its attributes
Type the name of
port here

After typing the

name of port,
press button next
to it, to search for
port.
Name of port

Ports found after

pressing button.
Select the port.
• After correctly setting the appropriate
attributes of the signal add thesignal to
Forces list by pressing add button
Select the type of force
(voltage/current) Press button to add
the force

Provide
appropriate
waveform
Ensure that reference node is
set to GROUND, not GND,
before adding force.
Force added
• Force will appear as...
• Now we have to set nature of analysis likeAC,
DC, Transientetc
• Click ‘Analyses...’ on right sidebar & select
appropriate one
• Then click on setup to enter detail ofanalysis
• Finally click ‘OK’
• For transient simulation we always put
starting time as0
• Keep Stop time as per the requrements
• Max time step should be kept as low as
possible to get higher accuracy but thisleads
to more simulation time
• Now before simulating we should store our
input & output signals
• Select Setup, the Outputs
• Add all input & output signals to the list by
clicking add button
• Now we can initiate simulation
• Toinitiate the simulation press button ‘Run
ELDO’
• Toview waveforms select arrow on the side of
“View Waves" & click on “Reload”
• Select correct analysis type & appropriate
signals
• Can change color scheme for waveforms
• Monochrome
 • White Background

For change of line colour, line width, etc., double click the waveform name.
• On double clicking V(VIN) waveform name.
After change of line width and/or line color of the 2
waveforms.
• We can also put grids & cursor formeasurements
• Right click on the plot in the waveform window (on the empty
portion) and select
• “Grid Lines”
• “Add cursor”
With grid on one of the waveforms, and with a cursor
added.
 DCAnalysis
• For DCanalysis select DCfrom Analyses...
• Click on setup
• During DCanalysis we can sweep any voltage
signal between two values with propervoltage
steps
• In shown example input voltage of the
inverter has been swept from 0V to 1.8V & we
got the proper output.
• Note: You have to select the voltage
source from the drop down list in the
source tab, rather than type the name.
• Here, V1 (Name of the voltage source) refers to supply voltage, VDD.
• V1 name can be verified if you check the properties of voltage
source (refer back to slide 57).
• VFORCE_VIN refers to the input force applied.
• Similarly simulate the circuit using ‘RunELDO’
& observe the waveforms appropriately
• ACanalysis basically provides the frequency
response of the circuit
• For ACanalysis we have to force the input
signal as sinusoidal signal of appropriate
magnitude
AC magnitude should be small signal, say 1mV.
DC magnitude is the bias.
• Then we have to set the analysis asAC
• While setup we need to specify start &stop
frequency
• Also we need to specify input port (where
signal freq is varied) & output portwhere we
saw the effect
• Similarly results are seen through View Waves
• db(Vout)=20*log(Vout,dc_magnitude)
• cphase(Vout) implies phase of output signal wrt input.
• Phase of output is 1800. It is correct, as Vout decreases with increase in Vin.
Input and output of inverters are out of phase as expected.
• With increase in frequency, due to input-output coupling capacitance, phase
and gain decreases as expected.
• db(Vin)=-60 because dc magnitude of Vin provided was 0.001. (20log(0.001)=-60)
Calculating gain using waveform calculator

Waveform calculator
Calculating gain using waveform calculator

• Select Vout signal from left hand side of waveform viewer (EZwave)
• Right click the signal and select “Copy Waveform Name(s)”.
Calculating gain using waveform calculator

• In the waveform calculator, right click and select paste.

Calculating gain using waveform calculator

• To find gain, we have to divide Vout by Vin. So click divided by

symbol, and, like Vout, paste waveform name of Vin.
• Then select Eval.
Calculating gain using waveform calculator

• Calculated gain and phase.

• Can do any waveform calculations using the waveform
calculator.
• Tofinish the simulation press End Simbutton
• Save your work
• Close the icstudio
• Then type exit in the terminal & press enter
• Again type exit & pressenter
Appendix- I
 Simulation – On Pressing Simulation Button
• In the “Existing Configurations”
section, already saved simulation
setups are shown.
• In this case, “tsmc018a” is a
saved configuration.
• Saved configuration means the
waveforms to be provided to the
inputs, the analysis to be done,
waveforms to be plotted, library
• If you want to start a new to be added, etc., whatever done
setup, follow the steps in in the past under this
slides 67-69. configuration in this simulation
• Above window may not turn setup is already saved.
up if you are doing the first • You may select one of the saved
simulation, as there are no configurations, if you again want
saved configurations. (The to do the same simulation.
case in slide 66)
Appendix- II
 Points to Remember
• Channel length, L, of transistor
>=180nm VDD
• Width, W, of transistor >=270nm
• VDD – VSS <=1.8V Circuit
– If VDD = 1.8V, VSS >=0V
– If VDD = 0.9V, VSS >=-0.9V
• Input voltages should also be VSS
within the range [VSS, VDD].
 Points to Remember
• Do not use circuits that have L
inductors.
– tsmc018 technology we are using
does not have inductors.
• In general, in a circuit, if
connection of body of a MOSFET
is not explicitly shown,
– Body of NMOS is connected to VDD
ground (VSS).
– Body of PMOS is connected to VDD.
 Points to Remember
• Technology we are using (tsmc018) uses N-well process
– ie., PMOS is made on an N-well, while NMOS is directly made on
the p-substrate (no p-well).
– No p-well implies body of all NMOS transistors are shorted
together.
• Therefore body of NMOS transistors cannot be connected to different
potentials.
– Body of all PMOS transistors made on single n-well are
connected together.
• If bodies of PMOS transistors have to be connected to different
potentials, PMOS transistors have to be made in different n-wells.

Ref: https://www.edgefx.in/understanding-cmos-fabrication-technology/
 Points to Remember
• Do not use circuits that
require input to be applied on A
body of NMOS transistors
(reason mentioned in
previous slide). B
• Inputs can be applied on
body of PMOS transistors.
Cannot be drawn in
– Those transistors have to be
made in separate n-wells. layout with tsmc018
technology
as body of NMOS transistors cannot be
applied different potentials (in this case
different inputs A and B).
Appendix- III
 Prob. I

If the palette at the side of the window is missing (shown

in next slide).
 Prob. I

Palette at the side of the window missing.

 Prob. I - Solution

Setup -> Windows -> Palette Area.

 Prob. I - Solution

Problem solved. Side palette returned.

 Prob. II

Similar to prob. I. Side palette is missing (shown in next

slide) during simulation configuration.
 Prob. II

Palette at the side of the window missing.

 Prob. II - Solution

Setup -> Windows -> Palette Area. (Solution is same as

that of prob. I)
 Prob. II - Solution

Problem solved. Side palette returned.

Prob. III – Troubleshooting Wrong Output
in Circuit Simulation

Simulated Circuit. On GUI, the circuit looks perfect.

Prob. III – Troubleshooting Wrong Output
in Circuit Simulation

Input and Output Waveforms on simulation. Output waveform

(bottom waveform) is not inverted. Therefore wrong output.
Prob. III – Troubleshooting

View -> Simulation Log File.

 Prob. III – Troubleshooting

1 Warning

Simulation log file should be observed after every simulation. Ideally,

there should not be any warnings or errors. If warnings are present,
simulation output will be provided (need not be correct). If errors are
present, simulations are aborted.
 Prob. III – Troubleshooting

• Go back to the circuit.

• View -> Netlist File.
Prob. III – Troubleshooting
 Prob. III – Troubleshooting

• Go back to the circuit.

• View -> Command File.
 Prob. III – Troubleshooting

• Now we have to troubleshoot using both command

file and the netlist file.
 Prob. III – Troubleshooting
• Command file and netlist files are written based on
the syntax of Mentor Graphics Eldo circuit
simulator.
• ICStudio tool generates these files based on the
circuit drawn and based on the forces provided.
• Circuit simulator simulates the circuit based on
these command and netlist files.
• Syntax is mostly same as SPICE syntax.
• Troubleshooting of these command and netlist files
are provided in Appendix IV (Slide 163) (brief
explanation on understanding SPICE commands is
provided in this appendix).
 Prob. III – Solution (Method I)

• Force 0V dc to GROUND, as well, wrt. GND

Prob. III – Solution (Method I)
 Prob. III – Solution (Method I)

• Simulation Log file. No errors or warnings.

 Prob. III – Solution (Method I)

• Simulation results.
• Inverter output waveform (bottom waveform) is now
correct.
Prob. III – Solution (Method II) - Preferred

• Force VIN wrt. GROUND, not GND.

• We should choose GROUND in Reference field.
Prob. III – Solution (Method II) - Preferred
Prob. III – Solution (Method II) - Preferred

• Simulation Log file. No errors or warnings.

Prob. III – Solution (Method II) - Preferred

GROUND gets assigned

to 0V, instead of GND.

• Netlist file
• GND node is removed from the netlist.
Prob. III – Solution (Method II) - Preferred

GND node is replaced

with GROUND node

• Command file
• GND node is removed from both the netlist and
command file.
Prob. III – Solution (Method II) - Preferred

• Correct output waveforms

 Prob. IV

• Simulation Log File with an error.

 Prob. IV - troubleshooting

• There should not be space between 1.8 and V.

 Prob. IV - Solution

• End simulation, remove the space in the voltage

source properties, and then simulate.
Prob. V- Mismatch in analysis and forces
provided

• AC analysis. Simulation failed.

• Simulation log file shows two errors.
 Prob. V- Troubleshooting

Force provided is DC.

Analysis is AC.

• Command file.
• Analysis and atleast one of the input forces should be the
same.
• Therefore, if AC analysis is to be done, force provided to
Vin should be also AC (solution).
 Prob. V- Solution

• Provide AC force to input.

 Prob. V- Solution

• Ensure that the AC force is selected, not DC.

• In the above figure, DC force is selected.
 Prob. V- Solution

• Now AC force is selected.

• If DC or transient analysis is to be done, force provided
should not be AC.
• Force should be DC/pulse/….
Appendix- IV
Understanding Netlist and Command
Files’ Syntax
• Syntax of these files are that of Mentor Graphics Eldo
circuit simulator.
• However, many of the commands are same/similar to
SPICE syntax.
• Are easy to understand.
• Netlist File
• Describes the circuit (Excluding forces applied).
• Command File
• Main file
• Netlist File is included in this file.
• Describes the forces applied in the circuit.
• Libraries/models used.
• Analysis done, etc.
Understanding Netlist File Syntax
Reference node is defined.
GND node is connected to 0V.

Description of the circuit,

except for voltage sources.
Understanding Netlist File Syntax

• V1 is a voltage source.
• Line starts with V => voltage source.
• Next two nodes, VDD and GROUND are positive
and negative nodes, respectively of the voltage
source.
• After that waveform of voltage source is defined.
• In short, the line defines
• A DC voltage source of 1.8V, named V1, is
applied between terminals VDD and GROUND.
Understanding Netlist File Syntax

• M2 is a MOSFET.
• Line starts with M => MOSFET.
• Next four nodes, VOUT, VIN, VDD and VDD are
drain, gate, source and body nodes, respectively of
the MOSFET.
• P denotes that it is PMOS.
• After that, channel length (L) and channel
width(W) of the MOSFET is defined as 0.18u and
0.45u respectively.
Understanding Netlist File Syntax

• M1 is a MOSFET.
• Line starts with M => MOSFET.
• Next four nodes, VOUT, VIN, GROUND and
GROUND are drain, gate, source and body nodes,
respectively of the MOSFET.
• N denotes that it is NMOS.
• After that, channel length (L) and channel
width(W) of the MOSFET is defined as 0.18u and
0.45u respectively.
Understanding Netlist File Syntax
All the device
VDD VDD nodes are marked
in white text
according to the
Vin circuit netlist.
VDD
Vout Can verify
from this that
Vout the netlist
correctly
GROUND
represents the
Vin GROUND inverter
circuit.
GROUND
 Understanding Netlist File Syntax
Reference node is defined. GND node is
connected to 0V. It should have been GROUND.

GROUND node is not

assigned any voltage.

These three lines show that VIN is also not assigned any voltage.
the netlist do represent the However, it is assigned in command
circuit of the inverter. file (will see in the coming slides)
Understanding Command File Syntax

Netlist file is included in command

file with .INCLUDE statement

Voltage is applied as force between

VIN and GND nodes of type PULSE.

Analysis is done at a
Transient temperature of 27⁰C.
analysis from
0ns to 100ns
Understanding Command File Syntax

Waveforms that are to

be displayed: VIN and
“tsmc018.mod “
VOUT are provided in model file is included
.PROBE statement. with .LIB statement

Voltage source is defined between VIN and GND.

However, GND is not part of the circuit, as seen from the
netlist (GROUND is part of the circuit).
 Fixing the netlist/command file
• 2 methods of solving the problems in the
netlist/command files are discussed in Appendix III.
• Concept between the two methods is given below.
• Method I
• Node GROUND is also forced with 0V wrt. GND.
Thus GND and GROUND are shorted, and made
the nodes equivalent.
• Method II
• GND node is unnecessary.
• In the circuit, defined in netlist file, only
GROUND node is used.
• If Vin is also applied force wrt GROUND, instead
of GND, problem can be solved.
Appendix- V
Measuring Current, Energy and Power

• M2 is PMOS and M1 is NMOS.

• Supply voltage is V1.
• Current can be plotted for DC and transient simulation.
• Energy and power can be calculated only with transient simulation.
Measuring Current, Energy and Power

“Probe All Voltages” is selected

• Setup -> Outputs.

• Selecting “Probe all voltages” plots the voltages of all nodes in the
circuit. (Otherwise, plot whatever is required. VDD is required for
plotting total energy.)
Measuring Current, Energy and Power

Current flowing through M2 is updated.

Type
transistor
name M2
and add.

• “Probe all currents” can be selected to plot all the currents.

• Otherwise, we can choose what to plot
• Currents are plotted as the current flowing into a device.
Measuring Current, Energy and Power

V1 is the name of voltage source that

provides supply voltage.
Measuring Current, Energy and Power

Also has the option to choose power,

instead of current.
Measuring Current, Energy and Power

• Power dissipation is also plotted.

• Force should be a pulse, not DC, for energy/power calculation.

Measuring Current, Energy and Power

Current flowing
into source
terminal of M2
 Measuring Current, Energy and Power

Current flowing into

positive terminal of
voltage source V1

Current is negative as current is flowing out of voltage source, and not into the voltage source.
Measuring Current, Energy and Power

Instantaneous power
dissipation in M2, and at
voltage source V1.

Power dissipation is negative as current is flowing out of voltage source.

Power is delivered by the voltage source.
Measuring Current, Energy and Power
• Energy consumed= ∫(instantaneous_power)dt
• Negate the above if the energy delivered from time 0 till time t is required
• Use waveform calculator for integration.

• (Energy delivered by the supply voltage) / (Energy

consumed by the circuit) from time 0 till time t
Measuring Current, Energy and Power
Time period of the input clock

(Energy delivered by the

If input to inverter switches at a frequency supply voltage)/(Energy
of 10MHz, average power consumed by consumed by the circuit)
the inverter circuit = 27.20524fJ from time 0 till time t
Appendix- VI
Not able to work with the tool as editing is
disabled: Killing the process

Problem : Not able

to do any editing.
Shows waning in
“message area” (If
message area is not
visible, select Setup
-> Windows ->
Message Area

Written: “Warning: This operation not allowed in read-only mode.

Use $set_edit_mode() to enable edits/write.”
 Troubleshooting
• Most likely problem is that you already have one license
occupied.
• Might be open in the same computer.
• In different computer.
• Or you may have not previously released the license
properly.
• To release license properly, you have to close all the
windows of the tool. You should have closed ICStudio.
• You should not close the terminal/mobaXterm before
closing the tools.
• You should not lose net connection while you hold the
license.
• While holding the license, you should neither log out,
shut down or restart your computer, nor make it go to
sleep or hibernation.
 Solution
• Release one of the two licenses. If the problem is due to
previous improper release of license, follow the given below
steps.
• First close all the tool licenses you already have.
• In the terminal, type “ps –u <cc_login_id>” and press enter.
• Type “kill -9 <pids>” in the terminal and press enter.
• <pids>: You are supposed to provide all PID numbers
corresponding to the Mentor Graphics ICStudio tools
separated by spaces.
• If you are not sure, which pids are to be provided, better to use
the following command, which will kill all the licenses and
close all your logins. You should login again to use the tool.
• “pkill -kill -u <cc_login-id”
 Solution

• Only one of the last two commands need to be used. If last

command is used, you would have been logged out. So
should login again to use the tool.
Appendix- VII
 Unable to Login
• While trying to login, it says “too many logins for __”, and
therefore not able to login.
• A user is allowed to have maximum 3 sessions logged in at a
time.
• Problem happens when you are trying to login for the 4th
session.
• Solution:
• Logout all other sessions before new login.
• For logout,
• In Workstations in the VLSI lab, you have to type exit
and press enter in the command terminal until the
terminal window gets closed. Then logout from the
workstation.
• In MobaXterm, press exit and press enter until it shows
like given in screenshot in the next slide.
 Unable to Login

• If “too many logins” problem occurs, and you are unaware of

any extra logins, you might not have closed some previous
sessions incorrectly. You have to wait for approximately 10-15
minutes. By that time, the old logins would have been
automatically made to exit. Then you can login.
 Unable to Login
• Incorrect ways of session closing may happen due to the
following reasons.
• You should not lose net connection while you are
logged in. In the server point of view, you might be
holding the license.
• While logged in to the session, you should neither
log out, shut down or restart your computer, nor
make it go to sleep or hibernation.
• If any of the above things happen by mistake, to ensure
there are no logins,
• Log in to a new session, and type
“pkill –kill –u <cc_login_id>” in the terminal and
press enter. (Can refer to last slide in appendix VI, in
case of doubt on the use of command.)
Thanks...

Prepared byHIMANSHU(Y11)
Edited and Appended by DINESH(Y15)