Advanced Low-Power flow Using RC

Integrating CPF into the Flow

Product Version 12.1

July 31, 2013

Advanced Low-power techniques are becoming a routine affair while defining synthesis
methodology. It is important for designers to understand the intricacies of way to define the
power intent in RC. This guide covers the basics of CPF and some commonly used commands
while implementing a CPF based design in RC.
Copyright Statement

© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence
logo are registered trademarks of Cadence Design Systems, Inc. All others are the property of
their respective holders.

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Contents
Introduction .................................................................................................................. 4
Some Common Low Power Techniques...................................................................... 4
The Need for a Power Format ..................................................................................... 5
Understanding the CPF Format ................................................................................... 5
Design Objects ......................................................................................................... 5
Special Library Cells for Power Management .......................................................... 6
lCPF Objects ............................................................................................................ 6
Capturing Power Intent Using CPF .............................................................................. 8
Common CPF related RC commands ....................................................................... 11
check_cpf ............................................................................................................... 11
check_library .......................................................................................................... 12
commit_cpf ............................................................................................................. 12
write_cpf ................................................................................................................. 12
read_cpf ................................................................................................................. 13
Above command will return all the power-domains.................................................... 13
report level_shifter.................................................................................................. 13
report isolation........................................................................................................ 13
report power_domain ............................................................................................. 14
report state_retention ............................................................................................. 14
verify_power_structure ........................................................................................... 14
Power Intent Validation .............................................................................................. 15
Command to invoke CLP ....................................................................................... 15
Command Template for Logical Netlist Checking .................................................. 16
Command Template for Physical Netlist Checking ................................................ 16

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Introduction

The shift in the use of chips to consumer applications and the change in the latest process
technologies have made power one of the primary design criteria for a majority of the chips
worldwide. However, the industry’s design infrastructure has not evolved at the same pace. The
lack of support in the infrastructure for designs using advanced low power design techniques
has resulted in a gap between the design techniques needed to control power dissipation and
the ability of the design environment to support those techniques in a safe and efficient
manner.

Some Common Low Power Techniques

The extreme need for power savings dictate that apt consideration is provided to low-power
techniques at each stage of the design. In fact even the design architecture has to be such that
power consumed is minimal, without compromising on the features or functions of the device.
Few of the architecture level decisions available to designers are demonstrated in the diagram
below:

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The Need for a Power Format

Conventional design flows have failed to address the additional considerations for incorporating
advanced low-power techniques as talked above. Consequently, design teams often resorted to
methodologies that were ad hoc or highly inflexible. These methodologies required the
designer to manually model the impact of low-power during simulation, and provide multiple
definitions for the same information: one set for synthesis, one for placement, one for
verification, and yet another for equivalency checking.

Yet after all that manual work, the old flows had no way of guaranteeing consistency.
This posed a tremendous risk to the SoC as there was no way to be sure that what was verified
matched with what was implemented. This resulted in lower productivity, longer time to
market, increased risk of silicon failure, and inferior tradeoffs among performance, timing, and
power. The Common Power Format (CPF), approved by the Silicon Integration Initiative (Si2), is
a format for specifying power-saving techniques early in the design process, enabling designers
to share and reuse low-power intelligence.

Understanding the CPF Format

The CPF is a Tcl based file and in essence contains the power specification for design. This
implies that the functionality of the design does not change when sourcing a CPF file. The CPF
file complements the HDL description of the design and can be used throughout the design
creation, design implementation, and design verification flow. The CPF file contains two
categories of objects:

• Design Objects are objects those already exist in the description of the design.
• CPF Objects are objects that are created through the CPF file

Design Objects

Design objects are objects that are being named in the description of the design, which can be
in the form of RTL files or a netlist. Various design objects that can be referenced by the CPF
commands are shown below:

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Object Definition
Special Library Cells for Power Management

lCPF Objects

CPF objects are objects that are being defined (named) in the CPF constraint file. CPF objects
can be referenced by the CPF commands for building the power intent.

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Capturing Power Intent Using CPF

The power intent for any design can be effectively captured using the CPF. Now design tools
ensure that they support the low-power intent captured in the CPF commands. The RTL files are
not modified with the power intent and this ensures that the power intent is inherently
separate from design intent.

In this flow, the RTL files (design intent), CPF file (power intent) and SDC files (timing intent)
capture the full design requirements. In the past when designers had to change the RTL to
include low-power constructs, it precluded design reuse. Designers found they had to change
legacy code that was golden—and of course, if it were changed, it had to be verified again. And
if the same block were used in multiple places in the design, designers would have to copy and
modify the block for every power domain it was used in. This was a huge problem with the old
flow; and consequently, a huge benefit for the CPF-enabled flow.

Figure illustrates a circuit with multiple power domains and power shut-off.

The scope of the design for which CPF is intended is set by using the “set_design” command.
The CPF file for a hierarchical design can contain multiple set_design commands. The first
set_design command specifies the top module of the design, which is at the root of the design
hierarchy and is referred to as the top design. Subsequent set_design commands must each be

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preceded by a set_instance command, which specifies the name of a hierarchical instance in

the top design. For the design shown in the diagram following command can be used:

# Define the top domain

set_design TOP

The create_power_domain command creates a power domain and specifies the instances and
boundary ports and pins that belong to it. By default, an instance inherits the power domain
setting from its parent hierarchical instance or the design, unless that instance was associated
with a specific power domain. In addition, all top-level boundary ports are considered to belong
to the default power domain, unless they have been associated with a specific domain. Created
power domains are associated with the design objects based on the order of the logical
hierarchy. The order in which they are created is irrelevant. A default power domain must be
specified for the top design, identified by the first set_design command.

create_power_domain \
–name pdA \
–instances {uA uC}
–shutoff_condition {!uPCM/pso[0]}
# Define PDB – PSO when pso is low
create_power_domain
–name pdB \
–instances {uB} \
–shutoff_condition {!uPCM/pso[1]}

When a block is powered down, there is a need to isolate the outputs and drive it to the
appropriate value. This is done by the create_isolation_rule command in CPF. Some key control
flops need to be retained in a powered-down block. This is specified by the
create_retention_rule command.

## All outputs of Power-Domain pdB

# isolated high on rising edge of “iso”
set hiPin {uB/en1 uB/en2}
create_isolation_rule \
–name ir1 \
–from pdB \
–isolation_condition {uPCM/iso} \
–isolation_output high \
–pins $hiPin

The create_isolation_rule command defines a rule for adding isolation cells. Individual pins can
be selected to have an isolation value of high, low, or hold. Both input and output isolation can
be supported. A number of other conditions for isolation can be selected using an appropriate

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combination of the –to and –from options triggered by the control signal specified by the –
isolation_condition. Isolation behavior is virtually imposed by the simulator based on the
defined rules, without the need for isolation cells in the RTL. The isolation cells are then
inserted using the same rules during the synthesis phase.

# Define Level-Shifters in the

# “to” domain
create_level_shifter_rule –name lsr1 \
–to {pdB} –from {pdA}
create_level_shifter_rule –name lsr2 \
–to {pdA} –from {pdB}
create_level_shifter_rule –name lsr3 \
– to {pdTop} –from {pdB}
create_level_shifter_rule –name lsr4 \
–to {pdA} –from {pdTop}

The create_level_shifter_rule command defines rules for adding level shifters in the design:
The CPF for the state retention is as follows:

# Define State-Retention (SRPG)

# State stored on falling edge of
# restore[0] and restored on rising-edge
set srpgList {uB/reg1 uB/reg2}
create_state_retention_rule \
–name sr1 \
–restore_edge {uPCM/restore[0]} \
–instances $srpgList

The create_state_retention_rule command defines the rule for replacing selected registers or
all registers in the specified power domain with state retention registers, as shown above. The
store and restore behavior is triggered in simulation by the control signals from the power
controller, as specified in the –save and –restore expression. Note that if –save is not specified,
it is the logical NOT of the –restore signal.

The create_nominal_condition specifies a nominal operating condition with the specified

voltage. It is used to track the different voltage levels required by individual power modes.

The create_power_mode command is used to define all legal modes of operation in a design
such that each power mode represents a unique combination of operating voltage levels for
individual power domains. This is needed to support power saving schemes like dynamic
voltage and frequency scaling (DVFS). Note that at least one –default mode must be specified,
which represents the power mode at the initial state of the design.

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# First, define the conditions.

# Top is always high, pdA/pdB can be
# medium or low
create_nominal_condition –name high \
–voltage 1.2
create_nominal_condition –name medium \
–voltage 1.0
create_nominal_condition –name low \
–voltage 0.8
create_nominal_condition –name off \
–voltage 0
# Define the modes
create_power_mode –name PM1 \
–domain_conditions {pdTop@high \
pdA@medium pdB@medium}
create_power_mode –name PM2 \
–domain_conditions {pdTop@high \
pdA@low pdB@low}
# Mode where pdB is off
create_power_mode –name PM3 \
–domain_conditions {pdTop@high \
pdA@low pdB@off}
# Close the design (for completeness)
end_design

In order to make it easy for the user to write a cpf file, RC provides a command called
“write_template –cpf” which writes out a template cpf. This file can then be edited as per
power intent of the design to create a cpf file. Essentially it requires user to just fill in the blanks
to create a CPF file and greatly reduces the effort needed to create a power intent file.

Common CPF related RC commands

Following are few of the commonly used commands while using CPF based flow in RC. These
commands allow users to debug in case of any unexpected behavior.
check_cpf

check_cpf
[-isolation | -level_shifter | -retention | -all]
[-detail] [-continue_on_error]
[-debug] [-run_dir directory] [-license string] [> file]

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This command checks the validity of the CPF rules against the RTL of the design. This enables
designers to capture any violations of the low power intent of the design early in the cycle.

• If no low power rule check errors are detected, the command returns 1
• If rule check errors are detected, the command returns 0. In this case, you need to make
the necessary changes to your CPF file before proceeding further with synthesis.

check_library
check_library
[-isolation_cell] [-level_shifter_cell]
[-retention_cell]
[-library_domain library_domain_list]
[-libcell libcell_list]
[> file]

This command allows users to check specific information in the loaded libraries with regards to
level shifters, isolation cells and state retention cells. The report also lists the unusable cells.
The information returned can be fine tuned by combining several options. Without any options
specified, this command list the number of level shifters, isolation cells, and state retention
cells available in each of the library domains. If no library domains exist, the report lists the
library names instead.

commit_cpf
commit_cpf
[-level_shifter_only]
[-isolation_cell_only]
[-design design]

This command inserts level-shifter logic and isolation logic as requested based on the rules
specified in previously read in CPF file(s). If specified without any options, both level-shifter
logic and isolation logic are inserted.

write_cpf
write_cpf
[-design design]
[-separate_library_cpf | -use_library_cpf file]
[-no_sdc_update

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| [-write_sdc_options string] [-honor_cpf_sdc] ]

[-output_directory string]
[-prefix string] [-overwrite] [-to_macro]

This command writes out an updated CPF file or a CPF macro. The command returns the path to
the file with the design CPF information. The golden (original) CPF file references design objects
in the RTL or original netlist. During synthesis, changes to instance and pin names can occur.
The new CPF file contains the power intent of the golden CPF file but with updated references
to the design objects.

read_cpf
read_cpf [-library] [-design design]
[-read_sdc_options string...] file [file]...
This command reads the power intent for the design from the specified Common Power Format
(CPF) file(s). After this command one can see various power-intent object are created i.e.
power_domain, power_mode, isolation_rules, level_shifter_rules, state_retention_rules etc.
One can do find on the power-intent object i.e.

find / -power_domain *

Above command will return all the power-domains.

report level_shifter
report level_shifter
{ [instance_list]
| [-detail] [-hierarchical]
[-from_power_domain power_domain_list]
[-to_power_domain power_domain_list] }
[-verbose] [> file]

This command reports level-shifter information for the design. The return value of the report
corresponds to the number of leaf level-shifter instances found.

report isolation
{ [instance_list]
| [-detail] [-hierarchical]
[-from_power_domain power_domain...]

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[-to_power_domain power_domain...] }
[-width integer] [> file]

This command reports isolation cell information for the design. The return value of the report
corresponds to the number of leaf isolation cell instances found. The information returned
depends on your current position in the design hierarchy.

report power_domain
report power_domain
[-detail] [-power_mode] [-qor]
[> file]

This command reports power domain related information.

Note: An asterisk (*) identifies the default power domain. Without any options specified, a
summary report is given which shows for each power domain.

• The name of the shutoff signal

• Whether the power domain is an always-on domain
• Whether the power domain is externally controlled
• The operating voltage in the default power mode

report state_retention
report state_retention
{ [instance_list]
| [-hierarchical] [-detail]
[-power_gating_pin_driver {port|pin}...]
[-power_domain power_domain-list]
[-verbose] [> file]

This command reports state retention information for the design. The return value of the
report corresponds to the number of state-retention registers found.
verify_power_structure
verify_power_structure
[-isolation] [-level_shifter] [-retention] [-all]
{-pre_synthesis | -post_synthesis} [-detail]
[-run_dir directory] [-debug]
[continue_on_error] [-license string] [> file]

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This command verifies whether the low power cells in the design conform to the rules and
specifications in the loaded CPF file. Specifically, RC will flag if there are any missing isolation,
level shifter, or state retention cells or if the low power cells are not connected appropriately.
To run this command you need to have access to Conformal – Low Power.

Power Intent Validation

Validation of the power intent and implementation is extremely important to ensure that
everything is as per the requirement. The first task here is to perform power intent validation,
sometimes known as CPF quality checks. This actually verifies the correctness of the CPF file
itself, and can be done with formal verification technologies such as Conformal Low-Power
(CLP). The goal is to identify all CPF errors as soon as possible and have a clean CPF before
starting the low-power simulation effort. Basically, a raw or freshly created CPF can have
multiple errors (like the ones mentioned below) and these needs to be rectified:

• Syntax
• Semantics
• Design object
• Inconsistent power intent
• Incomplete power intent

Some of the validation checks include:

• Design object check to see that all objects referenced in CPF are in the design database
• Library CPF check for consistency between CPF, Liberty, and LEF
• CPF specification inconsistency check to see, for example, if an isolation rule specifies an
inconsistent location
• CPF specification completeness check to discover, for example, if there are missing isolation
rule definitions between two power domains
• CPF implementation consistency check to find, for example, if a power net is not connected to
any power domain in the RTL

Command to invoke CLP

Users need to use following command for invoking Conformal – Low Power and carry out the
power intent validation checks:

lec –lp –verify

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Command Template for Logical Netlist Checking

set lowpower option -netlist_style logical
read library -liberty -lp <file* ...>
analyze library -lowpower
read design <design models>
read power intent <power spec> -cpf
commit power intent
analyze power domain

Command Template for Physical Netlist Checking

The following example illustrates reading power and ground pins from LEF, and reading low
power cells from CPF declarations:
set lowpower option –netlist_style physical
read lef file <lef file* …>
read library [–liberty] <functional library file* ...>
read design <gate netlist>
read power intent <cell and design power spec*> -cpf
commit power intent
analyze power domain
The following example illustrates reading in a liberty file with low power attributes:
set lowpower option –netlist_style physical
read library -liberty -lp <file* ...>
analyze library –lowpower
read design <gate netlist>
read power intent <power spec> -cpf
commit power intent
analyze power domain

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