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New Digital Expriment

The document describes several digital logic experiments involving basic gates and circuits such as transmission gates, tristate buffers, flip-flops, counters, adders and a successive approximation register. It includes the Verilog code modules for each circuit element and their corresponding testbenches to simulate and verify the circuit behavior. The experiments cover fundamental concepts in digital logic design and implementation in Verilog.

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Spoorthi B
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
53 views

New Digital Expriment

The document describes several digital logic experiments involving basic gates and circuits such as transmission gates, tristate buffers, flip-flops, counters, adders and a successive approximation register. It includes the Verilog code modules for each circuit element and their corresponding testbenches to simulate and verify the circuit behavior. The experiments cover fundamental concepts in digital logic design and implementation in Verilog.

Uploaded by

Spoorthi B
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Expriment1 Transmission gate

module tr_gate(a,en,y);
input a,en;
output y;
always@(en,a)
if(en = 1’b1)
y = a;
else
y = 1’bZ;
end
endmodule

//Test Bench for Transmission Gate

module trm_gate_tb;
reg a;
reg en;
wire y;
// Instantiate the Unit Under Test (UUT)
tr_gate uut ( .a(a), .en(en), .y(y) );
initial
begin
a = 0;
en = 0;
#10 en = 1'b1;
#20 a = 1'b1;
#20 en = 1'b0;
#20 a = 1'b0;
end
endmodule

Expriment2 Tristate Buffer

module tr_buf(x,en,y);
input x,en;
output y;
reg y;
always @(en,x)
begin
case(en)
1'b1: y=x;
1'b0: y=1'bZ;
endcase
end
endmodule

//Testbench for Tristate Bufferuffer

module tribuf_tb;
// Inputs
reg x;
reg en;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)

tr_buf uut ( .x(x), .en(en), .y(y) );


initial
begin
x = 1'b0;
en = 1'b0;
#50 x = 1'b1;
#70 en = 1'b0;
#40 en = 1'b1;
#80 x = 1'b0;
end
endmodule

Expriment3A SR Flip-Flop

module sr_flip(sr,q,qb,clk);
input [1:0] sr;
output q,qb;
reg q,qb;
input clk;
initial q = 0;
always @(posedge clk)
begin
case(sr)
2'b00 : begin
q = q; qb = ~q;
end
2'b01 : begin
q = 1'b0; qb = ~q;
end
2'b10 : begin
q = 1'b1; qb = ~q;
end
default : qb = q;
endcase
end
endmodule

//Testbench for SR Flip-Flop

module sr_tb;
// Inputs
reg [1:0] sr;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
sr_flip uut ( .sr(sr),.q(q),.qb(qb),.clk(clk));
initial
begin
sr = 2'b00;
clk = 0;
end
always #10 clk = ~clk;
initial
begin
#40 sr = 2'b01;
#40 sr = 2'b10;
#40 sr = 2'b00;
#40 sr = 2'b01;
end
endmodule

Expriment3B JK Flip-Flop

module jk_flip(j,k,clk,q,qb);
input j,k,clk;
output q,qb;
reg q,qb;
initial
begin
q = 1'b0;
qb = 1'b1;
end
always @(posedge clk)
begin
case({j,k})
2'b00 : q = q;
2'b01 : q = 1'b0;
2'b10 : q = 1'b1;
2'b11 : q = qb;
endcase
qb = ~q;
end
endmodule

//Testbench for JK Flip-Flop

module jk_tb;
// Inputs
reg j;
reg k;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT) jk_flip uut ( .j(j),k(k),.clk(clk),.q(q),.qb(qb) );
initial
begin
j = 0;
k = 0;
clk = 0;
end
always #10 clk = ~clk;
initial
begin
#30 {j,k} = 2'b01;
#30 {j,k} = 2'b00;
#30 {j,k} = 2'b10;
#30 {j,k} = 2'b11;
end
endmodule

Expriment3C D Flip-Flop

module dFlip(d,clk,q,qb);
input d,clk;
output q,qb;
reg q,qb;
always @(posedge clk)
begin
q = d;
qb = ~q;
end
endmodule

//Testbench for D Flip-Flop

module dflip_tb;
// Inputs
reg d;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT) dFlip uut (.d(d),.clk(clk),.q(q),.qb(qb));
initial
begin
$monitor ("d=%b then q=%b,qb=%b",d,q,qb);
d = 0;
clk = 0;
end
always #10 clk = ~clk;
initial
begin
#10 d = 1;
#20 d = 0;
#40 d = 1;
end
endmodule
Expriment3D T Flip-Flop

module tFlip(t,clk,q,qb);
input t,clk;
output q,qb;
reg q,qb;
always @(posedge clk)
begin
case(t)
1'b0: q=q;
1'b1: q = ~q;
endcase
qb=~q;
end
endmodule

//Testbench for T Flip-Flop

module tflip_tb;
// Inputs
reg t;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT) tFlip uut (.t(t),.clk(clk),.q(q),.qb(qb));
initial
begin
$monitor ("t=%b then q=%b,qb=%b",t,q,qb);
t = 1'b0;
clk = 1'b0;
end
always #10 clk = ~clk;
initial
begin
#10 t = 1'b1;
#20 t = 1'b0;
#40 t = 1'b1;
end
endmodule

Expriment4A Serial Adder


module serial_adr(a,b,clk,sum,cout,sft_ldbr);
input [3:0]a;
input[3:0]b;
input clk,sft_ldbr;
output [3:0]sum;
output cout;
reg [3:0]sum;
reg cout;
reg [2:0]mc;
reg [1:0]state;//,mb;
always @(posedge clk)
begin
if (sft_ldbr == 1'b0)
begin
state = 2'b00;
end
else
begin
case(state)
2'b00 : begin
{mc[0],sum[0]}=a[0]+b[0];
state = 2'b01;
end
2'b01 : begin
{mc[1],sum[1]}=a[1]+b[1]+mc[0];
state = 2'b10;
end
2'b10 : begin
{mc[2],sum[2]}=a[2]+b[2]+mc[1];
state = 2'b11;
end
default : {cout,sum[3]} =a[3]+b[3]+mc[2];
endcase
end
end
endmodule

//Testbench for Serial Adder

module ser_adt_tb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg clk;
reg sft_ldbr;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT) serial_adr uut
(.a(a),.b(b),.clk(clk),.sum(sum),.cout(cout), .sft_ldbr(sft_ldbr));
initial
begin // Initialize Inputs
$monitor ("a=%b b=%b sft_ldbr=%b then sum=%b & cout=%b",a,b,sft_ldbr,sum,cout);
a = 0;
b = 0;
clk = 1'b0;
sft_ldbr = 1'b0;
end
always #10 clk = ~clk;
initial
begin
a = 4'b1011;
b = 4'b1110;
sft_ldbr = 1'b0;
#30 sft_ldbr = 1'b1;
#130 sft_ldbr = 1'b0;
#20 sft_ldbr = 1'b1;
end
endmodule

Expriment4B Parallel Adder

module parlel_adr(a,b,sum,cout,cin);
input [3:0]a;
input[3:0]b;
input cin;
output [3:0]sum;
output cout;
reg [2:0]mc;
reg cout;
reg [3:0]sum;
always @(a,b,cin)
begin
{mc[0],sum[0]}=a[0]+b[0]+cin;
{mc[1],sum[1]}=a[1]+b[1]+mc[0];
{mc[2],sum[2]}=a[2]+b[2]+mc[1];
{cout,sum[3]} =a[3]+b[3]+mc[2];
end
endmodule

//Testbench for Parallel Adder

module par_adr_tb;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] sum; w
ire cout;
// Instantiate the Unit Under Test (UUT) parlel_adr uut (.a(a), .b(b), .sum(sum), .cout(cout),
.cin(cin));
initial
begin // Initialize Inputs
$monitor ("a=%b b=%b cin=%b then sum=%b & cout=%b",a,b,cin,sum,cout);
a = 4'b1010;
b = 4'b1110;
cin = 1'b0;
#20 a = 4'b1011;
b = 4'b1110;
end
endmodule

Expriment5A Synchronous Counter

module sync_counter(cnt,clk,up_dwnbr,clr);
output [3:0] cnt;
input clk,clr;
input up_dwnbr;
reg [3:0]cnt;
initial cnt = 1'd0;
always @(posedge clk)
begin
case(clr)
1'b1 : cnt = 1'd0;
default : begin
case
(up_dwnbr) 1'b0 : cnt = cnt - 4'b0001;
default : cnt = cnt + 1'b1;
endcase
end
endcase
end
endmodule

// Testbench for Synchronous Counter

module sync_tb;
// Inputs
reg clk;
reg up_dwnbr;
reg clr;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT) sync_counter uut (.cnt(cnt), .clk(clk),
.up_dwnbr(up_dwnbr), .clr(clr));
initial
begin // Initialize Inputs
clk = 1'b0;
up_dwnbr = 1'b0;
clr = 1'b1;
end
always #10 clk = ~clk;
initial
begin
#40 clr = 1'b0;
#70 up_dwnbr = 1'b1;
#80 up_dwnbr = 1'b0;
end
endmodule

Expriment5B Asynchronous Counter

module async_cntr(clk,cnt,up_dwnbr,clr);
input up_dwnbr,clr,clk;
output [3:0]cnt;
reg [3:0]cnt;
always @(posedge clk)
begin
if(clr == 1'b1)
cnt = 4'b0000;
else
begin
case(up_dwnbr)
1'b0 : begin
if(cnt[1:0] == 2'b10)
cnt[1:0] = 2'b01;
else if(cnt[2:0] == 3'b100)
cnt[2:0] = 3'b011;
else if(cnt[3:0] == 4'b1000)
cnt[3:0] = 4'b0111;
else if(cnt[3:0] == 4'b0000)
cnt[3:0] = 4'b1111;
else
cnt[0] = ~cnt[0];
end
1'b1 :begin
if(cnt[1:0] == 2'b01)
cnt[1:0] = 2'b10;
else if(cnt[2:0] == 3'b011)
cnt[2:0] = 3'b100;
else if(cnt[3:0] == 4'b0111)
cnt[3:0] = 4'b1000;
else if(cnt[3:0] == 4'b1111)
cnt[3:0] = 4'b0000;
else
cnt[0] = ~cnt[0];
end
endcase
end
end
endmodule

//TestBench for Asynchronous Counter

module async_cntr_tb;
reg up_dwnbr;
reg clr;
reg clk;
wire [3:0] cnt;
async_cntr asyn1 ( .clk(clk), .cnt(cnt), .up_dwnbr(up_dwnbr), .clr(clr) );
initial
begin
$monitor ("if clr=%b and up_dwnbr = %b and cnt=%b",clr,up_dwnbr,cnt);
clk =1'b0;
up_dwnbr = 1'b0;
clr = 1'b1;
end
always #10 clk = ~clk;
initial
begin
#30 clr = 1'b0;
#60 up_dwnbr = 1'b1;
#60 up_dwnbr = 1'b0;
#60 up_dwnbr = 1'b1;
end
endmodule

Expriment6 Successive Approcimation Resgister

module SAR(clk,reset,SOC,comp_in,EOC,q);
input clk,reset,SOC,comp_in;
output EOC;
output [3:0] q;
reg [3:0] q;
reg EOC;
reg [1:0]cnt;
always @(posedge(clk),reset)
begin
if(reset == 1'b1)
begin
q = 4'b1000;
EOC = 1'b0;
cnt = 2'b00;
end
else if(reset==1'b0 && SOC == 1'b1 && EOC == 1'b0)
begin
case(cnt)
2'b00 : begin
q[3:2] = {comp_in,1'b1}; cnt = cnt + 1;
end
2'b01 : begin
q[2:1] = {comp_in,1'b1}; cnt = cnt + 1;
end
2'b10 : begin
q[1:0] = {comp_in,1'b1}; cnt = cnt + 1;
end
2'b11 : begin
{q[0],EOC} = {comp_in,1'b1}; cnt = cnt + 1;
end
endcase
end
end
endmodule

//TestBench for SAR

module SAR_tb;
// Inputs reg clk;
reg reset;
reg SOC;
reg comp_in;
wire [3:0]q;
// Outputs
wire EOC;
reg [3:0] tst1,tst2;
// Instantiate the Unit Under Test (UUT) SAR uut ( .clk(clk), .reset(reset), .SOC(SOC),
.comp_in(comp_in), .EOC(EOC), .q(q) );
initial
begin
clk = 1'b0;
reset = 1'b1;
SOC = 1'b0;
comp_in = 1'b0;
tst1 = 4'b1001;
tst2 = 4'b1101;
$monitor ("reset = %b,SOC=%b,comp_in=%b,q=%b,EOC=%b",reset,SOC,comp_in,q,EOC);
end
always #10 clk = ~clk;
initial
begin
#20 reset = 1'b0;
#20 SOC = 1'b1;
comp_in = tst1[3];
#20 comp_in = tst1[2];
#20 comp_in = tst1[1];
#20 comp_in = tst1[0];
#20 reset = 1'b1;
SOC = 1'b0;
#40 reset = 1'b0;
#20 SOC = 1'b1;
comp_in = tst2[3];
#20 comp_in = tst2[2];
#20 comp_in = tst2[1];
#20 comp_in = tst2[0];
end
endmodule

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