1

Introduction to:
Microprocessors (EEE-347)
Embedded Systems Development (CNG 336)

Lecture Notes
Dr. Gürtaç Yemişçioğlu
Spring 2020
METU Northern Cyprus Campus

References:
Lecture Notes: Prof.Dr. Ali Muhtaroğlu, Electrical and Electronics Engineering, METU NCC
Main Textbook: M. A. Mazidi, S. Naimi, & S. Naimi, “The AVR Microcontroller and Embedded Systems: Using
Assembly and C” (International Ed.), Pearson, 2014
Auxiliary Textbooks: E. A. Lee, S. A. Seshia, “Introduction to Embedded Systems: A Cyber-Physical Systems
Approach” (2nd Ed.), LeeSeshia.org, 2015
Barry B. Brey, “The Intel Microprocessors” (7th/8th Ed.), Prentice Hall, 2006/2014
Other: Lecture notes of Prabal Dutta, U. of Michigan
 Introduction

Lectures 1-2

Reading:
Mazidi: Chapter 1; Lee: Chapter 1

3
Outline

• Technology Trends
• Course Administration, Goals, and Tools
• Definitions of Microprocessor, Microcontroller,
Embedded System
• Example System
• Introduction to Computing
– CPU Fundamentals
– Main Memory Types
– Buses
– Fetch-Decode-Execute Cycle for Instruction Execution
– von Neumann vs. Harvard Architecture

4
The Internet of Things - some popular projections
50T:10B
5K:1!

1T

1B

Jan Rabaey, “The Human Intranet – Where Swarms and Humans

Meet,” IEEE Pervasive Computing Magazine, January—March, 2015
5
Moore’s Law (a statement about economics):
IC transistor count doubles every 18-24 mo

Photo Credit: Intel6

The number of computers per person grows

Mainframe [Bell et al. Computer,

1 per Enterprise 1972, ACM, 2008]
10T
1T
100G
10G
per computer)

1G
100M Workstation
1 per Engineer Laptop
10M
)
3

1 per
Size (mm

1M Professional

Smart
log (people

100k
Sensors
10k
Mini Ubiquitous
1k Computer
100 1 per Company
Personal
10
Computer 100 – 1000’s
1 1 per Family 1 per person per person
Smartphone
100m
1950 1960 1970 1980 1990 2000 2010 2020 7
Computer volume shrinks by 100x every decade

Mainframe
1 per Enterprise
10T
1T 100x smaller
100G every decade
10G [Nakagawa08]
1G
100M Workstation
1 per Engineer Laptop
10M
Size (mm )
3

1 per
1M Professional

100k Smart
Sensors
10k
Mini Ubiquitous
1k Computer
100 1 per Company
Personal
10
Computer 100 – 1000’s
1 1 per Family 1 per person per person
Smartphone
100m
1950 1960 1970 1980 1990 2000 2010 2020 8
Price falls dramatically,
and enables new applications
Mainframe
100000 Workstation
Inflation Adjusted Price (1000s of USD)

10000

Number Crunching
1000 Data Storage

100 Laptop

10
productivity
interactive
1 Mini
Computer streaming
Smart information
Personal Sensors
0.1 to/from the
Computer physical
Smartphone world
0.01
1950 1960 1970 1980 1990 2000 2010 2020 9
Bell’s Law: A new computer class every decade

“Roughly every decade a new,

lower priced computer class
forms based on a new
programming platform, network,
and interface resulting in new
usage and the establishment of a
new industry.”

- Gordon Bell [1972,2008]

10
What is driving Bell’s Law?

Technology Scaling Technology Innovations

• Moore’s Law • MEMS technology
– Made transistors cheap – Micro-fabricated sensors
• Dennard’s Scaling • New memories
– Made them fast – New cell structures (11T)
– And low-power – New tech (FeRAM, FinFET)
• Result • Near-threshold computing
– Holding #T’s constant – Minimize active power
• Exponentially lower cost – Minimize static power
• Exponentially lower power
• New wireless systems
– Small, cheap & low-power
– Radio architectures
• Microcontrollers
– Modulation schemes
• Memory
• Radios • Energy harvesting

11
Broad availability of inexpensive, low-power MCUs
(with enough memory to do interesting things)

12
Hendy’s “Law”:
Pixels per dollar doubles annually

Keeping pixels fixed,

size, power, cost fall

Credit: Barry Hendy/Wikipedia

G. Kim, Z. Foo, Y, Lee, P. Pannuto, Y-S. Kuo, B. Kempke, M. Ghaed, S. Bang, I. Lee, Y. Kim, S. Jeong, P. Dutta, D. Sylvester, D. Blaauw,
“A Millimeter-Scale Wireless Imaging System with Continuous Motion Detection and Energy Harvesting,
In Symposium of VLSI Technology (VLSI’14), Jun. 2014. 13
 Radio technologies enabling pervasive computing,
IoT

Source: Steve Dean, Texas Instruments

http://eecatalog.com/medical/2009/09/23/current-and-future-trends-in-medical-electronics/
14
Established comms interfaces: 802.15.4, BLE, NFC

• IEEE 802.15.4 (a.k.a. “ZigBee” stack)

– Workhorse radio technology for sensornets
– Widely adopted for low-power mesh protocols
– Middle (6LoWPAN, RPL) and upper (CoAP layers)
– Can last for years on a pair of AA batteries

• Bluetooth Low-Energy (BLE)

– Short-range RF technology
– On phones and peripherals
– Can beacon for years on coin cells

• Near-Field Communications (NFC)

– Asymmetric backscatter technology
– Small (mobile) readers in smartphones
– Large (stationary) readers in infrastructure
– New: ambient backscatter communications 15
Emerging Proximal Interfaces:
Ultrasonic, Visible Light, Vibration
• Ultrasonic
– Small, low-power, short-range
– Supports very low-power wakeup
– Can support pairwise ranging of nodes

• Visible Light
– Enabled by pervasive LEDs and cameras
– Supports indoor localization and comms
– Easy to modify existing LED lighting

• Vibration
– Pervasive accelerometers
– Pervasive Vibration motors
– Bootstrap desktop area context

16
Non-volatile memory capacity & read/write bandwidth

Lower capacity but

Higher R/W speeds
*and*
Lower energy per
atomic operation
*and*
High write
endurance

17
MEMS Sensors:
Rapidly falling price and power of accelerometers

O(mA)

[Analog Devices, 2009]

25 µA @ 25 Hz ADXL345

10 µA @ 10 Hz @ 6 bits
[ST Microelectronics, annc. 2009]
ADXL362

1.8 µA @ 100 Hz @ 2V
300 nA wakeup mode
[Analog Devices, 2012]
18
Energy harvesting and storage:
Small doesn’t mean powerless…

RF [Intel] Clare Solar Cell

Thin-film batteries
Shock Energy Harvesting
CEDRAT Technologies

Electrostatic Energy
Harvester [ICL]
Piezoelectric
[Holst/IMEC]

Thermoelectric Ambient
Energy Harvester [PNNL] 19
MCU-32 and PLDs are tied in embedded market share

21
FPGA based designs in EEE-248/CNG-232, EEE-446
MCU based designs here…

MCU FPGA

RAM EEPROM Timers

PROGRAM
Flash ROM

Program Data
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

22
Course goals

• Understand the fundamentals of microprocessors,

microcontrollers, hardware interfacing and system
design techniques.

• Learn assembly programming and hardware

interfacing on a selected microcontroller as a
preparation to do embedded system design on any
architecture.

- Prerequisite: Logic Design

- Any other programming or hardware design experience
will help

23
Topics
• MCU basics
– Hardware organization, instruction set, instruction execution
– Programming basics at assembly level and high level

• I/O interfaces
– Parallel and serial buses, memory access, digital and analog interfaces
– Working with analog signals i.e. real world is not digital

• Common peripheral devices and interfaces

– Memories, switches, LEDs, keyboards, motors, sensors, timers, etc.

• Interrupts
– How to get the processor to become “event driven” and react to
things as they happen.

24
Learning Tools

• MCU Learning Vehicle

– AVR Atmega128 8-bit Microcontroller

• Assembly Code Verification / MCU Simulation

– AtmelStudio 7 Integrated Development Environment (IDE)

• System Design & Simulation

– Proteus ISIS

• System Prototyping & Testing

– UNI-DS6 Development Board with a mikroBoard for AVR 64-pin

• Will add a C-compiler later on…

25
Microprocessor
A microprocessor is the general purpose (not specialized) integrated (one
chip) controlling element (brain) of a computer system. 3 main tasks:
1. Data transfer between memory or I/O systems and itself
2. Arithmetic and logic operations
3. Program flow, decision making based on conditions

Microcontroller (MCU)
An MCU is a controlling IC component typically programmed for a special
purpose embedded systems application. One can think of a microcontroller as
a small-scale microprocessor. A microcontroller has different desirable
characteristics depending on the application, some of which may be:
• Cost, System integration (size), Power consumption, Performance/speed
and addressable memory size, Programmability in embedded applications,
Reliability (Lifetime, noise tolerance, etc.)
• Different I/O interfaces for a variety of peripherals

27
Embedded Systems

28
What do we mean by Systems?

SOME THING

INPUT(S) AFFECTED BY INPUTS OUTPUT(S)

PRODUCES OUTPUTS

OR
TRANSFORMS
INPUTS TO OUTPUTS

29
What do we mean by Systems?

30
What do we mean by Embedded Systems?

Computation Network Computation

Sensors Actuators

Physical Plant

31
Embedded System

A special purpose computer dedicated to a particular task, e.g. an ABS or

Cruise control system in an automobile, power electronics controllers, etc.
Some typical characteristics are:
1. A low cost microcontroller that is no more complex than the
requirements of the application
2. Small storage (memory, disk) compared to a general purpose
computer
3. Fewer and task oriented peripherals/interface compared to a
general purpose computer e.g. LEDs, switches, a menu driven front-
end, etc.

32
Will do Simple Modeling,
Design, & Analysis

Modeling is the process of

gaining a deeper understanding
of a system through imitation.
Models specify what a system does.
Design is the structured creation of artifacts.
It specifies how a system does what it does.
Analysis is the process of gaining a deeper understanding of a
system through dissection.
It specifies why a system does what it does
(or fails to do what a model says it should do).

33
A System Example
A quadrotor aircraft
Modeling:
• Flight dynamics
• Modes of operation
• Transitions between modes
• Composition of behaviors
• Multi-vehicle interaction

Design:
• Processors
• Memory system
• Sensor interfacing
• Concurrent software
• Real-time scheduling

Analysis
• Specifying safe behavior
• Achieving safe behavior
• Verifying safe behavior
• Guaranteeing timeliness
34
A System Example
STARMAC quadrotor aircraft
LIDAR RS232
URG-04LX 115 kbps
10 Hz ranges PC/104 WiFi
USB 2
Stereo Cam Pentium M 802.11g+
Firewire 1GB RAM, 1.8GHz 480 Mbps ≤ 54 Mbps
Videre STOC
30 fps 320x240 480 Mbps RS232 Est. & control

GPS UART
Superstar II 19.2
Stargate 1.0 WiFi
10 Hz kbps CF
Intel PXA255 802.11b
UART 64MB RAM, 400MHz 100 ≤ 5 Mbps
IMU 115 Kbps UART Mbps
3DMG-X1 UART Supervisor, GPS
Robostix
76 or 100 Hz 115 Atmega128
kbps Low level control
Ranger I2C PPM
SRF08
400 kbps 100 Hz
13 Hz Altitude Analog

Ranger Beacon
Mini-AE ESC & Motors
Timing/ Tracker/DTS Phoenix-25, Axi 2208/26
10-50 Hz Altitude 1 Hz
Analog

Since this is an introductory course to processors and embedded systems, will

look at simpler systems here… but the learning will be applicable and
scaleable to more complex systems. 35
Introduction to Computing
Internal organization of computers
– The different parts of a computer
• I/O
– Input e.g. Keyboard, Mouse, Sensor
– Output e.g. LCD, printer, hands of a robot
• Memory
• CPU

– Connecting the different parts

• Connecting memory to CPU
• Connecting I/Os to CPU

– Need to understand how computers work in order to

understand how microprocessor or microcontroller
based systems work
36
Common Computer Organization
Computer Organization Main Computer Buses

ALU (Arithmetic Logic Unit) executes Address bus: carries the address of a
arithmetic and logic operations (for unique memory or input/output (I/O)
example ADD, SHIFT, AND, OR, etc) device
on certain on-chip registers. Data bus: carries data stored in memory
CPU (Central Processing Unit) is the (or an I/O device) to the CPU or from the
combination of the control logic, CPU to the memory (or I/O device)
associated registers and the Control bus: is a collection of control
arithmetic logic unit (brains of the signals that coordinate and synchronize
computer). the whole system 37
A Typical Microcontroller System

Power
Converters
Supply

BUS
Memory

Microcontroller
(MCU) Peripherals

Clock
Generator

Buffers

Data, Address, Control

Bus
Power Delivery

OUTSIDE WORLD

38
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 5 V DC
Converters
Supply

BUS
Memory

Microcontroller
(MCU) Peripherals

Clock
Generator

Buffers

Data, Address, Control

Bus
Power Delivery

OUTSIDE WORLD

39
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components

Microcontroller
(MCU) Peripherals

Clock
Generator

Buffers

Data, Address, Control

Bus
Power Delivery

OUTSIDE WORLD

40
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components
3. The clock circuit generates a timing
reference to all of the system
Microcontroller
Peripherals components by supplying a fixed
(MCU)
frequency square wave

Clock
Generator

Buffers

Data, Address, Control

Bus
Power Delivery

OUTSIDE WORLD

41
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components
3. The clock circuit generates a timing
reference to all of the system
Microcontroller
Peripherals components by supplying a fixed
(MCU)
frequency square wave
4. Control signals communicate and
Clock coordinate the operation of all
Generator components

Buffers

Data, Address, Control

Bus
Power Delivery

OUTSIDE WORLD

42
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components
3. The clock circuit generates a timing
reference to all of the system
Microcontroller
Peripherals components by supplying a fixed
(MCU)
frequency square wave
4. Control signals communicate and
Clock coordinate the operation of all
Generator components
5. Data signals (bidirectional) carry
Buffers information on instructions and values
of system variables

Data, Address, Control

Bus
Power Delivery

OUTSIDE WORLD

43
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components
3. The clock circuit generates a timing
reference to all of the system
Microcontroller
Peripherals components by supplying a fixed
(MCU)
frequency square wave
4. Control signals communicate and
Clock coordinate the operation of all
Generator components
5. Data signals (bidirectional) carry
Buffers information on instructions and values
of system variables
6. Address signals are unidirectional,
Data, Address, Control generated by MCU, and indicate where
Bus
the data is located
Power Delivery

OUTSIDE WORLD

44
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components
3. The clock circuit generates a timing
reference to all of the system
Microcontroller
Peripherals components by supplying a fixed
(MCU)
frequency square wave
4. Control signals communicate and
Clock coordinate the operation of all
Generator components
5. Data signals (bidirectional) carry
Buffers information on instructions and values
of system variables
6. Address signals are unidirectional,
Data, Address, Control generated by MCU, and indicate where
Bus
the data is located
Power Delivery
7. Buffers, together with converters,
OUTSIDE WORLD condition the I/O signal levels as
necessary
45
A Typical Microcontroller System
1. Power Supply converts incoming 220 V
Power AC or 12 V DC down to 3.3 or 5 V DC
Converters
Supply 2. Converters typically do further DC-DC
conversion to obtain various voltages
BUS (e.g. 1.5 V, 2 V) required by system
Memory components
3. The clock circuit generates a timing
reference to all of the system
Microcontroller
Peripherals components by supplying a fixed
(MCU)
frequency square wave
? Clock
4. Control signals communicate and
coordinate the operation of all
Generator components
5. Data signals (bidirectional) carry
Buffers information on instructions and values
of system variables
6. Address signals are unidirectional,
Data, Address, Control generated by MCU, and indicate where
Bus
the data is located
Power Delivery
7. Buffers, together with converters,
OUTSIDE WORLD condition the I/O signal levels as
necessary
46
 Microcontroller Unit

VDD

INTERNAL MEMORY
DATA BUS
ROM
CLOCK
Central RAM
CONTROL
Processing
LINES
Unit (CPU) EPROM or
EEPROM

I/O CONTROL
and STATUS
REGISTERS
I/O
I/O DATA PORTS
REGISTERS

47
 Microcontroller Unit

VDD 1. CPU controls the operation and is

INTERNAL
where most of the processing
MEMORY
DATA BUS happens
ROM
CLOCK
Central RAM
CONTROL
Processing
LINES
Unit (CPU) EPROM or
EEPROM

I/O CONTROL
and STATUS
REGISTERS
I/O
I/O DATA PORTS
REGISTERS

48
 Microcontroller Unit

VDD 1. CPU controls the operation and is

INTERNAL
where most of the processing
MEMORY
DATA BUS happens
ROM 2. I/O Control, Status and Data
CLOCK
Central
registers are used in I/O
RAM operations together with the I/O
CONTROL
Processing
LINES
Unit (CPU) EPROM or Ports
EEPROM

I/O CONTROL
and STATUS
REGISTERS
I/O
I/O DATA PORTS
REGISTERS

49
 Microcontroller Unit

VDD 1. CPU controls the operation and is

INTERNAL
where most of the processing
MEMORY
DATA BUS happens
ROM 2. I/O Control, Status and Data
CLOCK
Central
registers are used in I/O
RAM operations together with the I/O
CONTROL
Processing
LINES
Unit (CPU) EPROM or Ports
EEPROM 3. Data and program are stored in
the memory block:
I/O CONTROL
and STATUS ROM: Read-Only Memory
REGISTERS
I/O permanently programmed by the
I/O DATA PORTS manufacturer
REGISTERS
EPROM: Erasable Programmable
ROM – erased by the UV light
EEPROM: Electrically Erasable
Programmable ROM – can be
erased and reprogrammed using
the regular supply voltage (Vdd).

50
 Microcontroller Unit

VDD 1. CPU controls the operation and is

INTERNAL
where most of the processing
MEMORY
DATA BUS happens
ROM 2. I/O Control, Status and Data
CLOCK
Central
registers are used in I/O
RAM operations together with the I/O
CONTROL
Processing
LINES
Unit (CPU) EPROM or Ports
EEPROM 3. Data and program are stored in
the memory block:
I/O CONTROL
and STATUS ROM: Read-Only Memory
REGISTERS
I/O permanently programmed by the
I/O DATA PORTS manufacturer
REGISTERS
EPROM: Erasable Programmable
ROM – erased by the UV light
EEPROM: Electrically Erasable
Programmable ROM – can be
erased and reprogrammed using
the regular supply voltage (Vdd).

51
Memory
• Everything that can store, retain, and recall information.
e.g. hard disk, a piece of paper, etc.

Memory Characteristics
• Capacity
– The number of bits that a memory can store.
• e.g. 128 Kbits, 256 Mbits 4 bits
0

128 locations
1
2
• Organization

…
– How the locations are organized 127

• e.g. a 128 x 4 memory has 128 locations, 4 bits each

• Access time (a performance metric)

– How long it takes to get data from memory
52
Semiconductor Memories

• ROM
– Mask ROM
– PROM (Programmable ROM)
– EPROM (Erasable PROM)
– EEPROM (Electronic Erasable PROM)
– Flash EPROM

• RAM
– SRAM (Static RAM)
– DRAM (Dynamic RAM)
– NV-RAM (Nonvolatile RAM)
53
Semiconductor Memories  ROM  Mask ROM
• Programmed by the IC manufacturer
– Cost effective for producers only in large quantities
since content is fixed
– e.g. MPR-18-201

Semiconductor Memories  ROM  PROM

(Programmable ROM)
• OTP (One-Time Programmable) Non-Volatile Memory (NVM)
– Field Programmable ROM (FPROM)
– You can program it only once using ~10 V
– e.g. 74S188 54
Semiconductor Memories  ROM  EPROM (Erasable
Programmable ROM)
• UV-EPROM
– You can shine ultraviolet (UV) radiation to erase it
– Erasing takes up to 20 minutes
– The entire contents of ROM are erased
– e.g. 2764 EPROM
2764

55
Semiconductor Memories  ROM  EEPROM
(Electrically Erasable Programmable ROM)
• Erased electrically and instantly with a RDY/BSY
A12
VCC
WE

regular computer A7
A6 8K x 8
NC
A8
• Each byte can be programmed in 1 - 10ms A5 A9
A4 A11
or erased separately in 5 - 50 ms A3 OE

• More costly than EPROM due to more A2 A10

A1 CE

transistors A0
I/O0
I/O7
I/O6
• e.g. 2864A EEPROM I/O1
I/O2
I/O5
I/O4
VSS I/O3

ATMega128 has 4 KBytes of data EEPROM memory

56
 Semiconductor Memories  ROM  Flash EPROM
• Erased in a flash
• The entire device or large chunks is erased at once
• Each chunk can be programmed in 10 - 100 µs
• “F” in the part name suggests “flash”
• e.g. 28F256 Flash EPROM

ATMega128 has in-system reprogrammable 64K x 16 (64K x 2 Bytes) = 128 KBytes flash memory
57
Semiconductor Memories

• ROM
– Mask ROM
– PROM (Programmable ROM)
– EPROM (Erasable PROM)
– EEPROM (Electronic Erasable PROM)
– Flash EPROM

• RAM
– SRAM (Static RAM)
– DRAM (Dynamic RAM)
– NV-RAM (Nonvolatile RAM)
58
Semiconductor Memories  RAM  Static RAM (SRAM)
• Made of latches (which are made up of transistors)
• Advantages:
– Faster
– No need for refreshing
• Disadvantages:
– High power consumption*
– Expensive
• e.g. 6116 SRAM – 2K x 8 bit (2 kBytes or 16,384 bits of
capacity) with access time as fast as 15 ns

* Take with a grain of salt – many power management

features compensate effectively nowadays for this
disadvantage
ATMega128 has 4096 x 8 (4096 Bytes) internal SRAM that can be extended to 64 KB with
addition of external memory. 59
Semiconductor Memories  RAM  Dynamic RAM
(DRAM)
• Made of capacitors

• Advantages:
– Less power consumption (again depends on power
management modes)
– Cheaper due to high integration
– High capacity

• Disadvantages:
– Slower
– Refresh needed

• Recently DDR SDRAM

Credit: Samsung
(Double Data Rate synchronous
dynamic RAM)
60
Semiconductor Memories  RAM  Nonvolatile RAM
(NVRAM)
• Made of SRAM, built-in
battery (or duplicate EEPROM
memory array), control
circuitry

• Advantages: NVRAM with built-in battery

DS1220 (Dallas semiconductor)
– Very fast
– Infinite program/erase
cycle
– Non-volatile

• Disadvantage:
– Expensive
NVRAM with built-in EEPROM
X22C10 (Xicor)
61
Memory Access

Highest Nibble (4 bits)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 Binary

BIT
High Byte Low Byte

. ~ ~
.
$5C13 …
$5C16 $5C14 …
$5C15 … Data
$5C16 $34 %00110100
$5C17 …
.
. ~ ~
62
CPU
• Tasks:
– It should execute instructions
• It should fetch (recall) the instructions one after
another and execute them

Connecting Memory to CPU

VCC

CS’: Active low Chip

GND VCC
Select
8
D0-D7 WE’: Active low Write
CPU n
A0-An-1 Enable
WE
OE’: Active low Output
OE
CS
Enable
63
 Connecting Memory to CPU
Writing to memory Reading from memory

Address Address
CS CS
OE
Data Data
tsu tho
WE
WE
Time Time

VCC
tsu: Min data setup time
GND VCC
before WE’ rising
edge
8
D0-D7 tho: Min data hold time
CPU n
A0-An-1
after WE’ rising
WE
edge
OE
tRC : Read Cycle Time
CS tAA : Address Access
Time 64
Connecting I/O devices to CPU
• CPU should have lots of pins!

Mouse

Network
CPU Keyboard

Sound Card

Graphic Card
65
Connecting I/O devices to CPU
using a Shared Bus

Address bus

Data bus
Write
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

66
Connecting I/Os and Memory to CPU

Address bus

Data bus
Write
Control bus Read

CPU I/O 0 I/O 1 I/O 2 I/O n

VCC

GND VCC

n
A0-An-1
8
D0-D7
Increased number of buses/wires
WE means higher cost !
OE
CS

67
Connecting I/Os and Memory to CPU
Using a Shared Bus

VCC
0
1
2
3

A0-An-1
GND

D0-D7

WE

OE
CS
Address bus

Data bus
Write
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

68
Connecting I/Os and Memory to CPU
Using a Shared Bus

VCC
0
1

How could we manage it? 2

3

A0-An-1
GND

D0-D7

WE

OE
CS
00H
Address bus

Data bus
Write
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

(Note, will 3 notations for hexadecimal numbers interchangeably:

69
$Number, NumberH, 0xNumber)
Connecting I/Os and Memory to CPU
Using a Shared Bus (Peripheral I/O scheme)

VCC
0
1
..
63

A0-An-1
GND

D0-D7

WE

OE
CS
Address bus

Data bus
Write
Control bus Read
IO/MEM
CPU
I/O 0 I/O 1 I/O 2 I/O n

70
Connecting I/Os and Memory to CPU
Using a Shared Bus (Memory Mapped I/O scheme)
The logic circuit

VCC
0
1 enables CS
..
15
when address is

A0-An-1
GND

D0-D7
between 0 and

WE

OE
CS
15
Logic circuit
Address bus

Data bus
Write
Control bus Read

CPU
I/O 16 I/O 17 I/O 18 I/O n

71
Connecting I/Os and Memory to CPU
Using a Shared Bus (Memory Mapped I/O scheme)
The logic circuit

VCC
0
1 enables CS
How to design the logic ..
when address is
circuit? 15

A0-An-1
GND

D0-D7
between 0 and

WE

OE
CS
15
8 Logic circuit
Address bus

Data bus
Solution
Control 1.
bus Write
Write the address range in binary
Read
2. Separate the fixed part of address
3. Using a NAND, design a logic circuit whose output
CPU activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0  0 0 0 0 0 0 0 0 a4
I/O 16 I/O 17 I/O a5
18 I/OCS
n
To address15  0 0 0 0 1 1 1 1 a6
a7

72
Another Example for Address Decoder

• Design an address decoder for address of 300H to 3FFH

(for a 12-bit address bus)

Solution
1. Write the address range in binary
2. Separate the fixed part of address
3. Design the logic circuit.

a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8
a9
From address 300H  001100000000 a10 CS
a11
To address 3FFH  001111111111

An easy way of
designing

73
 Inside the CPU

The main functions of the CPU

INTERNAL
DATA BUS
are:
Control ARITHMETIC
CLOCK
& LOGIC UNIT • Data transfer
Sequencer
CONTROL
(ALU) • Arithmetic and logic
LINES operations
• Decision making (instruction
CPU
REGISTERS INSTRUCTION flow control)
DECODER

Control Sequencer:
Controls the operations in the
CPU
PROGRAM
COUNTER
Register Array:
ADDRESS Temporary storage (faster than
REGISTER
memory)

ADDRESS BUS DATA BUS

74
 von Neumann Fetch/(Decode)/Execute Cycle

1. CPU keeps track of the location of

INTERNAL the next instruction or data byte (to
ARITHMETIC DATA BUS
CLOCK Control fetch) through the Program
& LOGIC UNIT
Sequencer (ALU) Counter (PC).
CONTROL
LINES

CPU
REGISTERS INSTRUCTION
DECODER

PROGRAM
COUNTER

ADDRESS
REGISTER

ADDRESS BUS DATA BUS

75
 von Neumann Fetch/(Decode)/Execute Cycle

1. CPU keeps track of the location of

INTERNAL the next instruction or data byte (to
ARITHMETIC DATA BUS
CLOCK Control fetch) through the Program
& LOGIC UNIT
Sequencer (ALU) Counter (PC).
CONTROL
LINES 2. Instruction Decoder decodes the
received data and configures the
CPU
REGISTERS INSTRUCTION Arithmetic Logic Unit (ALU) to
DECODER process it. Arithmetic or logic
operations execute in the ALU.

PROGRAM
COUNTER

ADDRESS
REGISTER

ADDRESS BUS DATA BUS

76
 von Neumann Fetch/(Decode)/Execute Cycle

1. CPU keeps track of the location of

INTERNAL the next instruction or data byte (to
ARITHMETIC DATA BUS
CLOCK Control fetch) through the Program
& LOGIC UNIT
Sequencer (ALU) Counter (PC).
CONTROL
LINES 2. Instruction Decoder decodes the
received data and configures the
CPU
REGISTERS INSTRUCTION Arithmetic Logic Unit (ALU) to
DECODER process it. Arithmetic or logic
operations execute in the ALU.
3. After the execution, the relevant
bits are set, and data gets stored to
PROGRAM a register or memory location if
COUNTER
applicable.
ADDRESS
REGISTER

ADDRESS BUS DATA BUS

77
 von Neumann Fetch/(Decode)/Execute Cycle

1. CPU keeps track of the location of

INTERNAL the next instruction or data byte (to
ARITHMETIC DATA BUS
CLOCK Control fetch) through the Program
& LOGIC UNIT
Sequencer (ALU) Counter (PC).
CONTROL
LINES 2. Instruction Decoder decodes the
received data and configures the
CPU
REGISTERS INSTRUCTION Arithmetic Logic Unit (ALU) to
DECODER process it. Arithmetic or logic
operations execute in the ALU.
3. After the execution, the relevant
bits are set, and data gets stored to
PROGRAM a register or memory location if
COUNTER
applicable.
ADDRESS 4. The Control Sequencer ensures the
REGISTER
Fetch/Decode/Execute cycle
repeats until the last instruction is
ADDRESS BUS DATA BUS detected.

78
Example: Consider a Simple CPU
• PC (Program Counter)
• Instruction decoder
• ALU (Arithmetic Logic Unit)
• Registers

PC A
ALU B

CPU C
D
Instruction decoder registers

79
 Instruction Decode
Opcode Operand

Instruction

Operation Code Meaning

000 Ax
0011 0001 0 31h A [17]
1100 0100 1 C4h BA 001 A  [x]
Instructions 0010 0110 2 26h A  [6] 010 A  A – register (x)
1000 0001 3 81h AA+B
1110 0111 4 E7h [7]A 011 AA+x
0000 0000
Data 5 00h 100 A  A + register (x)
0000 0101 6 05h
7
101 AA–x
110 Register (xH)  Register (xL)
111 [x]  A

Note: These are hypothetical instructions used for this example…

Instruction Fetch(Decode)Execute in CPU
0 31h
31 A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 0 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

81
Instruction Fetch(Decode)Execute in CPU
0 31h
31 A [17]
Instructions 1 C4h BA
and Data in 2 26h A  [6]

VCC
3 81h AA+B
Memory 4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit Operation
Address bus for each
instruction
Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 0 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

82
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 0 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

83
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 0 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

31h

84
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus 17

Data bus
Write
Control bus Read

ALU
CPU A
B
PC: 1 C 9

D I/O 16 I/O 17 I/O 18 I/O n

Inst. Dec. registers

31h

85
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4
C4h BA
2 26
26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus 17

Data bus
Write
Control bus Read

ALU
CPU 9
A
B
PC: 1 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

31h

86
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
B
PC: 1 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

31h

87
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
1 Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
B
PC: 1 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

C4h

88
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
B
PC: 2 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

C4h

89
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
9
B
PC: 2 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

C4h

90
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
9
B
PC: 2 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

C4h

91
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
2 Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
9
B
PC: 2 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

26h

92
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5
5h

D0-D7
6

WE
7

OE
CS
6 Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 9
A
9
B
PC: 3 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

26h

93
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 5
9
A
9
B
PC: 3 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

26h

94
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU 5
A
9
B
5

PC: 3 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

26h

95
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

+
ALU
E CPU A
9
B
5E

PC: 4 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

81h

96
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
9
B
E
5

PC: 4 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

81h

97
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
9
B
E
5

PC: 4 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

81h

98
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6

WE
7

OE
CS
7 Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
9
B
E
5

PC: 4
35 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

E7h

99
Instruction Fetch(Decode)Execute in CPU
0 31h A [17]
1 C4h BA
2 26h A  [6]

VCC
3 81h AA+B
4 E7h [7]A
5 0h

A0-An-1
GND
5h

D0-D7
6
E

WE
7

OE
CS
7 Logic circuit
Address bus

Data bus
Write
Control bus Read

ALU
CPU A
9
B
E
5

PC: 4
35 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers

E7h

100
von Neumann vs. Harvard Architecture
• von Neumann architecture
Code Data
Memory Memory

Data bus
CPU Address bus
Control bus

• Harvard architecture

Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus

AVR MCU uses Harvard architecture internally, but accesses external memory
through von Neumann type memory interface, i.e. externally data/instructions
share the same bus. 101