Muftah Aldabbar

..‫ اﻟﻤﺎدة اﻟﺘﺼﻤﯿﻢ اﻟﻤﻨﻄﻘﻲ‬: ‫أﺳﺌﻠﺔ وإﺟﺎﺑﺔ‬

1: In which of the following gates, the output is 1, if and only if at least one
input is 1?
A.NOR
B.AND
C.OR
D.NAND

Option: C
Explanation :
In OR gate we need at least one bit to be equal to 1 to generate the output as
1 because OR means any of the condition out of two is equal to 1 which
means if at least one input is 1 then it shows output as 1 . Number of 1's in
input may be more than one but the output will always be 1 in OR gate. So
the answer is 'C'.
2: The time required for a gate or inverter to change its state is called
A.Rise time
B.Decay time
C.Propagation time
D.Charging time

Option: C
3: The time required for a pulse to change from 10 to 90 percent of its
maximum value is called
A.Rise time
B.Decay time
C.Propagation time
D.Operating speed

Option: A

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4: The maximum frequency at which digital data can be applied to gate is

caled
A.Operating speed
B.Propagation speed
C.Binary level transaction period
D.Charging time

Option: A
5: What is the minimum number of two-input NAND gates used to perform
the function of two input OR gate ?
A.one
B.two
C.three
D.four

Option: C
Explanation :
Y=A+B. This is the equation of OR gate. We require 3 NAND gates to create
OR gate. We can also write
After 1st NAND operation
Y = (A AND B)'
Y= A' + B' (Demorgan's Law)
After 2nd NAND operation
Y= ( A' + B')'
Y= A . B (Demorgan's Law)
After 3rd NAND operation
Y= ( A . B )'
Y= A' + B ' (Demorgan's Law)
So we need 3 NAND gates.

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6: Odd parity of word can beconveniently tested by

A.OR gate

B.AND gate

C.NOR gate

D.XOR gate

Option: D

7: Identify the logic function performed by the circuit shown in the given
figure

A.Exclusive OR

B.Exclusive NOR

C.NAND

D.NOR

Option: B

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8: Which one of the following will give the sum of full adders as output ?

A.Three point majority circuit

B.Three bit parity checker

C.Three bit comparator

D.Three bit counter

Option: D

9: The number of full and half-adders required to add 16-bit numbers is

A.8 half-adders, 8 full-adders

B.1 half-adder, 15 full-adders

C.16 half-adders, 0 full-adders

D.4 half-adders, 12 full-adders

Option: B

Explanation :

The one half-adder can add the least significant bit of the two numbers. Full
adders are required to add the remaining 15 bits as they all involve adding
carries.

10: The time required for a pulse to decrease from 90 to 10 per cent of its
maximum value is called

A.Rise time

B.Decay time

C.Binary level transition period

D.Propagation delay

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Option: B

11: Which of the following gates would output 1 when one input is 1 and
other input is 0 ?

A.OR gate

B.AND gate

C.NAND gate

D.both (a) and (c)

Option: D

12: Which of the following statements is wrong ?

A.Propagation delay is the time required for a gate to change its state

B.Noise immunity is the amount of noise which can be applied to the input of a
gate without causing the gate to change state

C.Fan-in of a gate is always equal to fan-out of the same gate

D.Operating speed is the maximum frequency at which digital data can be

applied to a gate

Option: C

13: Which of the following expressions is not equivalent to X ' ?

A.X NAND X

B.X NOR X

C.X NAND 1

D.X NOR 1

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Option: D

Explanation :

Answer is C as
if X= 0 then X NAND 1 = 1 = X '
if X=1 then X NAND 1= 0= X'

In Option (d)
if X= 0 then X NOR 0 = 1 = X'
if X=1 then X NOR 1= 0 <> X'

14: Which of the following gates are added to the inputs of the OR gate to
convert it to the NAND gate ?

A.NOT

B.AND

C.OR

D.XOR

Option: A

15: The EXCLUSIVE NOR gate is equivalent to which gate followed by an

inverter ?

A.OR

B.AND

C.NAND

D.XOR

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Option: D

16: A one-to-four line de-multiplexer is to be implemented using a memory.

How many bits must each word have ?

A.1 bit

B.2 bits

C.4 bits

D.8 bits

Option: A

Explanation :

2 select line A and B will work as address lines, so we have 4 addresses (or
words)

Each word will have 4 bits so memory required is 4 x 4 = 16 bits

17: What logic function is produced by adding an inverter to the output of an

AND gate ?

A.NAND

B.NOR

C.XOR

D.OR

Option: A

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18: Which of the following gates is known as coincidence detector ?

A.AND gate

B.OR gate

C.NOT gate

D.NAND gate

Option: A

19: Which table shows the logical state of a digital circuit output for every
possible combination of logical states in the inputs ?

A.Function table

B.Truth table

C.Routing table

D.ASCII table

Option: B

20: A positive AND gate is also a negative

A.NAND gate

B.NOR gate

C.AND gate

D.OR gate

Option: D

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Explanation :

Truth Table For AND

0 0 => 0

0 1 => 0

1 0 => 0

1 1 => 1

Now invert all values (as if you place inverters on the two inputs and the one
output):

1 1 => 1

1 0 => 1

0 1 => 1

0 0 => 0

21: A demultiplexer is used to

A.Route the data from single input to one of many outputs

B.Perform serial to parallel conversion

C.Both (a) & (b)

D.Select data from several inputs and route it to single output

Option: C

Explanation :

In demultiplexer, inputs is inserted serially and then it gives multiple outputs

which are in parallel form.

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22: An OR gate can be imagined as

A.Switches connected in series

B.Switches connected in parallel

C.MOS transistors connected in series

D.None of these

Option: B

23: Which combination of gates does not allow the implementation of an

arbitrary boolean function?

A.OR gates and AND gates only

B.OR gates and exclusive OR gate only

C.OR gates and NOT gates only

D.NAND gates only

Option: A

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