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Timing Diagram PDF

The document discusses timing diagrams and machine cycles for the 8085 microprocessor. It explains that timing diagrams show the execution time of each instruction graphically using T-states. The 8085 has 5 basic machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write. Each cycle takes a certain number of T-states. The document provides details on the control signals and data flow during each of the 5 machine cycles. It also includes examples of timing diagrams for sample instructions.

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Sneha Singh
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572 views

Timing Diagram PDF

The document discusses timing diagrams and machine cycles for the 8085 microprocessor. It explains that timing diagrams show the execution time of each instruction graphically using T-states. The 8085 has 5 basic machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write. Each cycle takes a certain number of T-states. The document provides details on the control signals and data flow during each of the 5 machine cycles. It also includes examples of timing diagrams for sample instructions.

Uploaded by

Sneha Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Timing Diagram

Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in
a graphical format. The execution time is represented in T-states.
Instruction Cycle: The time required to execute an instruction is called instruction cycle.
Machine Cycle: The time required to access the memory or input/output devices is called machine cycle.
T-State:
• The machine cycle and instruction cycle takes multiple clock periods.
• A portion of an operation carried out in one system clock period is called as T-state.

Machine Cycles of 8085:


The processor takes a definite time to execute the machine cycles. The time taken by the processor to
execute a machine cycle is expressed in T-states. One T-state is equal to the time period of the internal
clock signal of the processor. The T-state starts at the falling edge of a clock. The 8085 microprocessor
has 5 basic machine cycles.

A
D B

1. Opcode fetch cycle (4T)


2. Memory read cycle (3 T) 4. I/O read cycle (3 T)
3. Memory write cycle (3 T) 5. I/O write cycle (3 T)
Control Signals status during following operations:

Data bus will Point from Processor to


Memory
Data bus will Point from Memory
to processor
1. OPCODE FETCH CYCLE (4T)
T1 State:
During T1 state, the content of the program counter are placed on the 16-bit address bus.
Higher order 8 bits on A8-A15 and lower order 8 bits on AD0-AD7 when ALE goes high.
As soon as ALE goes high the memory latches the AD0-AD7 bus at middle of the this
state ALE goes low again.
T2 State:
During the beginning of this state the signal goes low to enable memory. During this
state the selected memory location’s content i.e. opcode is placed on the data bus.
T3 State:
In this state opcode is transferred to the instruction register of the microprocessor and
signal goes high and thus disables the memory.
T4 State:
In this state the Opcode which was fetched from memory is decoded.

 Each instruction of the processor has one byte opcode.


 The Opcodes are stored in memory. So, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T/6T.
 In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.
2. MEMORY READ CYCLE (3T)
T1 State:
During this state ALE goes high and 16-bit address is available on address and
multiplexed AD bus so that memory location is selected.
T2 State:
During this state signal goes low and the content available at selected memory
location is placed on D0-D7.
T3 State:
The data loaded on previous state is transferred to the processor and at the middle of this
state signal goes high and disables the memory. The data is then decoded and ready
for execution.

 The memory read machine cycle is executed by the processor to read a data byte from memory.
 The processor takes 3T states to execute this cycle.
 The instructions which have more than one byte word size will use the machine cycle after the
opcode fetch machine cycle. Otherwise for 1B instructions the number of machine cycles will be
equals to the number instruction byte because these instructions do not involve memory for
operand fetching only opcode fetch cycle takes place.
Ex: ADD R, CMP R, INR R, MOV A, B and so on all are 1B instructions and do not involve any
memory access for operand fetch since R (register) is the part of processor and no need to
access memory for operand reading.
3. MEMORY WRITE CYCLE (3T)
T1 State:
During this state ALE goes high and 16-bit address is available on address and
multiplexed AD bus so that memory location is selected.
T2 State:
During this state signal goes low and the content is placed on D0-D7 bus for data
writing on selected memory.
T3 State:
The data loaded on previous state is transferred to the memory and at the middle of this
state signal goes high and disables the memory. The data is then decoded and ready
for execution.

 The memory write machine cycle is executed by the processor to write a data byte in a memory
location.
 The processor takes, 3T states to execute memory write machine cycle.

00H
2500 25H

Transfer DATA from ACC to 2500H (WRITE)


Ex: TIMING DIAGRAM of given instruction:
41FF STA 526AH (3 Byte Instruction)
Opcode Fetch Machine Cycle
41FF 32(OPCODE of STA)
Memory Read Machine Cycle to get lower address from
4200 6A (Lower order address fetch for data store) 4200
Memory Read Machine Cycle to get higher address from 4201
4201 52 (Higher order address fetch for data store)
Memory Write Machine Cycle to store A content at
526A location of memory
4. I/O READ CYCLE (3T)

 The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the
peripheral.
 The processor takes 3T states to execute this machine cycle.
 The IN instruction uses this machine cycle during the execution.
IN PORT#: The current 8-bit content of the PORT# will be made available on to the Accumulator. Let us
suppose with the PORT#, 8 DIP switches are connected. And their states are ON-ON-OFF-ON-ON-ON-
OFF-ON. So after execution of the instruction IN PORT#, the Accumulator content will be 1101 1101.
5. I/O WRITE CYCLE (3T)

 The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or
to a peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.
 The OUT instruction uses this machine cycle during the execution.

OUT PORT#: The current 8-bit content of the Accumulator will be copied on to the PORT#. Let us
suppose that Accumulator’s initial content is 0101 0101. And with the 8-bit port 8 LEDs are connected.
So after execution of the instruction OUT PORT#, LEDs will have the OF-OFF states as shown below –

Timing diagram for IN C0H.

IN C0H 3 machine cycles

 Fetching the Opcode DBH from the


memory 4125H.
 Read the port address C0H from 4126H.
 Read the content of port C0H and send it to
the accumulator.
Timing diagram for OUT 12H.
OUT 12H 3 machine cycles
1. Opcode fetch
2. Memory access to read the given PORT address.
3. Write the ACC content on the PORT # location fetched at previous cycle.
Timing diagram for ADD M
ADD M 2 machine cycles
1. Opcode fetch
2. Memory access to read address stored at HL pair

Timing diagram for INR M


INR M 3 machine cycles
4. Opcode fetch
5. Memory access to read address stored at HL pair
6. Write the incremented content on the same location pointed by HL pair

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