Bugbook 0 PDF
Bugbook 0 PDF
Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE
• Experiment 2-1. Truth Table for a 2-input Positive NAND Gate
• Experiment 2-2. Construction of an Inverter
• Experiment 2-3. What Happens if I Forget to Wire Up an Input Pin to a NAND Gate?
• Experiment 2-4. Inverting a Clock Output
• Experiment 2-5. What Happens When I Cionnect Both the Normal and Inverted Clock Outputs
to a 2-Input NAND Gate?
Experiment No. 5. THE 7476 DUAL J-K MASTER-SLAVE FLIP-FLOP WITH PRESET AND CLEAR
• Experiment 5-1. A Working Flip-Flop
• Experiment 5-2. What do the J-K Inputs Do?
• Experiment 5-3. What do the Clear and Preset Inputs Do?
• Experiment 5-4. Truth Table for a J-K Master-Slave Flip-flop
• Experiment 5-5. When does the Flip-flop State Change, on the Leading Edge or the Trailing Edge
of the Clock Pulse?
• Experiment 5-6. Divide-by-two and Divide-by-four circuits using a Pair of Flip-Flops
Experiment No. 7. PARALLEL AND SERIAL DATA TRANSMISSION AND THE 74198 8-BIT SHIFT REGISTER
• Experiment 7-1. Serial Entry of Data into an 8-Bit Shift Register
• Experiment 7-2. A Circulating 8-Bit Shift Register
• Experiment 7-3. A Serial Transmitter and Serial Receiver
• Experiment 7-4. A Parallel Transmitter and Parallel Receiver
Experiment No. 10. CONSTRUCTION OF A MULTIPLEXER THAT CONVERTS BCD TO SERIAL ASCII
CHARACTERS
• Experiment 10-1. Characteristics of the 74193 Synchronous 4-Bit Binary Up/Down Counter with
Preset Inputs
• Experiment 10-2. Construction of a Synchronous Binary Down Counter that Counts from
Decimal Eleven to Decimal Zero and Stops
• Experiment 10-3. Construction of a Multiplexer that Converts BCD to Serial ASCII Characters